JP2006235609A - Light-emitting device and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problems in reduction in yield and aperture ratio accompanying increase in the number of transistors which form pixels, and increase in the power consumption for holding desired luminance. <P>SOLUTION: A light-emitting device having a novel pixel configuration is provided. The light-emitting device has structure, including a unit for applying a forward bias voltage to a first light emitting element so that a first pixel emits light and applying reverse bias voltage to a second light-emitting element, and a unit for applying a reverse bias voltage to the first light-emitting element so that the first pixel emits no light and applying a forward bias voltage to the second light-emitting element. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  In the present invention, fluorescence or phosphorescence is obtained by applying an electric field by a TFT (Thin Film Transistor) to an element in which a film containing an organic compound (hereinafter referred to as “organic compound layer”) is provided between a pair of electrodes. The present invention relates to an active matrix light emitting device using a light emitting element. Note that the light-emitting device in this specification refers to an image display device, a light-emitting device, or a light source. Also, a module in which a connector such as an FPC (Flexible Printed Circuit) or TAB (Tape Automated Bonding) tape or TCP (Tape Carrier Package) is attached to a light emitting element, or a printed wiring board provided on the end of a TAB tape or TCP In addition, a module in which an IC (integrated circuit) is directly mounted on a light emitting element by a COG (Chip On Glass) method is also included in the light emitting device.

  2. Description of the Related Art In recent years, a display device that replaces a liquid crystal display (LCD) is composed of a display panel in which light emitting elements are arranged for each pixel and a peripheral circuit that inputs a signal to the panel, and controls light emission of the light emitting elements. There is a light-emitting device that displays an image.

  Development of a light-emitting device using a module in which light-emitting elements are arranged in a matrix has been widely promoted, and an organic EL (Electro Luminescence) element using an organic material for a light-emitting layer has attracted attention. This is also due to the fact that the use of an organic compound that can be expected to have good light-emitting characteristics for the light-emitting layer of the EL element has led to an increase in efficiency and longevity that can withstand practical use.

  In such a light emitting device, typically two or three TFTs (thin film transistors) are arranged for each pixel.

  FIG. 28 shows a conventional pixel configuration in which two transistors are arranged for one pixel. A control transistor 2801, a driving transistor 2802, a capacitor 2803, a light emitting element 2804, a data line sig, and a scanning line gate. And a power supply line com (see Patent Document 1).

  FIG. 29 shows a circuit configuration of a conventional pixel in which three transistors are arranged for one pixel. A control transistor 2901, a driving transistor 2902, an erasing transistor 2903, a capacitor element 2904, and a light emitting element. 2905, a data line sig, a control scanning line gate1, an erasing scanning line gate2, and a power supply line com (see Patent Document 2).

  In the circuit configuration of the pixel shown in FIGS. 28 and 29, the current supplied to the light emitting element of each pixel, that is, the luminance of the light emitting element of each pixel and light emission / non-light emission are controlled by controlling on and off of the transistor To do.

Further, the light emitting element has a predetermined light emission luminance with current I ₀ when a certain voltage V ₀ is applied due to a change in luminance characteristics over time, but only current I ₀ ′ is applied even when voltage V ₀ is applied. Since it does not flow to the light emitting element, there is a problem that a predetermined luminance cannot be obtained.

  This is presumably because the light emitting element generates heat when a voltage or current is applied, and the properties of the film quality interface or electrode interface of the light emitting element change. Further, in a deteriorated state of the light emitting element, image sticking occurs because the light emitting element is different.

Therefore, in order to suppress deterioration of the light emitting element and improve reliability, a voltage (reverse bias voltage) opposite to the voltage applied during light emission of the light emitting element is applied, and the charge of the light emitting element is periodically biased. There is a method of mitigating (see Patent Document 3).
JP 2001-343933 A JP 2001-324958 A JP 2001-117534 A

  As described in the above-mentioned patent documents, a pixel circuit having a light emitting element can take various configurations. Furthermore, the number of transistors used in the pixels is increasing due to the increase in the number of pixels accompanying the increase in definition of the display portion. For this reason, problems such as a decrease in the aperture ratio and an increase in power consumption for maintaining a desired luminance become apparent as the number of transistors constituting each pixel increases.

  In addition, since the light-emitting device includes a plurality of pixels, the number of wiring lines such as scanning lines and power supply lines connected to each pixel increases as the display portion becomes higher definition and larger. Therefore, there are problems such as an increase in the layout area of the display panel and a decrease in yield due to an increase in the number of wiring connections, a decrease in aperture ratio due to an increase in the number of wirings, and an increase in power consumption for maintaining a desired luminance.

  Further, in the light emitting device, in order to control the deterioration of the light emitting element and improve the reliability, there is a demand for a light emitting device that periodically applies a reverse voltage (hereinafter referred to as a reverse bias voltage) to the light emitting element.

  Further, when display is performed using the time-division gray scale method in the light emitting device, there is a problem that pseudo contours are generated and image quality is disturbed. A pseudo contour is an unnaturally bright line or dark line that appears when the adjacent gradation (halftone) is displayed. This is a display disorder such as visibility.

  The present invention has been devised in view of the above-described problems, and solves the above problems in a unified manner.

  Specifically, the present invention is a light-emitting device including two light-emitting elements that emit light in accordance with a signal input from a data line through a transistor electrically connected to the data line. The present invention is characterized in that when a forward bias is applied to one of these light emitting elements, a reverse bias is applied to the other.

  One of the present invention is a scan line, a data line, a first power supply line, a second power supply line, a third power supply line, a first light emitting element, a second light emitting element, The light-emitting device includes a third light-emitting element, a first transistor, and a second transistor. The first light emitting element and the second light emitting element are connected to the first power supply line and the second power supply line, respectively. The gate of the first transistor is electrically connected to the scan line. The gate of the second transistor is electrically connected to the data line through the source and drain of the first transistor. One of the source and the drain of the second transistor is electrically connected to the third power supply line, and the other is electrically connected to the first light-emitting element and the second light-emitting element. In this light emitting device, when a forward bias is applied to one of the first light emitting element and the second light emitting element, a reverse bias is applied to the other. Note that the first transistor and the second transistor are also referred to as a selection transistor and a driving transistor, respectively.

  One of the present invention is to provide a scan line, a data line, a first power supply line, a second power supply line, a first light emitting element, a second light emitting element, a first transistor, A light-emitting device having two transistors and a third transistor. The first light emitting element and the second light emitting element are connected to the first power supply line and the second power supply line, respectively. The gate of the first transistor is electrically connected to the scan line. The gate of the first transistor is electrically connected to the scan line. The gate of the second transistor is electrically connected to the data line through the source and drain of the first transistor. One of the source and the drain of the second transistor is electrically connected to the first power supply line, and the other is electrically connected to the first light-emitting element. The gate of the third transistor is electrically connected to the data line through the source and drain of the first transistor. One of the source and the drain of the third transistor is electrically connected to the second power supply line, and the other is electrically connected to the second light-emitting element. In this light emitting device, when a forward bias is applied to one of the first light emitting element and the second light emitting element, a reverse bias is applied to the other. Note that each of the first transistors is also referred to as a selection transistor. The second transistor and the third transistor are also referred to as driving transistors.

  One of the present invention is to provide a first scan line, a second scan line, a data line, a first power supply line, a second power supply line, a first light emitting element, and a second light emission. A light emitting device including an element, a first transistor, a second transistor, a third transistor, a first capacitor element, a second capacitor element, and an erasing element is there. The first light emitting element and the second light emitting element are connected to the first power supply line and the second power supply line, respectively. The gate of the first transistor is electrically connected to the scan line. The gate of the first transistor is electrically connected to the scan line. The gate of the second transistor is electrically connected to the data line through the source and drain of the first transistor. One of the source and the drain of the second transistor is electrically connected to the first power supply line, and the other is electrically connected to the first light-emitting element. The gate of the third transistor is electrically connected to the data line through the source and drain of the first transistor. One of the source and the drain of the third transistor is electrically connected to the second power supply line, and the other is electrically connected to the second light-emitting element. The first capacitor is provided to hold a voltage applied to the gate of the second transistor. The second capacitor element is provided to hold a voltage applied to the gate of the third transistor. The erasing element is provided so that the voltage held in the first capacitor element or the second capacitor element is erased when the erasing element is turned on. In this light emitting device, when a forward bias is applied to one of the first light emitting element and the second light emitting element, a reverse bias is applied to the other. Note that each of the first transistors is also referred to as a selection transistor. The second transistor and the third transistor are also referred to as driving transistors.

  The present invention also provides an electronic apparatus equipped with the light emitting device.

  According to the present invention, the number of transistors included in a pixel and the number of wirings such as a scan line and a power supply line connected to each pixel can be reduced, so that an increase in aperture ratio can be achieved.

  In the light-emitting device of the present invention, the number of transistors included in a pixel and the number of wirings such as a scanning line and a power supply line connected to each pixel can be reduced, so that an increase in aperture ratio can be expected. The voltage applied to the light emitting element for maintaining the power can be suppressed, and low power consumption can be achieved.

  In the light-emitting device of the present invention, in a pixel adjacent to a region provided at each intersection of the scan line and the data line, a forward bias voltage is applied to one pixel to cause the light-emitting element to emit light, and the other pixel is The reverse bias voltage can be applied simultaneously. Therefore, since it is not necessary to provide a reverse bias voltage application time, it is possible to control the deterioration of the light emitting element and improve the reliability without reducing the duty ratio (the ratio of the lighting period in one frame period).

  Further, in the light emitting device of the present invention, by adopting a method (interlace method) that sequentially emits pixels every other row in the data line extending direction or the scanning line extending direction. It is possible to reduce the visual recognition of the pseudo contour, which is a problem when the image is displayed by the gradation method. In addition, the pixels are sequentially turned on every two pixels in each row, and in the next row, the pixels are turned on by shifting one pixel in the data line extending direction from the pixel in which the pixel is lit in the previous row. By adopting a method of performing light emission (checker method), the visual recognition of the pseudo contour can be reduced.

  In addition, in an electronic device using the light-emitting device of the present invention, as described above, the number of transistors connected to each pixel, the number of wiring lines such as a scanning line and a power supply line can be reduced. The layout area of the drive circuit around the area can be reduced, and the layout area of the display panel can be reduced. Therefore, the electronic device can be reduced in size and weight. Moreover, a product with a high yield can be manufactured, and a cheaper product can be provided to the customer.

  Embodiments of the present invention will be described below with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode. Note that in all the drawings for describing the following embodiments, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

(Embodiment 1)
FIG. 1 shows a circuit diagram in which pixel portions of this embodiment are arranged in a matrix. FIG. 2 shows an enlarged circuit configuration of the pixel portion of this embodiment mode. A region 100 illustrated in FIG. 1 includes a first pixel pix1 and a second pixel pix2. In addition, the enlarged region 100 illustrated in FIGS. 1 and 2 includes a scanning line gate, a data line sig, a first power supply line com1, a second power supply line com2, and a third power supply line com3. have.

  Note that in the present invention, a pixel portion refers to a region provided at each intersection of a plurality of scanning lines and a plurality of data lines. In this embodiment mode, the region 100 is a pixel portion.

  In FIG. 2, the pixel portion includes a selection transistor 101, a driving transistor 102, a first light-emitting element 103, a second light-emitting element 104, a first capacitor element 105, and a second capacitor element 106. ing.

  In the present invention, the light emitting element may be anything as long as it has a rectifying property. Any light emitting element such as an EL element (an organic EL element, an inorganic EL element, or an EL element containing an organic substance and an inorganic substance) or an element used in a field emission display (FED) may be used.

  One of the source and drain of the selection transistor 101 is connected to the data line sig, and the other is connected to the gate of the driving transistor 102. One electrode of the first capacitor 105 is connected to the gate of the driving transistor 102, and the other electrode is connected to the first power supply line com1. One electrode of the second capacitor 106 is connected to the gate of the driving transistor 102, and the other electrode is connected to the second power supply line com2.

  In addition, the first electrode of the first light-emitting element 103 is connected to the first power supply line com1, and the second electrode of the first light-emitting element 103 is either the source or the drain of the driving transistor 102. Connected to. In addition, the first electrode included in the second light-emitting element 104 is connected to the second power supply line com2, and the second electrode included in the second light-emitting element 104 includes either the source or the drain of the driving transistor 102. Connected to. The second electrode included in the first light-emitting element 103 and the second electrode included in the second light-emitting element 104 are connected to each other. A third power supply line com3 is connected to an electrode of the source and drain electrodes of the driving transistor 102 that is not connected to the first light emitting element 103 and the second light emitting element 104.

  Note that in this specification, “connected” means electrical connection unless otherwise specified.

  Note that in this embodiment mode, the first light-emitting element 103 emits light when current flows from the first electrode to the second electrode. In the second light-emitting element 104, light is emitted when a current flows from the first electrode to the second electrode. Note that the polarity of the first electrode is opposite to the polarity of the second electrode.

  Note that the first capacitor 105 and the second capacitor 106 for holding a video signal input to the gate of the driving transistor 102 are different from the gate of the driving transistor 102 (a dedicated wiring, A capacitor element may be disposed between the pixel signal and the gate signal line of the previous pixel. Note that in this embodiment mode, the selection transistor 101 is an N-channel type, and the driving transistor 102 is a P-channel type. However, it is not limited to this.

  Next, the operation method of the pixel configuration of the present embodiment shown in FIG. 2 will be specifically described.

  FIG. 3 is a diagram illustrating a voltage of each wiring and a timing chart when the first light-emitting element 103 is selected to emit light with respect to the pixel of this embodiment mode.

The state (initial state) in FIG. A high potential (hereinafter abbreviated as H) or a low potential (hereinafter abbreviated as L) is input to the data line sig, an H potential is input to the first power supply line com1, and the second power supply first Low potential in line com2 potential (hereinafter, _{L 1} and abbreviated) is inputted, the third power supply line com3 potential to the potential of the second Low (hereinafter, abbreviated as _{L 2)} Is entered. In this embodiment, it is assumed that H >> L ₂ > L ₁ and the potentials of L ₁ and L ₂ are approximately equal to the potential of L.

Next, the state (signal input period) of FIG. Here, the data line sig is set to the L potential. In order to turn on the selection transistor 101, an H potential is input to the scanning line gate. When the selection transistor 101 is turned on, the potential of L from the data line sig is input to one electrode of the first capacitor element 105 and the second capacitor element 106 in pix1 and pix2. The other electrode of the first capacitor 105 is input with H which is the potential of the first power supply line com 1, and charges are accumulated in the first capacitor 105. In the other electrode of the second capacitor 106, the potential of L ₁ from the second power supply line com2 is input, the potential difference applied to the two electrodes of the second capacitor 105 becomes substantially the same potential difference Almost no charge is accumulated.

When the L potential is applied to the gate of the driving transistor 102 from the charge accumulated in the first capacitor 105, the driving transistor 102 is turned on. In this case the third power supply line potential of L ₂ is input. Therefore, the potential of H is applied to the first electrode of the first light-emitting element 103, and the potential of L2 is applied to the _second electrode of the first light-emitting element 103. The first light-emitting element 103 emits light when current flows in the direction of the dotted arrow illustrated in FIG. That is, a forward bias voltage is applied to the first light emitting element 103.

Further, the first electrode of the second light emitting element 104, the potential of L ₁ is input to the second electrode voltage of L ₂ is input. As described above, the potential is set such that L ₂ > L ₁ , and a reverse bias voltage is applied to the second light emitting element 104 from the second electrode side to the first electrode side. Therefore, it is possible to periodically alleviate the unevenness of the charge of the light emitting element, and it is possible to achieve reliability and long life of the light emitting element while emitting light from the light emitting element.

  Next, the state (signal holding period) shown in FIG. The selection transistor 101 is turned off by setting the scanning line gate to the L potential. The first capacitor element 105 holds a voltage for turning on the driving transistor 102, and the first light-emitting element 103 can hold a light-emitting state.

  FIG. 3D illustrates a scanning line gate, a data line sig, a first power supply line com1, and a second line in each stage (initial state, signal input period, signal holding period) of FIGS. 6 is a timing chart of each voltage of a power supply line com2 and a third power supply line com3. As shown in FIG. 3D, by controlling the potential of each wiring, the light emission of the light emitting element and the operation of applying the reverse bias voltage can be controlled simultaneously. In FIG. 3D, the hatched section of the potential in the data line sig is an indefinite value section (Don't care) in which the potential may be H or L.

Note that the potentials of L ₁ and L ₂ may be the same. In this case, a reverse bias voltage is not applied to the second light emitting element 104.

  Next, FIG. 4 is a diagram illustrating a voltage of each wiring and a timing chart when the second light-emitting element 104 is selected to emit light with respect to the pixel of this embodiment mode.

The state (initial state) in FIG. 4A will be described. An H or L potential is input to the data line sig, an L ₁ potential is input to the first power supply line com1, an H potential is input to the second power supply line com2, and the third power supply line potential of _{L 2} is input to the com3.

Next, the state shifts to the state (signal input period) in FIG. Here, the data line sig is set to L. In order to turn on the selection transistor 101, an H potential is input to the scanning line gate. When the selection transistor 101 is turned on, the potential of L from the data line sig is input to one electrode of the first capacitor element 105 and the second capacitor element 106 in pix1 and pix2. The other electrode of the first capacitor 105, the potential of L ₁ is input from the first power source line com1, the potential difference applied to the two electrodes of the first capacitor 105 becomes substantially the same potential, Almost no charge is accumulated. The other electrode of the second capacitor 106 is input with H which is the potential of the second power supply line com 2, and charges are accumulated in the second capacitor 106.

When the L potential is applied to the gate of the driving transistor 102 from the electric charge accumulated in the second capacitor 106, the driving transistor 102 is turned on. In this case the third power source line voltage of L ₂ is input. Therefore, a voltage of H is applied to the first electrode of the second light-emitting element 104, and a voltage of L2 is applied to the _second electrode of the second light-emitting element 104. The second light-emitting element 104 emits light when current flows in the direction of the dotted arrow illustrated in FIG. That is, a forward bias voltage is applied to the second light emitting element 104.

In addition, an L ₁ potential is input to the _first electrode of the first light-emitting element 103, and an L ₂ voltage is input to the _second electrode. As described above, the potential is set such that L ₂ > L ₁ , and a reverse bias voltage is applied to the first light-emitting element 103 from the second electrode side to the first electrode side. Therefore, it is possible to periodically alleviate the unevenness of the charge of the light emitting element, and it is possible to achieve reliability and long life of the light emitting element while emitting light from the light emitting element.

  Next, the state shifts to the state (signal holding period) shown in FIG. By setting the scanning line gate to the L potential, the selection transistor 101 is turned off. The second capacitor element 106 holds a voltage for turning on the driving transistor 102, and the second light-emitting element 104 can hold a light-emitting state.

  FIG. 4D illustrates the scanning line gate, the data line sig, the first power supply line com1, and the second line in each stage (initial state, signal input period, signal holding period) of FIGS. 6 is a timing chart of each voltage of a power supply line com2 and a third power supply line com3. As shown in FIG. 4D, by controlling the potential of each wiring, the light emission of the light emitting element and the operation of applying the reverse bias voltage can be controlled at the same time. In FIG. 4D, the hatched section of the potential in the data line sig is an indefinite value section where the potential may be H or L.

Note that the potentials of L ₁ and L ₂ may be the same. In this case, a reverse bias voltage is not applied to the first light emitting element 103.

  FIG. 5 shows an actual top view of the circuit configuration in the present embodiment. Each wiring connection portion has a contact portion 130. The top view shown in FIG. 5 is an example, and the present invention is not particularly limited to this configuration.

  Next, the structure of the display panel and the driver circuit having the circuit configuration of the light emitting device of this embodiment will be described.

  FIG. 6 is a block diagram in which the scan line driver circuit 901 and the signal line driver circuit 902 are provided around the display portion 600.

  The scanning line driver circuit 901 includes a shift register 301, a level shifter 304, and a buffer 305. The signal line driver circuit 902 includes a shift register 401, a first latch circuit 402, a second latch circuit 403, a level shifter 404, and a buffer 405. The display unit 600 includes a region 100 where the first pixel pix1 and the second pixel pix2 are provided, and each pixel is provided with a light emitting element. The circuit configuration of the region 100 is as shown in FIG.

  The signal line driver circuit 902, the scan line driver circuit 901, and the display portion 600 can be formed using semiconductor elements provided over the same substrate. For example, it can be formed using a thin film transistor provided over a glass substrate. Further, the signal line driver circuit 902 and the scan line driver circuit 901 can be mounted on a glass substrate by using an IC chip.

  In the light-emitting device of this embodiment, the first light-emitting element and the second light-emitting element are selected to emit light, and an image is displayed. In the light-emitting element of this embodiment mode, display is performed with time-division gradation. For this reason, the light emitting device of the present invention employs a display using an interlace method in which screen display of one frame is divided into odd and even rows of pixels. By performing display using the interlace method, it is possible to prevent a phenomenon in which a pseudo contour is generated in the display unit and the image quality is deteriorated and recognized. The pseudo contour is a phenomenon in which bright and dark lines appear to be mixed when displaying a halftone.

  FIG. 7 is a schematic diagram of a pixel portion of an active matrix light-emitting device in which the circuit configuration of this embodiment is arranged in a matrix. Display pixels are white and non-display pixels are black.

  In the present embodiment, the first pixel pix1 including the first light emitting element and the second pixel pix2 including the second light emitting element may be arranged in the extending direction of the data line sig illustrated in FIG.

  In such a pixel portion, in the first frame, only the odd-numbered pixels that are the first pixels pix1 are displayed (see FIG. 7A), and in the second frame, the pixels are the second pixels pix2. Only even rows of pixels are displayed (see FIG. 7B). That is, a display area and a non-display area are provided in a stripe shape in the pixel portion.

  In the present embodiment, the first frame is represented as an odd frame, and the second frame is represented as an even frame.

  In the pixel portion of the present invention, only the even-numbered pixels including the second light-emitting elements may be displayed in the odd-numbered frames, and only the odd-numbered pixels including the first light-emitting elements may be displayed in the even-numbered frames. .

  FIG. 8 shows a timing chart for performing such display. FIG. 8A shows a scanning line start pulse (GSP), a scanning line clock signal (GCK), and a selection (ENB) signal for selecting a scanning line in the row direction in an odd frame. In addition, a start pulse (SSP) and a start clock signal (SCK) for selecting a data line in the column direction are shown. These signals indicate the timing of the video signal (DATA).

  FIG. 8B shows a timing chart in an even frame. 8B, the ENB signal is inverted and the other timings are the same.

  In the odd-numbered frame, the odd-numbered pixels in the pixel portion are selected only when the ENB signal is High. In the even frame, the pixels in the even rows of the pixel portion are selected only when the ENB signal is High. That is, in the display unit of the present embodiment, the scanning line of the display unit is selected only when the ENB signal is High.

  The video signal (DATA) is input after the SSP signal and input to the selected pixel. The video signal (DATA) may be captured within one gate clock period. Note that the selected pixel is a pixel having a semiconductor element connected to the selected scanning line.

  According to the present invention as described above, the occurrence of pseudo contour can be reduced in the active light emitting device that performs time-division gradation.

  In order to prevent false contours, it was necessary to increase the frame frequency. However, when the frame frequency is increased, the driving circuit is burdened and the information amount of the video signal may be increased. As a result, the burden on the drive circuit, particularly the frequency of the latch circuit, increases, and the number of wires for inputting video signals increases. Therefore, by adopting the circuit configuration of the present embodiment, it is possible to prevent the false contour without increasing the frame frequency, and it is preferable without increasing the burden on the driving circuit.

  By using the interlace method, the information amount of the video signal can be halved. As a result, the number of signal lines and scanning lines can be reduced, and the aperture ratio can be improved.

  If the interlace method is used, there is a concern about a decrease in luminance. However, when an organic material is used for the light-emitting element of the light-emitting device of this embodiment, the light-emitting element exponentially decreases in luminance, so that there is no problem with an increase in supply voltage accompanying the luminance decrease.

  In addition, by using the interlace method, the light emission of the pixels in the odd rows in the first frame and the pixels in the even rows in the second frame is performed separately. Therefore, the information amount of the video signal is halved, and the frame frequency can be increased without imposing a burden on the drive circuit. As a result, a pseudo contour can be prevented without causing a decrease in luminance, which is preferable because a load is not imposed on the drive circuit.

  When the first pixel pix1 and the second pixel pix2 shown in FIG. 1 are arranged in the extending direction of the scanning line, the first pixel pix1 and the second pixel pix2 are sequentially arranged in the extending direction of the scanning line gate. It can be set as the structure arranged. In the case of this configuration, display can also be performed as an interlace method in the extension direction of the data line sig.

  Note that in this embodiment mode, a thin film transistor can be used for a semiconductor element connected to a signal line or a scan line.

  Note that this embodiment can be implemented in free combination with the description of the other embodiments in this specification. Since the number of transistors constituting the pixel and the number of wiring lines such as scanning lines and power supply lines connected to each pixel can be reduced and an increase in aperture ratio can be expected, it is applied to a light emitting element for maintaining a desired luminance. Voltage can be suppressed and low power consumption can be achieved. In the light-emitting device of the present invention, in a pixel adjacent to a region provided at each intersection of the scan line and the data line, a forward bias voltage is applied to one pixel to cause the light-emitting element to emit light, and the other pixel is The reverse bias voltage can be applied simultaneously. Therefore, since it is not necessary to provide a reverse bias voltage application time, it is possible to control the deterioration of the light emitting element and improve the reliability without reducing the duty ratio (the ratio of the lighting period in one frame period).

  Further, in the light emitting device of the present invention, by adopting a method (interlace method) that sequentially emits pixels every other row in the data line extending direction or the scanning line extending direction. It is possible to reduce the visual recognition of the pseudo contour, which is a problem when the image is displayed by the gradation method. In addition, the pixels are sequentially turned on every two pixels in each row, and in the next row, the pixels are turned on by shifting one pixel in the data line extending direction from the pixel in which the pixel is lit in the previous row. By adopting a method of performing light emission (checker method), the visual recognition of the pseudo contour can be reduced.

(Embodiment 2)
In Embodiment 1, the driving transistor for driving the first light-emitting element and the second light-emitting element is driven in common to cause the first light-emitting element to emit light and reverse to the second light-emitting element. A circuit diagram of a light emitting device capable of achieving application of a bias voltage is shown. In this embodiment, a specific structure in which a driving transistor is provided in each of the first light-emitting element and the second light-emitting element is described below.

  FIG. 9 is a circuit diagram in which the pixel portions of this embodiment are arranged in a matrix. FIG. 10 shows an enlarged configuration of the circuit of the pixel portion of this embodiment mode. A region 100 which is a pixel portion illustrated in FIG. 9 includes a first pixel pix1 and a second pixel pix2. Further, the enlarged region 100 shown in FIGS. 9 and 10 includes a scanning line gate, a data line sig, a first power supply line com1, and a second power supply line com2.

  In FIG. 10, the pixel portion includes a selection transistor 101, a first driving transistor 1001, a second driving transistor 1002, a first light emitting element 103, a second light emitting element 104, a first capacitor element 105, A second capacitor 106.

  One of the source and drain of the selection transistor 101 is connected to the data line sig, and the other is connected to the gate of the first driving transistor 1001 and the gate of the second driving transistor 1002. In addition, one electrode of the first capacitor 105 is connected to the gate of the first driving transistor 1001, and the other electrode is connected to the first power supply line com1. In addition, one electrode of the second capacitor 106 is connected to the gate of the second driving transistor 1002 and the other electrode is connected to the second power supply line com2.

  In addition, the first electrode included in the first light-emitting element 103 is connected to either the source or the drain of the first driving transistor 1001, and the second electrode included in the first light-emitting element 103 is the second electrode. Connected to the power supply line com2. In addition, the first electrode included in the second light-emitting element 104 is connected to either the source or drain electrode of the driving transistor, and the second electrode included in the second light-emitting element is connected to the first power supply line com1. It is connected to the. The first power supply line com1 is connected to the electrode that is not connected to the first light emitting element 103 among the source electrode and the drain electrode of the first driving transistor 1001. The second power supply line com2 is connected to the electrode that is not connected to the first light-emitting element 104 among the source and drain electrodes of the second driving transistor 1002.

  Note that in this embodiment mode, the first light-emitting element 103 emits light when current flows from the first electrode to the second electrode. In the second light-emitting element 104, light is emitted when a current flows from the first electrode to the second electrode. Note that the polarity of the first electrode is opposite to the polarity of the second electrode.

  Note that the first capacitor 105 and the second capacitor 106 for holding a video signal input to the gates of the first driver transistor 1001 and the second driver transistor 1002 are the first driver transistors. A capacitor may be provided between the gates of the transistor 1001 and the second driving transistor 1002 and another wiring (a dedicated wiring, a gate signal line of a pixel in the previous stage, or the like). Note that in this embodiment mode, the selection transistor 101 is an N-channel type, and the first driving transistor and the second driving transistor are P-channel types. However, it is not limited to this.

  Next, an operation method of the pixel configuration of this embodiment mode illustrated in FIG. 10 will be specifically described.

  FIG. 11 is a diagram illustrating a voltage of each wiring and a timing chart when the first light-emitting element 103 is selected to emit light for the pixel of this embodiment mode.

  The state (initial state) in FIG. 11A will be described. A high potential (hereinafter abbreviated as H) or a low potential (hereinafter abbreviated as L) is input to the data line sig, an H potential is input to the first power supply line com1, and the second power supply An L potential is input to the line com2.

  Next, the state shifts to the state (signal input period) in FIG. Here, the data line sig is set to L. In order to turn on the selection transistor 101, an H potential is input to the scanning line gate. When the selection transistor 101 is turned on, the potential of L from the data line sig is input to one electrode of the first capacitor element 105 and the second capacitor element 106 in pix1 and pix2. The other electrode of the first capacitor 105 is input with H which is the potential of the first power supply line com 1, and charges are accumulated in the first capacitor 105. In addition, since the L potential is input from the second power supply line com2 to the other electrode of the second capacitor element 106, the potential difference applied to the two electrodes in the second capacitor element 106 becomes the same potential difference, and the charge Is not accumulated.

  By applying an L voltage to the gates of the first driving transistor 1001 and the second driving transistor 1002 from the electric charge accumulated in the first capacitor 105, the first driving transistor 1001 and the second driving transistor 1001 The driving transistor 1002 is turned on. At this time, an L voltage is input to the second power supply line. Therefore, a voltage of H is applied to the first electrode of the first light-emitting element 103, and a voltage of L is applied to the second electrode of the first light-emitting element 103. The first light-emitting element 103 emits light when current flows in the direction of the dotted arrow illustrated in FIG. That is, a forward bias voltage is applied to the first light emitting element 103.

  In addition, when the second driving transistor 1002 is turned on, an L potential is input to the first electrode of the second light-emitting element 104, and an H voltage is input to the second electrode. That is, a reverse bias voltage is applied to the second light emitting element 104 from the second electrode side to the first electrode side. Therefore, it is possible to periodically alleviate the unevenness of the charge of the light emitting element, and it is possible to achieve reliability and long life of the light emitting element while emitting light from the light emitting element.

  Next, the state shifts to the state (signal holding period) in FIG. By setting the scanning line gate to the L potential, the selection transistor 101 is turned off. The first capacitor 105 holds a voltage for turning on the first driving transistor 1001 and the second driving transistor 1002, and the first light-emitting element 103 can hold a light-emitting state. it can.

  FIG. 11D shows a scanning line gate, a data line sig, a first power supply line com1, and a second line in each stage (initial state, signal input period, signal holding period) of FIGS. It is a timing chart of each voltage of power supply line com2. As shown in FIG. 11D, by controlling the potential of each wiring, the light emission of the light emitting element and the operation of applying the reverse bias voltage can be controlled at the same time. In FIG. 11D, the hatched section of the potential in the data line sig is an indefinite value section in which the potential may be H or L.

  Next, FIG. 12 is a diagram illustrating a voltage of each wiring and a timing chart when the second light-emitting element 104 is selected to emit light with respect to the pixel of this embodiment mode.

  The state (initial state) in FIG. 12A will be described. An H or L potential is input to the data line sig, an L potential is input to the first power supply line com1, and an H potential is input to the second power supply line com2.

  Next, the state shifts to the state (signal input period) in FIG. Here, the data line sig is set to L. In order to turn on the selection transistor 101, an H potential is input to the scanning line gate. When the selection transistor 101 is turned on, the potential of L from the data line sig is input to one electrode of the first capacitor element 105 and the second capacitor element 106 in pix1 and pix2. At the other electrode of the first capacitor 105, an L potential is input from the first power supply line com1, and the potential difference applied to the two electrodes in the first capacitor 105 becomes the same potential difference. Not done. The other electrode of the second capacitor 106 is input with H which is the potential of the second power supply line com 2, and charges are accumulated in the second capacitor 106.

  By applying an L voltage to the gates of the first driving transistor 1001 and the second driving transistor 1002 from the electric charge accumulated in the second capacitor 106, the first driving transistor 1001 and the second driving transistor 1002 The driving transistor 1002 is turned on. At this time, an L voltage is input to the first power supply line. Therefore, a voltage of H is applied to the first electrode of the second light-emitting element 104, and a voltage of L is applied to the second electrode of the second light-emitting element 104. The second light-emitting element 104 emits light when current flows in the direction of the dotted arrow illustrated in FIG. That is, a forward bias voltage is applied to the second light emitting element 104.

  In addition, an H potential is input to the first electrode of the first light-emitting element 103, and an L voltage is input to the second electrode. That is, a reverse bias voltage is applied to the first light emitting element 103 from the second electrode side to the first electrode side. Therefore, it is possible to periodically relieve the bias of the light-emitting element, and it is possible to achieve the reliability and long life of the other light-emitting element while emitting light from one light-emitting element.

  Next, the state (signal holding period) of FIG. By setting the scanning line gate to the L potential, the selection transistor 101 is turned off. The second capacitor 106 holds a voltage for turning on the first driving transistor 1001 and the second driving transistor 1002, and the second light-emitting element 104 can hold a light-emitting state. it can.

  FIG. 12D illustrates a scanning line gate, a data line sig, a first power supply line com1, and a second line in each stage (initial state, signal input period, signal holding period) of FIGS. It is a timing chart of each voltage of power supply line com2. As shown in FIG. 12D, by controlling the potential of each wiring, the light emission of the light emitting element and the operation of applying the reverse bias voltage can be controlled at the same time. In FIG. 12D, the hatched section of the potential on the data line sig is an indefinite value section (Don't care) in which the potential may be H or L.

  Note that the potential held in the first capacitor element 105 and the second capacitor element 106 for turning on the first driver transistor 1001 and the second driver transistor 1002 is erased from the scan line gate. It is good also as a structure which inputs a signal.

  Note that this embodiment can be implemented in free combination with the description of the other embodiments in this specification. Since the number of transistors constituting the pixel and the number of wiring lines such as scanning lines and power supply lines connected to each pixel can be reduced and an increase in aperture ratio can be expected, it is applied to a light emitting element for maintaining a desired luminance. Voltage can be suppressed and low power consumption can be achieved. In the light-emitting device of the present invention, in a pixel adjacent to a region provided at each intersection of the scan line and the data line, a forward bias voltage is applied to one pixel to cause the light-emitting element to emit light, and the other pixel is The reverse bias voltage can be applied simultaneously. Therefore, since it is not necessary to provide a reverse bias voltage application time, it is possible to control the deterioration of the light emitting element and improve the reliability without reducing the duty ratio (the ratio of the lighting period in one frame period).

  Further, in the light emitting device of the present invention, by adopting a method (interlace method) that sequentially emits pixels every other row in the data line extending direction or the scanning line extending direction. It is possible to reduce the visual recognition of the pseudo contour, which is a problem when the image is displayed by the gradation method. In addition, the pixels are sequentially turned on every two pixels in each row, and in the next row, the pixels are turned on by shifting one pixel in the data line extending direction from the pixel in which the pixel is lit in the previous row. By adopting a method of performing light emission (checker method), the visual recognition of the pseudo contour can be reduced.

(Embodiment 3)
In the above embodiment, an erasing transistor for erasing the potential held in the first capacitor and the second capacitor may be provided. The specific configuration will be described below.

  FIG. 13 is a circuit diagram in which the pixel portions of this embodiment are arranged in a matrix. FIG. 14A shows an enlarged circuit configuration of a pixel portion in this embodiment mode. A region 100 which is a pixel portion illustrated in FIG. 13 includes a first pixel pix1 and a second pixel pix2. Further, the enlarged region 100 shown in FIGS. 13 and 14A includes a scanning line gate1, an erasing line gate2, a data line sig, a first power supply line com1, and a second power supply line com2. ,have.

  In FIG. 14A, the pixel portion includes a selection transistor 101, a first driving transistor 1001, a second driving transistor 1002, an erasing transistor 1401, a first light-emitting element 103, and a second light-emitting element 104. , The first capacitor element 105 and the second capacitor element 106.

  One of the source and drain of the selection transistor 101 is connected to the data line sig, and the other is connected to the gate of the first driving transistor 1001 and the gate of the second driving transistor 1002. One of the source and the drain of the erasing transistor 1401 is connected to one electrode of the first capacitor 105, and the other is connected to the erasing line gate2. The gate of the erasing transistor 1401 is connected to the erasing line gate2. In addition, one electrode of the first capacitor 105 is connected to the gate of the first driving transistor 1001, and the other electrode is connected to the first power supply line com1. In addition, one electrode of the second capacitor 106 is connected to the gate of the second driving transistor 1002 and the other electrode is connected to the second power supply line com2.

  Note that the erasing transistor 1401 uses an erasing diode 1402 having a configuration in which the first electrode is connected to the erasing line gate2 and the second electrode is connected to the first capacitor element 105 and the second capacitor element. It may be. FIG. 14B shows a structure in the case where the erasing transistor 1401 used in FIG. 14A is replaced with an erasing diode 1402. In this case, the erasing diode 1402 has rectification characteristics in the direction from the first electrode to the second electrode. The erasing diode may be anything as long as it has a rectifying property. It may be a PN type diode, a PIN type diode, a Schottky type diode, or a Zener type diode.

  In addition, the first electrode included in the first light-emitting element 103 is connected to either the source or the drain of the first driving transistor 1001, and the second electrode included in the first light-emitting element 103 is the second electrode. Connected to the power supply line com2. The first electrode included in the second light-emitting element 104 is connected to either the source or the drain of the driving transistor, and the second electrode included in the second light-emitting element 104 is connected to the first power supply line com1. It is connected to the. The first power supply line com1 is connected to the electrode that is not connected to the first light emitting element 103 among the source electrode and the drain electrode of the first driving transistor 1001. The second power supply line com2 is connected to the source and drain of the second driving transistor 1002 which are not connected to the first light emitting element 104.

  Note that in this embodiment mode, the first light-emitting element 103 emits light when current flows from the first electrode to the second electrode. In the second light-emitting element 104, light is emitted when a current flows from the first electrode to the second electrode. Note that the polarity of the first electrode is opposite to the polarity of the second electrode.

  Note that the first capacitor and the second capacitor for holding a video signal input to the gates of the first driver transistor and the second driver transistor are the first driver transistor and the second capacitor, respectively. A capacitive element may be disposed between the gate of the driving transistor and another wiring (such as a dedicated wiring or a gate signal line of a pixel in the previous stage). Note that in this embodiment mode, the selection transistor 101 and the erasing transistor 1401 are n-channel transistors, and the driving transistor is a p-channel transistor. However, it is not limited to this.

  Next, an operation method of the pixel structure of this embodiment mode illustrated in FIG. 14A will be specifically described.

  FIG. 15 is a diagram showing a potential of each wiring and a timing chart when the first light-emitting element 103 is selected to emit light for the pixel of this embodiment mode.

  The state (initial state) in FIG. 15A will be described. A high potential (hereinafter abbreviated as H) or a low potential (hereinafter abbreviated as L) is input to the data line sig, an H potential is input to the first power supply line com1, and the second power supply An L potential is input to the line com2.

  Next, the state shifts to the state (signal input period) in FIG. Here, the data line sig is set to the L potential. In order to turn on the selection transistor 101, an H potential is input to the scanning line gate1. When the selection transistor 101 is turned on, the potential of L from the data line sig is input to one electrode of the first capacitor element 105 and the second capacitor element 106 in pix1 and pix2. The other electrode of the first capacitor 105 is input with H which is the potential of the first power supply line com 1, and charges are accumulated in the first capacitor 105. In addition, since the L potential is input from the second power supply line com2 to the other electrode of the second capacitor element 106, the potential difference applied to the two electrodes in the second capacitor element 106 becomes the same potential difference, and the charge Is not accumulated.

  By applying an L voltage to the gates of the first driving transistor 1001 and the second driving transistor from the electric charge accumulated in the first capacitor 105, the first driving transistor 1001 and the second driving transistor 1001 The driving transistor is turned on. At this time, an L voltage is input to the second power supply line. Therefore, a voltage of H is applied to the first electrode of the first light-emitting element 103, and a voltage of L is applied to the second electrode of the first light-emitting element 103. The first light-emitting element 103 emits light when current flows in the direction of the dotted arrow illustrated in FIG. That is, a forward bias voltage is applied to the first light emitting element 103.

  In addition, when the second driving transistor 1002 is turned on, an L potential is input to the first electrode of the second light-emitting element 104, and an H voltage is input to the second electrode. That is, a reverse bias voltage is applied to the second light emitting element 104 from the second electrode side to the first electrode side. Therefore, it is possible to periodically alleviate the unevenness of the charge of the light emitting element, and it is possible to achieve reliability and long life of the light emitting element while emitting light from the light emitting element.

  Next, the state (signal holding period) shown in FIG. The selection transistor 101 is turned off by setting the scanning line gate1 to the L potential. The first capacitor 105 holds a voltage for turning on the first driving transistor 1001 and the second driving transistor 1002, and the first light-emitting element 103 can hold a light-emitting state. it can.

  Next, the state (signal erasure period) of FIG. The erase transistor 1401 is turned on by setting the potential of the erase line gate2 to H. Then, an H potential is input from the erase line gate2, and the L charge held in the first capacitor element 105 is discharged. Further, an H potential is applied to one electrode of the second capacitor element from the erase line gate2, and an L potential is applied to the other electrode of the second capacitor element 106 from the second power supply line com2. As a result, charges are accumulated in the second capacitor element 106. When the second capacitor 106 is charged, a voltage of H is applied to the gates of the first driving transistor 1001 and the second driving transistor 1002, but the first driving transistor 1001 and the second driving transistor 1002 Since the driving transistor 1002 is a P-channel type, it is not turned on. As a result, the charge for turning on the first driver transistor 1001 and the second driver transistor 1002 held in the first capacitor element 105 and the second capacitor element can be erased, and the first capacitor element 105 can be erased. Light emission / non-light emission of the light emitting element and the second light emitting element can be controlled.

  FIG. 15E shows the scanning line gate1, the erasing line gate2, the data line sig, and the first line in each stage (initial state, signal input period, signal holding period, signal erasing period) of FIGS. 6 is a timing chart of each voltage of a power supply line com1 and a second power supply line com2. As shown in FIG. 15E, by controlling the potential of each wiring, the light emission of the light emitting element and the operation of applying the reverse bias voltage can be controlled simultaneously. In FIG. 15E, the hatched section of the potential in the data line sig is an indefinite value section where the potential may be H or L.

  Next, FIG. 16 is a diagram illustrating a voltage of each wiring and a timing chart when the second light-emitting element 104 is selected to emit light with respect to the pixel of this embodiment mode.

  The state (initial state) in FIG. 16A will be described. An L potential is input to the data line sig, an L potential is input to the first power supply line com1, and an H potential is input to the second power supply line com2.

  Next, the state (signal input period) in FIG. In order to turn on the selection transistor 101, an H potential is input to the scanning line gate. When the selection transistor 101 is turned on, an L potential is input to one electrode of the first capacitor element 105 and the second capacitor element 106 in pix1 and pix2. At the other electrode of the first capacitor 105, an L potential is input from the first power supply line com1, and the potential difference applied to the two electrodes in the first capacitor 105 becomes the same potential difference. Not done. The other electrode of the second capacitor 106 is input with H which is the potential of the second power supply line com 2, and charges are accumulated in the second capacitor 106.

  By applying an L voltage to the gates of the first driving transistor 1001 and the second driving transistor 1002 from the electric charge accumulated in the second capacitor 106, the first driving transistor 1001 and the second driving transistor 1002 The driving transistor 1002 is turned on. At this time, an L voltage is input to the first power supply line. Therefore, a voltage of H is applied to the first electrode of the second light-emitting element 104, and a voltage of L is applied to the second electrode of the second light-emitting element 104. The second light-emitting element 104 emits light when current flows in the direction of the dotted arrow illustrated in FIG.

  In addition, an H potential is input to the first electrode of the first light-emitting element 103, and an L voltage is input to the second electrode. That is, a reverse bias voltage is applied to the first light emitting element 103 from the second electrode side to the first electrode side. Therefore, it is possible to periodically alleviate the unevenness of the charge of the light emitting element, and it is possible to achieve reliability and long life of the light emitting element while emitting light from the light emitting element.

  Next, the state (signal holding period) of FIG. By setting the scanning line gate to the L potential, the selection transistor 101 is turned off. The second capacitor 106 holds a voltage for turning on the first driving transistor 1001 and the second driving transistor 1002, and the second light-emitting element 104 can hold a light-emitting state. it can.

  Next, the state (signal erasure period) shown in FIG. The erase transistor 1401 is turned on by setting the potential of the erase line gate2 to H. Then, an H potential is input from the erase line gate 2, an H potential is input to one electrode of the first capacitor 105, and the first power supply line com 1 is input to the other electrode of the first capacitor 105. When a further potential of L is input, electric charge is accumulated in the first capacitor 105. Further, the other electrode of the second capacitor element 106 is applied with an H potential from the erase line gate2, and the other electrode of the second capacitor element 106 is applied with an H potential from the second power supply line com2. By being applied, the second capacitor element 106 does not hold a charge. When the first capacitor 105 is charged, a voltage of H is applied to the gates of the first driving transistor 1001 and the second driving transistor 1002, but the first driving transistor 1001 and the second driving transistor 1002 Since the driving transistor 1002 is a P-channel type, it is not turned on. As a result, the charge for turning on the first driving transistor 1001 and the second driving transistor 1002 held in the first capacitor 105 and the second capacitor 106 can be erased, and the first The light emission / non-light emission of the light emitting element and the second light emitting element can be controlled.

  FIG. 16E shows a scanning line gate1, an erasing line gate2, a data line sig, and a first line in each stage (initial state, signal input period, signal holding period, signal erasing period) of FIGS. 6 is a timing chart of each voltage of a power supply line com1 and a second power supply line com2. As shown in FIG. 16E, by controlling the potential of each wiring, the light emission of the light emitting element and the operation of applying the reverse bias voltage can be controlled simultaneously. In FIG. 16E, the hatched section of the potential in the data line sig is an indefinite value section where the potential may be H or L.

  Note that this embodiment can be implemented in free combination with the description of the other embodiments in this specification. That is, the number of transistors constituting the pixel and the number of wiring lines such as scanning lines and power supply lines connected to each pixel can be reduced, and an increase in the aperture ratio can be expected. Therefore, a light-emitting element for maintaining desired luminance can be obtained. The applied voltage can be suppressed, and low power consumption can be achieved. In the light-emitting device of the present invention, in a pixel adjacent to a region provided at each intersection of the scan line and the data line, a forward bias voltage is applied to one pixel to cause the light-emitting element to emit light, and the other pixel is The reverse bias voltage can be applied simultaneously. Therefore, it is not necessary to provide an application time of the reverse bias voltage, so that deterioration of the light emitting element can be controlled and reliability can be improved without reducing the duty ratio (the ratio of the lighting period in one frame period).

  Further, in the light emitting device of the present invention, by adopting a method (interlace method) that sequentially emits pixels every other row in the data line extending direction or the scanning line extending direction. It is possible to reduce the visual recognition of the pseudo contour, which is a problem when the image is displayed by the gradation method. In addition, the pixels are sequentially turned on every two pixels in each row, and in the next row, the pixels are turned on by shifting one pixel in the data line extending direction from the pixel in which the pixel is lit in the previous row. By adopting a method of performing light emission (checker method), the visual recognition of the pseudo contour can be reduced.

(Embodiment 4)
In this embodiment, an example in which an image is displayed by causing the first pixel and the second pixel in the light-emitting device of the present invention to emit light by a method different from the interlace method described in Embodiment 1 will be described.

  FIG. 17 shows a pixel portion of a light-emitting device in which semiconductor elements are arranged in a matrix. Display pixels are shown in white and non-display pixels are shown in black. In such a pixel portion, in the first frame, only odd row / odd column pixels and even row / even column pixels are displayed (see FIG. 17A), and in the second frame, odd rows are displayed. Only the pixels in even columns and the pixels in even rows and odd columns are displayed (see FIG. 17B). That is, a display area and a non-display area are provided in a lattice shape in the pixel portion.

  In the present embodiment, the first pixels pix1 are arranged in odd-numbered and odd-numbered pixels, and even-numbered and even-numbered columns, and the second pixels pix2 are arranged in odd-numbered and even-numbered columns, and even-numbered rows, What is necessary is just to arrange | position to an odd number column. Of course, the first pixel pix1 and the second pixel pix2 may be interchanged.

  In the present embodiment, the first frame is represented as an odd frame, and the second frame is represented as an even frame.

  In the pixel portion of the present embodiment, only odd-numbered / even-numbered pixels and even-numbered / odd-numbered pixels are displayed in odd-numbered frames, and odd-numbered / odd-numbered pixels and even-numbered rows in even-numbered frames. -Only even columns of pixels may be displayed.

  FIG. 18 shows a timing chart for performing such display. FIG. 18A shows a scanning line start pulse (GSP), a scanning line clock signal (GCK), and an inversion signal (SW) for selecting a scanning line in the row direction in an odd-numbered frame. In addition, a start pulse (SSP) and a start clock signal (SCK) for selecting the scanning lines in the column direction in the odd and even rows are shown. These signals indicate the timing of the video signal (DATA) to be written.

  FIG. 18B shows a timing chart in an even-numbered frame. The SW signal is inverted from that in FIG. 18A, and other timings are the same.

  In the odd-numbered frame, when the SW signal is High, odd-numbered columns of pixels are selected, and when the SW signal is Low, even-numbered columns of pixels are selected. In the even frame, even column pixels are selected when the SW signal is High, and odd column pixels are selected when the SW signal is High.

  The video signal (DATA) is input after the SSP signal is input, and is input to the selected pixel. Note that the selected pixel is a pixel having a semiconductor element connected to the selected scanning line.

  As described above, the pixels are sequentially turned on every two pixels in each row, and in the next row, the pixels are turned on by shifting one pixel in the data line extending direction from the pixel in which the pixel is lit in the previous row. The lighting and non-lighting of pixels can be selected in a pattern.

  By adopting the structure of this embodiment mode, in the light-emitting device that performs time-division gradation, generation of a stripe pattern can be reduced and generation of a pseudo contour can be reduced as compared with an interlace method.

  When applied to a pixel configuration in which the number of transistors is reduced and the aperture ratio is increased as in the pixel configuration of the light-emitting device of the present invention, the effect of the present invention is synergistic by displaying using the checker method of this embodiment. And is suitable.

  If the checker method is used, there is a concern about a decrease in luminance. However, if an organic material is used for the light-emitting element of the matrix light-emitting device, the light-emitting element exponentially decreases in luminance. Therefore, there is no problem because the supply voltage is improved with the decrease in luminance. That is, the checker method is very suitable for use in the light emitting device of the present invention including a light emitting element having an organic material.

  Note that this embodiment can be implemented in free combination with the description of the other embodiments in this specification. That is, the number of transistors constituting the pixel and the number of wiring lines such as scanning lines and power supply lines connected to each pixel can be reduced, and an increase in aperture ratio can be expected. Therefore, a light-emitting element for maintaining desired luminance can be obtained. The applied voltage can be suppressed, and low power consumption can be achieved. In the light emitting device of the present invention, a forward bias voltage is applied to one of the pixels adjacent to a region provided at each intersection of the scanning line and the data line so that the light emitting element emits light. The reverse bias voltage can be applied simultaneously. Therefore, it is not necessary to provide an application time of the reverse bias voltage, so that deterioration of the light emitting element can be controlled and reliability can be improved without reducing the duty ratio (the ratio of the lighting period in one frame period).

(Embodiment 5)
In this embodiment, a cross-sectional structure of a pixel having a light-emitting element will be described. A cross-sectional structure of a pixel in the case where a transistor for controlling current supply to the light-emitting element as described above is a p-type thin film transistor (TFT) will be described with reference to FIGS. Note that in this embodiment mode, of two electrodes of an anode and a cathode included in a light-emitting element, one electrode whose potential can be controlled by a transistor is a first electrode, and the other electrode is a second electrode. In FIG. 19, the case where the first electrode is an anode and the second electrode is a cathode is described. However, the first electrode may be a cathode and the second electrode may be an anode.

  FIG. 19A is a cross-sectional view of a pixel in the case where the TFT 6001 is a p-type and light emitted from the light-emitting element 6003 is extracted from the first electrode 6004 side. In FIG. 19A, the first electrode 6004 of the light-emitting element 6003 and the TFT 6001 are electrically connected.

  The TFT 6001 is covered with an interlayer insulating film 6007, and a partition wall 6008 having an opening is formed over the interlayer insulating film 6007. A part of the first electrode 6004 is exposed in the opening of the partition wall 6008, and the first electrode 6004, the electroluminescent layer 6005, and the second electrode 6006 are sequentially stacked in the opening.

  The interlayer insulating film 6007 is formed using an organic resin film, an inorganic insulating film, or an insulating film including a Si—O—Si bond (hereinafter referred to as a siloxane-based insulating film) formed using a siloxane-based material as a starting material. Can do. The siloxane-based insulating film has hydrogen as a substituent and can have at least one of fluorine, an alkyl group, and aromatic hydrocarbon. A material called a low dielectric constant material (low-k material) may be used for the interlayer insulating film 6007.

  The partition wall 6008 can be formed using an organic resin film, an inorganic insulating film, or a siloxane-based insulating film. For example, acrylic resin, polyimide, polyamide, or the like can be used for the organic resin film, and silicon oxide, silicon nitride oxide, or the like can be used for the inorganic insulating film. In particular, a photosensitive organic resin film is used for the partition wall 6008, an opening is formed on the first electrode 6004, and the side wall of the opening is formed as an inclined surface formed with a continuous curvature. Thus, the connection between the first electrode 6004 and the second electrode 6006 can be prevented.

  The first electrode 6004 is formed using a light-transmitting material or film thickness, and is formed using a material suitable for use as an anode. For example, another light-transmitting oxide conductive material such as indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), or zinc oxide added with gallium (GZO) is used for the first electrode 6004. Is possible. In addition, indium tin oxide containing ITO and silicon oxide (hereinafter referred to as ITSO), or indium oxide containing silicon oxide mixed with 2 to 20% zinc oxide (ZnO) is used as the first electrode 6004. It may be used. In addition to the light-transmitting oxide conductive material, for example, a single layer film made of one or more of TiN, ZrN, Ti, W, Ni, Pt, Cr, Ag, Al, etc., titanium nitride and aluminum are used. The first electrode 6004 can be formed using a stack including a main component film, a three-layer structure including a titanium nitride film, an aluminum main component film, and a titanium nitride film. Note that in the case where a material other than the light-transmitting oxide conductive material is used, the first electrode 6004 is formed with a thickness enough to transmit light (preferably, about 5 nm to 30 nm).

  The second electrode 6006 can be formed using a material and a film thickness that reflect or shield light, and can be formed using a metal, an alloy, an electrically conductive compound, a mixture thereof, or the like with a low work function. Specifically, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, and Sr, alloys containing these (Mg: Ag, Al: Li, Mg: In, etc.), and compounds thereof ( In addition to calcium fluoride and calcium nitride, rare earth metals such as Yb and Er can be used. When an electron injection layer is provided, other conductive layers such as Al can be used.

  The electroluminescent layer 6005 is composed of one or more layers. When composed of a plurality of layers, these layers can be classified into a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, an electron injection layer, and the like from the viewpoint of carrier transport properties. In the case where the electroluminescent layer 6005 includes any of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer in addition to the light emitting layer, the first electrode 6004 to the positive hole injection layer, A hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer are laminated in this order. Note that the boundaries between the layers are not necessarily clear, and there are cases where the materials constituting the layers are partially mixed and the interface is unclear. For each layer, an organic material or an inorganic material can be used. As the organic material, any of a high molecular weight material, a medium molecular weight material, and a low molecular weight material can be used. The medium molecular weight material corresponds to a low polymer having a number of repeating structural units (degree of polymerization) of about 2 to 20. The distinction between a hole injection layer and a hole transport layer is not necessarily strict, and these are the same in the sense that hole transportability (hole mobility) is a particularly important characteristic. For convenience, the hole injection layer is a layer in contact with the anode, and the layer in contact with the hole injection layer is referred to as a hole transport layer to be distinguished. The same applies to the electron transport layer and the electron injection layer. The layer in contact with the cathode is called an electron injection layer, and the layer in contact with the electron injection layer is called an electron transport layer. The light emitting layer may also serve as an electron transport layer, and is also referred to as a light emitting electron transport layer.

  In the case of the pixel shown in FIG. 19A, light emitted from the light-emitting element 6003 can be extracted from the first electrode 6004 side as shown by a hollow arrow.

  Next, FIG. 19B is a cross-sectional view of a pixel in the case where the TFT 6011 is p-type and light emitted from the light-emitting element 6013 is extracted from the second electrode 6016 side. In FIG. 19B, the first electrode 6014 of the light-emitting element 6013 and the TFT 6011 are electrically connected. In addition, an electroluminescent layer 6015 and a second electrode 6016 are sequentially stacked over the first electrode 6014.

  The first electrode 6014 is formed using a material and a film thickness that reflect or shield light, and is formed using a material that is suitable for use as an anode. For example, in addition to a single layer film made of one or more of TiN, ZrN, Ti, W, Ni, Pt, Cr, Ag, Al, etc., a laminate of titanium nitride and a film containing aluminum as a main component, a titanium nitride film A three-layer structure of a film mainly containing aluminum and aluminum and a titanium nitride film can be used for the first electrode 6014.

  The second electrode 6016 can be formed using a light-transmitting material or film thickness, and can be formed using a metal, an alloy, an electrically conductive compound, a mixture thereof, or the like with a low work function. Specifically, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, and Sr, alloys containing these (Mg: Ag, Al: Li, Mg: In, etc.), and compounds thereof ( In addition to calcium fluoride and calcium nitride, rare earth metals such as Yb and Er can be used. When an electron injection layer is provided, other conductive layers such as Al can be used. Then, the second electrode 6016 is formed with a thickness enough to transmit light (preferably, about 5 nm to 30 nm). Note that other light-transmitting oxide conductive materials such as indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), and zinc oxide to which gallium is added (GZO) can also be used. Alternatively, indium tin oxide containing ITO and silicon oxide (hereinafter referred to as ITSO) or indium oxide containing silicon oxide mixed with 2 to 20% zinc oxide (ZnO) may be used. In the case of using a light-transmitting oxide conductive material, it is preferable to provide an electron injection layer in the electroluminescent layer 6015.

  The electroluminescent layer 6015 can be formed in a manner similar to that of the electroluminescent layer 6005 in FIG.

  In the case of the pixel shown in FIG. 19B, light emitted from the light-emitting element 6013 can be extracted from the second electrode 6016 side as shown by a hollow arrow.

Next, FIG. 19C is a cross-sectional view of a pixel in the case where the TFT 6021 is p-type and light emitted from the light-emitting element 6023 is extracted from the first electrode 6024 side and the second electrode 6026 side. In FIG. 19C, the first electrode 6024 of the light-emitting element 6023 and the TFT 6021 are electrically connected. Further, an electroluminescent layer 6025 and a second electrode 6026 are sequentially stacked over the first electrode 6024.

The first electrode 6024 can be formed in a manner similar to that of the first electrode 6004 in FIG. The second electrode 6026 can be formed in a manner similar to that of the second electrode 6016 in FIG. The electroluminescent layer 6025 can be formed in a manner similar to that of the electroluminescent layer 6005 in FIG.

In the case of the pixel shown in FIG. 19C, light emitted from the light-emitting element 6023 can be extracted from the first electrode 6024 side and the second electrode 6026 side as indicated by white arrows.

This embodiment can be implemented in free combination with the description of the other embodiments in this specification. That is, the number of transistors constituting the pixel and the number of wiring lines such as scanning lines and power supply lines connected to each pixel can be reduced, and an increase in aperture ratio can be expected. Therefore, a light-emitting element for maintaining desired luminance can be obtained. The applied voltage can be suppressed, and low power consumption can be achieved. In the light emitting device of the present invention, a forward bias voltage is applied to one of the pixels adjacent to a region provided at each intersection of the scanning line and the data line so that the light emitting element emits light. The reverse bias voltage can be applied simultaneously. Therefore, it is not necessary to provide an application time of the reverse bias voltage, so that deterioration of the light emitting element can be controlled and reliability can be improved without reducing the duty ratio (the ratio of the lighting period in one frame period).

  Further, in the light emitting device of the present invention, by adopting a method (interlace method) that sequentially emits pixels every other row in the data line extending direction or the scanning line extending direction. It is possible to reduce the visual recognition of the pseudo contour, which is a problem when the image is displayed by the gradation method. In addition, the pixels are sequentially turned on every two pixels in each row, and in the next row, the pixels are turned on by shifting one pixel in the data line extending direction from the pixel in which the pixel is lit in the previous row. By adopting a method of performing light emission (checker method), the visual recognition of the pseudo contour can be reduced.

(Embodiment 6)
In this embodiment, a cross-sectional structure of a pixel in the case where an n-type TFT is used as a transistor for controlling current supply to a light-emitting element will be described with reference to FIGS. Note that although FIG. 20 illustrates the case where the first electrode is a cathode and the second electrode is an anode, the first electrode may be an anode and the second electrode may be a cathode.

  FIG. 20A is a cross-sectional view of a pixel in the case where the TFT 6031 is n-type and light emitted from the light-emitting element 6033 is extracted from the first electrode 6034 side. In FIG. 20A, the first electrode 6034 of the light-emitting element 6033 and the TFT 6031 are electrically connected. Further, an electroluminescent layer 6035 and a second electrode 6036 are sequentially stacked over the first electrode 6034.

  The first electrode 6034 can be formed using a light-transmitting material or film thickness, and can be formed using a metal, an alloy, an electrically conductive compound, a mixture thereof, or the like with a low work function. Specifically, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, and Sr, alloys containing these (Mg: Ag, Al: Li, Mg: In, etc.), and compounds thereof ( In addition to calcium fluoride and calcium nitride, rare earth metals such as Yb and Er can be used. When an electron injection layer is provided, other conductive layers such as Al can be used. Then, the first electrode 6034 is formed with a thickness enough to transmit light (preferably, about 5 nm to 30 nm). Further, a light-transmitting conductive layer is formed using a light-transmitting oxide conductive material so as to be in contact with or under the conductive layer having a thickness enough to transmit light, and the first electrode 6034 is formed. The sheet resistance may be suppressed. Note that only conductive layers using other light-transmitting oxide conductive materials such as indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), and zinc oxide added with gallium (GZO) should be used. Is also possible. Alternatively, indium tin oxide containing ITO and silicon oxide (hereinafter referred to as ITSO) or indium oxide containing silicon oxide mixed with 2 to 20% zinc oxide (ZnO) may be used. In the case of using a light-transmitting oxide conductive material, it is preferable to provide an electron injection layer in the electroluminescent layer 6035.

  The second electrode 6036 is formed of a material and a film thickness that reflect or shield light, and is formed using a material that is suitable for use as an anode. For example, in addition to a single layer film made of one or more of TiN, ZrN, Ti, W, Ni, Pt, Cr, Ag, Al, etc., a laminate of titanium nitride and a film containing aluminum as a main component, a titanium nitride film A three-layer structure of a film containing aluminum and aluminum as main components and a titanium nitride film can be used for the second electrode 6036.

  The electroluminescent layer 6035 can be formed in a manner similar to that of the electroluminescent layer 6005 in FIG. However, in the case where the electroluminescent layer 6035 includes any one of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer in addition to the light emitting layer, the first electrode 6034 to the electron injection layer The electron transport layer, the light emitting layer, the hole transport layer, and the hole injection layer are laminated in this order.

  In the case of the pixel shown in FIG. 20A, light emitted from the light-emitting element 6033 can be extracted from the first electrode 6034 side as shown by a hollow arrow.

  Next, FIG. 20B is a cross-sectional view of a pixel in the case where the TFT 6041 is an n-type and light emitted from the light-emitting element 6043 is extracted from the second electrode 6046 side. In FIG. 20B, the first electrode 6044 of the light-emitting element 6043 and the TFT 6041 are electrically connected. Further, an electroluminescent layer 6045 and a second electrode 6046 are sequentially stacked over the first electrode 6044.

  The first electrode 6044 can be formed using a material and a film thickness that reflect or shield light, and can be formed using a metal, an alloy, an electrically conductive compound, a mixture thereof, or the like with a low work function. Specifically, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, and Sr, alloys containing these (Mg: Ag, Al: Li, Mg: In, etc.), and compounds thereof ( In addition to calcium fluoride and calcium nitride, rare earth metals such as Yb and Er can be used. When an electron injection layer is provided, other conductive layers such as Al can be used.

  The second electrode 6046 is formed using a light-transmitting material or film thickness, and is formed using a material suitable for use as an anode. For example, another light-transmitting oxide conductive material such as indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), or zinc oxide added with gallium (GZO) is used for the second electrode 6046. Is possible. Alternatively, indium tin oxide containing ITO and silicon oxide, or indium oxide containing silicon oxide mixed with 2 to 20% zinc oxide (ZnO) may be used for the second electrode 6046. In addition to the light-transmitting oxide conductive material, for example, a single layer film made of one or more of TiN, ZrN, Ti, W, Ni, Pt, Cr, Ag, Al, etc., titanium nitride and aluminum are used. The second electrode 6046 can be formed using a stack of a main component film, a three-layer structure including a titanium nitride film, an aluminum main component film, and a titanium nitride film. Note that in the case where a material other than the light-transmitting oxide conductive material is used, the second electrode 6046 is formed with a thickness enough to transmit light (preferably, about 5 nm to 30 nm).

  The electroluminescent layer 6045 can be formed in a manner similar to that of the electroluminescent layer 6035 in FIG.

  In the case of the pixel shown in FIG. 20B, light emitted from the light-emitting element 6043 can be extracted from the second electrode 6046 side as shown by a hollow arrow.

  Next, FIG. 20C is a cross-sectional view of a pixel in the case where the TFT 6051 is an n-type and light emitted from the light-emitting element 6053 is extracted from the first electrode 6054 side and the second electrode 6056 side. In FIG. 20C, the first electrode 6054 of the light-emitting element 6053 and the TFT 6051 are electrically connected. Further, an electroluminescent layer 6055 and a second electrode 6056 are stacked over the first electrode 6054 in this order.

  The first electrode 6054 can be formed in a manner similar to that of the first electrode 6034 in FIG. The second electrode 6056 can be formed in a manner similar to that of the second electrode 6046 in FIG. The electroluminescent layer 6055 can be formed in a manner similar to that of the electroluminescent layer 6035 in FIG.

  In the case of the pixel shown in FIG. 20C, light emitted from the light-emitting element 6053 can be extracted from the first electrode 6054 side and the second electrode 6056 side as indicated by white arrows.

  This embodiment can be implemented in free combination with the description of the other embodiments in this specification. That is, the number of transistors constituting the pixel and the number of wiring lines such as scanning lines and power supply lines connected to each pixel can be reduced, and an increase in aperture ratio can be expected. Therefore, a light-emitting element for maintaining desired luminance can be obtained. The applied voltage can be suppressed, and low power consumption can be achieved. In the light emitting device of the present invention, a forward bias voltage is applied to one of the pixels adjacent to a region provided at each intersection of the scanning line and the data line so that the light emitting element emits light. The reverse bias voltage can be applied simultaneously. Therefore, it is not necessary to provide an application time of the reverse bias voltage, so that deterioration of the light emitting element can be controlled and reliability can be improved without reducing the duty ratio (the ratio of the lighting period in one frame period).

Further, in the light emitting device of the present invention, by adopting a method (interlace method) that sequentially emits pixels every other row in the data line extending direction or the scanning line extending direction. It is possible to reduce the visual recognition of the pseudo contour, which is a problem when the image is displayed by the gradation method. In addition, the pixels are sequentially turned on every two pixels in each row, and in the next row, the pixels are turned on by shifting one pixel in the data line extending direction from the pixel in which the pixel is lit in the previous row. By adopting a method of performing light emission (checker method), the visual recognition of the pseudo contour can be reduced.
(Embodiment 7)
In this embodiment, the appearance of a panel corresponding to one embodiment of the light-emitting device of the present invention will be described with reference to FIGS. FIG. 21A is a top view of a panel in which a transistor and a light-emitting element formed over the first substrate are sealed with a sealant between the second substrate and FIG. 21B. 21 corresponds to a cross-sectional view taken along line AA ′ of FIG.

  A sealant 4020 is provided so as to surround the pixel portion 4002, the signal line driver circuit 4003, the first scan line driver circuit 4004, and the second scan line driver circuit 4005 provided over the first substrate 4001. It has been. In addition, a second substrate 4006 is provided over the pixel portion 4002, the signal line driver circuit 4003, the first scan line driver circuit 4004, and the second scan line driver circuit 4005. Therefore, the pixel portion 4002, the signal line driver circuit 4003, the first scan line driver circuit 4004, and the second scan line driver circuit 4005 include the first substrate 4001, the sealant 4020, and the second substrate 4006. Is sealed together with the filler 4007.

  Further, the pixel portion 4002, the signal line driver circuit 4003, the first scan line driver circuit 4004, and the second scan line driver circuit 4005 provided over the first substrate 4001 each include a plurality of transistors. FIG. 21B illustrates a transistor 4008 included in the signal line driver circuit 4003, and a driving transistor 4009 and a switching transistor 4010 included in the pixel portion 4002.

  Reference numeral 4011 corresponds to a light-emitting element, and a part of the wiring 4017 connected to the drain of the driving transistor 4009 functions as a first electrode of the light-emitting element 4011. The transparent conductive film functions as the second electrode 4012 of the light-emitting element 4011. Note that the structure of the light-emitting element 4011 is not limited to the structure described in this embodiment. The structure of the light-emitting element 4011 can be changed as appropriate depending on the direction of light extracted from the light-emitting element 4011, the polarity of the driving transistor 4009, or the like.

  Various signals and voltages supplied to the signal line driver circuit 4003, the first scan line driver circuit 4004, the second scan line driver circuit 4005, or the pixel portion 4002 are not shown in the cross-sectional view in FIG. Although not provided, it is supplied from the connection terminal 4016 via the lead wirings 4014 and 4015.

  In this embodiment, the connection terminal 4016 is formed using the same conductive film as the second electrode 4012 included in the light-emitting element 4011. The lead wiring 4014 is formed from the same conductive film as the wiring 4017. The lead wiring 4015 is formed of the same conductive film as the gates of the driving transistor 4009, the switching transistor 4010, and the transistor 4008.

  The connection terminal 4016 is electrically connected to a terminal included in the FPC 4018 through an anisotropic conductive film 4019.

  Note that as the first substrate 4001 and the second substrate 4006, glass, metal (typically stainless steel), ceramics, or plastic can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a mylar film, a polyester film, or an acrylic resin film can be used. A sheet having a structure in which an aluminum foil is sandwiched between PVF films or mylar films can also be used.

  Note that the second substrate 4006 located in the direction in which light is extracted from the light-emitting element 4011 must have a light-transmitting property. Therefore, the second substrate 4006 is formed using a light-transmitting material such as a glass plate, a plastic plate, a polyester film, or an acrylic film.

  As the filler 4007, in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used. PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicon resin, PVB (Polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. In this embodiment, nitrogen is used as the filler.

  In addition, a driver circuit provided in the periphery includes a first scan line driver circuit 4004, a second scan line driver circuit 4005, and a signal line driver circuit 4003 which are connected to the pixel portion by gate wirings and source wirings, respectively.

  Note that the light-emitting device of the present invention includes in its category a panel in which a pixel portion having a light-emitting element is formed and a module in which an IC is mounted on the panel.

  In the panel and module configured as in this embodiment, the reliability of the light-emitting element can be improved by reducing the number of thin film transistors included in the pixels of the display portion and periodically applying a reverse bias to the light-emitting element. In addition, since the number of thin film transistors and the number of wirings constituting the pixel in the display portion can be reduced, an increase in the aperture ratio of the pixel portion can be expected, which can contribute to a reduction in power consumption. Further, a panel and a module that can reduce the layout area of the driver circuit portion around the pixel portion can be obtained.

  This embodiment can be implemented in free combination with the description of the other embodiments in this specification. That is, the number of transistors constituting the pixel and the number of wiring lines such as scanning lines and power supply lines connected to each pixel can be reduced, and an increase in aperture ratio can be expected. Therefore, a light-emitting element for maintaining desired luminance can be obtained. The applied voltage can be suppressed, and low power consumption can be achieved. In the light emitting device of the present invention, a forward bias voltage is applied to one of the pixels adjacent to a region provided at each intersection of the scanning line and the data line so that the light emitting element emits light. The reverse bias voltage can be applied simultaneously. Therefore, it is not necessary to provide an application time of the reverse bias voltage, so that deterioration of the light emitting element can be controlled and reliability can be improved without reducing the duty ratio (the ratio of the lighting period in one frame period).

  Further, in the light emitting device of the present invention, by adopting a method (interlace method) that sequentially emits pixels every other row in the data line extending direction or the scanning line extending direction. It is possible to reduce the visual recognition of the pseudo contour, which is a problem when the image is displayed by the gradation method. In addition, the pixels are sequentially turned on every two pixels in each row, and in the next row, the pixels are turned on by shifting one pixel in the data line extending direction from the pixel in which the pixel is lit in the previous row. By adopting a method of performing light emission (checker method), the visual recognition of the pseudo contour can be reduced.

(Embodiment 8)
In this embodiment, an example of manufacturing an active matrix display device using a channel-etch TFT as a switching element will be described with reference to drawings.

As shown in FIG. 30A, a material layer and a base layer 3011 for improving adhesion are formed over a substrate 3000 by a droplet discharge method to be formed later. The base layer 3011 is not necessarily required to have a layer structure because it may be formed extremely thin. The underlayer 3011 is manufactured by a photocatalytic substance (titanium oxide (TiO _x ), strontium titanate (SrTiO ₃ ), cadmium selenide (CdSe), potassium tantalate (KTaO ₃ ), cadmium sulfide (CdS) by spraying or sputtering. ), Zirconium oxide (ZrO ₂ ), niobium oxide (Nb ₂ O ₅ ), zinc oxide (ZnO), iron oxide (Fe ₂ O ₃ ), and tungsten oxide (WO ₃ ) are formed over the entire surface. Alternatively, an organic material (polyimide, acrylic, or a bond of silicon (Si) and oxygen (O) is used to form a skeletal structure using an inkjet method or a sol-gel method, and the substituent is hydrogen, fluorine, an alkyl group, or an aromatic group. A process of selectively forming a coating insulating film using a material having at least one kind of hydrocarbon may be performed. This can also be regarded as a base pretreatment.

Here, an example of performing base pretreatment for improving adhesion when discharging a conductive material on a substrate is shown. However, a material layer (for example, an organic layer, an inorganic layer, or a metal layer) or discharged conductivity When a material layer (for example, an organic layer, an inorganic layer, or a metal layer) is further formed on the layer by a droplet discharge method, a TiO _X film forming process for improving the adhesion between the material layer and the material layer is performed. May be. That is, when drawing is performed by discharging a conductive material by a droplet discharge method, it is desirable that the base pretreatment is sandwiched between the upper and lower interfaces of the conductive material layer to improve the adhesion.

  The underlayer 3011 is not limited to a photocatalytic material, but a 3d transition metal (Sc, Ti, Cr, Ni, V, Mn, Fe, Co, Cu, Zn, or the like), or an oxide, nitride, or oxynitride thereof. Can be used.

  Note that the substrate 3000 has heat resistance that can withstand the processing temperature of the manufacturing process in addition to an alkali-free glass substrate manufactured by a fusion method or a float method, such as barium borosilicate glass, aluminoborosilicate glass, or aluminosilicate glass. A plastic substrate or the like can be used.

  Next, a conductive film pattern 3012 is formed by dropping a conductive film material liquid by a droplet discharge method, typically an inkjet method. (FIG. 30 (A)) As a conductive material included in the conductive film material liquid, gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), tungsten (W), nickel (Ni), tantalum (Ta), bismuth (Bi), lead (Pb), indium (In), tin (Sn), zinc (Zn), titanium (Ti), or aluminum (Al), an alloy made of these, These dispersible nanoparticles or silver halide fine particles are used. In particular, since it is preferable to reduce the resistance of the gate wiring, it is preferable to use a material in which any of gold, silver, and copper is dissolved or dispersed in a solvent in consideration of the specific resistance value. More preferably, low resistance silver or copper is used. However, when silver or copper is used, it is preferable to provide a barrier film together to prevent impurity diffusion. The solvent corresponds to esters such as butyl acetate, alcohols such as isopropyl alcohol, organic solvents such as acetone, and the like. The surface tension and the viscosity are appropriately adjusted by adjusting the concentration of the solvent or adding a surfactant or the like.

  Here, an example of a droplet discharge device is shown in FIG. In FIG. 31, 3100 is a large substrate, 3104 is an imaging means, 3107 is a stage, 3111 is a marker, and 3103 is an area where one panel is formed. Heads 3105a, 3105b, and 3105c having the same width as that of one panel are provided. The stage is moved, and these heads are scanned, for example, zigzag or reciprocated to appropriately form a pattern of the material layer. Although it is possible to use a head having the same width as that of the large-sized substrate, it is easier to operate by adjusting it to one panel size as shown in FIG. In order to improve the throughput, it is preferable to discharge the material while moving the stage.

  The heads 3105a, 3105b, 3105c and the stage 3107 are preferably provided with a temperature adjustment function. The interval between the head (nozzle tip) and the large substrate is about 1 mm. The landing accuracy can be increased by shortening this interval.

  In FIG. 31, heads 3105a, 3105b, and 3105c arranged in three rows in the scanning direction may be capable of forming different material layers, or may eject the same material. When the same material is discharged by three heads to form the interlayer insulating film 3028 as a pattern, the throughput is improved. Note that the apparatus shown in FIG. 31 can scan by moving the substrate 3100 with the head portion fixed and moving the head portion with the substrate 3100 fixed.

  The individual heads 3105a, 3105b, and 3105c of the droplet discharge means are connected to the control means, which can draw a pre-programmed pattern by being controlled by a computer. The discharge amount is controlled by the applied pulse voltage. The drawing timing may be performed with reference to a marker formed on the substrate, for example. Alternatively, the reference point may be determined based on the edge of the substrate. This is detected by an image pickup means such as a CCD, and converted into a digital signal by the image processing means is recognized by a computer to generate a control signal and send it to the control means. Of course, the information on the pattern to be formed on the substrate is stored in the storage medium, and based on this information, a control signal is sent to the control means to individually control each head of the droplet discharge means. be able to.

  Next, laser light is selectively irradiated to expose part of the conductive film pattern (see FIG. 30B). A photosensitive material is included in advance in the conductive film material liquid to be discharged, and a chemical reaction is caused by the irradiated laser light. Here, an example in which the photosensitive material is a negative type that leaves a portion chemically irradiated by irradiation is shown. By irradiating the laser beam, an accurate pattern shape, particularly a wiring having a narrow width can be obtained.

  Here, the laser beam drawing apparatus will be described with reference to FIG. A laser beam drawing apparatus 3201 includes a personal computer (hereinafter also referred to as a PC) 3202 that executes various controls when irradiating a laser beam, a laser oscillator 3203 that outputs a laser beam, a power source 3204 for the laser oscillator 3203, An optical system (ND filter) 3205 for attenuating the laser beam, an acousto-optic modulator (AOM) 3206 for modulating the intensity of the laser beam, a lens and an optical path for enlarging or reducing the cross section of the laser beam An optical system 3207 composed of a mirror for changing the substrate, a substrate moving mechanism 3209 having an X stage and a Y stage, a D / A converter 3210 for digital-to-analog conversion of control data output from the PC, and D The acousto-optic modulator 3206 is turned on according to the analog voltage output from the A / A converter. And Gosuru driver 3211, and a driver 3212 for outputting a driving signal for driving the substrate moving mechanism 3209.

As the laser oscillator 3203, a laser oscillator that can oscillate ultraviolet light, visible light, or infrared light can be used. Examples of laser oscillators include excimer laser oscillators such as KrF, ArF, XeCl, and Xe, gas laser oscillators such as He, He—Cd, Ar, He—Ne, and HF, YAG, GdVO ₄ , YVO ₄ , YLF, and YAlO _3. A solid-state laser oscillator using a crystal doped with Cr, Nd, Er, Ho, Ce, Co, Ti, or Tm, and a semiconductor laser oscillator such as GaN, GaAs, GaAlAs, or InGaAsP can be used. In the solid-state laser oscillator, it is preferable to apply the first to fifth harmonics of the fundamental wave.

  A photosensitive material exposure method using a laser beam direct writing apparatus will be described below. In addition, the photosensitive material said here has pointed out the electrically conductive film material (photosensitive material is included) used as an electrically conductive film pattern.

  When the substrate 3208 is mounted on the substrate moving mechanism 3209, the PC 3202 detects the position of the marker attached to the substrate using a camera (not shown). Next, the PC 3202 generates movement data for moving the substrate movement mechanism 3209 based on the detected marker position data and drawing pattern data input in advance. Thereafter, the PC 3202 controls the output light amount of the acousto-optic modulator 3206 via the driver 3211, so that the laser beam output from the laser oscillator 3203 is attenuated by the optical system 3205 and then the acousto-optic modulator 3206. The light amount is controlled so as to be a predetermined light amount. On the other hand, the laser beam output from the acousto-optic modulator 3206 is changed in optical path and beam shape by the optical system 3207, condensed by the lens, and then irradiated to the photosensitive material formed on the substrate. The photosensitive material is exposed to light. At this time, the substrate moving mechanism 3209 is controlled to move in the X and Y directions according to the movement data generated by the PC 3202. As a result, a predetermined position is irradiated with a laser beam, and the photosensitive material is exposed.

  Note that a part of the energy of the laser light irradiated to the photosensitive material is converted into heat and reacts a part of the photosensitive material. Therefore, the pattern width is slightly larger than the width of the laser beam. Further, since the laser beam with a shorter wavelength can be condensed with a smaller beam diameter, it is preferable to irradiate a laser beam with a shorter wavelength in order to form a pattern with a fine width.

  The spot shape of the laser beam on the surface of the photosensitive material is processed by an optical system so as to be a dot, circle, ellipse, rectangle, or line (strictly, an elongated rectangle). The spot shape may be circular, but a linear pattern can form a pattern with a uniform width.

  32 shows an example in which exposure is performed by irradiating a laser beam from the front surface side of the substrate. However, the optical system and the substrate moving mechanism are appropriately changed to irradiate the laser beam from the back surface side of the substrate. Alternatively, a laser beam drawing apparatus that performs exposure may be used. Note that here, the laser beam is selectively irradiated by moving the substrate; however, the present invention is not limited to this, and the laser beam can be irradiated by scanning the laser beam in the X and Y axis directions. In this case, it is preferable to use a polygon mirror or a galvanometer mirror for the optical system 3207.

  Next, development is performed using an etchant (or a developer), an excess portion is removed, and main baking is performed to form a metal wiring 3015 to be a gate or a gate wiring (see FIG. 30C).

  Similarly to the metal wiring 3015, a wiring 3040 extending to the terminal portion is also formed. Although not shown here, a power supply line for supplying current to the light emitting element may also be formed. In addition, a capacitor electrode or a capacitor wiring for forming a storage capacitor is formed if necessary. Note that when a positive photosensitive material is used, a portion to be removed may be irradiated with a laser to cause a chemical reaction, and the portion may be dissolved with an etchant. Further, after dropping the conductive film material solution, exposure by laser light irradiation may be performed after drying at room temperature or pre-baking.

  Next, a gate insulating film 3018, a semiconductor film, and an n-type semiconductor film are sequentially formed by a plasma CVD method or a sputtering method. As the gate insulating film 3018, a material mainly containing silicon oxide, silicon nitride, or silicon nitride oxide obtained by a PCVD method is used. The gate insulating film 3018 may be a SiOx film containing an alkyl group by discharging and baking by a droplet discharging method using a siloxane polymer.

The semiconductor film is formed of an amorphous semiconductor film or a semi-amorphous semiconductor film which is manufactured by a vapor deposition method, a sputtering method, or a thermal CVD method using a semiconductor material gas typified by silane or germane. The amorphous semiconductor film, SiH _4, or can be used to obtain an amorphous silicon film by a PCVD method using a mixed gas of SiH ₄ and _{H 2.} Further, (also referred to as microcrystal or microcrystalline) semi-amorphous as the semiconductor film, a mixed gas obtained by diluting the SiH ₄ to 3 to 1000 times with _{H 2,} the gas flow rate ratio of _Si 2 _{H 6} and GeF ₄ 20 to 40 : Semi-amorphous obtained by PCVD using a mixed gas diluted with 0.9 (Si ₂ H ₆ : GeF ₄ ), a mixed gas of Si ₂ H ₆ and F ₂ , or a mixed gas of SiH ₄ and F ₂ A silicon film can be used. Note that a semi-amorphous silicon film is preferable because the interface with the base can be more crystalline.

Further, the crystallinity may be further improved by irradiating a semi-amorphous silicon film obtained by a PCVD method using a mixed gas of SiH ₄ and F _{2 with} a laser beam.

  The n-type semiconductor film may be formed by a PCVD method using silane gas and phosphine gas, and can be formed by an amorphous semiconductor film or a semi-amorphous semiconductor film. The n-type semiconductor film 3020 is preferably provided because contact resistance between the semiconductor film and an electrode (an electrode formed in a later step) is reduced, but it may be provided as necessary.

  Next, a mask 3021 is provided, and the semiconductor film and the n-type semiconductor film are selectively etched to obtain an island-shaped semiconductor film 3019 and an n-type semiconductor film 3020 (see FIG. 30D). The mask 3021 is formed by a droplet discharge method or a printing method (such as a relief plate, a flat plate, an intaglio plate, or a screen). Although a desired mask pattern may be directly formed by a droplet discharge method or a printing method, after forming a rough resist pattern by a droplet discharge method or a printing method in order to form with high definition, a laser beam is emitted. It may be selectively exposed to form a fine resist pattern.

  If the laser beam drawing apparatus shown in FIG. 32 is used, resist exposure can also be performed. In that case, the resist mask 3021 may be formed by performing exposure with a laser beam using a photosensitive material as a resist.

  Next, after removing the mask 3021, a mask (not shown) is provided, and the gate insulating film is selectively etched to form a contact hole. Further, the gate insulating film is removed from the terminal portion. The mask may be formed by a normal photolithography technique, a resist pattern formation by a droplet discharge method, or a resist pattern formation in which a positive resist coating is performed on the entire surface, followed by exposure and development with a laser beam. In an active matrix light-emitting device, a plurality of TFTs are arranged in one pixel and have a connection portion between a gate and an upper wiring through a gate insulating film.

  Next, a composition containing a conductive material (Ag (silver), Au (gold), Cu (copper), W (tungsten), Al (aluminum), etc.)) is selectively discharged by a droplet discharge method, and the source Wiring or drain wirings 3022 and 3023 and an extraction electrode 3017 are formed. Similarly, a power supply line for supplying current to the light-emitting element and a connection wiring (not shown) are also formed in the terminal portion (see FIG. 30E).

  Next, the n-type semiconductor film and the upper layer portion of the semiconductor film are etched using the source or drain wirings 3022 and 3023 as a mask to obtain the state shown in FIG. At this stage, a channel etch type TFT including a channel formation region 3024, a source region 3026, and a drain region 3025 to be active layers is completed.

  Next, a protective film 3027 for preventing the channel formation region 3024 from being contaminated with impurities is formed (see FIG. 33B). As the protective film 3027, silicon nitride obtained by a sputtering method or a PCVD method, or a material mainly containing silicon nitride oxide is used. Although an example in which the protective film 3027 is formed is shown here, it is not necessary to provide it unless particularly necessary.

  Next, an interlayer insulating film 3028 is selectively formed by a droplet discharge method. For the interlayer insulating film 3028, a resin material such as an epoxy resin, an acrylic resin, a phenol resin, a novolac resin, an acrylic resin, a melamine resin, or a urethane resin is used. In addition, droplets using organic materials such as benzocyclobutene, parylene, permeable polyimide, compound materials made by polymerization of siloxane polymers, composition materials containing water-soluble homopolymers and water-soluble copolymers, etc. It is formed by a discharge method. The formation method of the interlayer insulating film 3028 is not particularly limited to the droplet discharge method, and may be formed over the entire surface using a coating method, a PCVD method, or the like.

Next, the protective film 3027 is etched using the interlayer insulating film 3028 as a mask, so that convex portions (pillars) 3029 made of a conductive member are formed on part of the source wirings or drain wirings 3022 and 3023. The convex portion (pillar) 3029 repeats discharge and firing of a composition containing a conductive material (Ag (silver), Au (gold), Cu (copper), W (tungsten), Al (aluminum), etc.). May be formed.

Next, a first electrode 3030 which is in contact with the convex portion (pillar) 3029 is formed over the interlayer insulating film 3028 (see FIG. 33C). Similarly, a terminal electrode 3041 in contact with the wiring 3040 is also formed. Here, since the driving TFT is an n-channel type, the first electrode 3030 preferably functions as a cathode. In the case of transmitting light emission, a composition containing indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO), tin oxide (SnO ₂ ), or the like by a droplet discharge method or a printing method. A predetermined pattern made of a material is formed and baked to form the first electrode 3030 and the terminal electrode 3041. When light emission is reflected by the first electrode 3030, metal particles such as Ag (silver), Au (gold), Cu (copper), W (tungsten), and Al (aluminum) are mainly used by a droplet discharge method. A predetermined pattern made of the composition as a component is formed and baked to form the first electrode 3030 and the terminal electrode 3041. As another method, a transparent conductive film or a light reflective conductive film is formed by a sputtering method, a mask pattern is formed by a droplet discharge method, and etching is combined to form the first electrode 3030. good.

  FIG. 34 shows an example of a top view of the pixel at the stage of FIG. 34, the cross section taken along the chain line AA ′ corresponds to the cross sectional view on the right side of the pixel portion in FIG. 33C, and the cross sectional line BB ′ corresponds to the cross sectional view on the left side of the pixel portion in FIG. is doing. In FIG. 34, the same reference numerals are used for portions corresponding to FIGS. 30 and 33. Further, in FIG. 34, a portion that becomes an end portion of a partition wall 3034 to be formed later is indicated by a dotted line.

  In addition, since the protective film 3027 is provided here, the interlayer insulating film 3028 and the convex portion (pillar) 3029 are formed separately. However, when the protective film 3027 is not provided, the same apparatus is used by a droplet discharge method. It can also be formed.

  Next, a partition wall 3034 which covers the peripheral edge portion of the first electrode 3030 is formed. A partition wall (also referred to as a bank) 3034 is formed using a material containing silicon, an organic material, and a compound material. A porous film may be used. However, it is preferable to use a photosensitive or non-photosensitive material such as acrylic or polyimide because the side surface has a shape in which the radius of curvature continuously changes and the upper thin film is formed without being cut off.

  Through the above process, a TFT substrate for a light-emitting display panel in which a bottom-gate (also referred to as an inverted staggered) TFT and a first electrode 3030 are formed over a substrate 3000 is completed.

  Next, a layer functioning as an electroluminescent layer (EL layer), that is, a layer 3036 containing an organic compound is formed. The layer 3036 containing an organic compound has a stacked structure and is formed using an evaporation method or a coating method, respectively. For example, an electron transport layer (electron injection layer), a light emitting layer, a hole transport layer, and a hole injection layer are sequentially stacked on the cathode.

The electron transport layer contains a charge injecting and transporting material. Examples of the charge injecting and transporting material having a particularly high electron transporting property include, for example, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), tris (5-methyl-8- Quinolinolato) aluminum (abbreviation: Almq ₃ ), bis (10-hydroxybenzo [h] -quinolinato) beryllium (abbreviation: BeBq ₂ ), bis (2-methyl-8-quinolinolato) -4-phenylphenolato-aluminum (abbreviation) : BAlq) and the like, and metal complexes having a quinoline skeleton or a benzoquinoline skeleton. As a substance having a high hole-transport property, for example, 4,4′-bis [N- (1-naphthyl) -N-phenyl-amino] -biphenyl (abbreviation: α-NPD), 4,4′-bis [ N- (3-methylphenyl) -N-phenyl-amino] -biphenyl (abbreviation: TPD) or 4,4 ′, 4 ″ -tris (N, N-diphenyl-amino) -triphenylamine (abbreviation: TDATA) ), 4,4 ′, 4 ″ -tris [N- (3-methylphenyl) -N-phenyl-amino] -triphenylamine (abbreviation: MTDATA) (ie, benzene ring-nitrogen) And a compound having a bond of

Among the charge injecting and transporting materials, materials having particularly high electron injecting properties include alkali metals or alkaline earths such as lithium fluoride (LiF), cesium fluoride (CsF), calcium fluoride (CaF ₂ ) and the like. Metal compounds can be mentioned. In addition, a mixture of a substance having a high electron transporting property such as Alq ₃ and an alkaline earth metal such as magnesium (Mg) may be used.

  The light-emitting layer is formed of a charge injecting and transporting substance containing an organic compound or an inorganic compound and a light-emitting material, and based on the number of molecules thereof, a low molecular weight organic compound or a medium molecular weight organic compound (having no sublimation property and having Is an organic compound having a chain length of 10 μm or less, and includes one or a plurality of layers selected from high-molecular organic compounds, and has an electron injection / transport property or a hole injection / transport property. You may combine with these inorganic compounds.

There are various kinds of light emitting materials. As the low molecular weight organic light-emitting material, 4-dicyanomethylene-2-methyl-6- [2- (1,1,7,7-tetramethyl-9-julolidyl) ethenyl] -4H-pyran (abbreviation: DCJT), 4-dicyanomethylene-2-t-butyl-6- [2- (1,1,7,7-tetramethyljulolidin-9-yl) ethenyl] -4H-pyran (abbreviation: DCJTB), periflanthene, 2, 5-dicyano-1,4-bis [2- (10-methoxy-1,1,7,7-tetramethyljulolidin-9-yl) ethenyl] benzene, N, N′-dimethylquinacridone (abbreviation: DMQd) , Coumarin 6, Coumarin 545T, Tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), 9,9′-bianthryl, 9,10-diphenylanthracene (abbreviation: DPA) and 9 , 10-bis (2-naphthyl) anthracene (abbreviation: DNA) or the like can be used. Other substances may also be used.

  The polymer organic light emitting material has higher physical strength and higher device durability than the low molecular weight material. In addition, since the film can be formed by coating, the device can be manufactured relatively easily. The structure of the light emitting element using the high molecular weight organic light emitting material is basically the same as that when the low molecular weight organic light emitting material is used, and has a structure in which a cathode, an organic light emitting layer, and an anode are sequentially laminated. However, when forming a light emitting layer using a high molecular weight organic light emitting material, it is difficult to form a laminated structure as in the case of using a low molecular weight organic light emitting material. . Specifically, the cathode, the light emitting layer, the hole transport layer, and the anode are sequentially laminated.

  Since the light emission color is determined by the material for forming the light emitting layer, a light emitting element exhibiting desired light emission can be formed by selecting these materials. Examples of the polymer electroluminescent material that can be used for forming the light emitting layer include polyparaphenylene vinylene, polyparaphenylene, polythiophene, and polyfluorene.

  Examples of polyparaphenylene vinylene include poly (paraphenylene vinylene) (PPV) derivatives, poly (2,5-dialkoxy-1,4-phenylene vinylene) [RO-PPV], poly (2- (2′- Ethyl-hexoxy) -5-methoxy-1,4-phenylenevinylene) [MEH-PPV], poly (2- (dialkoxyphenyl) -1,4-phenylenevinylene) [ROPh-PPV] and the like. Examples of polyparaphenylene include derivatives of polyparaphenylene [PPP], poly (2,5-dialkoxy-1,4-phenylene) [RO-PPP], poly (2,5-dihexoxy-1,4-phenylene). ) And the like. The polythiophene series includes polythiophene [PT] derivatives, poly (3-alkylthiophene) [PAT], poly (3-hexylthiophene) [PHT], poly (3-cyclohexylthiophene) [PCHT], poly (3-cyclohexyl). -4-methylthiophene) [PCHMT], poly (3,4-dicyclohexylthiophene) [PDCHT], poly [3- (4-octylphenyl) -thiophene] [POPT], poly [3- (4-octylphenyl) -2,2 bithiophene] [PTOPT] and the like. Examples of the polyfluorene series include polyfluorene [PF] derivatives, poly (9,9-dialkylfluorene) [PDAF], poly (9,9-dioctylfluorene) [PDOF], and the like.

  Note that when a hole-transporting polymer-based organic light-emitting material is sandwiched between an anode and a light-emitting polymer-based organic light-emitting material, hole injection properties from the anode can be improved. In general, an acceptor material dissolved in water is applied by spin coating or the like. In addition, since it is insoluble in an organic solvent, it can be stacked with the above-described light-emitting organic light-emitting material. Examples of the hole-transporting polymer organic light emitting material include a mixture of PEDOT and camphor sulfonic acid (CSA) as an acceptor material, a mixture of polyaniline [PANI] and polystyrene sulfonic acid [PSS] as an acceptor material, and the like. .

  Furthermore, a triplet excitation material containing a metal complex or the like may be used for the light emitting layer in addition to a singlet excitation light emitting material. For example, among red light emitting pixels, green light emitting pixels, and blue light emitting pixels, a red light emitting pixel having a relatively short luminance half time is formed of a triplet excitation light emitting material, and the other A singlet excited light emitting material is used. The triplet excited luminescent material has a feature that the light emission efficiency is good, so that less power is required to obtain the same luminance. That is, when applied to a red pixel, the amount of current flowing through the light emitting element can be reduced, so that reliability can be improved. As a reduction in power consumption, a red light-emitting pixel and a green light-emitting pixel may be formed using a triplet excitation light-emitting material, and a blue light-emitting pixel may be formed using a singlet excitation light-emitting material. By forming a green light-emitting element having high human visibility with a triplet excited light-emitting material, power consumption can be further reduced.

  Examples of triplet excited luminescent materials include those using a metal complex as a dopant, and metal complexes having a third transition series element platinum as the central metal and metal complexes having iridium as the central metal are known. Yes. The triplet excited light-emitting material is not limited to these compounds, and a compound having the above structure and having an element belonging to group 8 to 10 in the periodic table as a central metal can also be used.

The hole transport layer contains a charge injecting and transporting material, and examples of the material having a high hole injecting property include molybdenum oxide (MoOx), vanadium oxide (VOx), ruthenium oxide (RuOx), Examples thereof include metal oxides such as tungsten oxide (WOx) and manganese oxide (MnOx). In addition, phthalocyanine compounds such as phthalocyanine (abbreviation: H ₂ Pc) and copper phthalocyanine (CuPc) can be given.

  Note that plasma treatment in an oxygen atmosphere or heat treatment in a vacuum atmosphere is preferably performed before the formation of the layer 3036 containing an organic compound. When the vapor deposition method is used, the organic compound is vaporized by resistance heating in advance, and is scattered in the direction of the substrate when the shutter is opened during vapor deposition. The vaporized organic compound scatters upward and is deposited on the substrate through an opening provided in the metal mask. In order to achieve full color, the mask may be aligned for each emission color (R, G, B).

  The light emitting layer may be configured to perform full color display by forming light emitting layers having different emission wavelength bands for each pixel. Typically, a light emitting layer corresponding to each color of R (red), G (green), and B (blue) is formed. In this case, a filter (colored layer) that transmits light in the emission wavelength band is provided on the light emission side of the pixel to improve color purity and prevent mirror reflection (reflection) of the pixel portion. Can be achieved. By providing the filter (colored layer), it is possible to omit a circularly polarized plate that has been considered necessary in the past, and it is possible to eliminate the loss of light emitted from the light emitting layer. Furthermore, a change in color tone that occurs when the pixel portion (display screen) is viewed obliquely can be reduced.

  Further, full color display can be performed by combining a color filter and a color conversion layer using a material that emits monochromatic light as the layer 3036 containing an organic compound without performing separate coating. For example, when an electroluminescent layer that emits white or orange light is formed, a full color display can be achieved by separately providing a color filter or a color conversion layer, or a combination of a color filter and a color conversion layer on the light emission side of the pixel. it can. The color filter and the color conversion layer may be formed on, for example, a second substrate (sealing substrate) and attached to the substrate. In addition, as described above, any of the material that emits monochromatic light, the color filter, and the color conversion layer can be formed by a droplet discharge method.

To form a light emitting layer that emits white light, for example, Alq _{3, Alq} 3 partially doped with Nile red that is a red light emitting pigment, p-EtTAZ, TPD (aromatic diamine) are sequentially stacked by a vapor deposition method Thus, white can be obtained. In the case of forming an EL by a coating method using spin coating, it is preferable that the coated film is baked by vacuum heating after coating. For example, a poly (ethylenedioxythiophene) / poly (styrenesulfonic acid) aqueous solution (PEDOT / PSS) that acts as a hole injection layer is applied and baked on the entire surface, and then a luminescent center dye (1, 1,4,4-tetraphenyl-1,3-butadiene (TPB), 4-dicyanomethylene-2-methyl-6- (p-dimethylamino-styryl) -4H-pyran (DCM1), Nile Red, Coumarin 6 Etc.) A doped polyvinyl carbazole (PVK) solution may be applied to the entire surface and fired.

  The light emitting layer can also be formed as a single layer, and an electron transporting 1,3,4-oxadiazole derivative (PBD) may be dispersed in hole transporting polyvinyl carbazole (PVK). Further, white light emission can be obtained by dispersing 30 wt% PBD as an electron transporting agent and dispersing an appropriate amount of four kinds of dyes (TPB, coumarin 6, DCM1, Nile red).

  The substances forming the layer containing an organic compound listed above are examples, and examples thereof include a hole injection transport layer, a hole transport layer, an electron injection transport layer, an electron transport layer, a light emitting layer, an electron block layer, and a hole block layer. A light-emitting element can be formed by appropriately stacking functional layers. Moreover, you may form the mixed layer or mixed junction which combined these each layer. The layer structure of the light-emitting layer can be changed, and instead of having a specific electron injection region or light-emitting region, it is possible to provide a modification with an electrode for this purpose or a dispersed light-emitting material. Can be permitted without departing from the spirit of the present invention.

  Of course, monochromatic light emission may be displayed. For example, an area color type light emitting display device may be formed using monochromatic light emission. As the area color type, a passive matrix type display unit is suitable, and characters and symbols can be mainly displayed.

  Next, a second electrode 3037 is formed. The second electrode 3037 functioning as an anode of the light-emitting element is formed using a transparent conductive film that transmits light. For example, in addition to ITO and ITSO, indium oxide is mixed with 2 to 20% zinc oxide (ZnO). A conductive film is used. The light-emitting element has a structure in which a layer 3036 containing an organic compound is sandwiched between a first electrode 3030 and a second electrode 3037. Note that the materials of the first electrode 3030 and the second electrode 3037 need to be selected in consideration of the work function, and the first electrode 3030 and the second electrode 3037 are both anodes or Can be a cathode.

  A light-emitting element formed using the above materials emits light by being forward-biased. A pixel of a display device formed using a light-emitting element can be driven by a simple matrix method or an active matrix method. In any case, each pixel emits light by applying a forward bias at a specific timing, but is in a non-light emitting state for a certain period. By applying a reverse bias during this non-light emitting time, the reliability of the light emitting element can be improved. The light emitting element has a degradation mode in which the light emission intensity decreases under a constant driving condition and a degradation mode in which the non-light emitting area is enlarged in the pixel and the luminance is apparently decreased. However, alternating current that applies a bias in the forward and reverse directions. By performing typical driving (AC driving), the progress of deterioration can be delayed, and the reliability of the light-emitting device can be improved.

In order to reduce the resistance of the second electrode 3037, an auxiliary electrode may be provided over the second electrode 3037 in a region that does not serve as a light-emitting region. Further, a protective layer for protecting the second electrode 3037 may be formed. For example, the protective film made of a silicon nitride film can be formed by using a disk-shaped target made of silicon and setting the film formation chamber atmosphere to a nitrogen atmosphere or an atmosphere containing nitrogen and argon. Further, a thin film containing carbon as a main component (DLC film, CN film, amorphous carbon film) may be formed as a protective film, or a film formation chamber using a CVD method may be provided separately. Diamond-like carbon film (also called DLC film) is formed by plasma CVD method (typically RF plasma CVD method, microwave CVD method, electron cyclotron resonance (ECR) CVD method, hot filament CVD method, etc.), combustion flame method It can be formed by sputtering, ion beam vapor deposition, laser vapor deposition or the like. The reaction gas used for film formation was hydrogen gas and a hydrocarbon-based gas (for example, CH ₄ , C ₂ H ₂ , C ₆ H _6, etc.), ionized by glow discharge, and negative self-bias was applied. Films are formed by accelerated collision of ions with the cathode. The carbon nitride film (CN film) may be formed using C ₂ H ₄ gas and N ₂ gas as reaction gases. Note that the DLC film and the CN film are insulating films that are transparent or translucent to visible light. “Transparent to visible light” means that the visible light transmittance is 80 to 100%, and “Translucent to visible light” means that the visible light transmittance is 50 to 80%. Point to. Note that this protective film is not particularly required if it is not necessary.

Next, the sealing substrate 3035 is attached with a sealant (not shown) to seal the light emitting element. Note that a region surrounded by the sealing material is filled with a transparent filler 3038. The filler 3038 is not particularly limited as long as it is a light-transmitting material. Typically, an ultraviolet curable or thermosetting epoxy resin may be used. Here, a highly heat-resistant UV epoxy resin having a refractive index of 1.50, a viscosity of 500 cps, a Shore D hardness of 90, a tensile strength of 3000 psi, a Tg point of 150 ° C., a volume resistance of 1 × 10 ¹⁵ Ω · cm, and a withstand voltage of 450 V / mil (electro Wright Corporation: 2500 Clear) is used. Further, the entire transmittance can be improved by filling the filler 3038 between the pair of substrates.

  Finally, an FPC 3046 is attached to the terminal electrode 3041 by a known method with an anisotropic conductive film 3045 (see FIG. 33D). Through the above steps, an active matrix light-emitting device can be manufactured.

  FIG. 35 is a top view showing an example of an EL display panel configuration. FIG. 35 shows a structure of a light-emitting display panel in which signals input to the scan lines and the signal lines are controlled by an external drive circuit. A pixel portion 3501 in which pixels 3502 are arranged in a matrix, a scanning line side input terminal 3503, and a signal line side input terminal 3504 are formed over a substrate 3500 having an insulating surface. The number of pixels may be provided in accordance with various standards. For XGA, 1024 × 768 × 3 (RGB), for UXGA, 1600 × 1200 × 3 (RGB), and for full specification high vision, 1920 × 1080. X3 (RGB) may be used.

  The pixels 3502 are arranged in a matrix by a scan line extending from the scan line side input terminal 3503 and a signal line extending from the signal line side input terminal 3504 intersecting. Each of the pixels 3502 includes a switching element and a pixel electrode connected to the switching element. A typical example of the switching element is a TFT. By connecting the gate side of the TFT to a scanning line and the source or drain side to a signal line, each pixel can be independently controlled by a signal input from the outside. .

  Note that if the first electrode 3030 shown in FIG. 33 is made of a transparent material and the second electrode 3037 is made of a metal material, a structure in which light is extracted through the substrate 3000, that is, a bottom emission type is obtained. When the first electrode 3030 is a metal material and the second electrode 3037 is a transparent material, a structure in which light is extracted through the sealing substrate 3035, that is, a top emission type is obtained. Further, when the first electrode 3030 and the second electrode 3037 are made of a transparent material, a structure in which light is extracted through both the substrate 3000 and the sealing substrate 3035 can be obtained. The present invention may have any one structure as appropriate. In addition, a driver circuit for driving may be mounted on the EL display panel. One mode thereof will be described with reference to FIG.

  First, a display device employing a COG method is described with reference to FIG. Over the substrate 3600, a pixel portion 3601 for displaying information such as characters and images, and a driving circuit 3602 on the scanning side are provided. A substrate provided with a plurality of drive circuits is divided into rectangular shapes, and the divided drive circuits (hereinafter referred to as driver ICs) 3605a and 3605b are mounted on the substrate 3600. FIG. 36 shows a form in which a plurality of driver ICs 3605a and 3605b and tapes 3604a and 3604b are mounted on the ends of the driver ICs 3605a and 3605b. Further, the size to be divided may be substantially the same as the length of the side of the pixel portion on the signal line side, and a tape may be mounted on the tip of the driver IC on a single driver IC.

  Alternatively, a TAB method may be employed. In that case, a plurality of tapes may be attached and a driver IC may be mounted on the tapes. As in the case of the COG method, a single driver IC may be mounted on a single tape. In this case, a metal piece or the like for fixing the driver IC may be attached together due to strength problems.

  A plurality of driver ICs mounted on these EL display panels are preferably formed on a rectangular substrate having a side of 300 mm to 1000 mm or more from the viewpoint of improving productivity. That is, a plurality of circuit patterns having a drive circuit portion and an input / output terminal as one unit may be formed on the substrate, and finally divided and taken out. The driver IC may be formed in a rectangular shape having a long side of 15 to 80 mm and a short side of 1 to 6 mm in consideration of the length of one side of the pixel portion and the pixel pitch. May be formed to have a length obtained by adding one side to one side of each drive circuit.

  The advantage of the external dimensions of the driver IC over the IC chip lies in the length of the long side. When a driver IC formed with a long side of 15 to 80 mm is used, the number required for mounting corresponding to the pixel portion is as follows. This is less than when an IC chip is used, and the manufacturing yield can be improved. Further, when a driver IC is formed over a glass substrate, the shape of the substrate used as a base is not limited, and thus productivity is not impaired. This is a great advantage compared with the case where the IC chip is taken out from the circular silicon wafer.

  In FIG. 36, driver ICs 3605a and 3605b in which a driver circuit is formed are mounted in a region outside the pixel portion 3601. These driver ICs 3605a and 3605b are drive circuits on the signal line side. In order to form a pixel region corresponding to RGB full color, the number of signal lines in the XGA class is 3072 and the number in the UXGA class is 4800. The signal lines formed in such a number are divided into several blocks at the end of the pixel portion 3601 to form lead lines, and are collected according to the pitch of the output terminals of the driver ICs 3605a and 3605b.

  The driver IC is preferably formed of a crystalline semiconductor formed over a substrate, and the crystalline semiconductor is preferably formed by irradiating continuous-emitting laser light. Therefore, a continuous light emitting solid state laser or gas laser is used as an oscillator for generating the laser light. When a continuous light emission laser is used, a transistor can be formed using a polycrystalline semiconductor layer having a large grain size with few crystal defects. In addition, since the mobility and response speed are good, high-speed driving is possible, the operating frequency of the element can be improved as compared with the prior art, and there is less variation in characteristics, so that high reliability can be obtained. Note that for the purpose of further improving the operating frequency, the channel length direction of the transistor and the scanning direction of the laser light are preferably matched. This is because, in the laser crystallization process using a continuous emission laser, the highest mobility is obtained when the channel length direction of the transistor and the scanning direction of the laser beam with respect to the substrate are substantially parallel (preferably −30 ° to 30 °). It is because it is obtained. Note that the channel length direction corresponds to the direction in which current flows in the channel formation region, in other words, the direction in which charges move. The transistor thus fabricated has an active layer composed of a polycrystalline semiconductor layer in which crystal grains extend in the channel direction, which means that the crystal grain boundaries are formed substantially along the channel direction. means.

  In order to perform laser crystallization, it is preferable to significantly narrow the laser beam, and the width of the beam spot is preferably about 1 to 3 mm, which is the same width of the short side of the driver IC. In order to ensure a sufficient and efficient energy density for the irradiated object, the laser light irradiation region is preferably linear. However, the line shape here does not mean a line in a strict sense, but means a rectangle or an ellipse having a large aspect ratio. For example, the aspect ratio is 2 or more (preferably 10 to 10,000). In this manner, a method for manufacturing a display device with improved productivity can be provided by setting the width of the beam spot of the laser light to the same length as the short side of the driver IC.

  In FIG. 36, the scanning line driving circuit is formed integrally with the pixel portion, and a driver IC is mounted as the signal line driving circuit. However, the present invention is not limited to this mode, and a driver IC may be mounted as both the scanning line driving circuit and the signal line driving circuit. In that case, the specifications of the driver ICs used on the scanning line side and the signal line side may be different.

In the pixel portion 3601, a signal line and a scanning line intersect to form a matrix, and a transistor is arranged corresponding to each intersection. The present invention is characterized in that a TFT using an amorphous semiconductor or a semi-amorphous semiconductor as a channel portion is used as a transistor provided in the pixel portion 3601. The amorphous semiconductor is formed by a method such as a plasma CVD method or a sputtering method. A semi-amorphous semiconductor can be formed by a plasma CVD method at a temperature of 300 ° C. or lower. For example, even a non-alkali glass substrate having an outer dimension of 550 × 650 mm has a film thickness necessary for forming a transistor. Is formed in a short time. Such a feature of the manufacturing technique is effective in manufacturing a large-screen display device. In addition, a semi-amorphous TFT can obtain a field effect mobility of ² to 10 cm ² / V · sec by forming a channel formation region with SAS. Therefore, this TFT can be used as a switching element for a pixel or an element constituting a driving circuit on the scanning line side. Therefore, an EL display panel that realizes system-on-panel can be manufactured.

  Note that FIG. 36 shows a premise that the scanning line side driver circuit is also formed over the substrate by using a TFT having a semiconductor layer formed of SAS. In the case of using a TFT having a semiconductor layer formed of SAS, a driver IC may be mounted on both the scanning line side driving circuit and the signal line side driving circuit.

  In that case, it is preferable that the specifications of the driver ICs used on the scanning line side and the signal line side are different. For example, although a transistor constituting the driver IC on the scanning line side is required to have a withstand voltage of about 30 V, the driving frequency is 100 kHz or less, and a relatively high speed operation is not required. Therefore, it is preferable to set the channel length (L) of the transistors forming the driver on the scanning line side to be sufficiently large. On the other hand, it is sufficient for the transistor of the driver IC on the signal line side to have a withstand voltage of about 12V, but the drive frequency is about 65 MHz at 3V, and high speed operation is required. Therefore, it is preferable to design a transistor that constitutes a driver with high integration.

  The method for mounting the driver IC is not particularly limited, and a known COG method, wire bonding method, or TAB method can be used. By setting the thickness of the driver IC to be the same as that of the counter substrate, the height between the two becomes substantially the same, which contributes to the reduction in thickness of the entire display device. In addition, since each substrate is made of the same material, thermal stress is not generated even when a temperature change occurs in the display device, and the characteristics of a circuit made of TFTs are not impaired. In addition, the number of driver ICs to be mounted in one pixel region can be reduced by mounting the drive circuit with a driver IC that is longer than the IC chip as shown in this embodiment.

As described above, a fine pattern can be realized by exposing and developing a conductive film pattern using a droplet discharge method with a laser beam. In addition, by forming various patterns directly on the substrate by using a droplet discharge method, it is easy to manufacture an EL display panel even if a glass substrate of 5th generation or more with one side exceeding 1000 mm is used. Can be.

  In the present embodiment, the spin coating is not performed, and the light exposure process using the photomask is performed as much as possible. However, the process is not particularly limited, and the light exposure process using the photomask for partial patterning is performed. You can go there.

  Note that this embodiment can be freely combined with the description in the other embodiments in this specification. That is, the number of transistors constituting the pixel and the number of wiring lines such as scanning lines and power supply lines connected to each pixel can be reduced, and an increase in aperture ratio can be expected. Therefore, a light-emitting element for maintaining desired luminance can be obtained. The applied voltage can be suppressed, and low power consumption can be achieved. In the light emitting device of the present invention, a forward bias voltage is applied to one of the pixels adjacent to a region provided at each intersection of the scanning line and the data line so that the light emitting element emits light. The reverse bias voltage can be applied simultaneously. Therefore, it is not necessary to provide an application time of the reverse bias voltage, so that deterioration of the light emitting element can be controlled and reliability can be improved without reducing the duty ratio (the ratio of the lighting period in one frame period).

Further, in the light emitting device of the present invention, by adopting a method (interlace method) that sequentially emits pixels every other row in the data line extending direction or the scanning line extending direction. It is possible to reduce the visual recognition of the pseudo contour, which is a problem when the image is displayed by the gradation method. In addition, the pixels are sequentially turned on every two pixels in each row, and in the next row, the pixels are turned on by shifting one pixel in the data line extending direction from the pixel in which the pixel is lit in the previous row. By adopting a method of performing light emission (checker method), the visual recognition of the pseudo contour can be reduced.
(Embodiment 9)

Next, a partial cross-sectional view of a pixel portion of the display panel is shown.

First, the case where a crystalline semiconductor film (polysilicon (p-Si: H) film) is used for a semiconductor layer of a transistor will be described with reference to FIGS.

Here, as the semiconductor layer, for example, an amorphous silicon (a-Si) film is formed on a substrate by a known film formation method. Note that the semiconductor film is not limited to an amorphous silicon film, and any semiconductor film including an amorphous structure (including a microcrystalline semiconductor film) may be used. Further, a compound semiconductor film including an amorphous structure such as an amorphous silicon germanium film may be used.

Then, the amorphous silicon film is crystallized by a laser crystallization method, a thermal crystallization method using an RTA or a furnace annealing furnace, or a thermal crystallization method using a metal element that promotes crystallization. Of course, these may be combined.

  By the above crystallization, a partially crystallized region is formed in the amorphous semiconductor film.

  Further, the crystalline semiconductor film partially improved in crystallinity is patterned into a desired shape, and an island-shaped semiconductor film is formed from the crystallized region. This semiconductor film is used for a semiconductor layer of a transistor.

As shown in FIG. 37, a base film 26102 is formed over a substrate 26101, and a semiconductor layer is formed thereover. The semiconductor layer includes a channel formation region 26103 of the driving transistor 26118 and an impurity region 26105 serving as a source or drain region, a channel formation region 26106 serving as a lower electrode of the capacitor 26119, an LDD region 26107, and an impurity region 26108. Note that channel doping may be performed on the channel formation region 26103 and the channel formation region 26106.

As the substrate, a glass substrate, a quartz substrate, a ceramic substrate, a plastic substrate, or the like can be used. As the base film 26102, a single layer of aluminum nitride (AlN), silicon oxide (SiO ₂ ), silicon oxynitride (SiOxNy), or a stacked layer thereof can be used.

Over the semiconductor layer, a gate 26110 and an upper electrode 26111 of a capacitor are formed with a gate insulating film 26109 interposed therebetween.

An interlayer insulator 26112 is formed so as to cover the driving transistor 26118 and the capacitor 26119. A wiring 26113 is in contact with the impurity region 26105 over the interlayer insulator 26112 through a contact hole. A pixel electrode 26114 is formed in contact with the wiring 26113, and a second interlayer insulator 26115 is formed to cover the end portion of the pixel electrode 26114 and the wiring 26113. Here, a positive photosensitive acrylic resin film is used. A layer 26116 containing an organic compound and a counter electrode 26117 are formed over the pixel electrode 26114, and a light-emitting element 26120 is formed in a region where the layer 26116 containing an organic compound is sandwiched between the pixel electrode 26114 and the counter electrode 26117. .

In addition, as illustrated in FIG. 37B, a region 26202 in which an LDD region that forms part of the lower electrode of the capacitor 26119 overlaps with the upper electrode 26111 may be provided. Note that portions common to FIG. 37A are denoted by common reference numerals, and description thereof is omitted.

As shown in FIG. 38A, a second upper electrode 26301 formed in the same layer as the wiring 26113 in contact with the impurity region 26105 of the driving transistor 26118 may be provided. Note that portions common to FIG. 37A are denoted by common reference numerals, and description thereof is omitted. An interlayer insulator 26112 is sandwiched between the second upper electrode 26301 and the upper electrode 26111 to form a second capacitor element. In addition, since the second upper electrode 26301 is in contact with the impurity region 26108, the first capacitor element in which the gate insulating film 26109 is sandwiched between the upper electrode 26111 and the channel formation region 26106, the upper electrode 26111, A second capacitor element including an interlayer insulator 26112 sandwiched between the second upper electrode 26301 and a second capacitor element connected in parallel to form a capacitor element 26302 including the first capacitor element and the second capacitor element. is doing. Since the capacitance of the capacitor 26302 is a combined capacitance obtained by adding the capacitances of the first capacitor and the second capacitor, a capacitor having a large capacity can be formed with a small area. That is, the aperture ratio can be further improved when used as a capacitor having a pixel structure of the present invention.

Further, a structure of a capacitor as shown in FIG. A base film 27102 is formed over the substrate 27101, and a semiconductor layer is formed thereover. The semiconductor layer includes a channel formation region 27103 of the driving transistor 27118 and an impurity region 27105 serving as a source or drain region. Note that channel doping may be performed in the channel formation region 27103.

As the substrate, a glass substrate, a quartz substrate, a ceramic substrate, a plastic substrate, or the like can be used. As the base film 26102, a single layer of aluminum nitride (AlN), silicon oxide (SiO ₂ ), silicon oxynitride (SiOxNy), or a stacked layer thereof can be used.

A gate 27107 and a first electrode 27108 are formed over the semiconductor layer with a gate insulating film 27106 interposed therebetween.

A first interlayer insulator 27109 is formed to cover the driving transistor 27118 and the first electrode 27108, and a wiring 27110 is in contact with the impurity region 27105 over the first interlayer insulator 27109 through a contact hole. In addition, a second electrode 27111 in the same layer made of the same material as the wiring 27110 is formed.

Further, a second interlayer insulator 27112 is formed so as to cover the wiring 27110 and the second electrode 27111, and a pixel electrode 27113 is formed on the second interlayer insulator 27112 in contact with the wiring 27110 through a contact hole. Has been. A third electrode 27114 in the same layer made of the same material as the pixel electrode 27113 is formed. Here, a capacitor 27119 including the first electrode 27108, the second electrode 27111, and the third electrode 27114 is formed.

A third interlayer insulator 27115 is formed so as to cover end portions of the pixel electrode 27113 and the third electrode 27114, and a layer 27116 containing an organic compound and the counter electrode are formed over the third interlayer insulator 27115 and the third electrode 27114. 27117 is formed, and a light-emitting element 27120 is formed in a region where the pixel electrode 27113 and the counter electrode 27117 sandwich the layer 27116 containing an organic compound.

As described above, the structure of the transistor in which the crystalline semiconductor film is used for the semiconductor layer includes the structures illustrated in FIGS. Note that the structure of the transistor illustrated in FIGS. 37 and 38 is an example of a top-gate transistor. That is, the transistor may be P-type or N-type. In the case of N-type, the LDD region may overlap with the gate, may not overlap with the gate, or a part of the LDD region may overlap. Further, the gate may have a tapered shape, and an LDD region may be provided in a self-aligned manner below the tapered portion of the gate. Further, the number of gates is not limited to two, but may be a multi-gate structure of three or more, or a single gate.

By using a crystalline semiconductor film for a semiconductor layer (a channel formation region, a source region, a drain region, or the like) of a transistor included in the pixel of the present invention, for example, the scan line driver circuit 901 and the signal line driver circuit 902 in FIG. Can be formed integrally with the display unit 600.

Further, as a transistor structure using polysilicon (p-Si: H) as a semiconductor layer, a structure in which a gate is sandwiched between a substrate and a semiconductor layer, that is, a bottom gate in which a gate is located under the semiconductor layer. FIG. 39 shows a partial cross section of a display panel to which a transistor is applied.

  A base film 7502 is formed over the substrate 7501. Further, a gate 7503 is formed over the base film 7502. A first electrode 7504 made of the same material is formed in the same layer as the gate. As a material for the gate 7503, polycrystalline silicon to which phosphorus is added can be used. In addition to polycrystalline silicon, silicide which is a compound of metal and silicon may be used.

A gate insulating film 7505 is formed so as to cover the gate 7503 and the first electrode 7504. As the gate insulating film 7505, a silicon oxide film, a silicon nitride film, or the like is used.

  In addition, a semiconductor layer is formed over the gate insulating film 7505. The semiconductor layer includes a channel formation region 7506, an LDD region 7507, and an impurity region 7508 serving as a source or drain region of the driving transistor 7522, and a channel formation region 7509, an LDD region 7510, and an impurity region 7511 serving as a second electrode of the capacitor 7523. Have. Note that channel doping may be performed on the channel formation region 7506 and the channel formation region 7509.

As the substrate, a glass substrate, a quartz substrate, a ceramic substrate, a plastic substrate, or the like can be used. As the base film 7502, a single layer of aluminum nitride (AlN), silicon oxide (SiO2), silicon oxynitride (SiOxNy), or a stacked layer thereof can be used.

A first interlayer insulator 7512 is formed to cover the semiconductor layer, and a wiring 7513 is in contact with the impurity region 7508 over the first interlayer insulator 7512 through a contact hole. A third electrode 7514 is formed using the same material in the same layer as the wiring 7513. A capacitor 7523 is formed by the first electrode 7504, the second electrode, and the third electrode 7514.

In addition, an opening 7515 is formed in the first interlayer insulator 7512. A second interlayer insulator 7516 is formed so as to cover the driving transistor 7522, the capacitor 7523, and the opening 7515, and a pixel electrode 7517 is formed over the second interlayer insulator 7516 through a contact hole. In addition, an insulator 7518 is formed to cover an end portion of the pixel electrode 7517. For example, a positive photosensitive acrylic resin film can be used. A layer 7519 containing an organic compound and a counter electrode 7520 are formed over the pixel electrode 7517, and a light-emitting element 7521 is formed in a region where the layer 7519 containing an organic compound is sandwiched between the pixel electrode 7517 and the counter electrode 7520. . An opening 7515 is located below the light emitting element 7521. That is, when light emitted from the light-emitting element 7521 is extracted from the substrate side, the transmittance can be increased because the opening 7515 is provided.

In FIG. 39A, the fourth electrode 7524 may be formed using the same material in the same layer as the pixel electrode 7517 so that the structure shown in FIG. Then, a capacitor 7525 including the first electrode 7504, the second electrode, the third electrode 7514, and the fourth electrode 7524 can be formed.

Next, the case where an amorphous silicon (a-Si: H) film is used for the semiconductor layer of the transistor will be described. FIG. 40 shows the case of a top gate transistor, and FIGS. 41 and 42 show the case of a bottom gate transistor.

FIG. 40A shows a cross section of a forward staggered transistor using amorphous silicon as a semiconductor layer. As shown, a base film 7602 is formed on the substrate 7601. Further, a pixel electrode 7603 is formed over the base film 7602. In addition, a first electrode 7604 made of the same material is formed in the same layer as the pixel electrode 7603.

As the substrate, a glass substrate, a quartz substrate, a ceramic substrate, a plastic substrate, or the like can be used. As the base film 7602, a single layer of aluminum nitride (AlN), silicon oxide (SiO ₂ ), silicon oxynitride (SiOxNy), or a stacked layer thereof can be used.

Further, a wiring 7605 and a wiring 7606 are formed over the base film 7602, and an end portion of the pixel electrode 7603 is covered with the wiring 7605. An N-type semiconductor layer 7607 and an N-type semiconductor layer 7608 having an N-type conductivity are formed over the wirings 7605 and 7606. A semiconductor layer 7609 is formed between the wiring 7605 and the wiring 7606 and over the base film 7602. A part of the semiconductor layer 7609 extends to the N-type semiconductor layer 7607 and the N-type semiconductor layer 7608. Note that this semiconductor layer is formed of an amorphous semiconductor film such as amorphous silicon (a-Si: H) or microcrystalline semiconductor (μ-Si: H). In addition, a gate insulating film 7610 is formed over the semiconductor layer 7609. An insulating film 7611 made of the same material and in the same layer as the gate insulating film 7610 is also formed over the first electrode 7604. Note that a silicon oxide film, a silicon nitride film, or the like is used as the gate insulating film 7610.

  A gate 7612 is formed over the gate insulating film 7610. A second electrode 7613 made of the same material and in the same layer as the gate is formed over the first electrode 7604 with an insulating film 7611 interposed therebetween. A capacitor element 7619 in which an insulating film 7611 is sandwiched between the first electrode 7604 and the second electrode 7613 is formed. Further, an interlayer insulator 7614 is formed so as to cover an end portion of the pixel electrode 7603, the driving transistor 7618, and the capacitor 7619.

A region 7615 containing an organic compound and a counter electrode 7616 are formed over the interlayer insulator 7614 and the pixel electrode 7603 located in the opening, and the layer 7615 containing an organic compound is sandwiched between the pixel electrode 7603 and the counter electrode 7616 Then, a light emitting element 7617 is formed.

Alternatively, the first electrode 7604 illustrated in FIG. 40A may be formed using the first electrode 7620 as illustrated in FIG. The first electrode 7620 is formed using the same material in the same layer as the wirings 7605 and 7606.

FIG. 41 shows a partial cross section of a display panel using a bottom-gate transistor using amorphous silicon as a semiconductor layer.

  A base film 7702 is formed over the substrate 7701. Further, a gate 7703 is formed over the base film 7702. A first electrode 7704 made of the same material is formed in the same layer as the gate. As a material for the gate 7703, polycrystalline silicon to which phosphorus is added can be used. In addition to polycrystalline silicon, silicide which is a compound of metal and silicon may be used.

A gate insulating film 7705 is formed so as to cover the gate 7703 and the first electrode 7704. As the gate insulating film 7705, a silicon oxide film, a silicon nitride film, or the like is used.

  In addition, a semiconductor layer 7706 is formed over the gate insulating film 7705. In addition, a semiconductor layer 7707 made of the same material is formed in the same layer as the semiconductor layer 7706.

As the substrate, a glass substrate, a quartz substrate, a ceramic substrate, a plastic substrate, or the like can be used. As the base film 7602, a single layer of aluminum nitride (AlN), silicon oxide (SiO ₂ ), silicon oxynitride (SiOxNy), or a stacked layer thereof can be used.

N-type semiconductor layers 7708 and 7709 having N-type conductivity are formed over the semiconductor layer 7706, and an N-type semiconductor layer 7710 is formed over the semiconductor layer 7707.

Wirings 7711, 7712, and 7713 are formed over the N-type semiconductor layers 7708, 7709, and 7710, respectively, and a conductive layer 7713 made of the same material as the wirings 7711 and 7712 is formed over the N-type semiconductor layer 7710. Yes.

A second electrode including the semiconductor layer 7707, the N-type semiconductor layer 7710, and the conductive layer 7713 is formed. Note that a capacitor 7720 having a structure in which the gate insulating film 7705 is sandwiched between the second electrode and the first electrode 7704 is formed.

In addition, one end portion of the wiring 7711 extends, and a pixel electrode 7714 is formed in contact with the upper portion of the extended wiring 7711.

An insulator 7715 is formed so as to cover an end portion of the pixel electrode 7714, the driving transistor 7719, and the capacitor 7720.

A layer 7716 containing an organic compound and a counter electrode 7717 are formed over the pixel electrode 7714 and the insulator 7715, and a light-emitting element 7718 is formed in a region where the layer 7716 containing an organic compound is interposed between the pixel electrode 7714 and the counter electrode 7717. Has been.

The semiconductor layer 7707 and the N-type semiconductor layer 7710 which are part of the second electrode of the capacitor may not be provided. That is, the capacitor may have a structure in which the second electrode is the conductive layer 7713 and the gate insulating film is sandwiched between the first electrode 7704 and the conductive layer 7713.

Note that in FIG. 41A, the pixel electrode 7714 is formed before the wiring 7711 is formed, so that the second electrode 7721 and the first electrode including the pixel electrode 7714 as illustrated in FIG. A capacitor 7722 having a structure in which the gate insulating film 7705 is sandwiched by 7704 can be formed.

Note that although an inverted staggered channel-etched transistor is shown in FIG. 41, a channel-protective transistor may of course be used. The case of a transistor with a channel protective structure will be described with reference to FIGS.

A transistor with a channel protective structure shown in FIG. 42A is an insulator 7801 serving as an etching mask over a region where a channel of the semiconductor layer 7706 of the driving transistor 7719 having the channel etch structure shown in FIG. Are different from each other, and other common parts use common reference numerals.

Similarly, in the channel protection type transistor shown in FIG. 42B, an etching mask is formed over the region where the channel of the semiconductor layer 7706 of the channel etching structure driving transistor 7719 shown in FIG. 41B is formed. The difference is that an insulator 7802 is provided, and common points are used for other common parts.

  In addition, manufacturing costs can be reduced by using an amorphous semiconductor film for a semiconductor layer (a channel formation region, a source region, a drain region, or the like) of a transistor included in the pixel of the present invention.

Note that the structure of the transistor to which the pixel structure of the present invention can be applied and the structure of the capacitor are not limited to those described above, and transistors having various structures and structures of capacitors can be used. .

  Note that this embodiment can be freely combined with the description in the other embodiments in this specification. That is, the number of transistors constituting the pixel and the number of wiring lines such as scanning lines and power supply lines connected to each pixel can be reduced, and an increase in aperture ratio can be expected. Therefore, a light-emitting element for maintaining desired luminance can be obtained. The applied voltage can be suppressed, and low power consumption can be achieved. In the light emitting device of the present invention, a forward bias voltage is applied to one of the pixels adjacent to a region provided at each intersection of the scanning line and the data line so that the light emitting element emits light. The reverse bias voltage can be applied simultaneously. Therefore, it is not necessary to provide an application time of the reverse bias voltage, so that deterioration of the light emitting element can be controlled and reliability can be improved without reducing the duty ratio (the ratio of the lighting period in one frame period).

  Further, in the light emitting device of the present invention, by adopting a method (interlace method) that sequentially emits pixels every other row in the data line extending direction or the scanning line extending direction. It is possible to reduce the visual recognition of the pseudo contour, which is a problem when the image is displayed by the gradation method. In addition, the pixels are sequentially turned on every two pixels in each row, and in the next row, the pixels are turned on by shifting one pixel in the data line extending direction from the pixel in which the pixel is lit in the previous row. By adopting a method of performing light emission (checker method), the visual recognition of the pseudo contour can be reduced.

(Embodiment 10)
Electronic devices including the light-emitting device of the present invention include television receivers, video cameras, digital cameras and other cameras, goggle-type displays, navigation systems, sound playback devices (such as car audio components), computers, game devices, and portable information terminals. (Mobile computer, mobile phone, portable game machine, electronic book, or the like), an image playback apparatus (specifically, a digital versatile disc (DVD)) provided with a recording medium, and can display the image And a device equipped with a display). Specific examples of these electronic devices are shown in FIGS. 22, 23, 24 (A) to 24 (B), 25 (A) to 25 (B), 26, 27 (A) to 27 ( E).

  FIG. 22 shows a module in which a display panel 5001 and a circuit board 5011 are combined. A circuit board 5011 is provided with a control circuit 5012, a signal dividing circuit 5013, and the like, and is electrically connected to the display panel 5001 through a connection wiring 5014.

  The display panel 5001 includes a pixel portion 5002 provided with a plurality of pixels, a scanning line driver circuit 5003, and a signal line driver circuit 5004 for supplying a video signal to the selected pixel. Note that in the case of manufacturing the display panel 5001, the above embodiment mode may be used. Further, a control driver circuit portion such as the scan line driver circuit 5003 or the signal line driver circuit 5004 can be manufactured using thin film transistors. As described above, the module shown in FIG. 22 can be completed.

  FIG. 23 is a block diagram illustrating a main configuration of a television receiver. A tuner 5101 receives a video signal and an audio signal. The video signal includes a video signal amplifying circuit 5102, a video signal processing circuit 5103 that converts a signal output from the video signal into a color signal corresponding to each color of red, green, and blue, and the video signal as input specifications of the driver IC. Processing is performed by a control circuit 5012 for conversion. The control circuit 5012 outputs a signal to each of the scanning line side and the signal line side. In the case of digital driving, a signal dividing circuit 5013 may be provided on the signal line side so that an input digital signal is divided into m pieces and supplied.

  Of the signals received by the tuner 5101, the audio signal is sent to the audio signal amplifier circuit 5105, and the output is supplied to the speaker 5107 through the audio signal processing circuit 5106. The control circuit 5108 receives control information on the receiving station (reception frequency) and volume from the input unit 5109 and sends a signal to the tuner 5101 and the audio signal processing circuit 5106.

  As shown in FIG. 24A, a television set can be completed by incorporating a module into a housing 5201. A display screen 5202 is formed by the module. In addition, a speaker 5203, an operation switch 5204, and the like are provided as appropriate.

  FIG. 24B shows a television receiver that can carry only a display wirelessly. A housing and a signal receiver are incorporated in the housing 5212, and the display portion 5213 and the speaker portion 5217 are driven by the battery. The battery can be repeatedly charged by a charger 5210. The charger 5210 can transmit and receive a video signal, and can transmit the video signal to a signal receiver of the display. The housing 5212 is controlled by operation keys 5216. The device illustrated in FIG. 24B can also be referred to as a video / audio bidirectional communication device because a signal can be sent from the housing 5212 to the charger 5210 by operating the operation key 5216. In addition, by operating the operation key 5216, a signal is transmitted from the housing 5212 to the charger 5210, and further, a signal that can be transmitted by the charger 5210 is received by another electronic device, thereby controlling communication of the other electronic device. It can be said to be a general-purpose remote control device.

  By using the light-emitting device of the present invention in the television receiver shown in FIGS. 22, 23, 24A to 24B, the number of transistors constituting the pixel of the display portion is reduced and the reverse bias is applied. Improvement of the reliability of the light emitting element can be expected by applying a voltage to the light emitting element periodically. In addition, since the number of transistors and the number of wirings constituting the pixel in the display portion can be reduced, an increase in the aperture ratio of the pixel portion can be expected, which can contribute to a reduction in power consumption. In addition, the layout area of the driver circuit portion around the pixel portion can be reduced, and a product with a high yield can be provided to the customer.

  Of course, the present invention is not limited to a television receiver, and is applied to various uses as a display medium of a particularly large area such as a monitor of a personal computer, an information display board in a railway station or airport, an advertisement display board in a street, etc. can do.

  FIG. 25A shows a module in which a display panel 5301 and a printed wiring board 5302 are combined. The display panel 5301 includes a pixel portion 5303 provided with a plurality of pixels, a first scan line driver circuit 5304, a second scan line driver circuit 5305, and a signal line driver circuit that supplies a video signal to the selected pixel. 5306 is provided.

  The printed wiring board 5302 is provided with a controller 5307, a central processing unit (CPU) 5308, a memory 5309, a power supply circuit 5310, an audio processing circuit 5311, a transmission / reception circuit 5312, and the like. The printed wiring board 5302 and the display panel 5301 are connected by a flexible wiring board (FPC) 5313. The printed wiring board 5313 may be provided with a capacitor, a buffer circuit, or the like so that noise is added to the power supply voltage or the signal or the rise of the signal is not slowed. The controller 5307, the audio processing circuit 5311, the memory 5309, the CPU 5308, the power supply circuit 5310, and the like can be mounted on the display panel 5301 using a COG (Chip On Glass) method. The scale of the printed wiring board 5302 can be reduced by the COG method.

  Various control signals are input and output through an interface (I / F) unit 5314 provided in the printed wiring board 5302. An antenna port 5315 for transmitting and receiving signals to and from the antenna is provided on the printed wiring board 5302.

  FIG. 25B shows a block diagram of the module shown in FIG. This module includes a VRAM 5316, a DRAM 5317, a flash memory 5318, and the like as the memory 5309. The VRAM 5316 stores image data to be displayed on the panel, the DRAM 5317 stores image data or audio data, and the flash memory stores various programs.

  The power supply circuit 5310 supplies power for operating the display panel 5301, the controller 5307, the CPU 5308, the sound processing circuit 5311, the memory 5309, and the transmission / reception circuit 5312. Depending on the specifications of the panel, the power supply circuit 5310 may be provided with a current source.

  The CPU 5308 includes a control signal generation circuit 5320, a decoder 5321, a register 5322, an arithmetic circuit 5323, a RAM 5324, an interface 5319 for the CPU 5308, and the like. Various signals input to the CPU 5308 through the interface 5319 are temporarily held in the register 5322 and then input to the arithmetic circuit 5323, the decoder 5321, and the like. The arithmetic circuit 5323 performs an operation based on the input signal and designates a place to send various commands. On the other hand, the signal input to the decoder 5321 is decoded and input to the control signal generation circuit 5320. The control signal generation circuit 5320 generates a signal including various instructions based on the input signal, and a location designated by the arithmetic circuit 5323, specifically, a memory 5309, a transmission / reception circuit 5312, an audio processing circuit 5311, a controller 5307, and the like. Send to.

  The memory 5309, the transmission / reception circuit 5312, the sound processing circuit 5311, and the controller 5307 operate according to the received commands. The operation will be briefly described below.

  A signal input from the input unit 5325 is sent to the CPU 5308 mounted on the printed wiring board 5302 via the I / F unit 5314. The control signal generation circuit 5320 converts the image data stored in the VRAM 5316 into a predetermined format according to a signal sent from the input unit 5325 such as a pointing device or a keyboard, and sends the image data to the controller 5307.

  The controller 5307 performs data processing on a signal including image data sent from the CPU 5308 in accordance with the specifications of the panel, and supplies the processed signal to the display panel 5301. Further, the controller 5307 generates an Hsync signal, a Vsync signal, a clock signal CLK, an AC voltage (AC Cont), and a switching signal L / R based on the power supply voltage input from the power supply circuit 5310 and various signals input from the CPU 5308. Generated and supplied to the display panel 5301.

  In the transmission / reception circuit 5312, signals transmitted / received as radio waves in the antenna 5328 are processed. Specifically, high-frequency signals such as an isolator, a band-pass filter, a VCO (Voltage Controlled Oscillator), an LPF (Low Pass Filter), a coupler, and a balun. Includes circuitry. A signal including audio information among signals transmitted and received in the transmission / reception circuit 5312 is sent to the audio processing circuit 5311 in accordance with a command from the CPU 5308.

  A signal including audio information sent in accordance with a command from the CPU 5308 is demodulated into an audio signal by the audio processing circuit 5311 and sent to the speaker 5327. An audio signal sent from the microphone 5326 is modulated in the audio processing circuit 5311 and sent to the transmission / reception circuit 5312 in accordance with a command from the CPU 5308.

  The controller 5307, the CPU 5308, the power supply circuit 5310, the sound processing circuit 5311, and the memory 5309 can be mounted as a package of this embodiment mode. This embodiment can be applied to any circuit other than a high-frequency circuit such as an isolator, a band-pass filter, a VCO (Voltage Controlled Oscillator), an LPF (Low Pass Filter), a coupler, and a balun.

  FIG. 26 illustrates one mode of a mobile phone including the module illustrated in FIGS. 25 (A) to 25 (B). The display panel 5301 is incorporated in a housing 5330 so as to be detachable. The shape and size of the housing 5330 can be changed as appropriate in accordance with the size of the display panel 5301. The housing 5330 to which the display panel 5301 is fixed is fitted to the printed board 5331 and assembled as a module.

  The display panel 5301 is connected to the printed board 5331 through the FPC 5313. A signal processing circuit 5335 including a speaker 5332, a microphone 5333, a transmission / reception circuit 5334, a CPU, a controller, and the like is formed over the printed board 5331. Such a module is combined with the input means 5336, the battery 5337, and the antenna 5340 and stored in the housing 5339. The pixel portion of the display panel 5301 is arranged so that it can be seen from an opening window formed in the housing 5339.

  By using the present invention for the mobile phone shown in FIGS. 25A to 25B and FIG. 26, the number of transistors constituting the pixel of the display panel is reduced, and the reverse bias voltage is periodically changed to the light emitting element. By applying the voltage to, the reliability of the light emitting element can be improved. In addition, since the number of transistors and wirings included in the pixel of the display panel can be reduced, an increase in the aperture ratio of the pixel portion can be expected, which can contribute to a reduction in power consumption. In addition, the layout area of the driver circuit portion around the pixel portion can be reduced, and a product with a high yield can be provided to the customer.

  The mobile phone according to the present embodiment can be transformed into various modes depending on the function and application. For example, even if a plurality of display panels are provided, or a case is divided into a plurality of cases and is configured to be openable / closable by a hinge, the number of transistors constituting the pixels of the display panel is reduced in the display panel, and The reliability of the light emitting element can be improved by periodically applying a reverse bias voltage to the light emitting element. In addition, since the number of transistors and wirings included in the pixel of the display panel can be reduced, an increase in the aperture ratio of the pixel portion can be expected, which can contribute to a reduction in power consumption. In addition, it is possible to reduce the layout area of the drive circuit portion around the pixel portion, and to provide an effect that it is possible to provide a product with a high yield to the customer.

  FIG. 27A illustrates a display, which includes a housing 6071, a support base 6072, a display portion 6073, and the like. The present invention can be applied to the pixel portion of the display portion 6073 using the structure of the display panel shown in FIG.

  By using the present invention, it is possible to improve the reliability of the light emitting element by reducing the number of transistors included in the pixel of the display portion 6073 and periodically applying a reverse bias voltage to the light emitting element. In addition, since the number of transistors and wirings included in the pixel of the display panel can be reduced, an increase in the aperture ratio of the pixel portion can be expected, which can contribute to a reduction in power consumption. In addition, the layout area of the driver circuit portion around the pixel portion can be reduced, and a product with a high yield can be provided to the customer.

  FIG. 27B illustrates a computer, which includes a main body 6101, a housing 6102, a display portion 6103, a keyboard 6104, an external connection port 6105, a pointing mouse 6106, and the like. The present invention can be applied to the display portion 6103 using the structure of the display panel shown in FIG.

  By using the present invention, the number of transistors included in the pixel of the display portion 6103 can be reduced, and the reliability of the light-emitting element can be improved by periodically applying a reverse bias voltage to the light-emitting element. In addition, since the number of transistors and wirings included in the pixel of the display panel can be reduced, an increase in the aperture ratio of the pixel portion can be expected, which can contribute to a reduction in power consumption. In addition, the layout area of the driver circuit portion around the pixel portion can be reduced, and a product with a high yield can be provided to the customer.

  FIG. 27C illustrates a portable computer, which includes a main body 6201, a display portion 6202, a switch 6203, operation keys 6204, an infrared port 6205, and the like. The present invention can be applied to the display portion 6202 using the structure of the display panel shown in FIG.

  By using the present invention, the number of transistors included in the pixel of the display portion 6202 is reduced, and a reverse bias voltage is applied to the light emitting element without providing a period for applying the reverse bias voltage. Reliability can be improved. In addition, since the number of transistors and wirings included in the pixel of the display panel can be reduced, an increase in the aperture ratio of the pixel portion can be expected, which can contribute to a reduction in power consumption. In addition, the layout area of the driver circuit portion around the pixel portion can be reduced, and a product with a high yield can be provided to the customer.

  FIG. 27D illustrates a portable game machine including a housing 6301, a display portion 6302, speaker portions 6303, operation keys 6304, a recording medium insertion portion 6305, and the like. The present invention can be applied to the display portion 6302 using the structure of the display panel shown in FIG.

  By using the present invention, the reliability of the light-emitting element can be improved by reducing the number of transistors included in the pixel of the display portion 6302 and periodically applying a reverse bias voltage to the light-emitting element. In addition, since the number of transistors and wirings included in the pixel of the display panel can be reduced, an increase in the aperture ratio of the pixel portion can be expected, which can contribute to a reduction in power consumption. In addition, the layout area of the driver circuit portion around the pixel portion can be reduced, and a product with a high yield can be provided to the customer.

  FIG. 27E illustrates a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 6401, a housing 6402, a display portion A6403, a display portion B6404, and a recording medium (such as a DVD). A reading unit 6405, operation keys 6406, a speaker unit 6407, and the like are included. The display portion A 6403 mainly displays image information, and the display portion B 6404 mainly displays character information. The present invention can be applied to the display portion A 6403, the display portion B 6404, the control circuit portion, and the like by using the structure of the display panel shown in FIG. Note that an image reproducing device provided with a recording medium includes a home game machine and the like.

  By using the present invention, the number of transistors included in the pixels of the display portion A 6403 and the display portion B 6404 can be reduced, and by applying a reverse bias voltage to the light emitting element periodically, the reliability of the light emitting element can be improved. . In addition, since the number of transistors and wirings included in the pixel of the display panel can be reduced, an increase in the aperture ratio of the pixel portion can be expected, which can contribute to a reduction in power consumption. In addition, the layout area of the driver circuit portion around the pixel portion can be reduced, and a product with a high yield can be provided to the customer.

  Light-emitting devices used in these electronic devices can use not only a glass substrate but also a heat-resistant plastic substrate depending on the size, strength, or purpose of use. As a result, the weight can be further reduced.

  Note that the example shown in the present embodiment is only an example, and is not limited to these applications.

  This embodiment mode can be implemented freely combining with any description in the embodiment modes. That is, the number of transistors constituting the pixel and the number of wiring lines such as scanning lines and power supply lines connected to each pixel can be reduced, and an increase in aperture ratio can be expected. Therefore, a light-emitting element for maintaining desired luminance can be obtained. The applied voltage can be suppressed, and low power consumption can be achieved. In the light emitting device of the present invention, a forward bias voltage is applied to one of the pixels adjacent to a region provided at each intersection of the scanning line and the data line so that the light emitting element emits light. The reverse bias voltage can be applied simultaneously. Therefore, since it is not necessary to provide a period for applying a reverse bias voltage, the deterioration of the light emitting element can be controlled and the reliability can be improved without reducing the duty ratio (the ratio of the lighting period in one frame period). .

  In addition, in an electronic device including the light emitting device of the present invention, a method (interlace method) is employed in which pixels are emitted sequentially every other row in the data line extension direction or the scanning line extension direction. By doing so, it is possible to reduce the visual recognition of the pseudo contour which becomes a problem when the image display is performed by the time gradation method. In addition, the pixels are sequentially turned on every two pixels in each row, and in the next row, the pixels are turned on by shifting one pixel in the data line extending direction from the pixel in which the pixel is lit in the previous row. By adopting a method of performing light emission (checker method), the visual recognition of the pseudo contour can be reduced. In addition, in an electronic device including the light-emitting device of the present invention, as described above, the number of transistors connected to each pixel, the number of wirings such as a scanning line and a power supply line can be reduced. The layout area of the drive circuit around the area can be reduced, and the layout area of the display panel can be reduced. Therefore, the electronic device can be reduced in size and weight. Moreover, a product with a high yield can be manufactured, and a cheaper product can be provided to the customer.

FIG. 3 is a circuit diagram illustrating a configuration of the first embodiment. FIG. 3 is a circuit diagram illustrating a configuration of the first embodiment. FIG. 2 is a circuit diagram and a timing chart illustrating the configuration of Embodiment 1; FIG. 2 is a circuit diagram and a timing chart illustrating the configuration of Embodiment 1; FIG. 3 is a top view illustrating the structure of the first embodiment. FIG. 2 is a block diagram illustrating a configuration of the first embodiment. FIG. 3 is a display diagram of a display panel showing the configuration of the first embodiment. FIG. 6 is a timing chart in a display example of the display panel showing the configuration of Embodiment 1; FIG. 4 is a circuit diagram illustrating a configuration of a second embodiment. FIG. 4 is a circuit diagram illustrating a configuration of a second embodiment. FIG. 4 is a circuit diagram and a timing chart illustrating the configuration of Embodiment 2. FIG. 4 is a circuit diagram and a timing chart illustrating the configuration of Embodiment 2. FIG. 4 is a circuit diagram illustrating a configuration of a third embodiment. FIG. 4 is a circuit diagram illustrating a configuration of a third embodiment. FIG. 4 is a circuit diagram and a timing chart illustrating the configuration of Embodiment 3. FIG. 4 is a circuit diagram and a timing chart illustrating the configuration of Embodiment 3. FIG. 6 is a display diagram of a display panel showing the configuration of the fourth embodiment. FIG. 9 is a timing chart in a display example of a display panel showing the configuration of Embodiment 4; FIG. 6 is a configuration diagram of a fifth embodiment. FIG. 10 is a configuration diagram of a sixth embodiment. FIG. 20 is a perspective view and a cross-sectional view of an EL module according to Embodiment 7. FIG. 20 illustrates an example of an electronic device of Embodiment 10; FIG. 20 illustrates an example of an electronic device of Embodiment 10; FIG. 20 illustrates an example of an electronic device of Embodiment 10; FIG. 20 illustrates an example of an electronic device of Embodiment 10; FIG. 20 illustrates an example of an electronic device of Embodiment 10; FIG. 20 illustrates an example of an electronic device of Embodiment 10; The figure which shows the conventional circuit structure. The figure which shows the conventional circuit structure. FIG. 10 is a cross-sectional view illustrating Embodiment 8; FIG. 10 is a schematic diagram illustrating Embodiment 8. FIG. 9 is a block diagram illustrating Embodiment 8; FIG. 10 is a cross-sectional view illustrating Embodiment 8; FIG. 10 is a top view illustrating Embodiment Mode 8. FIG. 10 is a schematic diagram illustrating Embodiment 8. FIG. 10 is a schematic diagram illustrating Embodiment 8. FIG. 10 is a cross-sectional view illustrating Embodiment 9; FIG. 10 is a cross-sectional view illustrating Embodiment 9; FIG. 10 is a cross-sectional view illustrating Embodiment 9; FIG. 10 is a cross-sectional view illustrating Embodiment 9; FIG. 10 is a cross-sectional view illustrating Embodiment 9; FIG. 10 is a cross-sectional view illustrating Embodiment 9;

Explanation of symbols

100 region 101 selection transistor 102 driving transistor 103 light-emitting element 104 light-emitting element 105 capacitor element 106 capacitor element 130 contact part 301 shift register 304 level shifter 305 buffer 401 shift register 402 first latch circuit 403 second latch circuit 404 level shifter 405 Buffer 600 Display unit 901 Scanning line driving circuit 902 Signal line driving circuit 1001 Driving transistor 1002 Driving transistor 1401 Erasing transistor 1402 Erasing diode 2801 Control transistor 2802 Driving transistor 2803 Capacitance element 2804 Light emitting element 2901 Control transistor 2902 Driving Transistor 2903 erasing transistor 2904 capacitive element 2905 light emitting element 3000 substrate 30 2 Conductive film pattern 3015 Metal wiring 3017 Lead electrode 3018 Gate insulating film 3019 Island-shaped semiconductor film 3020 N-type semiconductor film 3021 Mask 3022 Drain wiring 3023 Drain wiring 3024 Channel formation region 3025 Drain region 3026 Source region 3027 Protective film 3028 Interlayer insulation Membrane 3029 Convex part (pillar)
3030 First electrode 3034 Partition wall 3035 Sealing substrate 3036 Layer 3037 containing an organic compound Second electrode 3038 Filler 3040 Wiring 3041 Terminal electrode 3045 Anisotropic conductive film 3046 FPC
3500 Substrate 3501 Pixel portion 3502 Pixel 3503 Scan line side input terminal 3504 Signal line side input terminal 3600 Substrate 3601 Pixel portion 3602 Driver circuit 3604a Tape 3604b Tape 3605a Driver IC
3605b Driver IC
3201 Laser beam drawing apparatus 3202 Personal computer 3203 Laser oscillator 3204 Power source 3205 Optical system 3206 Acousto-optic modulator 3207 Optical system 3208 Substrate 3209 Substrate moving mechanism 3210 D / A converter 3211 Driver 3212 Driver 3100 Substrate 3103 Area 3104 Imaging means 3105a Head 3105b Head 3105c Head 3107 Stage 3111 Marker 4001 Substrate 4002 Pixel portion 4003 Signal line driver circuit 4004 Scan line driver circuit 4005 Scan line driver circuit 4006 Substrate 4007 Filler 4008 Transistor 4009 Driving transistor 4010 Switching transistor 4011 Light emitting element 4012 Second electrode 4014 Wiring 4015 Wiring 4016 Connection terminal 4017 Wiring 4018 FPC
4019 Anisotropic conductive film 4020 Sealing material 5001 Display panel 5002 Pixel portion 5003 Scan line driver circuit 5004 Signal line driver circuit 5011 Circuit board 5012 Control circuit 5013 Signal dividing circuit 5014 Connection wiring 5101 Tuner 5102 Video signal amplifier circuit 5103 Video signal processing circuit 5105 Audio signal amplifying circuit 5106 Audio signal processing circuit 5107 Speaker 5108 Control circuit 5109 Input unit 5201 Case 5202 Display screen 5203 Speaker 5204 Operation switch 5210 Battery charger 5212 Case 5213 Display unit 5216 Operation key 5217 Speaker unit 5301 Display panel 5302 Print wiring Substrate 5303 Pixel portion 5304 Scanning line driving circuit 5305 Scanning line driving circuit 5306 Signal line driving circuit 5307 Controller 5308 C U
5309 Memory 5310 Power supply circuit 5311 Audio processing circuit 5312 Transmission / reception circuit 5313 FPC
5314 I / F Unit 5315 Antenna Port 5316 VRAM
5317 DRAM
5318 Flash memory 5320 Control signal generation circuit 5321 Decoder 5322 Register 5323 Arithmetic circuit 5324 RAM
5325 Input means 5326 Microphone 5327 Speaker 5328 Antenna 5330 Housing 5331 Printed circuit board 5332 Speaker 5333 Microphone 5334 Transmission / reception circuit 5335 Signal processing circuit 5336 Input means 5337 Battery 5339 Housing 5340 Antenna 6001 TFT
6003 Light emitting element 6004 First electrode 6005 Electroluminescent layer 6006 Second electrode 6007 Interlayer insulating film 6008 Partition 6011 TFT
6013 Light emitting element 6014 First electrode 6015 Electroluminescent layer 6016 Second electrode 6021 TFT
6023 Light emitting element 6024 First electrode 6025 Electroluminescent layer 6026 Second electrode 6031 TFT
6033 Light emitting element 6034 First electrode 6035 Electroluminescent layer 6036 Second electrode 6041 TFT
6043 Light emitting element 6044 First electrode 6045 Electroluminescent layer 6046 Second electrode 6051 TFT
6053 Light emitting element 6054 First electrode 6055 Electroluminescent layer 6056 Second electrode 6071 Housing 6072 Support base 6073 Display unit 6101 Main body 6102 Housing unit 6103 Display unit 6104 Keyboard 6105 External connection port 6106 Pointing mouse 6201 Main body 6202 Display unit 6203 Switch 6204 Operation key 6205 Infrared port 6301 Case 6302 Display unit 6303 Speaker unit 6304 Operation key 6305 Recording medium insertion unit 6401 Main body 6402 Case 6403 Display unit A
6404 Display portion B
6405 Recording medium reading portion 6406 Operation key 6407 Speaker portion 7501 Substrate 7502 Base film 7503 Gate 7504 First electrode 7505 Gate insulating film 7506 Channel formation region 7507 LDD region 7508 Impurity region 7509 Channel formation region 7510 LDD region 7511 Impurity region 7512 Interlayer insulation Object 7513 Wiring 7514 Electrode 7515 Opening 7515 Interlayer insulator 7517 Pixel electrode 7518 Insulator 7519 Layer containing organic compound 7520 Opposite electrode 7521 Light emitting element 7522 Drive transistor 7523 Capacitor element 7524 Capacitor element 7601 Substrate 7602 Base film 7603 Pixel electrode 7604 First electrode 7605 Wiring 7606 Wiring 7607 N-type semiconductor layer 7608 N-type semiconductor layer 7609 Semiconductor layer 7610 Gate insulating film 7611 insulating film 7612 gate 7613 second electrode 7614 interlayer insulator 7615 layer containing an organic compound 7616 counter electrode 7617 light-emitting element 7618 driving transistor 7619 capacitor element 7620 first electrode 7701 substrate 7702 base film 7703 gate 7704 first 1 electrode 7705 gate insulating film 7706 semiconductor layer 7707 semiconductor layer 7708 N type semiconductor layer 7709 N type semiconductor layer 7710 N type semiconductor layer 7711 wiring 7712 wiring 7713 conductive layer 7714 pixel electrode 7715 insulator 7716 layer containing organic compound 7717 counter electrode 7718 Light-emitting element 7719 Drive transistor 7720 Capacitor element 7721 Second electrode 7722 Capacitor element 7801 Insulator 7802 Insulator 26101 Substrate 26102 Base film 26103 Channel formation Region 26105 Impurity region 26106 Channel formation region 26107 LDD region 26108 Impurity region 26109 Gate insulating film 26110 Gate 26111 Upper electrode 26112 Interlayer insulator 26113 Wiring 26114 Pixel electrode 26115 Interlayer insulator 26116 Layer 26117 containing organic compound Counter electrode 26118 Drive transistor 26119 Capacitor Element 26120 Light emitting element 26201 Channel formation region 26202 Region 26301 Second upper electrode 26302 Capacitor element 27101 Substrate 27102 Base film 27103 Channel formation region 27105 Impurity region 27106 Gate insulation film 27107 Gate 27108 First electrode 27109 Interlayer insulator 27110 Wiring 27111 First 2 electrode 27112 Interlayer insulator 27113 Pixel electrode 27114 Electrode 27115 Interlayer insulator 27116 Layer 27117 containing organic compound Counter electrode 27118 Drive transistor 27119 Capacitor element 27120 Light-emitting element pix1 First pixel pix2 Second pixel

Claims (10)

Scanning lines;
Data lines,
A first power line;
A second power line;
A third power line;
A first light emitting element electrically connected to the first power line;
A second light emitting element electrically connected to the second power line;
A first transistor having a gate electrically connected to the scan line;
A gate is electrically connected to the data line through a source and a drain of the first transistor, one of the source and the drain is electrically connected to the third power supply line, and the other is the first light emission. And a second transistor electrically connected to the second light-emitting element. 2. The light-emitting device according to claim 1, wherein the first transistor is an N-channel type and the second transistor is a P-channel type. 3. The diode according to claim 1, wherein each of the first light emitting element and the second light emitting element is a diode having a first electrode and a second electrode having a polarity different from that of the first electrode. The light emitting device is characterized in that the second electrode and the second transistor are electrically connected. 4. The light emitting device according to claim 3, wherein the first electrode is a cathode and the second electrode is an anode. 5. The light-emitting element according to claim 1, wherein the first light-emitting element emits light when a potential of the third power supply line is lower than a potential of the first power supply line. 2. The light emitting device according to claim 1, wherein the second light emitting element is a light emitting element that emits light when the potential of the third power supply line is lower than the potential of the second power supply line. Scanning lines;
Data lines,
A first power line;
A second power line;
A first light emitting element electrically connected to the first power line;
A second light emitting element electrically connected to the second power line;
A first transistor having a gate electrically connected to the scan line;
A gate is electrically connected to the data line through a source and a drain of the first transistor, one of a source and a drain is electrically connected to the first power supply line, and the other is the first light emission. A second transistor electrically connected to the element;
A gate is electrically connected to the data line through the source and drain of the first transistor, one of the source and drain is electrically connected to the second power supply line, and the other is the second light emission. And a third transistor which is electrically connected to the element. A first scan line;
A second scan line;
Data lines,
A first power line;
A second power line;
A first light emitting element electrically connected to the first power line;
A second light emitting element electrically connected to the second power line;
A first transistor having a gate electrically connected to the first scan line;
A gate is electrically connected to the data line through a source and a drain of the first transistor, one of a source and a drain is electrically connected to the first power supply line, and the other is the first light emission. A second transistor electrically connected to the element;
A gate is electrically connected to the data line through the source and drain of the first transistor, one of the source and drain is electrically connected to the second power supply line, and the other is the second light emission. A third transistor electrically connected to the element;
A first capacitor that holds a voltage applied to the gate of the first transistor;
A second capacitive element for holding a voltage applied to the gate of the second transistor;
An erasing element provided between the second scanning line and the source and drain of the first transistor and erasing the voltage held in the first capacitor element or the second capacitor element; A light emitting device characterized by that. 8. The light-emitting device according to claim 6, wherein the first transistor is an N-channel type, and the second transistor and the third transistor are a P-channel type. The forward bias voltage is applied to any one of the first light emitting element and the second light emitting element, and the reverse bias voltage is applied to the other. A light-emitting device. An electronic device using the light emitting device according to claim 1.

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