JP2008187873A - Motor driving controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To surely diagnose a failure in switching elements at a stoppage, even if, naturally, a motor is operating. <P>SOLUTION: When the motor 8 is deactivated or operated under PWM control, a CPU 6 controls the switching elements (FET11, FET12, FET13, FET14), based on a switching instruction signal so as to selectively carry a current. A first diagnosis signal T1 at one motor terminal A, detected by a first diagnosis signal detecting circuit 3 and a second diagnosis signal T2 at the other motor terminal B, detected by a second diagnosis signal detecting circuit 4, are inputted. Rise/fall is detected in the inputted first and second diagnosis signals T1, T2, and the failure in the switching elements is diagnosed, based on the detection result. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a motor drive control device having a failure diagnosis function of a drive circuit that drives a motor.

Conventionally, as this kind of technology, for example, those described in the following documents are known (see Patent Documents 1 to 3). In the failure diagnosis techniques described in these documents, a plurality of switching elements constituting a bridge circuit for supplying and controlling drive current to the motor are selectively made conductive (ON) / non-conductive (OFF), and the motor at that time Terminal voltage is detected, and based on the detected voltage, motor terminal ground fault, power fault, motor disconnection, etc., switching element on (short) fault, off (open) fault, switching time abnormality The method of diagnosing such troubles was adopted.
JP-A-10-20001 Japanese Patent Laid-Open No. 11-75392 JP 2002-272177 A

  In the conventional failure diagnosis technique, the detection circuit that detects the motor terminal voltage at the time of failure diagnosis is configured by a circuit including a resistor and a capacitor. For this reason, when the motor is operating, the signal detected by the detection circuit is taken into the central CPU of the fault diagnosis with its rise and fall being dull, and PWM control (Pulse Width Modulation) When the motor is in the operating state by the control), the terminal voltage of the motor that fluctuates in synchronization with the PWM signal for controlling the on / off of the switching element is averaged and taken into the CPU.

  Therefore, when the on-duty (high level period) of the PWM signal in PWM control is remarkably longer than the off-duty (low level period), the CPU recognizes the motor terminal voltage as a high voltage such as a power supply voltage. Conversely, if the on-duty (high level period) is significantly shorter than the off-duty (low level period), the CPU may recognize the motor terminal voltage as a low voltage such as the ground potential. was there. For this reason, in fault diagnosis during motor operation, the CPU can distinguish from the terminal voltage of the motor when a failure such as an ON fault or an OFF fault occurs at the switching element, or a fault such as a power fault, ground fault, or disconnection occurs at the motor terminal. There was a risk of misdiagnosis due to difficulty.

  On the other hand, since the switching element is not PWM-controlled when the motor is stopped, the detection circuit detects the terminal voltage of the motor as a saturation voltage and applies it to the CPU by turning the switching element on or off for a sufficiently long time. It was possible. For this reason, it was possible to accurately recognize the switching time of the switching element. However, since the switching element is PWM controlled during motor operation, it cannot be set to an on state or an off state for a sufficiently long time, and the detection circuit includes a resistor and a capacitor as described above. Then, the saturation voltage could not be detected at the motor terminal. For this reason, the CPU cannot accurately obtain the terminal voltage of the motor in synchronization with the PWM signal, and it has been difficult to accurately diagnose the failure of the switching time in the switching element.

  As described above, in the conventional failure diagnosis technology, it is assumed that the failure is mainly diagnosed when the motor is stopped. Therefore, the failure diagnosis during the operation of the motor causes the above-described problems.

  In view of the above, the present invention has been made in view of the above, and an object of the present invention is to provide a failure diagnosis function that can reliably diagnose a failure of a switching element even during operation as well as when the motor is stopped. An object of the present invention is to provide a motor drive control device provided.

  In order to achieve the above object, the invention according to claim 1 controls the supply of drive current to the motor by conducting conduction control of a plurality of switching elements constituting the bridge circuit based on a switching command signal given from the control means. Then, in the motor drive control device that controls the drive of the motor, the first diagnostic signal that is composed of a resistance component and is output to one terminal of the motor, and the second that is output to the other terminal of the motor Signal detection means for detecting a diagnostic signal; and current supply means for selectively supplying a diagnostic current to the bridge circuit when diagnosing a failure of the switching element when the motor is stopped. The plurality of switching elements are selectively turned on at the time of failure diagnosis of the switching elements, and as a result, the first diagnosis detected by the signal detecting means is performed. A signal and a second diagnostic signal are input, rising / falling edges of the input first diagnostic signal and second diagnostic signal are detected, and at least a failure of the switching element is diagnosed based on the detection result It is characterized by.

  According to the first aspect of the present invention, when the motor is stopped, it is possible to reliably diagnose the failure of the switching element even during the operation of the motor.

  According to a second aspect of the present invention, in the motor drive control device according to the first aspect, the control means determines whether the first diagnostic signal and the second diagnostic signal rise / fall within a predetermined time set in advance. And detecting at least a failure of the switching element based on the detection result.

  According to the second aspect of the present invention, it is possible to reliably diagnose an abnormality in the switching time in the switching element.

  According to a third aspect of the present invention, in the motor drive control device according to the first or second aspect, the control means selectively controls the conduction of the switching element by PWM control and operates the motor to operate the switching element. It is characterized by diagnosing the failure of

  According to the third aspect of the present invention, the failure of the switching element can be reliably diagnosed when the conduction of the switching element is controlled by PWM control to operate the motor.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS The best embodiment for carrying out the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram illustrating a configuration of a motor drive control device according to a first embodiment of the present invention. 1 includes an H-bridge circuit 1, a pre-driver circuit 2, a first diagnostic signal detection circuit 3, a second diagnostic signal detection circuit 4, a diagnostic switching circuit 5, and a CPU 6. For example, power is supplied from a battery power supply (VB) 7 and the motor 8 is driven and controlled.

  The H-bridge circuit 1 includes FETs (field effect transistors) 11, 12, 13, and 14 that function as switching elements. A P-channel FET 11 and an N-channel FET 12 are connected to a battery power supply 7 and a ground potential (GND). The series connection point is connected to the motor terminal A serving as one terminal of the motor 8 and the first diagnostic signal detection circuit 3, and the P-channel FET 13 and the N-channel FET 14 are connected to the battery power source. 7 and the ground potential (GND) are connected in series, and the series connection point is connected to the motor terminal B serving as the other terminal of the motor 8 and the second diagnostic signal detection circuit 4.

  The pre-driver circuit 2 controls switching of the FETs 11, 12, 13, and 14 of the H bridge circuit 1 based on switching command signals (S1 to S4) given from the CPU 6.

  The first diagnostic signal detection circuit 3 includes two resistors R2 and R3. One end of the resistor R2 is connected to the motor terminal A, the other end is connected to the ground potential (GND), and the resistor R3 is one end thereof. Is connected to the motor terminal A, and the other end is connected to the CPU 6. The first diagnostic signal detection circuit 3 detects the potential of the motor terminal A as the first diagnostic signal T1 and gives it to the CPU 6 at the time of failure diagnosis of the apparatus.

  The second diagnostic signal detection circuit 4 is composed of two resistors R4 and R5. One end of the resistor R4 is connected to the motor terminal B, the other end is connected to the ground potential (GND), and the resistor R5 is one end thereof. Is connected to the motor terminal B, and the other end is connected to the CPU 6. The second diagnostic signal detection circuit 4 detects the potential of the motor terminal B as a second diagnostic signal T2 and gives it to the CPU 6 at the time of failure diagnosis of the apparatus.

  The diagnosis switching circuit 5 includes an NPN bipolar transistor Q1 and a resistor R1, and the transistor Q1 has a base terminal connected to the CPU 6, a collector terminal connected to the battery power supply 7, and an emitter terminal connected to the resistor R1. It is connected to the. The resistor R1 has one end connected to the emitter terminal of the transistor Q1 and the other end connected to one end of the resistors R2 and R3 of the first diagnostic signal detection circuit 3 and the motor terminal A.

  The diagnosis switching circuit 5 controls the conduction of the transistor Q1 based on the switching signal S5 output from the CPU 6 to thereby connect the common connection point of the resistors R1, R2, and R3 and the resistors R4 and R5 in the first diagnostic signal detection circuit 3. The potential at the common connection point is selectively controlled to a high level or a low level. That is, the diagnosis switching circuit 5 functions as a power supply (current supply means) at the time of diagnosis of the FETs 12 and 14 in the H bridge circuit 1, and when each of the FETs 11 to 14 is off and the motor 8 is stopped, When the transistor Q1 is turned on, the potential at each of the common connection points is set to a high level, while when the transistor Q1 is turned off, the potential at the common connection point is set to a low level, thereby switching the contents of the failure diagnosis. .

  Note that the resistance values of the resistors R1, R2, and R3 are set to be R2 >> R1, R3 >> R1 so that the potential at each common connection point is set to a high level when the transistor Q1 is turned on. Has been.

  The CPU 6 functions as a control center (control means) for controlling the operation of the apparatus, and includes resources such as a processing device, a storage device, and an input / output device necessary for a computer that controls various operation processes based on a program. For example, it is realized by a microcomputer or the like. The CPU 6 comprehensively manages and controls all operations necessary for failure diagnosis based on a signal for instructing diagnosis given from the outside and a control logic (program) stored in advance in the inside.

  That is, the CPU 6 gives a switching command signal (S1 to S4) to the pre-driver circuit 2, and gives a switching signal S5 to the transistor Q1. Further, the CPU 6 detects the rising and falling edges of the first diagnostic signal T1 detected by the first diagnostic signal detection circuit 3 and the second diagnostic signal T2 detected by the second diagnostic signal detection circuit 4. It has a function. Further, the CPU 6 determines the abnormality of the switching element based on the detection result of the rising / falling of the first diagnostic signal T1 and the second diagnostic signal T2.

  The motor 8 is used in, for example, a driving force distribution control device for a four-wheel drive vehicle equipped with a transfer, and is used in a motor drive system that changes a fastening force of a clutch that fastens a front wheel side and a rear wheel side according to a traveling state of the vehicle. Applied.

  Next, a failure diagnosis procedure will be described with reference to the flowchart shown in FIG. 2 and the timing charts shown in FIGS.

  First, failure diagnosis with the motor 8 stopped will be described. In FIG. 2, first, in the initial state, the switching command signals (S1 to S4) and the switching signal S5 all command the corresponding transistors to be turned off (step S200). As a result, as shown in FIG. 3, the first diagnostic signal T1 and the second diagnostic signal T2 are at a low level.

  In such a state, the switching signal S5 is changed from the low level to the high level to turn on the transistor Q1 (step S201). Thereafter, the first diagnostic signal detection circuit 3 detects the first diagnostic signal T1, the second diagnostic signal detection circuit 4 detects the second diagnostic signal T2, and these detected first diagnostic signals. T1 and the second diagnostic signal T2 are supplied to the CPU 6, and the CPU 6 determines whether or not the first diagnostic signal T1 and the second diagnostic signal T2 rise from low level to high level (step S202).

  If the diagnosis signal does not rise as a result of the determination, it is subsequently determined whether or not both diagnosis signals have risen (step S203). As a result of the determination, if both diagnosis signals do not rise as shown in FIG. 4, it is determined that an on failure of the FETs 12 and 14 or a ground fault of the motor terminal A or B has occurred (step S204). As shown in FIG. 5, when the first diagnostic signal T1 rises and the second diagnostic signal T2 does not rise, it is determined that a disconnection failure of the motor 8 has occurred (step S205).

  On the other hand, if both diagnosis signals rise as shown in FIG. 6 in the determination result of the previous step S202, it is determined that the signal is normal, and the next diagnosis operation is started.

  In the next diagnostic operation, the switching signal S5 is changed from the high level to the low level to turn off the transistor Q1 (step S206). Thereafter, the first diagnostic signal detection circuit 3 detects the first diagnostic signal T1, the second diagnostic signal detection circuit 4 detects the second diagnostic signal T2, and these detected first diagnostic signals. T1 and the second diagnostic signal T2 are supplied to the CPU 6, and the CPU 6 determines whether or not the first diagnostic signal T1 and the second diagnostic signal have fallen from the high level to the low level (step S207).

  As a result of the determination, if both diagnosis signals do not fall as shown in FIG. 7, it is determined that an on failure of the FETs 11 and 13 or a power fault of the motor terminal A or B has occurred (step S208) When both diagnostic signals fall as shown in FIG. 8, it is determined that the signal is normal, and the next diagnostic operation is started.

  In the next diagnostic operation, a command to turn on the FET 11 from OFF to ON is given to the pre-driver circuit 2 from the low level to the high level, and the pre-driver circuit 2 applies to the gate terminal of the FET 11 based on the switching command signal S1. A low level switching signal is applied (step S209). Thereafter, the first diagnostic signal detection circuit 3 detects the first diagnostic signal T1, the second diagnostic signal detection circuit 4 detects the second diagnostic signal T2, and these detected first diagnostic signals. T1 and the second diagnostic signal T2 are supplied to the CPU 6, and the CPU 6 determines whether or not the first diagnostic signal T1 and the second diagnostic signal T2 have risen from the low level to the high level within a predetermined time set in advance. (Step S210).

  As a result of the determination, if both diagnostic signals do not rise within the specified time as shown in FIG. 9, it is determined that the FET 11 has an off failure or an abnormal switching (off → on) time, Further, as shown in FIG. 10, when it rises a little after the specified time, it is determined that the switching time abnormality of the FET 11 has occurred (step S211). On the other hand, as shown in FIG. 11, when both of the diagnostic signals rise within a specified time, it is determined to be normal, and the next diagnostic operation is started.

  In the next diagnostic operation, a command for changing the switching command signal S1 from the high level to the low level to turn off the FET 11 is given to the pre-driver circuit 2, and the pre-driver circuit 2 applies to the gate terminal of the FET 11 based on the switching command signal S1. A high level switching signal is provided (step S212). Thereafter, the first diagnostic signal detection circuit 3 detects the first diagnostic signal T1, the second diagnostic signal detection circuit 4 detects the second diagnostic signal T2, and these detected first diagnostic signals. T1 and the second diagnostic signal T2 are supplied to the CPU 6, and the CPU 6 determines whether or not the first diagnostic signal T1 and the second diagnostic signal T2 have fallen from the high level to the low level within a predetermined time set in advance. (Step S213).

  As a result of the determination, if both the diagnostic signals do not fall within the specified time, it is determined that an abnormality in the switching (ON → OFF) time of the FET 11 has occurred (step S214). On the other hand, as shown in FIG. 11, when both of the diagnostic signals fall within the specified time, it is determined to be normal, and the next diagnostic operation is started.

  In the next diagnostic operation, the switching signal S5 is changed from low level to high level to turn on the transistor Q1. Thereafter, a command for changing the switching command signal S2 from the low level to the high level and turning the FET 12 on from OFF is given to the pre-driver circuit 2, and the pre-driver circuit 2 applies a high level to the gate terminal of the FET 12 based on the switching command signal S2. A switching signal is given (step S215). Subsequently, the first diagnostic signal detection circuit 3 detects the first diagnostic signal T1, the second diagnostic signal detection circuit 4 detects the second diagnostic signal T2, and these detected first diagnostic signals. T1 and the second diagnostic signal T2 are supplied to the CPU 6, and the CPU 6 determines whether or not the first diagnostic signal T1 and the second diagnostic signal T2 have fallen from the high level to the low level within a predetermined time set in advance. (Step S216).

  As a result of the determination, if both diagnostic signals do not fall within the specified time as shown in FIG. 12, it is determined that the FET 12 has an OFF fault or an abnormal switching (OFF → ON) time. If it falls after a certain time, it is determined that an abnormality in the switching time of the FET 12 has occurred (step S217). On the other hand, as shown in FIG. 13, when both of the diagnostic signals fall within the specified time, it is determined to be normal, and the next diagnostic operation is started.

  In the next diagnostic operation, a command for changing the switching command signal S2 from the high level to the low level to turn off the FET 12 is given to the pre-driver circuit 2, and the pre-driver circuit 2 applies the gate terminal of the FET 12 based on the switching command signal S2. A low level switching signal is applied (step S218). Thereafter, the first diagnostic signal detection circuit 3 detects the first diagnostic signal T1, the second diagnostic signal detection circuit 4 detects the second diagnostic signal T2, and these detected first diagnostic signals. T1 and the second diagnostic signal T2 are supplied to the CPU 6, and the CPU 6 determines whether or not the first diagnostic signal T1 and the second diagnostic signal T2 have risen from the low level to the high level within a predetermined time set in advance. (Step S219).

  As a result of the determination, if both the diagnostic signals do not rise within the specified time, it is determined that an abnormality in the switching (ON → OFF) time of the FET 12 has occurred (step S220). On the other hand, as shown in FIG. 13, when both diagnostic signals rise within a specified time, it is determined that the signal is normal, and the next diagnostic operation is started.

  In the next diagnostic operation, the switching signal S5 is changed from the high level to the low level to turn off the transistor Q1. Thereafter, a command for changing the switching command signal S3 from the low level to the high level to turn on the FET 13 is given to the predriver circuit 2, and the predriver circuit 2 switches the low level to the gate terminal of the FET 13 based on the switching command signal S3. A signal is given (step S221). Subsequently, the first diagnostic signal detection circuit 3 detects the first diagnostic signal T1, the second diagnostic signal detection circuit 4 detects the second diagnostic signal T2, and these detected first diagnostic signals. T1 and the second diagnostic signal T2 are supplied to the CPU 6, and the CPU 6 determines whether or not the first diagnostic signal T1 and the second diagnostic signal T2 have risen from the low level to the high level within a predetermined time set in advance. (Step S222).

  If both diagnosis signals do not rise within the specified time as a result of the determination, it is determined that an FET 13 OFF failure or an abnormal switching (OFF → ON) time has occurred, and the specified time has passed slightly. If it has risen, it is determined that the switching time abnormality of the FET 13 has occurred (step S223). On the other hand, when both the diagnostic signals rise within the specified time, it is determined that the signal is normal, and the next diagnostic operation is started.

  In the next diagnostic operation, a command for changing the switching command signal S3 from the high level to the low level to turn off the FET 13 is given to the pre-driver circuit 2, and the pre-driver circuit 2 applies the gate terminal of the FET 13 based on the switching command signal S3. A high level switching signal is provided (step S224). Thereafter, the first diagnostic signal detection circuit 3 detects the first diagnostic signal T1, the second diagnostic signal detection circuit 4 detects the second diagnostic signal T2, and these detected first diagnostic signals. T1 and the second diagnostic signal T2 are supplied to the CPU 6, and the CPU 6 determines whether or not the first diagnostic signal T1 and the second diagnostic signal T2 have fallen from the high level to the low level within a predetermined time set in advance. (Step S225).

  As a result of the determination, if both the diagnostic signals do not fall within the specified time, it is determined that an abnormality in the switching (ON → OFF) time of the FET 13 has occurred (step S226). On the other hand, if both diagnostic signals fall within the specified time, it is determined that the signal is normal, and the next diagnostic operation is started.

  In the next diagnostic operation, the switching signal S5 is changed from low level to high level to turn on the transistor Q1. Thereafter, the switching command signal S4 is changed from the low level to the high level, and a command for turning the FET 14 from OFF to ON is given to the pre-driver circuit 2, and the pre-driver circuit 2 applies the high level to the gate terminal of the FET 14 based on the switching command signal S4. A switching signal is given (step S227). Subsequently, the first diagnostic signal detection circuit 3 detects the first diagnostic signal T1, the second diagnostic signal detection circuit 4 detects the second diagnostic signal T2, and these detected first diagnostic signals. T1 and the second diagnostic signal T2 are supplied to the CPU 6, and the CPU 6 determines whether or not the first diagnostic signal T1 and the second diagnostic signal T2 have fallen from the high level to the low level within a predetermined time set in advance. (Step S228).

  If both diagnosis signals do not fall within the specified time as a result of the determination, it is determined that the FET 14 has an off failure or an abnormal switching (OFF → ON) time, and the specified time is somewhat If it falls too far, it is determined that an abnormality in the switching time of the FET 14 has occurred (step S229). On the other hand, if both diagnostic signals fall within the specified time, it is determined that the signal is normal, and the next diagnostic operation is started.

  In the next diagnostic operation, a command for changing the switching command signal S4 from a high level to a low level to turn off the FET 12 is given to the pre-driver circuit 2, and the pre-driver circuit 2 applies the gate terminal of the FET 14 based on the switching command signal S4. A low level switching signal is applied (step S230). Thereafter, the first diagnostic signal detection circuit 3 detects the first diagnostic signal T1, the second diagnostic signal detection circuit 4 detects the second diagnostic signal T2, and these detected first diagnostic signals. T1 and the second diagnostic signal T2 are supplied to the CPU 6, and the CPU 6 determines whether or not the first diagnostic signal T1 and the second diagnostic signal T2 have risen from the low level to the high level within a predetermined time set in advance. (Step S231).

  As a result of the determination, if both diagnostic signals do not rise within the specified time, it is determined that an abnormality in the switching (ON → OFF) time of the FET 14 has occurred (step S232). On the other hand, if both the diagnostic signals rise within the specified time, it is determined that all the diagnostic targets are normal (step S233), and the diagnostic operation is terminated.

  Next, with reference to the flowchart shown in FIG. 14 and the timing charts shown in FIGS. 15 to 19, the failure diagnosis in the state where the motor 8 is operating (rotating) due to the current flowing from the motor terminals A to B will be described. To do. In the diagnosis in the operating state of the motor 8, the constant switching signal S5 is set to a low level and the transistor Q1 is turned off.

  In FIG. 14, first, the switching command signals S2 and S3 are set to a low level, the FETs 12 and 13 are turned off, the PWM signal is applied to the FET 11, and the switching control signal S1 is PWM controlled to the pre-driver circuit 2. And a command for changing the switching command signal S4 from the low level to the high level to turn on the FET 14 from the OFF level to the pre-driver circuit 2. As a result, the pre-driver circuit 2 gives a switching signal from a low level to a high level to the gate terminal of the FET 14, and gives a switching command signal S1 to be a PWM signal to the gate terminal of the FET 11 (step S1400).

  Thereafter, the first diagnostic signal detection circuit 3 detects the first diagnostic signal T1, the second diagnostic signal detection circuit 4 detects the second diagnostic signal T2, and these detected first diagnostic signals. T1 and the second diagnostic signal T2 are supplied to the CPU 6, and when the switching command signal S1 is changed from the low level to the high level by the CPU 6, only the first diagnostic signal T1 is changed from the low level to the high level within a preset specified time. It is discriminated whether or not it has started (step S1401).

  As a result of the determination, if the first diagnostic signal T1 does not rise within the specified time, then the first diagnostic signal T1 and the second diagnostic signal when the switching command signal S1 changes from the low level to the high level. It is determined whether or not T2 has risen from a low level to a high level within a preset predetermined time (step S1402). As a result of the determination, when both diagnostic signals rise as shown in FIG. 15, it is determined that an off failure of the FET 14 has occurred (step S1403). When it is determined that the failure has occurred in the FET 14, the switching command signals S1 and S4 are immediately set to the low level to give a command for turning off the FET 11 and the FET 14 to the pre-driver circuit 2, and the driving of the motor 8 is stopped. (Step S1404).

  On the other hand, in the discrimination processing shown in the previous step S1402, if both diagnostic signals do not rise within the specified time as shown in FIGS. 16 and 17, the FET 12 on failure, the FET 11 off failure, the motor terminal It is determined that at least one of the ground faults A and B and the switching (OFF → ON) time failure of the FET 11 has occurred (step S1405). If it is determined that the failure has occurred, the pre-driver circuit 2 is immediately given a command to turn off the FET 11 and the FET 14 by setting the switching command signals S1 and S4 to the low level, and the driving of the motor 8 is stopped (step). S1404).

  On the other hand, when only the first diagnostic signal T1 rises within the specified time as shown in FIG. 18 in the result of the discrimination process shown in the previous step S1401, the switching command signal S1 subsequently changes from the high level to the low level. Whether or not only the first diagnostic signal T1 has fallen from the high level to the low level within a predetermined time set in advance is determined (step S1406).

  As a result of the determination, if the first diagnostic signal T1 does not fall within the specified time, the first diagnostic signal T1 and the second diagnostic when the switching command signal S1 subsequently changes from the high level to the low level. It is determined whether or not the signal T2 falls from a high level to a low level within a preset specified time (step S1407). As a result of the determination, if both diagnostic signals fall as shown in FIG. 15, it is determined that an off failure of the FET 14 has occurred (step S1408). When it is determined that the failure has occurred in the FET 14, the switching command signals S1 and S4 are immediately set to the low level to give a command for turning off the FET 11 and the FET 14 to the pre-driver circuit 2, and the driving of the motor 8 is stopped. (Step S1404).

  On the other hand, if both diagnostic signals do not fall within the specified time as shown in FIG. 19, the FET 11 on failure, the motor terminal A, B power fault, and the FET 11 switching (ON → OFF) time. It is determined that at least one of the above failures has occurred (step S1409). If it is determined that the failure has occurred, the pre-driver circuit 2 is immediately given a command to turn off the FET 11 and the FET 14 by setting the switching command signals S1 and S4 to the low level, and the driving of the motor 8 is stopped (step). S1404).

  On the other hand, if only the first diagnostic signal T1 falls within the specified time as shown in FIG. 18 in the result of the discrimination processing shown in the previous step S1406, it is judged that it is normal (step S1410). Returning to the process shown in the previous step S1401, the diagnostic failure procedure is repeated.

  Next, with reference to the flowchart shown in FIG. 20, a failure diagnosis in a state where a current flows from the motor terminal B to A and the motor 8 is operating (rotating) will be described.

  In FIG. 20, first, the switching command signals S1 and S4 are set to a low level, the FETs 11 and 14 are turned off, and the switching command signal S3 is supplied to the pre-driver circuit 2 so that the PWM signal is applied to the FET 13 and the FET 13 is PWM controlled. And a command for changing the switching command signal S2 from the low level to the high level to turn on the FET 12 from the OFF level to the pre-driver circuit 2. As a result, the pre-driver circuit 2 gives a switching signal from a low level to a high level to the gate terminal of the FET 12, and gives a switching command signal S3 to be a PWM signal to the gate terminal of the FET 13 (step S2000).

  Thereafter, the first diagnostic signal detection circuit 3 detects the first diagnostic signal T1, the second diagnostic signal detection circuit 4 detects the second diagnostic signal T2, and these detected first diagnostic signals. T1 and the second diagnostic signal T2 are supplied to the CPU 6, and when the switching command signal S3 is changed from the low level to the high level by the CPU 6, only the second diagnostic signal T2 is changed from the low level to the high level within a preset specified time. It is discriminated whether or not it has started up (step S2001).

  As a result of the determination, if the second diagnostic signal does not rise within the specified time, the first diagnostic signal T1 and the second diagnostic signal T2 when the switching command signal S3 subsequently changes from the low level to the high level. It is determined whether or not has risen from the low level to the high level within a preset predetermined time (step S2002). If both diagnosis signals rise as a result of the determination, it is determined that an off failure of the FET 12 has occurred (step S2003). When it is determined that the failure has occurred in the FET 12, the switching command signals S2 and S3 are immediately set to the low level to give a command for turning off the FET 12 and the FET 13 to the pre-driver circuit 2, and the driving of the motor 8 is stopped. (Step S2004).

  On the other hand, in the discrimination processing shown in the previous step S2002, if both diagnostic signals do not rise within the specified time, the FET 14 on failure, the FET 13 off failure, the ground fault of the motor terminals A and B, the FET 13 It is determined that at least one failure of the switching (OFF → ON) time has occurred (step S2005). If it is determined that the failure has occurred, the pre-driver circuit 2 is immediately given a command to turn off the FET 12 and the FET 13 by setting the switching command signals S2 and S3 to the low level, and the driving of the motor 8 is stopped (step). S2004).

  On the other hand, if only the second diagnostic signal T2 rises within the specified time in the result of the discrimination process shown in the previous step S2001, the second time when the switching command signal S3 changes from the high level to the low level. It is determined whether only the diagnostic signal T2 has fallen from the high level to the low level within a preset predetermined time (step S2006).

  If the second diagnostic signal T2 does not fall within the specified time as a result of the determination, the first diagnostic signal T1 and the second diagnostic are subsequently detected when the switching command signal S3 changes from the high level to the low level. It is determined whether or not the signal T2 falls from the high level to the low level within a preset specified time (step S2007). If both diagnosis signals fall as a result of the determination, it is determined that an off failure of the FET 12 has occurred (step S2008). When it is determined that the failure has occurred in the FET 12, the switching command signals S2 and S3 are immediately set to the low level to give a command for turning off the FET 12 and the FET 13 to the pre-driver circuit 2, and the driving of the motor 8 is stopped. (Step S2004).

  On the other hand, if both diagnosis signals do not fall within the specified time, at least one of FET 13 ON failure, motor terminal A and B power fault, and FET 13 switching (ON → OFF) time failure. It is determined that a failure has occurred (step S2009). If it is determined that the failure has occurred, the pre-driver circuit 2 is immediately given a command to turn off the FET 12 and the FET 13 by setting the switching command signals S2 and S3 to the low level, and the driving of the motor 8 is stopped (step). S2004).

  On the other hand, when only the second diagnostic signal T2 falls within the specified time in the result of the discrimination process shown in the previous step S2006, it is determined that it is normal (step S2010), and in the previous step S2001. Returning to the process shown, the above-described diagnostic failure procedure is repeated.

  As described above, in the above-described embodiment, the first diagnostic signal detection circuit 3 and the second diagnostic signal detection circuit 4 employ a configuration that does not use a capacitor. The rising / falling change of the second diagnostic signal T2 can be taken into the CPU 6 without dulling. As a result, even if the on-duty of the PWM signal is very large or very small, the CPU 6 synchronizes with the rising / rising change of the switching command signals (S1 to S4). Changes in the diagnostic signal T1 and the second diagnostic signal T2 can be detected. Therefore, based on the detection result, not only when the motor 8 is stopped but also when the motor 8 is operating (during PWM control), the switching element ON failure, OFF failure, motor terminals A and B power supply fault, ground fault failure Can be reliably detected.

  Further, in the failure diagnosis during the operation of the motor 8, the failure diagnosis can be started from the time when the PWM control of the motor 8 is started, so that the failure diagnosis can be performed in a shorter time than the conventional case. .

  Further, even when the operating frequency in the PWM control is high, the CPU 6 detects rising / falling of the first diagnostic signal T1 and the second diagnostic signal T2 in synchronization with the switching command signals (S1 to S4). By adopting the configuration, it is possible to reliably detect the switching time of the switching element even during motor operation (during PWM control), and it is possible to perform fault diagnosis of abnormalities that affect the switching time of the switching element. . Here, the abnormality affecting the switching time includes, for example, an abnormality in the resistance component and inductance component of the motor 8 in addition to the abnormality in the switching element itself. If an abnormality occurs in the resistance component or the inductance component of the motor 8, the switching time of the switching element varies. Therefore, the CPU 6 can diagnose the failure as an abnormality in the switching time of the switching element.

  In this way, according to the present invention, it is possible to carry out failure diagnosis over a wider range than in the prior art as shown in FIG. 21 not only when the motor 8 is stopped but also when the motor 8 is operating (PWM control). Become.

It is a figure which shows the structure of the motor drive control apparatus which concerns on Example 1 of this invention. It is a flowchart which shows the procedure of the failure diagnosis process at the time of the stop of the motor which concerns on Example 1 of this invention. It is a flowchart which shows the procedure of the failure diagnosis process at the time of the stop of the motor which concerns on Example 1 of this invention. It is a timing chart of each signal in failure diagnosis at the time of a motor stop concerning Example 1 of the present invention. It is a timing chart of each signal in failure diagnosis at the time of a motor stop concerning Example 1 of the present invention. It is a timing chart of each signal in failure diagnosis at the time of a motor stop concerning Example 1 of the present invention. It is a timing chart of each signal in failure diagnosis at the time of a motor stop concerning Example 1 of the present invention. It is a timing chart of each signal in failure diagnosis at the time of a motor stop concerning Example 1 of the present invention. It is a timing chart of each signal in failure diagnosis at the time of a motor stop concerning Example 1 of the present invention. It is a timing chart of each signal in failure diagnosis at the time of a motor stop concerning Example 1 of the present invention. It is a timing chart of each signal in failure diagnosis at the time of a motor stop concerning Example 1 of the present invention. It is a timing chart of each signal in failure diagnosis at the time of a motor stop concerning Example 1 of the present invention. It is a timing chart of each signal in failure diagnosis at the time of a motor stop concerning Example 1 of the present invention. It is a timing chart of each signal in failure diagnosis at the time of a motor stop concerning Example 1 of the present invention. It is a flowchart which shows the procedure of the failure diagnosis process at the time of operation | movement of the motor which concerns on Example 1 of this invention. It is a timing chart of each signal in failure diagnosis at the time of motor operation concerning Example 1 of the present invention. It is a timing chart of each signal in failure diagnosis at the time of motor operation concerning Example 1 of the present invention. It is a timing chart of each signal in failure diagnosis at the time of motor operation concerning Example 1 of the present invention. It is a timing chart of each signal in failure diagnosis at the time of motor operation concerning Example 1 of the present invention. It is a timing chart of each signal in failure diagnosis at the time of motor operation concerning Example 1 of the present invention. It is a flowchart which shows the procedure of the failure diagnosis process at the time of operation | movement of the motor which concerns on Example 1 of this invention. It is a figure which shows the failure which can be diagnosed in the past and this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... H bridge circuit 2 ... Pre-driver circuit 3 ... 1st diagnostic signal detection circuit 4 ... 2nd diagnostic signal detection circuit 5 ... Switching circuit 6 ... CPU
7 ... Battery power supply 8 ... Motor 11, 12, 13, 14 ... FET
Q1 ... transistor R1, R2, R3, R4, R5 ... resistance

Claims (3)

In a motor drive control device that controls driving of a motor by supplying a drive current to the motor by controlling conduction of a plurality of switching elements constituting the bridge circuit based on a switching command signal given from the control means,
A signal detection unit configured by a resistance component and detecting a first diagnostic signal output to one terminal of the motor and a second diagnostic signal output to the other terminal of the motor;
Current supply means for selectively supplying a diagnostic current to the bridge circuit at the time of failure diagnosis of the switching element when the motor is stopped;
The control means selectively controls conduction of the plurality of switching elements at the time of failure diagnosis of the switching elements, and as a result, inputs the first diagnosis signal and the second diagnosis signal detected by the signal detection means, A motor drive control device characterized by detecting rising / falling edges of an input first diagnostic signal and second diagnostic signal and diagnosing at least a failure of the switching element based on the detection result. The control means detects rising / falling of the first diagnostic signal and the second diagnostic signal within a preset specified time, and detects at least a failure of the switching element based on the detection result. The motor drive control device according to claim 1. 3. The motor drive control device according to claim 1, wherein the control unit selectively controls conduction of the switching element by PWM control and operates the motor to diagnose a failure of the switching element. 4. .

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