JP2008187060A - Mesa semiconductor element and method for manufacturing the same - Google Patents

Mesa semiconductor element and method for manufacturing the same Download PDF

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JP2008187060A
JP2008187060A JP2007020233A JP2007020233A JP2008187060A JP 2008187060 A JP2008187060 A JP 2008187060A JP 2007020233 A JP2007020233 A JP 2007020233A JP 2007020233 A JP2007020233 A JP 2007020233A JP 2008187060 A JP2008187060 A JP 2008187060A
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oxide film
silicon oxide
mesa
semiconductor substrate
forming
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Mitsuhiro Takeshita
充大 竹下
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a mesa semiconductor element, capable of having a high reliability and stable electrical characteristics and excluding factors containing environmentally hazardous substances, and to provide a method for manufacturing the same. <P>SOLUTION: The mesa semiconductor element 100 capable of excluding the factors, containing the environmentally hazardous substances while securing stability and reliability in electrical characteristics, is obtained by allowing a silicon oxide film 1a coating a slanted side in the mesa section 111 of a semiconductor substrate 102 to contain an Al ions to be charged fixedly and negatively, even if lead or zinc is not doped to the film. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明はメサ型半導体素子とその製造方法に関し、半導体素子の耐圧性、耐湿性、耐薬品性の技術に係るものである。   The present invention relates to a mesa semiconductor device and a method for manufacturing the same, and relates to a technology of pressure resistance, moisture resistance, and chemical resistance of the semiconductor device.

従来のメサ型半導体素子としては、例えば図3に示すように、半導体基体のメサ部を形成する傾斜側面がガラス粒子を含む樹脂で皮覆されているものが有った。
図3において、101はダイオード、102は半導体基体、103はアノード電極、104はカソード電極、105は保護膜、106はP型半導体領域、107はN型半導体領域、108はN型半導体領域、109は半導体基体の一方の主面、110は半導体基体の他方の主面、111は傾斜側面、112はPN接合、113は絶縁性樹脂、114はガラス粒子を示している。
As a conventional mesa type semiconductor element, for example, as shown in FIG. 3, there is one in which an inclined side surface forming a mesa portion of a semiconductor substrate is covered with a resin containing glass particles.
In FIG. 3, 101 is a diode, 102 is a semiconductor substrate, 103 is an anode electrode, 104 is a cathode electrode, 105 is a protective film, 106 is a P-type semiconductor region, 107 is an N type semiconductor region, and 108 is an N + type semiconductor region. , 109 is one main surface of the semiconductor substrate, 110 is the other main surface of the semiconductor substrate, 111 is an inclined side surface, 112 is a PN junction, 113 is an insulating resin, and 114 is a glass particle.

このメサ型半導体素子からなるダイオード101は、半導体基体102が第1層の高濃度のN型半導体領域108の上面にエピタキシャル層をなす複数の半導体結晶薄膜を形成してなり、N型半導体領域108の上面に同じ導電型をなす第2層の低濃度のN型半導体領域107を形成し、N型半導体領域107の上面に異なる導電型をなす第3層のP型半導体領域106を形成しており、N型半導体領域107とP型半導体領域106とがPN接合112を形成している。 Diode 101 consisting of the mesa type semiconductor device is made by forming a plurality of semiconductor crystal thin film semiconductor body 102 forms an epitaxial layer on the upper surface of the high-concentration N + -type semiconductor region 108 of the first layer, the N + -type semiconductor A second layer low concentration N type semiconductor region 107 having the same conductivity type is formed on the upper surface of the region 108, and a third layer P type semiconductor region 106 having a different conductivity type is formed on the upper surface of the N type semiconductor region 107. The N type semiconductor region 107 and the P type semiconductor region 106 form a PN junction 112.

半導体基体102の一方の主面109をなすP型半導体領域106の上面にアノード電極103を形成し、半導体基体102の他方の主面110をなすN型半導体領域108の下面にカソード電極104を形成している。半導体基体102は周囲に凹状の傾斜側面をなすメサ部111を形成しており、メサ部111を覆って保護膜105を形成している。保護膜105はガラス粒子114を含むエポキシ等の絶縁性樹脂113からなる。 An anode electrode 103 is formed on the upper surface of the P-type semiconductor region 106 that forms one main surface 109 of the semiconductor substrate 102, and a cathode electrode 104 is formed on the lower surface of the N + -type semiconductor region 108 that forms the other main surface 110 of the semiconductor substrate 102. Forming. The semiconductor substrate 102 is formed with a mesa portion 111 having a concave inclined side surface, and a protective film 105 is formed covering the mesa portion 111. The protective film 105 is made of an insulating resin 113 such as epoxy containing glass particles 114.

この構成によれば、メサ部111を皮覆する保護膜105が負電荷を帯びるガラス粒子114を含んでいるので、ガラス粒子114が帯びる負電荷によって安定した耐圧性を得ることができるとともに、ガラスからなる通常の保護膜を形成する際の温度に比して絶縁性樹脂113を硬化させる際の熱処理は低温で行なえるので製造プロセスの自由度を上げることができた。先行技術文献としては、特許文献1がある。
特開2001−110799号公報
According to this configuration, since the protective film 105 covering the mesa unit 111 includes the negatively charged glass particles 114, it is possible to obtain stable pressure resistance due to the negative charges of the glass particles 114, and the glass Since the heat treatment for curing the insulating resin 113 can be performed at a low temperature as compared with the temperature for forming the normal protective film made of, the degree of freedom of the manufacturing process can be increased. There exists patent document 1 as a prior art document.
JP 2001-110799 A

しかしながら、従来の構成では、保護膜105が樹脂からなるために耐湿性や耐薬品性等に劣り、信頼性が低くなる課題があった。
また、保護膜105中のガラス粒子114の分布には均一性が求められるが、不均一が生じた場合には、耐圧を含む逆方向の電気特性のバラツキや、元来樹脂が有する可動イオンの影響を打ち消す作用が阻害されるので、電気特性不安定等の不具合を生じる課題を有していた。
However, in the conventional configuration, since the protective film 105 is made of a resin, there is a problem that the moisture resistance and chemical resistance are inferior and the reliability is lowered.
In addition, the distribution of the glass particles 114 in the protective film 105 is required to be uniform, but when non-uniformity occurs, the electrical characteristics in the reverse direction including the withstand voltage and the mobile ions that the resin originally has are not uniform. Since the effect of canceling the influence is hindered, there is a problem that causes problems such as instability of electric characteristics.

また、ガラス粒子114に負電荷を帯びさせるためには、ガラス粒子114が鉛や亜鉛等の環境負荷物質を含まねばならない課題も有していた。
本発明は上記の課題を解決するものであり、耐湿性・耐薬品性に優れて安定した負電荷を得ることができ、しかも鉛や亜鉛等の環境負荷物質を含むことのない保護膜を有し、信頼性と安定した電気特性に優れたメサ型半導体素子とその製造方法を提供することを目的とする。
Moreover, in order to make the glass particles 114 have a negative charge, the glass particles 114 have a problem that they must contain an environmentally hazardous substance such as lead or zinc.
The present invention solves the above-mentioned problems, has a moisture and chemical resistance, can obtain a stable negative charge, and has a protective film that does not contain environmentally hazardous substances such as lead and zinc. It is an object of the present invention to provide a mesa semiconductor device having excellent reliability and stable electrical characteristics and a method for manufacturing the mesa semiconductor device.

上記の課題を解決するために、本発明のメサ型半導体素子は、半導体基体がメサ形状である半導体素子であって、前記半導体基体のメサ部をなす傾斜側面を被覆してAlイオンを含むシリコン酸化膜を形成したことを特徴とする。   In order to solve the above-described problems, a mesa semiconductor device according to the present invention is a semiconductor device having a mesa-shaped semiconductor substrate, which covers a slanted side surface forming a mesa portion of the semiconductor substrate and contains Al ions. An oxide film is formed.

本発明のメサ型半導体素子は、半導体基体がメサ形状である半導体素子であって、前記半導体基体のメサ部をなす傾斜側面を被覆してAl、Cl、Fの何れか一種または複数種のイオンを含むシリコン酸化膜を形成したことを特徴とする。   The mesa type semiconductor device of the present invention is a semiconductor device having a mesa-shaped semiconductor substrate, and covers one or more ions of Al, Cl, and F covering an inclined side surface forming a mesa portion of the semiconductor substrate. A silicon oxide film containing is formed.

本発明のメサ型半導体素子の製造方法は、メサ形状の半導体基体において、メサ部をなす傾斜側面を皮覆してシリコン酸化膜を形成し、前記シリコン酸化膜にAlをイオン注入して前記シリコン酸化膜をAlイオンを含むシリコン酸化膜となすことを特徴とする。   According to the method of manufacturing a mesa semiconductor device of the present invention, in a mesa-shaped semiconductor substrate, a silicon oxide film is formed by covering an inclined side surface forming a mesa portion, and Al is ion-implanted into the silicon oxide film to form the silicon oxide film. The film is a silicon oxide film containing Al ions.

本発明のメサ型半導体素子の製造方法は、メサ形状の半導体基体において、メサ部をなす傾斜側面を皮覆してシリコン酸化膜を形成し、前記シリコン酸化膜にAl、Cl、Fの何れか一種または複数種をイオン注入し、前記シリコン酸化膜をAl、Cl、Fの何れか一種または複数種のイオンを含むシリコン酸化膜とすることを特徴とする。   According to the method of manufacturing a mesa type semiconductor element of the present invention, a silicon oxide film is formed by covering an inclined side surface forming a mesa portion in a mesa-shaped semiconductor substrate, and any one of Al, Cl, and F is formed on the silicon oxide film. Alternatively, a plurality of types of ions are implanted, and the silicon oxide film is made of a silicon oxide film containing any one kind or a plurality of kinds of ions of Al, Cl, and F.

本発明のメサ型半導体素子の製造方法は、シリコンからなる第1層の高濃度半導体領域の上に同じ導電型をなす第2層の低濃度半導体領域をエピタキシャル成長によって形成し、前記低濃度半導体領域の表面から層内へ異なる導電型のドーパントを拡散させて第3層の半導体領域を形成し、前記第3層の半導体領域と前記第2層の低濃度半導体領域との界面を半導体接合面として半導体基体を形成する半導体基体形成工程と、前記半導体基体の一方の主面の外周に沿って、かつ前記高濃度半導体領域に達する側面をメサエッチングし、前記半導体基体の外周にメサ部をなす傾斜側面を形成して前記半導体基体をメサ形状となすメサ形成工程と、熱酸化法にて、前記半導体基体の一方の主面から前記傾斜側面にかけてシリコン酸化膜を形成する酸化膜形成工程と、前記半導体基体の一方の主面に対応するシリコン酸化膜をマスクで覆い、前記傾斜側面上の前記シリコン酸化膜にAlをイオン注入して前記傾斜側面上にAlイオンを含むシリコン酸化膜を形成するイオン注入工程と、前記シリコン酸化膜に選択的エッチング除去を施して、前記半導体基体の一方の主面をなす前記第3層の半導体領域を露出させ、前記第3層の半導体領域の表面から前記シリコン酸化膜の周辺へ延在するアノード電極を形成し、前記半導体基体の他方の主面をなす前記高濃度半導体領域を研削研磨して厚み調整し、前記高濃度半導体領域の表面にカソード電極を形なする電極形成工程とを含むことを特徴とする。   According to the method of manufacturing a mesa semiconductor device of the present invention, a low-concentration semiconductor region of the second layer having the same conductivity type is formed by epitaxial growth on a high-concentration semiconductor region of the first layer made of silicon, and the low-concentration semiconductor region A semiconductor layer of the third layer is formed by diffusing dopants of different conductivity types from the surface of the semiconductor layer into the layer, and an interface between the semiconductor region of the third layer and the low-concentration semiconductor region of the second layer is used as a semiconductor junction surface Semiconductor substrate forming step of forming a semiconductor substrate, and mesa etching along the outer periphery of one main surface of the semiconductor substrate and reaching the high-concentration semiconductor region, and an inclination forming a mesa portion on the outer periphery of the semiconductor substrate A silicon oxide film is formed from one main surface of the semiconductor substrate to the inclined side surface by a mesa forming step of forming a side surface to make the semiconductor substrate into a mesa shape and a thermal oxidation method. A silicon oxide film corresponding to one main surface of the semiconductor substrate is covered with a mask, Al ions are implanted into the silicon oxide film on the inclined side surface, and Al ions are included on the inclined side surface. An ion implantation step of forming a silicon oxide film, and selective etching removal of the silicon oxide film to expose the semiconductor region of the third layer that forms one main surface of the semiconductor substrate; Forming an anode electrode extending from the surface of the semiconductor region to the periphery of the silicon oxide film, grinding and polishing the high-concentration semiconductor region forming the other main surface of the semiconductor substrate, and adjusting the thickness; Forming a cathode electrode on the surface of the substrate.

以上のように本発明によれば、メサ形状の半導体基体のメサ部をなす傾斜側面上に形成するシリコン酸化膜が、少なくともAl、Cl、Fの何れか一種のイオンを含むことで、固定的に負電荷を帯びた状態となるので安定した電気特性を確保できる。また、半導体基体の傾斜側面を皮覆するものはシリコン酸化膜であるので、耐湿性と耐薬品性とに優れたものとすることが可能であり、信頼性に優れた半導体素子となる。更に、シリコン酸化膜には、鉛や亜鉛等の元素を添加することが無いので環境負荷物質を含む要素を除外することができる。   As described above, according to the present invention, the silicon oxide film formed on the inclined side surface forming the mesa portion of the mesa-shaped semiconductor substrate contains at least one of Al, Cl, and F ions, so that the fixed Therefore, a stable electrical characteristic can be secured. Moreover, since what covers the inclined side surface of the semiconductor substrate is a silicon oxide film, it can be excellent in moisture resistance and chemical resistance, and a semiconductor element having excellent reliability can be obtained. Furthermore, since elements such as lead and zinc are not added to the silicon oxide film, elements including environmentally hazardous substances can be excluded.

以下、本発明の実施の形態について図面を参照しながら説明する。図1は、本発明の実施の形態におけるメサ型半導体素子を示すものであり、先に図3において説明したものと同じ構成要素については同符号を用いてその説明を省略する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a mesa semiconductor device according to an embodiment of the present invention. The same components as those described in FIG.

図1において、1はシリコン酸化膜、1aはAlイオンを含むシリコン酸化膜、3は半導体基体の一方の主面、4は半導体基体の他方の主面、100はメサ型半導体素子を示している。   In FIG. 1, 1 is a silicon oxide film, 1a is a silicon oxide film containing Al ions, 3 is one main surface of a semiconductor substrate, 4 is the other main surface of the semiconductor substrate, and 100 is a mesa semiconductor element. .

図1に示すように、シリコン酸化膜1は、半導体基体102の一方の主面3であるP型半導体領域106の表面の周部から半導体基体102の傾斜側面をなすメサ部111の上方領域にかけて覆っており、特にメサ部111の傾斜側面を皮覆する部分は、負電荷を固定的に帯びるAlイオンを含むシリコン酸化膜1aからなる。   As shown in FIG. 1, the silicon oxide film 1 extends from the peripheral portion of the surface of the P-type semiconductor region 106, which is one main surface 3 of the semiconductor substrate 102, to the region above the mesa portion 111 that forms the inclined side surface of the semiconductor substrate 102. In particular, the portion covering the inclined side surface of the mesa 111 is made of the silicon oxide film 1a containing Al ions that are negatively charged.

この構成において、メサ部111の傾斜側面に露出するPN接合112が耐圧性等の素子特性に大きく影響する要素であるが、Alイオンを含むシリコン酸化膜1aでメサ部111を覆うことによりPN接合112が外部からの影響を受けにくくなり、従来のような鉛や亜鉛等の環境負荷物質を含まずとも、Alイオンを含むことで信頼性の向上と安定した耐圧性が得られるメサ型半導体素子が実現できる。しかも、シリコン酸化膜1aのシリコンの特性により耐湿性と耐薬品性に優れたものとすることができる。   In this configuration, the PN junction 112 exposed on the inclined side surface of the mesa portion 111 is an element that greatly affects the element characteristics such as pressure resistance. By covering the mesa portion 111 with the silicon oxide film 1a containing Al ions, the PN junction is covered. 112 is less susceptible to external influences, and a mesa type semiconductor device that can improve reliability and have stable pressure resistance by including Al ions without including environmentally hazardous substances such as lead and zinc as in the prior art. Can be realized. Moreover, the silicon oxide film 1a can be excellent in moisture resistance and chemical resistance due to the characteristics of silicon.

メサ部111に形成したAlイオンを含むシリコン酸化膜1aの上にさらに重ねてシリコン酸化膜を形成することで、メサ部111をより強固に保護する構成としても良い。
尚、本実施の形態では、半導体基体102がN型半導体領域108とN型半導体領域107とP型半導体領域106とで形成され、P型半導体領域106とN型半導体領域107との界面をPN接合112とするダイオードを例示して説明した。しかし、本発明は上述した構成に限定されるものではなく、メサ形状をなす半導体基体を用いて耐圧構造を得るものであるならばトランジスタ等の半導体素子一般に対して適用が可能である。
The mesa portion 111 may be more strongly protected by forming a silicon oxide film on the silicon oxide film 1a containing Al ions formed on the mesa portion 111.
In the present embodiment, the semiconductor substrate 102 is formed of the N + type semiconductor region 108, the N type semiconductor region 107, and the P type semiconductor region 106, and the P type semiconductor region 106 and the N type semiconductor region 107. The diode having the PN junction 112 as an interface has been described as an example. However, the present invention is not limited to the configuration described above, and can be applied to general semiconductor elements such as transistors as long as a withstand voltage structure is obtained using a semiconductor substrate having a mesa shape.

また、Alイオンを含むシリコン酸化膜1aでメサ部111を皮覆したが、Alイオンに替えてClイオンまたはFイオンを含むシリコン酸化膜としても同様の効果を得ることができる。   Further, although the mesa portion 111 is covered with the silicon oxide film 1a containing Al ions, the same effect can be obtained by using a silicon oxide film containing Cl ions or F ions instead of Al ions.

以下に本発明のメサ型半導体素子100の製造方法を説明する。図2(a)〜(e)はメサ型半導体素子100の製造過程の主な工程終了時点を示すものである。図2において、1はシリコン酸化膜、1aはAlイオンを含むシリコン酸化膜、2はマスク、3は半導体基体の一方の主面、4は半導体基体の他方の主面、102は半導体基体、103はアノード電極、104はカソード電極、106はP型半導体領域、107はN型半導体領域、108はN型半導体領域、111は傾斜側面、112はPN接合を示している。 A method for manufacturing the mesa semiconductor device 100 of the present invention will be described below. 2A to 2E show main process end points in the manufacturing process of the mesa semiconductor device 100. FIG. In FIG. 2, 1 is a silicon oxide film, 1a is a silicon oxide film containing Al ions, 2 is a mask, 3 is one main surface of the semiconductor substrate, 4 is the other main surface of the semiconductor substrate, 102 is a semiconductor substrate, 103 Denotes an anode electrode, 104 denotes a cathode electrode, 106 denotes a P-type semiconductor region, 107 denotes an N type semiconductor region, 108 denotes an N + type semiconductor region, 111 denotes an inclined side surface, and 112 denotes a PN junction.

図2(a)は半導体基体形成工程を示すものであり、シリコンからなる第1層の高濃度のN型半導体領域108の上にエピタキシャル成長によって同じ導電型をなす第2層の低濃度のN型半導体領域107を形成し、N型半導体領域107の表面からその層内へP型ドーパントを拡散させて異なる導電型をなす第3層のP型半導体領域106を形成し、P型半導体領域106とN型半導体領域107との界面を半導体接合面であるPN接合112として半導体基体102を形成する。 FIG. 2A shows a semiconductor substrate forming step, and a second layer low concentration N having the same conductivity type is formed on the first layer high concentration N + type semiconductor region 108 made of silicon by epitaxial growth. A − type semiconductor region 107 is formed, and a P type dopant is diffused from the surface of the N type semiconductor region 107 into the layer to form a third layer P type semiconductor region 106 having different conductivity types. The semiconductor substrate 102 is formed with the interface between the region 106 and the N type semiconductor region 107 as a PN junction 112 which is a semiconductor junction surface.

以下において、半導体基体102のP型半導体領域106の表面を半導体基体102の一方の主面3とし、この主面3と表裏をなす反対側のN型半導体領域108の表面を半導体基体102の他方の主面4とする。 Hereinafter, the surface of the P-type semiconductor region 106 of the semiconductor substrate 102 is defined as one main surface 3 of the semiconductor substrate 102, and the surface of the N + -type semiconductor region 108 opposite to the main surface 3 is the surface of the semiconductor substrate 102. The other main surface 4 is used.

図2(b)はメサ形成工程を示すものであり、先の半導体基体形成工程の後に、半導体基体102の一方の主面3の外周に沿って、かつN型半導体領域108に達する側面をメサエッチングし、半導体基体102の外周に傾斜側面のメサ部111を形成して半導体基体102をメサ形状とする。 FIG. 2B shows a mesa formation process. After the previous semiconductor substrate formation process, a side surface that reaches the N + type semiconductor region 108 along the outer periphery of one main surface 3 of the semiconductor substrate 102. Mesa etching is performed to form inclined mesa portions 111 on the outer periphery of the semiconductor substrate 102 to make the semiconductor substrate 102 a mesa shape.

図2(c)は酸化膜形成工程を示すものであり、先のメサ形成工程の後に、熱酸化法にて、半導体基体102の一方の主面3、および傾斜側面をなすメサ部111にかけてシリコン酸化膜1を形成する。   FIG. 2 (c) shows an oxide film forming step. After the previous mesa forming step, silicon is applied to one main surface 3 of the semiconductor substrate 102 and the mesa portion 111 forming the inclined side surface by thermal oxidation. An oxide film 1 is formed.

ここで、シリコン酸化膜を形成する方法としては、熱酸化法以外に、熱CVDやプラズマCVDで行っても良い。
図2(d)はイオン注入工程を示すものであり、先の酸化膜形成工程の後に、半導体基体102の一方の主面3に対応するシリコン酸化膜1をマスク2で覆い、シリコン酸化膜1のうちで傾斜側面をなすメサ部111に形成された部分のみにAlをイオン注入し、メサ部111の上にAlイオンを含むシリコン酸化膜1aを形成する。
Here, as a method of forming the silicon oxide film, thermal CVD or plasma CVD may be used in addition to the thermal oxidation method.
FIG. 2D shows an ion implantation process. After the previous oxide film forming process, the silicon oxide film 1 corresponding to one main surface 3 of the semiconductor substrate 102 is covered with a mask 2, and the silicon oxide film 1 is formed. Among them, Al is ion-implanted only into the portion formed in the mesa portion 111 having the inclined side surface, and the silicon oxide film 1 a containing Al ions is formed on the mesa portion 111.

前述したように、従来では保護膜中のガラス粒子の分布を確実に均一なものとすることが困難であるために、電気特性不安定等の不具合を生じることがあった。しかし、本実施の形態では、イオン注入を行なうことで、シリコン酸化膜1aの層中にAlイオンを確実に均一に分布させることができ、耐圧を含む逆方向の電気特性のバラツキをなくすことができ、電気特性不安定等の不具合が生じないメサ型半導体素子100を実現できる。   As described above, conventionally, it has been difficult to ensure a uniform distribution of the glass particles in the protective film, which may cause inconveniences such as unstable electrical characteristics. However, in this embodiment, by performing ion implantation, Al ions can be reliably distributed uniformly in the layer of the silicon oxide film 1a, and variations in reverse electrical characteristics including breakdown voltage can be eliminated. The mesa type semiconductor device 100 can be realized without inconveniences such as unstable electrical characteristics.

ここで、イオン注入の後に熱処理を施してアニーリングし、Alイオンを含むシリコン酸化膜1aの膜質改善と電荷の活性化を行っても良い。また、Alイオンを含むシリコン酸化膜1aの上に、更に上述の方法でシリコン酸化膜を形成して保護膜としての信頼性を高めても良い。   Here, heat treatment may be performed after ion implantation and annealing may be performed to improve the film quality of the silicon oxide film 1a containing Al ions and to activate the charge. Further, a silicon oxide film may be further formed on the silicon oxide film 1a containing Al ions by the above-described method to improve the reliability as a protective film.

尚、イオン注入の照射角度は特に限定しないが、メサ部111の傾斜面に合わせて斜め方向に照射しても良い。これによれば、イオン注入の照射効率を高めることができる。
図2(e)は電極形成工程を示すものであり、先のイオン注入工程の後に、シリコン酸化膜1に選択的エッチング除去を施して半導体基体102の一方の主面3であるP型半導体領域106を露出させ、P型半導体領域106の表面からシリコン酸化膜1の周辺へ延在するAl等からなるアノード電極を形成する。そして、半導体基体102の他方の主面4であるN型半導体領域108を研削研磨して厚み調整し、N型半導体領域108の表面に金や銀等を最表に有する多層または単層のカソード電極104を形成することにより、図1に示すメサ型半導体素子とする。
The irradiation angle of ion implantation is not particularly limited, but irradiation may be performed in an oblique direction in accordance with the inclined surface of the mesa unit 111. According to this, the irradiation efficiency of ion implantation can be increased.
FIG. 2E shows an electrode formation process. After the previous ion implantation process, the silicon oxide film 1 is selectively etched away to form a P-type semiconductor region which is one main surface 3 of the semiconductor substrate 102. 106 is exposed and an anode electrode made of Al or the like extending from the surface of the P-type semiconductor region 106 to the periphery of the silicon oxide film 1 is formed. Then, the N + type semiconductor region 108 which is the other main surface 4 of the semiconductor substrate 102 is ground and polished to adjust the thickness, and the surface of the N + type semiconductor region 108 is a multilayer or single layer having gold, silver or the like as the outermost surface. By forming the cathode electrode 104, the mesa type semiconductor element shown in FIG. 1 is obtained.

ここでは、一例としてイオン注入の後にシリコン酸化膜1に選択的エッチング除去を施す製造過程としたが、イオン注入の前にシリコン酸化膜1に選択的エッチング除去を施し、マスク2で覆ってイオン注入を施しても良い。   Here, as an example, a manufacturing process in which the silicon oxide film 1 is selectively etched and removed after the ion implantation is performed. However, the silicon oxide film 1 is selectively etched and removed before the ion implantation, and the mask 2 is covered with the ion implantation. May be applied.

尚、本実施の形態では、半導体基体102がN型半導体領域108とN型半導体領域107とP型半導体領域106とで形成され、P型半導体領域106とN型半導体領域107との界面をPN接合112とするダイオードを例示して説明したが、双方の導電型を入れ替えて実施することも可能である。その場合、アノード電極とカソード電極も入れ替わることとなる。 In the present embodiment, the semiconductor substrate 102 is formed of the N + type semiconductor region 108, the N type semiconductor region 107, and the P type semiconductor region 106, and the P type semiconductor region 106 and the N type semiconductor region 107. Although the diode having the PN junction 112 as an example has been described, it is also possible to carry out by exchanging both conductivity types. In that case, the anode electrode and the cathode electrode are also exchanged.

本発明はメサ型半導体素子として有用であり、特に環境負荷物質を含むことなく電気的に安定で信頼性を必要なものに適している。   The present invention is useful as a mesa-type semiconductor device, and is particularly suitable for a device that is electrically stable and requires reliability without containing an environmental load substance.

本発明の実施の形態におけるメサ型半導体素子の断面図Sectional drawing of the mesa type semiconductor element in embodiment of this invention 本発明の実施の形態におけるメサ型半導体素子の製造過程を示す断面図Sectional drawing which shows the manufacturing process of the mesa type semiconductor element in embodiment of this invention 従来の半導体素子の断面図Sectional view of a conventional semiconductor device

符号の説明Explanation of symbols

1 シリコン酸化膜
1a Alイオンを含むシリコン酸化膜
2 マスク
3 半導体基体の一方の主面
4 半導体基体の他方の主面
100 メサ型半導体素子
101 ダイオード
102 半導体基体
103 アノード電極
104 カソード電極
105 保護膜
106 P型半導体領域
107 N型半導体領域
108 N型半導体領域
109 半導体基体の一方の主面
110 半導体基体の他方の主面
111 メサ部
112 PN接合
113 絶縁性樹脂
114 ガラス粒子
DESCRIPTION OF SYMBOLS 1 Silicon oxide film 1a Silicon oxide film containing Al ion 2 Mask 3 One main surface of a semiconductor substrate 4 The other main surface 100 of a semiconductor substrate 100 Mesa type semiconductor element 101 Diode 102 Semiconductor substrate 103 Anode electrode 104 Cathode electrode 105 Protective film 106 P-type semiconductor region 107 N -type semiconductor region 108 N + -type semiconductor region 109 One main surface 110 of the semiconductor substrate The other main surface 111 of the semiconductor substrate 111 Mesa portion 112 PN junction 113 Insulating resin 114 Glass particles

Claims (5)

半導体基体がメサ形状である半導体素子であって、前記半導体基体のメサ部をなす傾斜側面を被覆してAlイオンを含むシリコン酸化膜を形成したことを特徴とするメサ型半導体素子。 A semiconductor device having a mesa-shaped semiconductor substrate, wherein a silicon oxide film containing Al ions is formed by covering an inclined side surface forming a mesa portion of the semiconductor substrate. 半導体基体がメサ形状である半導体素子であって、前記半導体基体のメサ部をなす傾斜側面を被覆してAl、Cl、Fの何れか一種または複数種のイオンを含むシリコン酸化膜を形成したことを特徴とするメサ型半導体素子。 A semiconductor element having a mesa-shaped semiconductor substrate, and a silicon oxide film containing any one kind or plural kinds of ions of Al, Cl, F is formed by covering an inclined side surface forming a mesa portion of the semiconductor body. Mesa type semiconductor device characterized by the above. メサ形状の半導体基体において、メサ部をなす傾斜側面を皮覆してシリコン酸化膜を形成し、前記シリコン酸化膜にAlをイオン注入して前記シリコン酸化膜をAlイオンを含むシリコン酸化膜となすことを特徴とするメサ型半導体素子の製造方法。 In a mesa-shaped semiconductor substrate, a silicon oxide film is formed by covering the inclined side surface forming the mesa portion, and Al is ion-implanted into the silicon oxide film so that the silicon oxide film becomes a silicon oxide film containing Al ions. A method for manufacturing a mesa semiconductor element. メサ形状の半導体基体において、メサ部をなす傾斜側面を皮覆してシリコン酸化膜を形成し、前記シリコン酸化膜にAl、Cl、Fの何れか一種または複数種をイオン注入し、前記シリコン酸化膜をAl、Cl、Fの何れか一種または複数種のイオンを含むシリコン酸化膜とすることを特徴とするメサ型半導体素子の製造方法。 In a mesa-shaped semiconductor substrate, a silicon oxide film is formed by covering an inclined side surface forming a mesa portion, and one or more of Al, Cl, and F are ion-implanted into the silicon oxide film, and the silicon oxide film Is a silicon oxide film containing any one kind or plural kinds of ions of Al, Cl and F. シリコンからなる第1層の高濃度半導体領域の上に同じ導電型をなす第2層の低濃度半導体領域をエピタキシャル成長によって形成し、前記低濃度半導体領域の表面から層内へ異なる導電型のドーパントを拡散させて第3層の半導体領域を形成し、前記第3層の半導体領域と前記第2層の低濃度半導体領域との界面を半導体接合面として半導体基体を形成する半導体基体形成工程と、
前記半導体基体の一方の主面の外周に沿って、かつ前記高濃度半導体領域に達する側面をメサエッチングし、前記半導体基体の外周にメサ部をなす傾斜側面を形成して前記半導体基体をメサ形状となすメサ形成工程と、
熱酸化法にて、前記半導体基体の一方の主面から前記傾斜側面にかけてシリコン酸化膜を形成する酸化膜形成工程と、
前記半導体基体の一方の主面に対応するシリコン酸化膜をマスクで覆い、前記傾斜側面上の前記シリコン酸化膜にAlをイオン注入して前記傾斜側面上にAlイオンを含むシリコン酸化膜を形成するイオン注入工程と、
前記シリコン酸化膜に選択的エッチング除去を施して、前記半導体基体の一方の主面をなす前記第3層の半導体領域を露出させ、前記第3層の半導体領域の表面から前記シリコン酸化膜の周辺へ延在するアノード電極を形成し、前記半導体基体の他方の主面をなす前記高濃度半導体領域を研削研磨して厚み調整し、前記高濃度半導体領域の表面にカソード電極を形なする電極形成工程とを含むことを特徴とするメサ型半導体素子の製造方法。
A second low-concentration semiconductor region having the same conductivity type is formed on the high-concentration semiconductor region of the first layer made of silicon by epitaxial growth, and dopants of different conductivity types are formed from the surface of the low-concentration semiconductor region into the layer. A semiconductor substrate forming step of forming a semiconductor region of a third layer by diffusing, and forming a semiconductor substrate with an interface between the semiconductor region of the third layer and the low concentration semiconductor region of the second layer as a semiconductor bonding surface;
A mesa-etched side surface that reaches the high-concentration semiconductor region along the outer periphery of one main surface of the semiconductor substrate to form an inclined side surface that forms a mesa portion on the outer periphery of the semiconductor substrate, thereby forming the semiconductor substrate in a mesa shape Nassus mesa formation process,
An oxide film forming step of forming a silicon oxide film from one main surface of the semiconductor substrate to the inclined side surface by a thermal oxidation method;
A silicon oxide film corresponding to one main surface of the semiconductor substrate is covered with a mask, and Al is ion-implanted into the silicon oxide film on the inclined side surface to form a silicon oxide film containing Al ions on the inclined side surface. An ion implantation process;
The silicon oxide film is selectively etched away to expose the third layer semiconductor region that forms one main surface of the semiconductor substrate, and from the surface of the third layer semiconductor region to the periphery of the silicon oxide film Forming an anode electrode extending to the surface, adjusting the thickness by grinding and polishing the high-concentration semiconductor region that forms the other main surface of the semiconductor substrate, and forming an electrode that forms a cathode electrode on the surface of the high-concentration semiconductor region A method for manufacturing a mesa semiconductor element.
JP2007020233A 2007-01-31 2007-01-31 Mesa semiconductor element and method for manufacturing the same Withdrawn JP2008187060A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015025754A1 (en) * 2013-08-19 2015-02-26 株式会社村田製作所 Diode device and method for producing same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015025754A1 (en) * 2013-08-19 2015-02-26 株式会社村田製作所 Diode device and method for producing same

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