JP2008186924A - P contamination evaluating method of semiconductor substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a P contamination evaluating method for a semiconductor substrate, capable of easily judging presence of P contamination at high precision. <P>SOLUTION: The P contamination method evaluates a semiconductor substrate in which Sb ion or As ion is implanted by ion implantation. After the semiconductor substrate in which Sb ion or As ion has been implanted is at least subjected to heat treatment, a diffusion concentration profile of impurities in depth direction of the semiconductor substrate that has been subjected to the heat treatment is acquired. Based on the inflection point of the diffusion concentration profile, presence of P contamination from an ion implanting device is judged and evaluated. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for evaluating a semiconductor substrate implanted with Sb ions or As ions by ion implantation, and more particularly to a method for evaluating the P contamination of the semiconductor substrate implanted with ions.

  MOS elements such as MOSFETs are usually manufactured using a substrate in which a thin semiconductor layer is formed on a semiconductor substrate. This thin-film semiconductor layer is generally formed by an epitaxial growth method. However, as the integration becomes higher, the thickness of the epitaxial layer is increasingly required.

  A semiconductor substrate (epitaxial wafer) on which an epitaxial layer for a MOS element as described above is formed generally contains low concentration impurities by a CVD (Chemical Vapor, Deposition) method on a silicon substrate containing high concentration impurities. It is formed by growing an epitaxial layer.

  In recent years, as an alternative, a method for manufacturing a substrate having a buried diffusion layer using ion implantation can be cited. This method is proposed in, for example, Patent Document 1, and a semiconductor substrate can be manufactured at a low cost by a simplified process compared to the conventional method.

In addition, in a semiconductor element such as a BiCMOS device, an embedded diffusion epitaxial wafer in which impurities such as Sb, As, P, and B are selectively or entirely buried between a silicon substrate and an epitaxial layer grown thereon. Is used. These embedded impurity layers have various functions such as device resistance control and element isolation. As a method for forming such a buried impurity layer, there is a method using ion implantation.

  However, when manufacturing a semiconductor substrate using ion implantation as described above, dopant contamination may occur in the ion implantation apparatus. And if dopant contamination arises in this way, it will have a bad influence on device characteristics. Therefore, there is a demand for a method capable of accurately and simply evaluating the dopant contamination of the manufactured semiconductor substrate.

JP-A-6-267880

Regarding the dopant contamination, in particular, when Sb ions or As ions are used as implanted ions, contamination by P ions occurs. However, an evaluation method that can easily determine the occurrence of P contamination has not been established.
Conventionally, in evaluating the P contamination, after the Sb ions and As ions are implanted into the semiconductor substrate, the evaluation has been performed by using a method such as TXRF, ICP-MS, SIMS or the like. However, when these conventional evaluation methods are actually performed, there is a problem that it takes a long time to evaluate and takes time, and the measuring device is expensive and expensive.
In addition, the detection sensitivity is about 1 × 10 ¹⁴ atoms / cm ^3. For example, when the standard of the impurity concentration is the same level or lower than this, the contamination cannot be evaluated with high accuracy.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a method for evaluating P contamination of a semiconductor substrate that can easily and accurately determine the presence or absence of P contamination.

  In order to solve the above problems, the present invention is a method for evaluating a semiconductor substrate implanted with Sb ions or As ions by ion implantation, and at least heat treatment is performed on the semiconductor substrate implanted with Sb ions or As ions. Then, a diffusion concentration profile of impurities in the depth direction of the heat-treated semiconductor substrate is obtained, and the presence or absence of P contamination from the ion implantation apparatus is determined and evaluated based on the inflection point of the diffusion concentration profile. A method for evaluating P contamination of a semiconductor substrate is provided.

  As described above, the semiconductor substrate into which Sb ions or As ions have been implanted by ion implantation is first subjected to heat treatment to diffuse the implanted ions into the substrate. At this time, if there is P contamination, the diffusion rate of P ions is faster than that of Sb ions or As ions implanted, so that during the heat treatment, the P ions diffuse into the substrate by overtaking the diffusion region of Sb ions or As ions. To do. Therefore, the impurity diffusion concentration profile in the depth direction of the semiconductor substrate subjected to the heat treatment has an inflection point where the degree of decrease in the impurity concentration changes in the depth direction of the substrate. Therefore, the presence or absence of P contamination from the ion implantation apparatus can be accurately determined and evaluated based on the inflection point of the diffusion concentration profile, and can be easily performed.

At this time, it is desirable to obtain a diffusion concentration profile of impurities in the depth direction of the semiconductor substrate subjected to the heat treatment by using angle polishing.
Thus, in particular, if the diffusion concentration profile of the impurity in the depth direction of the heat-treated semiconductor substrate is obtained using angle polishing, the labor and cost can be improved as compared with the measurement method using SIMS or the like. Evaluation efficiency can be significantly improved. In addition, accurate evaluation can be performed even if the impurity concentration is relatively low.

According to the present invention, it is possible to accurately and easily determine whether or not P contamination occurs in a semiconductor substrate into which Sb ions or As ions are implanted.
In particular, when performing the evaluation, if the diffusion concentration profile of the impurity in the depth direction of the semiconductor substrate is obtained using angle polishing, the evaluation efficiency and cost can be improved as compared with the case of using the method by SIMS and the like. Can be evaluated with high accuracy even at a relatively low concentration.

Hereinafter, embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited thereto.
FIG. 1 is a flowchart showing an example of the process of the P contamination evaluation method for a semiconductor substrate of the present invention.

First, an evaluation semiconductor substrate used for evaluation is prepared (step 1).
That is, a desired semiconductor substrate into which Sb ions or As ions are implanted using an ion implantation apparatus is prepared.
This Sb ion or As ion implantation may be performed using a conventionally used ion implantation apparatus as disclosed in, for example, Patent Document 1 and can be performed in the same manner as the conventional method. . The conditions for ion implantation energy of ion implantation, the dose amount of Sb ions and As ions, and the like are not limited, and can be appropriately determined according to the purpose.
As described above, when this Sb ion or As ion is implanted, contamination by P ions may occur unintentionally.

In the present invention, in order to determine whether or not P contamination has occurred in the prepared evaluation semiconductor substrate by the ion implantation apparatus, first, the evaluation semiconductor substrate is heat-treated using a heat treatment furnace or the like. (Step 2).
In this way, by performing heat treatment on the semiconductor substrate for evaluation, Sb ions and As ions that are intentionally implanted, and P ions that are unintentionally implanted are diffused into the substrate.

  In the evaluation method of the present invention, the difference in diffusion rates of Sb ions, As ions, and P ions at this time is used. That is, when the semiconductor substrate for evaluation is prepared and if contamination by P ions is caused by the ion implantation apparatus, if the heat treatment is performed on the semiconductor substrate for evaluation, P ions diffuse compared to Sb ions and As ions. Since it is fast, the P ions diffuse into the deeper region of the substrate, overtaking the diffusion region of Sb ions or As ions. As a result, as will be described later, the influence appears in the impurity diffusion concentration profile in the depth direction of the semiconductor substrate for evaluation, and the presence or absence of P contamination can be determined.

Note that the method for the heat treatment is not particularly limited, and for example, the heat treatment can be performed by introducing the semiconductor substrate for evaluation into a heat treatment furnace.
Conventional heat treatment furnaces such as rapid heating / cooling devices such as RTA (Rapid Thermal Annealer), which can perform heat treatment in a short time, and batch-type heat treatment furnaces capable of performing heat treatment in large quantities at once Can be used.

  Further, the heat treatment conditions such as the heat treatment temperature, the heat treatment time, and the heat treatment atmosphere at this time are not particularly limited. For example, if the heat treatment temperature is 800 ° C. or higher, a sufficient diffusion rate can be obtained, and the heat treatment time can be shortened. If the heat treatment temperature is 1150 ° C. or lower, contamination from the heat treatment furnace that occurs from the heat treatment furnace itself due to high temperature is excluded. It is possible to make the determination of the presence or absence of P contamination from the ion implantation apparatus more reliable. The heat treatment conditions can be appropriately determined according to the accuracy of evaluation, efficiency, cost, or the like.

Next, a diffusion concentration profile of impurities (ion-implanted Sb ions, As ions, and P ions) in the depth direction of the semiconductor substrate for evaluation thus heat-treated is obtained (step 3).
The method for obtaining the diffusion concentration profile is not particularly limited, but in particular, it may be obtained by using angle polishing. If it is the method by angle grinding | polishing, it can obtain | require easily, without requiring a long time and comparatively effort. At the same time, since no expensive equipment is required for the measurement, it can be carried out without cost.
Furthermore, even if the range of the diffusion concentration profile reaches a relatively low concentration range of about 1 × 10 ¹⁴ atoms / cm ^3, which is the SIMS detection sensitivity, for example, it can be accurately evaluated.

Here, a method using angle polishing will be described as an example. Note that a method for obtaining the impurity diffusion concentration profile using this angle polishing is disclosed in, for example, Japanese Patent Application Laid-Open No. 2005-223098.
First, the semiconductor substrate subjected to the heat treatment is angle-polished. In this angle polishing, an end surface perpendicular to the surface is formed by, for example, cleaving the evaluation semiconductor substrate, and this end surface is polished to have a predetermined angle with respect to the surface to form an angle polished surface. The impurity concentration distribution in the oblique direction on the angle polished surface is an extension of the impurity concentration distribution in the depth direction of the semiconductor substrate for evaluation according to the polishing angle. For example, if the polishing angle is 75 ′ to 1 ° 9 ′, the expansion rate is 10 to 50 times. This polishing angle can be set freely and can be determined each time according to various conditions.

Next, the resistivity distribution in the depth direction of the semiconductor substrate for evaluation is obtained.
FIG. 2 is a schematic diagram illustrating an example of a method for measuring resistivity distribution. SR measurement (not shown) connected to the probe 3 while moving the SR measurement probe 3 obliquely along the angle polishing surface from the position of the original surface of the wafer of the angle polishing surface 2 formed on the semiconductor substrate 1 for evaluation. The resistivity distribution in the depth direction of the semiconductor substrate for evaluation can be obtained by measuring the resistivity by the SR method using a container. In the SR method, it is possible to measure the resistivity in a minute region near the probe, and as described above, the impurity concentration distribution on the angle polished surface is expanded, so that it corresponds to the impurity concentration distribution. The resistivity distribution has also been expanded so that accurate resistivity distribution measurement can be performed with high resolution in the depth direction. For example, the resistivity can be measured at intervals of 0.05 μm in the depth direction. The SR method may be either a constant current method or a constant voltage method.
Then, the resistivity distribution in the depth direction is obtained in this way, and then the resistivity is converted by, for example, ASTM, so that a concentration profile of impurities diffused by the heat treatment can be obtained.

  FIG. 3 is a graph showing an example of a diffusion concentration profile of impurities obtained by the above method. For comparison, FIG. 3 shows a case where P contamination has not occurred (graph A in FIG. 3) and a case where P contamination has occurred (graph B in FIG. 3).

  As shown in graph A of FIG. 3, first, when no P contamination occurs, the concentration gradually decreases substantially uniformly in the depth direction of the substrate. It can be seen that impurities (in this case, Sb ions or As ions) are diffused by the heat treatment. Note that the reason why the concentration is constant at 5.00E + 13 after the substrate depth of 3 μm is due to the detection limit determined by the resistivity of the silicon substrate used.

On the other hand, when P contamination has occurred (graph B), the concentration distribution of impurities (in this case, Sb ions, As ions, and P ions) due to P ions that have been unintentionally implanted from the ion implanter. Has been affected. Moreover, as described above, since the diffusion of P ions is faster than that of Sb ions and As ions, if the heat treatment is performed in the same manner as in the case where P contamination is not generated, the difference in diffusion rate is different. As a result, the Sb ions and As ions are diffused to a deeper region of the substrate by overtaking the diffusion region. That is, although it depends on the heat treatment conditions and the like, a change is seen in the concentration profile in a deeper region of the substrate.
As a result, as shown in the graph B of FIG. 3, the slope of the graph changes to draw a tail, resulting in a diffusion density profile having an inflection point C.

As described above, when P contamination occurs, the concentration does not decrease almost uniformly as shown in graph A due to the influence of P ions diffused in the substrate. Thus, a change is seen in the degree of decrease in impurity concentration (diffusion degree) at a certain depth of the substrate, and an inflection point C is seen. On the other hand, when P contamination does not occur (graph A), the inflection point C is not seen.
Thus, the semiconductor substrate can be evaluated by determining the presence or absence of P contamination based on the inflection point C (step 4).

  As described above, according to the present invention, first, the diffusion concentration profile of impurities in the semiconductor substrate for evaluation subjected to the heat treatment is obtained. And since the presence or absence of P contamination can be determined from the inflection point in the profile, it is very simple. In particular, if a diffusion concentration profile is obtained by using angle polishing, it is possible to measure and evaluate a concentration range lower than SIMS with higher accuracy without cost and time. .

The present invention will be described in detail below with reference to examples of the present invention, but these examples do not limit the present invention.
(Examples 1-4)
As samples, first, four silicon wafers having a diameter of 150 mm, a thickness of 625 μm, and a resistivity of 100 Ωcm were prepared. Sb ions were similarly implanted into these silicon wafers with an ion implantation energy of 60 keV using a conventional ion implantation apparatus.
Of these silicon wafers, one is left as it is without P contamination, and the remaining three wafers are intentionally P contaminated by implanting P ions with an ion implantation energy of 32 keV (1E + 11 atoms / cm ² , 2E + 11 atoms / cm ²⁾ . ² and 1E + 12 atoms / cm ² ), a silicon wafer for evaluation.

  The evaluation method of the present invention was carried out on these four evaluation silicon wafers. First, using a conventional heat treatment furnace, heat treatment was performed at 1150 ° C. for 360 minutes under a 1% oxygen concentration atmosphere.

Thereafter, each evaluation silicon wafer was cleaved and polished at an angle of 1 ° 9 ′. Then, the resistivity distribution of angle polishing was measured with an SR measuring device. The measurement at this time was performed up to a depth of 6 μm in terms of the depth direction of the evaluation silicon wafer.
The resistivity distribution thus measured was converted into an impurity concentration profile. The result is shown in FIG. Detection was possible up to the order of 5E + 13 atoms / cm ³ .

As shown in FIG. 4, an inflection point is seen in the impurity concentration profile in the evaluation silicon wafer in which P ions are intentionally implanted, and the tail is drawn. That is, when P ions are implanted at 1E + 11 atoms / cm ² (circled graph), in the vicinity of 2.8 μm in the substrate depth direction, when implanted at 2E + 11 atoms / cm ² (triangled graph), the substrate depth direction In the case of implantation at 1E + 12 atoms / cm ² near 2.7 μm (square graph), it can be seen that there is an inflection point near 2.5 μm in the substrate depth direction.
It can also be seen that the higher the dose, that is, the greater the amount of implanted P ions, the more inflection points can be seen at a position closer to the surface of the substrate.

On the other hand, when P contamination was not performed (graph x), no inflection point was observed, and the profile gradually and uniformly decreased to the detection limit of 5E + 13 atoms / cm ³ .

(Examples 5 to 8)
The evaluation method of the present invention was carried out in the same manner as in Examples 1 to 4 except that As ions were implanted instead of Sb ions. As in Examples 1 to 4, P-contaminated silicon wafers for evaluation were used. Then, an inflection point was observed, and no inflection point was observed in the silicon wafer for evaluation not contaminated with P.

  As described above, as in the present invention, P contamination occurs based on the inflection point in the impurity diffusion concentration profile measured after the heat treatment of the semiconductor substrate in which Sb ions or As ions are implanted into the substrate. It has been found that the method of judging and evaluating whether or not is sufficiently accurate and effective. Moreover, it can be carried out easily and without cost.

  The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.

It is a flowchart which shows an example of the process of the P contamination evaluation method of the semiconductor substrate of this invention. It is the schematic which shows an example of the measuring method of resistivity distribution. . It is a graph which shows an example of the diffusion concentration profile of the impurity of the depth direction of a semiconductor substrate. It is a graph which shows the measurement result of the diffusion concentration profile of the impurity of the depth direction of the silicon wafer for evaluation in Examples 1-4.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate for evaluation, 2 ... Angle polishing surface, 3 ... Probe.

Claims (2)

  A method of evaluating a semiconductor substrate implanted with Sb ions or As ions by ion implantation, wherein at least the semiconductor substrate implanted with Sb ions or As ions is subjected to a heat treatment, and then the semiconductor substrate subjected to the heat treatment is subjected to heat treatment. A method for evaluating P contamination of a semiconductor substrate, comprising: obtaining a diffusion concentration profile of impurities in a depth direction; and determining and evaluating the presence or absence of P contamination from an ion implantation apparatus based on an inflection point of the diffusion concentration profile . 2. The method for evaluating P contamination of a semiconductor substrate according to claim 1, wherein a diffusion concentration profile of impurities in the depth direction of the semiconductor substrate subjected to the heat treatment is obtained by angle polishing.

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