JP2008181945A - Esd protection element and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an ESD (electrostatic discharge) protection element having high breakdown voltage, capable of preventing breakdown due to ESD surge of electrostatic discharge, and to provide a semiconductor device equipped with this ESD protection element. <P>SOLUTION: The ESD protection element 1 includes a first conductivity-type first region 12 formed on a semiconductor substrate 10; a first conductivity-type first well region 13 and a second conductivity-type second well region 14 formed with a predetermined distance on the first region 12; first conductivity-type second regions 19a, 19b formed on the first well region 13 and having density higher than that of the first well region 13; a first conductivity-type third region 18 formed on the second well region 14; and a first electrode 6b disposed on the second well region 14 via an insulating film 15b. A second electrode 6a disposed via an insulating film 15a is provided on the first well region 13 except the second regions 19a, 19b, and the first electrode 6b is connected to the second electrode 6a. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an electrostatic protection element and a semiconductor device including the electrostatic protection element.

  Generally, a semiconductor integrated circuit (IC) has a problem that it is easily broken because it is vulnerable to electrostatic discharge (ESD). One of the most common sources of ESD surges, which are electrostatic discharges, is a human body that accumulates 2000V of static electricity that contains an IC package that contains a semiconductor integrated circuit without any countermeasures taken by the user. By handling, an abrupt ESD surge is applied, causing physical destruction of each circuit and each element constituting the semiconductor integrated circuit. The ESD surge induced by electrostatic discharge often destroys the gate oxide film of a field effect transistor (FET) of a semiconductor integrated circuit. In particular, the gate oxide film is destroyed when the insulation strength is greater than 10E7 V / cm. Was supposed to be. In addition, the ESD surge sometimes deteriorates the PN junction and destroys the semiconductor integrated circuit.

  A general method for protecting a semiconductor integrated circuit from such electrostatic discharge is a diode that becomes a resistive path by shunting the path between the semiconductor integrated circuit and the electrode pad for the purpose of diverting the ESD surge from the protected circuit. It is to insert an electrostatic protection element.

  Alternatively, there is a method of releasing an ESD surge by connecting an electrostatic protection element, which is a field effect transistor, to a desired line between the electrode pad and the semiconductor integrated circuit and performing control in a gate-controlled drain avalanche breakdown mode. .

Alternatively, a technique of providing an ESD protection circuit in a semiconductor integrated circuit is taken. As shown in FIG. 6, in the ESD protection circuit 130, the MOS transistor turned off is connected to the input / output signal line 133. The ESD protection circuit 130 connects the drain of the n-type MOS transistor 132 with the gate, source, and p-well substrate grounded to the ground, to the input / output signal line 133, and supplies the gate, source, and n-well substrate to the external power supply The drain of the p-type MOS transistor 131 connected to (VDD) is similarly connected to the input / output signal line 133. Since the two MOS transistors 131 and 132 of the connected electrostatic protection element are both in the OFF state, no current flows during normal operation. On the other hand, when a surge current due to ESD flows, the MOS transistor generates a high surge current. The semiconductor integrated circuit is to be protected by flowing (see, for example, Patent Document 1).
JP 2003-133434 A

  By the way, with the recent increase in the size of home television receivers, a high withstand voltage process capable of forming high withstand voltage driving ICs, for example, high withstand voltage display driver ICs, has been developed in the semiconductor field. The driving IC formed by the above has a high breakdown voltage MOS transistor, and when this high breakdown voltage MOS transistor is used as an electrostatic protection element, it can withstand a high breakdown voltage from the current-voltage characteristics shown in FIG. On the other hand, the breakdown voltage (see region b in FIG. 7) is set high. Therefore, when the ESD surge is applied, the electrostatic protection element having a high withstand voltage has a breakdown voltage (see region a in FIG. 7) at the moment of snapback in the current-voltage characteristics (see region a in FIG. 7). Thus, the MOS transistor itself is destroyed.

In view of the above-described points, the present invention provides a high-breakdown-voltage electrostatic protection element capable of preventing destruction of an electrostatic discharge due to an ESD surge and a semiconductor device including the electrostatic protection element.

  In order to achieve the above object, according to a first aspect of the present invention, an electrostatic protection element is formed with a first region of a first conductivity type formed on a semiconductor substrate and a predetermined interval in the first region. A first conductivity type first well region and a second conductivity type second well region, and a first conductivity type second region formed on the first well region and having a higher concentration than the first well region. And a third region of the first conductivity type formed on the second well region, and the second well region between the first well region and the third region via an insulating film. An electrostatic protection element including a first electrode, wherein a second electrode disposed via an insulating film is provided on the first well region excluding the second region, and the first electrode and the first electrode Two electrodes are connected.

  According to a second aspect of the present invention, in the first aspect of the present invention, the area of the first electrode is made larger than the area of the second electrode.

  The invention according to claim 3 is the invention according to claim 1, wherein the thickness of the insulating film under the first electrode is made smaller than the thickness of the insulating film under the second electrode. .

  The invention according to claim 4 is a semiconductor device comprising an electrostatic protection element and a protected circuit protected by the electrostatic protection element, wherein the electrostatic protection element is a first conductivity type formed on a semiconductor substrate. A first conductivity type first well region and a second conductivity type second well region formed in the first region at a predetermined interval, and formed on the first well region. A first conductivity type second region having a concentration higher than that of the first well region; a first conductivity type third region formed on the second well region; the first well region and the third region; A first electrode disposed via an insulating film on the second well region between and a second electrode disposed via an insulating film on the first well region excluding the second region; The first electrode and the second electrode are connected.

  The invention according to claim 5 is the invention according to claim 4, further comprising a control circuit for setting the first electrode and the second electrode to a ground potential during operation of the protected circuit. To do.

  According to the present invention, the first conductivity type first region formed in the semiconductor substrate, the first conductivity type first well region and the second conductivity type second region formed in the first region at a predetermined interval. A second well region, a first conductivity type second region formed on the first well region and having a higher concentration than the first well region; and a first conductivity type formed on the second well region. An electrostatic protection element comprising: a third region; and a first electrode disposed via an insulating film on the second well region between the first well region and the third region, When an ESD surge is applied by providing a second electrode disposed via an insulating film on the first well region excluding the second region and connecting the first electrode and the second electrode, Applying a voltage smaller than the voltage applied to the second electrode to the first electrode to Since work, it is possible to obtain a strong electrostatic protection element ESD surge.

  The electrostatic protection element according to the present embodiment includes a first conductivity type first region formed in a semiconductor substrate, a first conductivity type first well region formed in the first region with a predetermined interval, and A second conductivity type second well region and a first well region formed in the first well region and having a higher concentration than the first well region, and a first well region formed on the second well region. An electrostatic protection element comprising: a conductive third region; and a first electrode disposed via an insulating film in a second well region between the first well region and the third region, A second electrode disposed via an insulating film is provided on the first well region excluding the region, and the first electrode and the second electrode are connected.

  Therefore, when an ESD surge is applied, the electrostatic protection element is operated by applying a potential smaller than the potential applied to the potential of the second electrode to the first electrode, so that the ESD surge can be released. An electrostatic protection element resistant to surge can be obtained. In addition, the depletion layer generated when the voltage applied to the second region is expanded to the first well region and the first region (so-called offset region), so that the electric field can be relaxed and a high breakdown voltage can be achieved.

  Here, the potential applied to the first electrode is determined by the voltage applied to the second electrode. In other words, the first electrode and the second well region below the first electrode (if the first electrode is formed across the second well region and the first region, the first electrode and the first electrode A capacitor composed of the second well region and the first region (hereinafter referred to as a capacitance value of the first electrode), a capacitor composed of the second electrode and the first well region (hereinafter referred to as “second electrode”). (Hereinafter, simply referred to as “capacity ratio”).

  This capacity ratio can be changed, for example, by changing the area ratio between the area of the first electrode and the area of the second electrode. Therefore, by making the area of the first electrode larger than the area of the second electrode, the potential applied to the first electrode can be made lower than the voltage applied to the second electrode. The electrostatic protection element is operated to prevent electrostatic breakdown by causing a current to flow between the third region, the second well region, the first region, the first well region, and the second region.

  In addition, the change in the capacitance ratio does not change the ratio between the area of the first electrode and the area of the second electrode, but the film thickness of the insulating film under the first electrode and the film thickness of the insulating film under the second electrode. This can also be done by changing the ratio.

  Therefore, by making the film thickness of the insulating film under the first electrode thinner than the film thickness of the insulating film under the second electrode, the potential applied to the first electrode is made lower than the voltage applied to the second electrode. The electrostatic protection element is operated by this low potential, and an electrostatic current flows between the third region, the second well region, the first region, the first well region, and the second region. Destruction can be prevented.

  The semiconductor device according to the present embodiment is a semiconductor device including the electrostatic protection element and a protected circuit protected by the electrostatic protection element. The electrostatic protection element is a first conductive formed on a semiconductor substrate. Formed in the first well region, the first well region of the first conductivity type and the second well region of the second conductivity type formed in the first region with a predetermined interval, and the first well region. A second region of the first conductivity type having a higher concentration than the one well region; a third region of the first conductivity type formed in the second well region; and a first region between the first well region and the third region. A first electrode disposed on the two-well region via an insulating film; and a second electrode disposed on the first well region excluding the second region via the insulating film. And connected.

  Therefore, when an ESD surge is applied, a voltage smaller than the voltage applied to the second electrode is applied to the first electrode to operate the electrostatic protection element, thereby preventing the semiconductor device from being destroyed from the ESD surge. it can.

  In addition, a control circuit is provided for connecting the second electrode and the first electrode to the grounding portion when the protected circuit is in operation and setting the ground potential, and for disconnecting the second electrode and the first electrode from the grounding portion when the protected circuit is not in operation. Yes.

  Therefore, electrostatic protection can be performed even during operation of the protected circuit, and destruction of the semiconductor device can always be prevented. A semiconductor device having high ESD resistance can be obtained.

  An embodiment of the present invention will be described below with reference to the drawings. As an example of the electrostatic protection element according to the present embodiment, a MOS transistor structure will be described. FIG. 1 is a configuration diagram showing an electrostatic protection element according to the present embodiment. FIG. 2 is a circuit diagram showing the electrostatic protection element according to the present embodiment.

  As shown in FIG. 1, the electrostatic protection element 1 according to the present exemplary embodiment has a high concentration n + in a low concentration n− second well region (corresponding to an example of a first conductivity type first well region) 13. The two drain regions (corresponding to an example of the second region of the first conductivity type) 19a and 19b are formed, and the potential extracting insulating film 15a (an example of the insulating film under the second electrode is formed on the surface of the second well region 13). 6) (corresponding to an example of the second electrode). Further, in the p-type third well region 14 (corresponding to an example of a second conductivity type second well region), a p-type back gate region 17 and an n-type source region 18 (an example of the first conductivity type third region). And a portion corresponding to the surface of the first well region 12, the surface of the third well region 14, and the surface of the field insulating layer 11 via a gate insulating film 15b (corresponding to an example of an insulating film under the first electrode). The gate electrode 6b (corresponding to an example of the first electrode) made of the gate electrode film 16b. A second well region 13 and a third well region 14 are formed in the first well region 12 with a predetermined interval. For example, on the surface of the p-type silicon semiconductor substrate 10 (corresponding to an example of a semiconductor substrate) and the n-type first well region 12 (corresponding to an example of the first region of the first conductivity type), an element isolation region is formed. 11. Element formation regions separated by the field insulating layer 11 are formed by, for example, selective oxidation (so-called LOCOS).

  Furthermore, as shown in FIG. 2, the electrostatic protection element 1 according to the present embodiment electrically connects the drain electrode 22a on the first drain region 19a and the drain electrode 22b on the second drain region 19b electrically in common. The electrode pad 9 is electrically connected to one drain electrode 22a. Next, the potential extraction electrode 6a and the gate electrode 6b are electrically connected to the control circuit 8 in common. The source electrode 21 of the n-type source region 18 and the back gate electrode 20 of the p-type back gate region 17 formed in the p-type well region 14 are obtained by being connected to the ground portion 7.

  The capacitance ratio is composed of the capacitance value C1 of the potential extraction electrode 6a and the capacitance value C2 of the gate electrode 6b. That is, the area S1 of the potential extraction electrode 6a, the area S2 of the gate electrode 6b, and the film thickness of the potential extraction insulating film 15a. It is determined appropriately by d1 and the film thickness d2 of the gate insulating film 15b.

Here, the capacitance of the potential extracting electrode 6a is C1, the capacitance of the gate electrode 6b is C2, the voltage applied to the electrode pad 9 is V1, the gate insulating film breakdown electric field is Eg, the potential extracting insulating film 15a and the gate insulating film 15b are formed. If the thickness d is common, the relationship of the capacity ratio is expressed by the following equation.

Capacity ratio = C2 / C1 = V1 / (Eg × d) (1)

By using the capacitance ratio derived from the previous equation (1) and the voltage V1 applied to the electrode pad 9, the voltage V2 of the gate electrode can be obtained by the following equation. Note that the gate electrode voltage V2 is the potential of the gate electrode 6b with respect to the ground potential.

V2 = V1 / capacity ratio (2)

Therefore, even when a high-voltage ESD surge voltage V1 is applied to the electrode pad 9, the voltage applied to the electrode pad 9 is adjusted by adjusting the capacitance value C1 of the potential extraction electrode 6a and the capacitance value C2 of the gate electrode 6b. Since the electrostatic protection element 1 is operated by applying a voltage V2 smaller than V1 to the gate electrode 6b, the ESD voltage can be released without causing element destruction. For example, assuming that the capacitance value C1 = 7.5 of the potential extraction electrode 6a and the capacitance value C2 = 200 of the gate electrode 6b, when V1 = 200V is applied, V2 = 7.5V and the gate voltage falls within the absolute maximum rating. I can. Further, when the capacitance value C1 = 0.6 of the potential extraction electrode 6a and the capacitance value C2 = 16 of the gate electrode 6b and V1 = 16V is applied, V2 = 0.6V and the electrostatic protection element 1 operates. It can protect against ESD.

  FIG. 3 is a configuration diagram showing a semiconductor device 41 including the electrostatic protection element 1 and the protected element 42 according to the present embodiment. The semiconductor device 41 according to the present embodiment includes an electrostatic protection element 1 and a protected circuit 42 that is protected by the electrostatic protection element 1. The electrostatic protection element 1 is connected so as to shunt between the electrode pad 9 and the protected circuit 42. Further, a control circuit 8 (see FIG. 1) is connected to the electrostatic protection element 1.

  The control circuit 8 controls the electrostatic protection element 1 according to the operation / non-operation state of the non-protection circuit 42.

  The operation of the semiconductor device 41 according to the present embodiment will be specifically described. In particular, a case where an ESD surge is applied from the electrode pad 9 will be described.

  The case where the protected circuit 42 is in a non-operating state and the ESD surge voltage V1 is applied will be described. The control circuit 8 is in a non-operating state. The capacitance ratio is set so that the capacitance value C1 of the potential extraction electrode 6a is smaller than the capacitance value C2 of the gate electrode 6b. The ESD surge voltage V1 applied from the electrode pad 9 is determined by the capacitance ratio consisting of the area S1 of the potential extraction electrode 6a and the area S2 of the gate electrode 6b, so that the voltage of the ESD surge applied to the potential extraction electrode 6a. V1 is applied to the gate electrode 6b as a smaller voltage V2. That is, the converted low voltage V2 turns on the gate electrode 6b of the electrostatic protection element 1, opens the channel of the p-type third well region 14 immediately below the gate electrode 6b, and directly below the gate electrode 6b from the n-type source region 18 A current flows between the source and the drain from the channel through the surface portion of the n-type first well region 12 and the second well region 13. Alternatively, the same effect can be obtained by changing the capacitance ratio formed by the film thickness d1 of the potential extraction insulating film 15a and the film thickness d2 of the gate insulating film 15b.

  The case where the protected circuit 42 is in an operating state and the ESD surge voltage V1 is applied will be described. The control circuit 8 is connected to the ground portion 7 so that the potential extraction electrode 6a and the gate electrode 6b are commonly at the ground potential. The ESD surge voltage V1 applied from the electrode pad 9 is applied to the ground portion 7 by electrically connecting the potential extraction electrode 6a and the gate electrode 6b. When the protected circuit 42 is in the operating state, it becomes the ground potential without depending on the capacitance ratio formed by the gate electrode 6b and the potential extraction electrode 6a. Such a structure in which the gate electrode 6b and the source electrode 21 are connected in common to the ground portion 7 is referred to as GGMOS (Gate Granded MOS).

  According to the electrostatic protection element 1 according to the present embodiment, the area S1 of the potential extraction electrode 6a is made smaller than the area S2 of the gate electrode 6b, and the ESD surge voltage V1 entering from the electrode pad 9 is different in the capacitance ratio. Thus, the electrostatic protection element 1 is operated by applying the voltage V2 smaller than the voltage applied to the potential extraction electrode 6a to the gate electrode 6b. In the current-voltage characteristics, the ESD current can be released before snapping back at a high breakdown voltage (lower than the junction withstand voltage), so that the electrostatic protection element 1 can be prevented from being broken.

  Alternatively, as described above, the capacitance value can be obtained by changing the areas of the potential extraction electrode 6a and the gate electrode 6b, but instead, the thickness of the two potential extraction insulating films 15a and the thickness of the gate insulating film 15b. Can be obtained by changing. The ESD surge entered from the electrode pad 9 operates the electrostatic protection element 1 by applying a voltage smaller than the voltage applied to the potential extraction electrode 6a to the gate electrode 6b according to the capacitance ratio of the two capacitance values. Thus, the ESD current can be released without causing element destruction.

  According to the semiconductor device 41 according to the present embodiment, the conventional electrostatic protection element having a high voltage MOS transistor structure has a high voltage until the snap-back of current-voltage characteristics and has a low ESD resistance. In the case of the device 41, when the protected circuit 42 is not in operation, after the ESD surge entered from the electrode pad 9 in the current-voltage characteristics is converted to a sufficiently low voltage due to the difference in capacitance ratio before the voltage becomes higher, By turning on Vth of the electric protection element 1, an ESD surge is released before snapping back at a high breakdown voltage, and the electrostatic protection element 1 can be prevented from being destroyed. An effect of improving resistance to ESD can be obtained. When the protected circuit 42 is in operation, the control circuit 8 connects the potential extraction electrode 6a and the gate electrode 6b to the ground portion 7 to operate as a GGMOS (Gate Granded MOS), so that the applied voltage from the electrode pad 9 is changed. The grounding portion 7 can be stably released.

  In the semiconductor device 41 according to the present embodiment, the electrostatic protection element 1 is connected so as to shunt between the electrode pad 9 and the protected circuit 42. However, the electrostatic protection is performed depending on the wiring layout of the internal circuit in the semiconductor device 41. The connection position of the element 1 can be determined as appropriate. The semiconductor device includes a semiconductor integrated circuit.

Next, a method for manufacturing an electrostatic protection element using a MOS transistor structure will be described.
FIG. 4 is a process diagram showing a method for manufacturing the electrostatic protection element 1 according to the present embodiment.
First, as shown in FIG. 4A, a second conductivity type, for example, a p-type silicon semiconductor substrate 10 is prepared, and a main part of the p-type silicon semiconductor substrate 10 is obtained by using a photolithography technique and an ion implantation technique. The field insulating layer 11 is formed on the surface by selective oxidation (LOCOS) treatment by thermal oxidation. For example, the field insulating layer 11 is formed with a silicon oxide layer having an oxide thickness of about 260 nm, and a required shape is formed by a photolithography technique.

  Next, as shown in FIG. 4B, an insulating film 31 having a required thickness is formed by thermal oxidation. For example, the insulating film 31 is formed by forming a silicon oxide film having a thickness of about 30 nm.

Next, as shown in FIG. 4C, using a photolithography technique and an ion implantation technique, a photoresist mask (not shown) is formed on a region corresponding to an element formation region where a high voltage MOS transistor is to be formed. ) And is ion-implanted through a photoresist mask into a region where the first conductivity type first well region 12 is to be formed. For example, phosphorus (P) ions are implanted into the first well region 12 with a dose amount of about 4 × 10 ¹² cm ⁻² through a resist mask. Further, after removing the photoresist mask, the n-type first well region 12 is formed by performing a heat treatment at about 1200 ° C. for a long time.

Next, as shown in FIG. 4D, a first conductivity type second well region 13 and a second conductivity type third well region 14 are formed by using a photolithography technique and an ion plating technique. For example, the p-type third well region 14 is ion-implanted with boron (B) ions at a dose of about 3 × 10 ¹² cm ⁻² through a resist mask. The n-type second well region 13 is implanted with phosphorus (P) ions at a dose of about 4 × 10 ¹² cm ⁻² through a resist mask. The diffusion region of the p-type third well region 14 is diffused at one end to immediately below the element isolation region 11 on the back gate region 17 side, and the other end is separated from the element isolation region 11 on the drain region 19b side. Diffusion is performed in a region immediately below the gate insulating film 15b. Since the resistance value increases as the required interval becomes narrower, design conditions are appropriately determined according to necessary characteristics.

  Next, as shown in FIG. 4E, the silicon oxide film, which is the insulating film 31 on the surface of the p-type silicon semiconductor substrate 10 formed by thermal oxidation, is removed, and the potential extraction insulating film 15a and the gate insulation are removed by thermal oxidation. An insulating film 32 to be the film 15b is formed. Further, an electrode film 33 to be the potential extraction electrode film 16a and the gate electrode film 16b is formed. For example, the insulating film 32 is formed of a SiO2 film of about 15 nm. Subsequently, a polycrystalline silicon film having a thickness of about 100 nm to be the potential extraction electrode film 16a and the gate electrode film 16b is formed by a CVD (chemical vapor deposition) method. In particular, the potential extraction insulating film 15a formed on the field insulating layer 11 and the insulating film 32 that becomes the gate insulating film 15b and the polycrystalline silicon film 33 that becomes the potential extraction electrode film 16a and the gate electrode film 16b are partially tapered. Formed.

  Next, as shown in FIG. 5F, for example, the insulating film 32 and the polycrystalline silicon film 33 are selectively removed using an anisotropic etching technique such as a photolithography technique and RIE (reactive ion etching). Then, the potential extracting electrode film 16a and the potential extracting insulating film 15a, and the gate electrode film 16b and the gate insulating film 15b are formed. At this time, the potential extraction electrode 6a is composed of the potential extraction electrode film 16a via the potential extraction insulating film 15a, and the gate electrode 6b is composed of the gate electrode film 16b via the gate insulating film 15b. The capacitance ratio is obtained from the capacitance value C1 of the potential extraction electrode 6a and the capacitance value C2 of the gate electrode 6b. The capacitance values C1 and C2 of the potential extraction electrode 6a and the gate electrode 6b are the area S1 of the potential extraction electrode 6a, the area S2 of the gate electrode 6b, or the film thickness d1 of the potential extraction insulating film 15a and the film thickness of the gate insulating film 15b. It is determined appropriately by d2. For example, for the purpose of converting an ESD surge, the capacitance value C1 of the potential extraction electrode 6a is a capacitance ratio that is smaller than the capacitance value C2 of the gate electrode 6b. That is, as shown in FIG. 2, the area S1 of the potential extraction electrode 6a is smaller than the area S2 of the gate electrode 6b.

Next, as shown in FIG. 5G, by using a photolithography technique and an ion implantation technique, for example, high concentration p + impurity ions are introduced into the potential extraction region of the p-type well region 14, that is, the so-called back gate region 17. inject. For example, boron (B) having a dose of about 1 × 10 ¹⁵ cm ⁻² is ion-implanted as a p-type impurity to form a p-type back gate region 17.

Next, as shown in FIG. 5H, after removing the photoresist mask, high concentration n + is applied to the drain regions 19a and 19b of the n-type well region 13 by using the photolithography technique and the ion implantation technique. N-type impurity ions are implanted. High concentration n + -type impurity ions are implanted into the source region of the p-type well region 14. For example, arsenic (As) having a dose of about 5 × 10 ¹⁵ cm ⁻² is ion-implanted to form the source region 18 and the drain regions 19a and 19b.

  Next, as shown in FIG. 5I, the back gate electrode 20 connected to the back gate region 17 and the source region 18, the source electrode 21, and the drain regions 19a and 19b are connected using photolithography technology and RIE technology. The drain electrodes 22a and 22b to be formed, two potential extraction electrodes 6a and gate electrodes 6b serving as floating gates are formed. The back gate electrode 20, the source electrode 21, the drain electrodes 22a and 22b, the potential extraction electrode 6a, and the extraction electrode (not shown) of the gate electrode 6b are formed by depositing a metal film containing AlCu or the like, for example. And it can be formed by patterning by RIE technology. At that time, the source electrode 21 and the back gate electrode 20 are electrically shared and grounded to the ground portion (GND) 7, and the potential extraction electrode 6 a and the gate electrode 6 b serving as two floating gates are electrically connected in common. Then, the electrode pad 9 can be patterned to be electrically connected to the drain electrode 22a.

  In this way, the desired high withstand voltage electrostatic protection element 1 can be obtained. In the semiconductor device 41 using the present electrostatic protection element 1, it is strong against ESD and can be prevented from being broken.

  As described above, the high withstand voltage electrostatic protection element 1 has a depletion layer generated when the drain regions 19a and 19b are applied to the n-well region 12 and the n-well region 13 on the right side from the right end of the low-concentration p-well region 14. By spreading over (so-called offset region), the electric field can be relaxed and high breakdown voltage can be achieved.

  In the electrostatic protection element 1 described above, the back gate region 17 is further provided and the back gate electrode 20 is connected to the ground portion 7. However, the source region 18 is not provided but the source region 18 is provided. The electrode 21 may be connected to the ground portion 7. When the back gate region 17 is provided, a voltage smaller than the voltage of the ESD surge applied to the potential extraction electrode 6a is applied to the gate electrode 6b to turn on the gate of the electrostatic protection element 1 and operate. By doing so, ESD surge can be released more stably without causing element destruction.

  In the above description, the first conductivity type is n-type and the second conductivity type is p-type. However, the first conductivity type may be p-type and the second conductivity type may be n-type. The electrostatic protection element according to the present embodiment is not limited to one using a MOS transistor structure.

  The electrostatic protection element 1 according to the present embodiment can be used for a semiconductor device 41 such as an LCD driving IC, a PDP driving IC, a power IC, and a power management IC. For example, since the power management IC has a large voltage and drive current, and the built-in output transistor is large, the output transistor has a higher tolerance than the conventional electrostatic protection element (for example, a diode). Protected, but with this electrostatic protection element, ESD protection is applied to the gate electrode by applying a voltage smaller than the voltage applied to the potential extraction electrode regardless of the size of the output transistor. By operating the element, the ESD surge can be effectively performed since the ESD surge is released without causing the element destruction.

It is a figure which shows the basic structural circuit of the electrostatic protection element in embodiment of this invention. It is a figure which shows the circuit connection of the electrostatic protection element in embodiment of this invention. It is a figure which shows the basic composition of the semiconductor device in embodiment of this invention. FIG. 3 is a diagram (part 1) illustrating a manufacturing process of the semiconductor device illustrated in FIG. 1; FIG. 3 is a diagram (part 2) illustrating a manufacturing process of the semiconductor device illustrated in FIG. 1; It is a figure which shows the circuit structure of the conventional electrostatic protection circuit. It is a figure which shows the current-voltage characteristic of the conventional high voltage | pressure-resistant MOS transistor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Electrostatic protection element 6a Potential extraction electrode 6b Gate electrode 7 Grounding part 8 Control circuit 9 Electrode pad 10 Semiconductor substrate 11 Field insulating film 12 n-type first well region 13 n-type second well region 14 p-type third well region 15a Potential extraction insulating film 15b Gate insulating film 16a Potential extraction electrode film 16b Gate electrode film 17 Back gate region 18 Source region 19a First drain region 19b Second drain region 20 Back gate electrode 21 Source electrodes 22a and 22b Drain electrode 31 Insulating film 32 Insulating film 33 Electrode film

Claims (5)

A first conductivity type first region formed in a semiconductor substrate; a first conductivity type first well region and a second conductivity type second well region formed in the first region at a predetermined interval; A first conductivity type second region formed in the first well region and having a higher concentration than the first well region; a first conductivity type third region formed in the second well region; An electrostatic protection element comprising: a first electrode disposed via an insulating film on the second well region between the well region and the third region;
Providing a second electrode disposed on the first well region excluding the second region via an insulating film;
The electrostatic protection element, wherein the first electrode and the second electrode are connected. The electrostatic protection element according to claim 1, wherein an area of the first electrode is larger than an area of the second electrode. The electrostatic protection element according to claim 1, wherein a film thickness of the insulating film under the first electrode is made thinner than a film thickness of the insulating film under the second electrode. In a semiconductor device including an electrostatic protection element and a protected circuit protected by the electrostatic protection element,
The electrostatic protection element includes a first conductivity type first region formed in a semiconductor substrate, a first conductivity type first well region and a second conductivity type formed in the first region at a predetermined interval. A second well region; a first conductivity type second region formed in the first well region and having a higher concentration than the first well region; and a first conductivity type second region formed in the second well region. Three regions, a first electrode disposed on the second well region between the first well region and the third region via an insulating film, and the first well region excluding the second region A semiconductor device comprising: a second electrode disposed through an insulating film; and connecting the first electrode and the second electrode. The semiconductor device according to claim 4, further comprising a control circuit that sets the first electrode and the second electrode to a ground potential during operation of the protected circuit.

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