JP2008181934A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress a crystal defect caused by damage by ion implantation and preventing the fluctuation of an operation threshold Vt of a semiconductor device when the density of a contact region inserted into a lower part of a source region is increased. <P>SOLUTION: In forming a p<SP>+</SP>-type contact region 9, skew ion implantation is executed. In this way, the impurity concentration can be easily made higher in a portion to be formed for insertion into the lower part of an n<SP>+</SP>-source region 8 in the p<SP>+</SP>-type contact region 9 than in a portion to be formed on the substrate surface side of a p-type base region 7. This skew ion implantation can suppress a crystal defect caused by damage by ion implantation on the surface of the substrate. Also, since this can eliminate the necessity of increasing an overlapping quantity between the n<SP>+</SP>-source region 7 and the p<SP>+</SP>-type contact region 9 and increasing a heat treatment time, the diffusion of the p<SP>+</SP>-type contact region 9 up to a channel region can be prevented and the fluctuation of the operation threshold Vt can be prevented. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device including a lateral MOSFET (LDMOS) in which a source region and a drain region are arranged in a lateral direction of a semiconductor substrate.

  Generally, a power element has a configuration in which tens of thousands to hundreds of thousands of small LDMOSs are connected in parallel, and outputs are obtained by operating these LDMOSs simultaneously. However, when a large current is going to flow instantaneously like an ESD (electrostatic discharge) static electricity, not all LDMOSs flow a uniform current. Flows, and there is a problem that the element is broken or the wiring connected to the element is blown.

For this reason, Patent Document 1 proposes a method for improving the ESD surge resistance of LDMOS. Specifically, a p ⁺ -type contact region formed adjacent to the n ⁺ -type source region is inserted into the lower portion of the source region.
JP 2001-352070 A

In the structure of Patent Document 1 described above, in order to further improve the ESD tolerance, it is effective to increase the concentration of the p-type impurity in the p ⁺ -type contact region that has entered the lower portion of the n ⁺ -type source region. It is believed that there is. However, when the dose amount of the ion implantation of the p-type impurity for forming the contact region is increased, there arises a problem that a crystal defect due to the ion implantation damage occurs.

It is also effective to increase the area of the p ⁺ -type contact region that enters the lower part of the n ⁺ -type source region. In order to realize such a method, the overlap amount (opposite amount) between the ion implantation region and the source region for forming the contact region is increased, or ion implantation for forming the contact region is performed. However, if the contact region extends to the channel region, there arises a problem that the operating threshold value Vt of the LDMOS varies.

  In view of the above points, the present invention makes it possible to suppress crystal defects caused by ion implantation damage and increase the operation threshold Vt of a semiconductor device when the concentration of a contact region that enters a lower portion of a source region is increased. The purpose is to prevent fluctuations.

  In order to achieve the above object, in the present invention, the step of forming the contact region includes a step of arranging a mask material (20, 30, 31) having an opening in a portion where the contact region is to be formed, and a step of using the mask material. The step of implanting the second conductivity type impurity into the lower portion of the source region by implanting the two conductivity type impurity obliquely with respect to the substrate surface, and activating the implanted second conductivity type impurity by heat treatment And a step of forming a contact region so as to enter the lower portion of the source region.

  In this manner, oblique ion implantation is performed when the contact region is formed. For this reason, the portion of the contact region that is formed so as to enter the lower portion of the source region can have a higher impurity concentration than the portion of the contact region that is formed on the substrate surface side of the base region. . Such oblique ion implantation makes it possible to suppress crystal defects due to ion implantation damage on the substrate surface. In addition, according to such oblique ion implantation, it is not necessary to increase the amount of overlap between the source region and the contact region or increase the heat treatment time, so that the contact region is prevented from diffusing up to the channel region. It becomes possible to do. Thereby, it is possible to prevent fluctuations in the operation threshold value Vt of the semiconductor device.

  In this case, an interlayer insulating film can be used as a mask material in the step of forming the contact region. Alternatively, Poly-Si for forming a gate electrode can be used as a mask material. Although only oblique ion implantation is described here, of course, the ion implantation step may be divided into oblique ion implantation and ion implantation in the direction perpendicular to the substrate.

  Further, the step of forming the contact region includes the step of arranging the first mask material (30) in which the portion where the contact region is to be formed and the oblique ion implantation using the first mask material, thereby forming the contact region. A step of introducing a second conductivity type impurity into a portion formed below the source region, and a second mask material (31) in which a portion where a contact region is to be formed opens after removing the first mask material (30). ) And a portion formed on the substrate surface side of the base region of the contact region by ion implantation of the second conductivity type impurity in the direction perpendicular to the substrate surface using the second mask material And a step of implanting a second conductivity type impurity.

  In this way, oblique ion implantation and ion implantation in the direction perpendicular to the substrate can be performed separately using two different mask materials, the first and second mask materials.

  In this case, for example, in the step of arranging the second mask material, an interlayer insulating film can be used as the second mask material. In the step of arranging the first mask material, Poly-Si for forming the gate electrode can be used as the first mask material.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
FIG. 1 shows a cross-sectional structure of an LDMOS to which an embodiment of the present invention is applied. The configuration of the LDMOS in this embodiment will be described below with reference to FIG.

  The LDMOS is formed on an SOI substrate in which an n-type substrate (semiconductor layer) 1 made of silicon and a p-type substrate 2 are bonded via an insulating film 3 made of a silicon oxide film.

The n-type substrate 1 has an impurity concentration of about 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻³ , and an insulating film 4 made of a LOCOS oxide film is formed on the surface of the n-type substrate 1. A high concentration n ⁺ -type drain region 5 is formed on the surface layer portion of the n-type substrate 1 so as to be in contact with the insulating film 4. An n-type region 6 is formed so as to surround this n ⁺ -type drain region 5. The n-type region 6 penetrates to the lower part of the insulating film 4 and is configured such that the concentration increases as the n ⁺ -type drain region 5 is approached with the n ⁺ -type drain region 5 as the center.

  A p-type base region 7 is formed in the surface layer portion of the n-type substrate 1. This p-type region terminates near the end of the insulating film. The p-type base region 7 is partially deepened, and the deepened region functions as a deep base layer.

An n ⁺ type source region 8 is formed on the surface layer portion of the p type base region 7 so as to be separated from the insulating film 4. Further, a p ⁺ type contact region 9 is formed on the surface layer portion of the p type base region 7 so as to be in contact with the n ⁺ type source region 8. The p ⁺ -type contact region 9, across the n ⁺ -type source region 8 is arranged closer to the opposite side of the n ⁺ -type drain region 5, a intruding structure to the lower part of the n ⁺ -type source region 8 ing.

A gate insulating film 10 is disposed on the surface of the p-type base region 7 sandwiched between the n ⁺ -type source region 8 and the n ⁺ -type drain region 5 (insulating film). A gate electrode 11 made of doped Poly-Si or the like is provided. With such a configuration, the surface layer portion of the p ⁺ type base region 7 located below the gate electrode 11 is used as a channel region, and the MOS operation is performed using the n type substrate 1 as an n type drift region. .

An interlayer insulating film 12 is disposed so as to cover the gate electrode 11, and the source electrode 13 and the drain electrode 14 are patterned on the interlayer insulating film 12. The source electrode 13 is connected to the n ⁺ type source region 8 and the p ⁺ type contact region 9 through the contact hole formed in the interlayer insulating film 12, and the drain electrode 14 is connected to the n ⁺ type drain region 5. ing.

  Although not shown, the SOI substrate surface is covered with a protective film or the like so as to cover the source electrode 13 and the drain electrode 14.

Next, a method for manufacturing the LDMOS according to the present embodiment will be described with reference to cross-sectional views showing the manufacturing steps shown in FIG. However, among the present embodiment LDMOS, with respect to other process of forming the p ⁺ -type contact region 9, since the conventional similar to that, only the step of forming the p ⁺ -type contact region 9 in FIG. 2, with respect to the other part The illustration and description are omitted.

First, an insulating film 4 is applied to an SOI substrate in which an n-type substrate (semiconductor layer) 1 and a p-type substrate 2 are bonded to each other through an insulating film 3 made of a silicon oxide film by the same method as in Patent Document 1. An n ⁺ type drain region 5, an n type region 6, a p type base region 7, an n ⁺ type source region 8, a gate insulating film 10 and a gate electrode 11 are formed. Then, p ⁺ -type contact region 9 is formed. In Patent Document 1, an example in which the n ⁺ -type drain region 5 and the n ⁺ -type source region 8 are formed after the p ⁺ -type contact region 9 is given. Of course, in the LDMOS manufacturing method of the present embodiment, Alternatively, this order may be adopted.

In the step of forming the p ⁺ -type contact region 9, as shown in FIG. 2, a mask material 20 is disposed so as to cover the n ⁺ -type source region 8, the gate electrode 11, the insulating film 4 and the n ⁺ -type drain region 5. The p-type impurity is ion-implanted from above the mask material 20 and the implanted p-type impurity is activated by heat treatment.

At this time, the ion implantation of the p-type impurity is an oblique ion implantation that is inclined with respect to the substrate surface, and the ion implantation range (implantation energy) is adjusted so that the p-type impurity is converted into the n ⁺ -type source region 8. Enter to the bottom of. The portion which is formed so as to enter under the n ⁺ -type source region 8 is formed on the substrate surface side of the p-type base region 7 of the p ⁺ -type contact region 9 of the p ⁺ -type contact region 9 as the impurity concentration is darker than the portion, a dose in the ion implantation of the portion which is formed so as to enter under the n ⁺ -type source region 8 of the p ⁺ -type contact region 9 p ⁺ -type contact region 9 The dose amount at the time of ion implantation of the portion of the p-type base region 7 formed on the substrate surface side is raised. Thereafter, the p-type impurity implanted by the heat treatment is thermally diffused and activated.

  Thereafter, although not shown, after the mask material 20 is removed, the formation process of the interlayer insulating film 12, the source electrode 13, the drain electrode 14, the protective film, and the like is performed, whereby the LDMOS of this embodiment can be manufactured. .

As described above, according to the LDMOS manufacturing method of this embodiment, oblique ion implantation is performed when the p ⁺ -type contact region 9 is formed. For this reason, the portion of the p ⁺ -type contact region 9 formed so as to enter under the n ⁺ -type source region 8 can easily have an impurity concentration higher than that of the portion on the substrate surface side. Such oblique ion implantation makes it possible to suppress crystal defects due to ion implantation damage on the substrate surface. Further, according to such oblique ion implantation, for or increase the amount of overlap between the n ⁺ -type source region 7 and the p ⁺ -type contact region 9, there is no need or increase the heat treatment time, to the channel region p ⁺ It is possible to prevent the mold contact region 9 from diffusing. This makes it possible to prevent fluctuations in the operating threshold value Vt of the LDMOS.

(Second Embodiment)
A second embodiment of the present invention will be described. In this embodiment, the process for forming the p ⁺ -type contact region 9 in the LDMOS is changed with respect to the first embodiment, and the structure of the LDMOS and other manufacturing processes are the same as those in the first embodiment. Only the step of forming the p ⁺ -type contact region 9 different from the first embodiment will be described.

FIG. 3 is a cross-sectional view showing the manufacturing process of the p ⁺ -type contact region 9 of this embodiment.

In the step of forming the p ⁺ -type contact region 9, first, as shown in FIG. 3A, a mask material 20 is formed so as to cover the n ⁺ -type source region, the gate electrode 11, the insulating film 4 and the n ⁺ -type drain region 5. Then, a p-type impurity is introduced below the n ⁺ -type source region 8 by oblique ion implantation with a high acceleration voltage from above the mask material 20. Subsequently, as shown in FIG. 3B, by using the mask material 20 as it is, p-type impurities are ion-implanted at a low acceleration voltage from the direction perpendicular to the substrate, whereby the p-type of the p ⁺ -type contact region 9 is implanted. A p-type impurity is also ion-implanted into a portion of the base region 7 formed on the substrate surface side. Here, p-type base region 7 of the dose of the ion implantation of the portion which is formed so as to enter under the n ⁺ -type source region 8 of the p ⁺ -type contact region 9 p ⁺ -type contact region 9 Higher than the dose at the time of ion implantation of the portion formed on the substrate surface side. Thereafter, the p-type impurity implanted by the heat treatment is thermally diffused and activated.

Thus, the ion implantation for forming the p ⁺ -type contact region 9 may be performed in two steps. Even if it does in this way, the effect similar to 1st Embodiment can be acquired.

(Third embodiment)
A second embodiment of the present invention will be described. In this embodiment, the process for forming the p ⁺ -type contact region 9 in the LDMOS is changed with respect to the first embodiment, and the structure of the LDMOS and other manufacturing processes are the same as those in the first embodiment. Only the step of forming the p ⁺ -type contact region 9 different from the first embodiment will be described.

FIG. 4 is a cross-sectional view showing the manufacturing process of the p ⁺ -type contact region 9 of this embodiment.

In the step of forming the p ⁺ -type contact region 9, first, as shown in FIG. 4A, a first mask is formed so as to cover the n ⁺ -type source region, the gate electrode 11, the insulating film 4, and the n ⁺ -type drain region 5. The material 30 is arranged. At this time, the opening end of the opening of the first mask material 30 is made to reach the n ⁺ type source region 7 (or the region where the n ⁺ type source region 7 is to be formed). Then, a p-type impurity is introduced from above the first mask material 30 to below the n ⁺ -type source region 8 by oblique ion implantation at a high acceleration voltage. Subsequently, as shown in FIG. 4B, after the first mask material 30 is removed, the second mask material 31 is disposed. At this time, the opening end of the opening of the first mask material 30 is made to coincide with the end of the n ⁺ type source region 7 (or the region where the n ⁺ type source region 7 is to be formed). Then, by using the second mask material 31, p-type impurities are ion-implanted from the direction perpendicular to the substrate at a low acceleration voltage to form the p ⁺ -type contact region 9 on the substrate surface side of the p-type base region 7. A p-type impurity is also ion-implanted into the portion. At the time of ion implantation of these p-type impurities, similarly to the second embodiment, the dose amount of the portion formed so as to enter the n ⁺ -type source region 8 in the p ⁺ -type contact region 9 is set to p ^+. The dose amount of the portion of the p-type base region 7 of the p-type contact region 9 formed on the substrate surface side is made higher. Thereafter, the p-type impurity implanted by the heat treatment is thermally diffused and activated.

As described above, ion implantation for forming the p ⁺ -type contact region 9 may be performed in two steps, and different mask materials 30 and 31 may be used in each step. Even if it does in this way, the effect similar to 1st Embodiment can be acquired.

(Other embodiments)
In the first embodiment, the P-type contact region 9 is formed by one-step oblique ion implantation using the mask material 20, and the mask material 20 is used only as an example during oblique ion implantation. In particular, the portion remaining in the LDMOS may be used as the mask material 20. In this way, the p ⁺ -type contact region 9 can be formed by self-alignment (self-alignment).

For example, as shown in the cross-sectional view of FIG. 5, the interlayer insulating film 12 made of BPSG or the like may be used as the mask material 20 and the p ⁺ -type contact region 9 may be formed by performing oblique ion implantation. In this case, the n ⁺ -type drain region 5 so as not doped with p-type impurity, is arranged a mask material 21 so as to cover at least the n ⁺ -type drain region 5.

Further, as shown in the sectional view of FIG. 6, the gate electrode 11 made of Poly-Si may be used as the mask material 20. In this case, the n ⁺ -type drain region 5 so as not doped with p-type impurity, is arranged a mask material 21 so as to cover at least the n ⁺ -type drain region 5.

Similarly, in the third embodiment, an example is shown in which ion implantation for forming the p ⁺ -type contact region 9 is performed in two steps, and different mask materials 30 and 31 are used in each step. However, the portions finally remaining in the LDMOS may be used as the mask materials 30 and 31.

For example, as shown in FIG. 7A, the first mask material 30 is used only for oblique ion implantation that does not finally remain in the LDMOS, and thereafter, as shown in FIG. The p ⁺ -type contact region 9 may be formed by using the interlayer insulating film 12 constituted by the above as the second mask material 31 and performing ion implantation from the direction perpendicular to the substrate. In this case also, the n ⁺ -type drain region 5 so as not doped with p-type impurity, to place the mask material 32 so as to cover at least the n ⁺ -type drain region 5.

Similarly, as shown in FIG. 8A, after performing oblique ion implantation at a high acceleration voltage using the gate electrode 11 made of Poly-Si as the first mask material 30, the second mask material 31 is arranged. Alternatively, the p ⁺ -type contact region 9 may be formed by ion implantation in the vertical direction at a low acceleration voltage. Also in this case, since no Ooe the n ⁺ -type drain region 5 in the gate electrode 11, n ⁺ -type as p-type impurities are not doped drain region 5, the mask so as to cover at least the n ⁺ -type drain region 5 The material 33 is arranged.

Further, as shown in FIG. 9, by performing etching using the mask material 20, the tapered recess 40 is formed in the regions where the n ⁺ -type source region 7 and the n ⁺ -type contact region 9 are to be formed, and then the mask is formed. The p ⁺ -type contact region 9 may be formed by performing oblique ion implantation using the material 20.

  In the above description, the n-channel type LDMOS has been described. Of course, the present invention can also be applied to a p-channel type LDMOS in which the conductivity type is inverted.

It is a figure which shows the cross-section of LDMOS in 1st Embodiment of this invention. It is a figure which shows the manufacturing process of LDMOS shown in FIG. It is a figure which shows the formation process of the p ⁺ type contact region of LDMOS in 2nd Embodiment of this invention. It is a figure which shows the formation process of the p ⁺ type contact region of LDMOS in 3rd Embodiment of this invention. It is a figure which shows the formation process of the p ⁺ type contact region of LDMOS demonstrated in other embodiment. It is a figure which shows the formation process of the p ⁺ type contact region of LDMOS demonstrated in other embodiment. It is a figure which shows the formation process of the p ⁺ type contact region of LDMOS demonstrated in other embodiment. It is a figure which shows the formation process of the p ⁺ type contact region of LDMOS demonstrated in other embodiment. It is a figure which shows the formation process of the p ⁺ type contact region of LDMOS demonstrated in other embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... N type substrate, 2 ... P type substrate, 3 ... Insulating film, 4 ... Insulating film, 5 ... N ^<+> type drain region,
6 ... n-type region, 7 ... p-type base region, 8 ... n ⁺ -type source region,
9 ... p ⁺ type contact region, 10 ... gate insulating film, 11 ... gate electrode,
12 ... interlayer insulating film, 13 ... source electrode, 14 ... drain electrode,
20, 30-33 ... mask material, 40 ... concave part.

Claims (6)

Forming a first conductivity type region (6) in a surface layer portion of the semiconductor layer among the substrates (1 to 3) having the first conductivity type semiconductor layer (1);
Forming a LOCOS oxide film (4) partially opening on a part of the first conductivity type region and a part of the semiconductor layer on the semiconductor layer including the first conductivity type region; ,
Forming a gate insulating film (10) in a portion of the semiconductor layer where the LOCOS oxide film (4) is opened;
Forming a gate electrode (11) on the gate insulating film including the LOCOS oxide film;
Forming a second conductivity type base region (7) in a surface layer portion of the semiconductor layer using the gate electrode as a mask;
Forming a second conductivity type contact region (9) having a concentration higher than that of the base region in a region including the substrate surface side of the base region in the base region;
A first conductivity type source region (8) is formed in the base region, and a first conductivity type drain region (5) having a higher concentration than the first conductivity type region is formed in the first conductivity type region. )
Forming an interlayer insulating film (12) on the substrate including the gate electrode; and
A source electrode (13) electrically connected to the source region and the contact region is formed through the interlayer insulating film, and a drain electrode (14) electrically connected to the drain region is formed. Including a process,
The step of forming the contact region includes:
A step of disposing a mask material (20, 30, 31) in which a portion where the contact region is to be formed is opened;
A step of allowing the second conductivity type impurity to enter the lower portion of the source region by performing oblique ion implantation of the second conductivity type impurity oblique to the substrate surface using the mask material;
And a step of forming the contact region so as to enter the lower portion of the source region by activating the implanted second conductivity type impurity by heat treatment. 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of forming the contact region, the interlayer insulating film is used as the mask material. In the step of forming the gate electrode, the gate electrode is formed using Poly-Si,
2. The method of manufacturing a semiconductor device according to claim 1, wherein, in the step of forming the contact region, the Poly-Si is used as the mask material to form the gate electrode. The step of forming the contact region includes:
The step of disposing the first mask material (30) in which the portion where the contact region is to be formed is disposed, and the oblique ion implantation is performed using the first mask material, whereby the source region of the contact region is formed. A step of introducing a second conductivity type impurity into a portion formed in the lower portion;
After removing the first mask material (30), placing a second mask material (31) in which a portion where the contact region is to be formed is opened; and
A second conductivity type impurity is ion-implanted in a direction perpendicular to the substrate surface using the second mask material, so that a second portion of the contact region is formed on the substrate surface side of the base region. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of injecting a conductivity type impurity. 5. The method of manufacturing a semiconductor device according to claim 4, wherein in the step of arranging the second mask material, the interlayer insulating film is used as the second mask material. In the step of forming the gate electrode, the gate electrode is formed using Poly-Si,
6. The method of manufacturing a semiconductor device according to claim 4, wherein, in the step of arranging the first mask material, the Poly-Si for forming the gate electrode is used as the first mask material. .

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