JP2008181179A - Processor and arithmetic unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve high speed arithmetic execution for preventing a bottleneck from being caused by a low-speed memory access. <P>SOLUTION: A processor 1 for performing arithmetic processing based on an instruction and an operand stored in a main memory 2 is provided with: a register 5; an internal memory 6; a fetch unit 4 to be operated by a first operation clock for transferring an instruction and an operand from the main memory 2 to the internal memory 6 for storage; and an arithmetic execution unit 3 to be operated by a second operation clock different from the first operation clock for performing an arithmetic operation by using the register 5 based on the instruction and the operand stored in the internal memory 6. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a processor and an arithmetic device using the processor.

  An apparatus that performs arithmetic processing in an electronic device is composed of a processor, a memory, and other peripheral circuits, and always requires higher speed. In a microprocessor based on an architecture such as CISC or RISC, pipeline processing in which instruction cycles are divided into stages and high-speed access by a cache memory in which memories are hierarchized are used for speeding up the processor. In other architectures, there are reconfigurable processors that enable high-speed arithmetic processing by performing dynamic reconfiguration.

  In pipeline processing, the execution process of one instruction of a processor is divided into a plurality of stages and executed in parallel. The number of stages varies depending on the processor. Generally, the higher the number of stages, the higher the speed, but the hardware structure of the processor becomes complicated and the circuit scale increases. Examples of the division into a plurality of stages include instruction fetch (IF), decode (ID), operand address calculation (OA), operand fetch (OF), instruction execution (EX), and operation result storage (RS). There is an example divided into six stages.

  In the memory hierarchization, for example, a register, a cache memory, a main memory, and an auxiliary storage device are configured from the hierarchy closest to the processor operation execution unit. In this case, the register can be accessed at the highest speed, but the storage capacity is the smallest. The auxiliary storage device has the largest storage capacity, but the access speed is the slowest.

  A method of accumulating instructions and operands accessed to the main memory in the cache memory inside the processor when fetching an instruction cycle, because access to the main memory outside the processor is slow for a register operating at the maximum operating frequency inside the processor (See, for example, Patent Document 1). In this case, when the cache memory is hit, high-speed access can be performed, but when the cache memory is miss-hit, the main memory having a lower speed than the cache memory is accessed.

A reconfigurable processor configures the operation content in a hardware circuit inside the processor, and transfers the operation content stored in the main memory to the processor and switches the hardware circuit to cope with various operations.
JP-A-6-242951

  In pipeline processing, memory access is required for instruction fetch (IF) and operand fetch (OF) in the pipeline stage. In the instruction cycle in which the cache memory is miss-hit, the instruction and operand that accessed the main memory are stored in the cache memory. At this time, if the amount stored in the cache memory exceeds the maximum capacity, the memory is overwritten according to a predetermined algorithm. For this reason, parallel execution in the pipeline is ideally performed when everything hits the cache memory, but a miss occurs according to the hit rate of the cache memory, and access to the main memory occurs, resulting in faster execution of operations. Bottleneck.

  In the reconfigurable processor, the capacity of the hard circuit is limited, and the arithmetic processing that can be arranged in the hard circuit can be executed at high speed. However, for the arithmetic contents exceeding the capacity of the hard circuit, access to the main memory and the hard circuit It is not possible to increase the speed because switching is required. Increasing the capacity of the hardware circuit directly increases the cost of the processor, and the maximum capacity is physically limited.

  Therefore, an object of the present invention is to enable high-speed arithmetic execution in which low-speed memory access does not become a bottleneck.

  In order to solve the above-described problems, the present invention provides a processor that performs arithmetic processing based on instructions and operands stored in a main memory, and operates with a register, an internal memory, and a first operation clock. Fetch unit for transferring and storing data from the main memory to the internal memory, and the register based on instructions and operands stored in the internal memory operating at a second operating clock different from the first operating clock. And an operation execution unit that performs an operation using.

  In the arithmetic device, the present invention provides a main memory, a register, an internal memory, a fetch unit that operates with a first operation clock and transfers instructions and operands from the main memory to the internal memory for storage. And a processor including an operation execution unit that operates using a second operation clock different from the first operation clock and performs an operation using the register based on an instruction and an operand stored in the internal memory. It is characterized by.

  According to the present invention, it is possible to execute high-speed computations in which low-speed memory access does not become a bottleneck.

  Embodiments of an arithmetic device according to the present invention will be described with reference to the drawings. In addition, the same code | symbol is attached | subjected to the same or similar structure, and the overlapping description is abbreviate | omitted. The following embodiments are merely examples, and the present invention is not limited to these.

  FIG. 1 is a block diagram of an embodiment of an arithmetic device according to the present invention.

  The arithmetic device 10 according to the present embodiment includes a processor 1 and a main memory 2. The processor 1 includes an operation execution unit 3, a fetch unit 4, a register 5, and an internal memory 6. The arithmetic execution unit 3, the fetch unit 4, the register 5, and the internal memory 6 are connected to each other. The processor 1 and the main memory 2 are connected via a fetch unit 4. The main memory 2 and the internal memory 6 include areas for instructions (instructions) and operands (operands), and these areas are referred to as instruction areas 21 and 61 and operand areas 22 and 62, respectively.

  The operation execution unit 3 performs operations using the internal memory 6 and the register 5. The fetch unit 4 performs data transfer between the main memory 2 and the internal memory 6.

  The operation execution unit 3 and the fetch unit 4 each constitute a pipeline.

  FIG. 2 is a diagram showing instruction cycles of the operation execution unit and the fetch unit in the present embodiment. The horizontal axis in FIG. 2 indicates the passage of time.

  The arithmetic execution unit 3 operates in an instruction cycle 7 having a 6-stage configuration. These six stages are instruction fetch (IF), instruction decode (ID), operand address calculation (OA), operand fetch (OF), instruction execution (EX), and operation result storage (RS). is there. Each stage at the same position on the vertical axis in FIG. 2 means the same instruction cycle.

  The fetch unit 4 operates in an instruction cycle 8 having a 5-stage configuration. These five stages are: instruction fetch from main memory 2 and instruction transfer to internal memory (IF2), instruction decode in fetch unit 4 (ID2), operand address calculation in fetch unit 4 (OA2) The operand fetch from the main memory 2 and the transfer to the internal memory (OF2), and the calculation result stored in the internal memory 6 is stored in the main memory 2 (RS2).

  The six stages of the instruction cycle of the arithmetic execution unit 3 are performed with the first operation clock. The five stages of the instruction cycle of the fetch unit 4 are performed with the second operation clock. The second operation clock of the fetch unit 4 that accesses the main memory 2 that is slower than the internal memory 6 is smaller than the first operation clock. Thus, the operation execution unit 3 and the fetch unit 4 operate asynchronously.

  FIG. 3 is a diagram showing a map of the instruction area 21 of the main memory 2 in the present embodiment.

  An instruction fetch address is a continuous area from a predetermined address to a branch instruction, and instruction fetch can be performed by burst access to the main memory 2 at high speed. When a branch instruction has no branch, it can be handled as a continuous area, but when a branch instruction has a branch, fetching from the address indicated by the operand of the branch instruction is required.

  Therefore, in the OF2 of the instruction cycle of the fetch unit 4, in the case of a branch instruction, the fetch unit 4 accumulates both instructions with and without a branch in the internal memory 6 according to the branch destination indicated by the operand. . As a result, the pipeline processing of the operation execution unit 3 can be continued without delay even for branch instruction execution.

  When the operand of the branch instruction uses the register 5 as an address, the fetch unit 4 accesses the register 5 to obtain the branch destination address in the main memory 2 and access the address.

  FIG. 4 is a diagram showing a map of the operand area 22 of the main memory 2 in the present embodiment.

  The address for fetching the operand of the main memory 2 is included in the instruction. Random access having a different value for each instruction is required except for the table processing instruction to the continuous area. The fetch unit 4 performs instruction fetch from the main memory 2, instruction transfer to the internal memory 6 (IF2), instruction decode (ID2), and operand address calculation (OA2). For this reason, the fetch unit 4 can grasp the address of an operand that takes a random value and transfer the operand to the internal memory 6.

  Further, the fetch unit 4 converts the operand address of the main memory 2 into the operand address of the internal memory 6. Thereby, the operation execution unit 3 can execute an instruction using the operand transferred to the internal memory 6 and stored. When the register 5 is used as the operand address of the main memory 2, the fetch unit 4 accesses the register 5 to obtain the operand address in the main memory 2, and accesses the address in the main memory 2. Can do.

  In this way, the operation execution unit 3 executes an operation using the instruction and operand that the fetch unit 4 has previously transferred to the internal memory 6. For this reason, the instruction cycle of the operation execution unit 3 can continue the pipeline processing at the maximum operating frequency inside the processor 1 without being restricted by the access cycle to the external low-speed main memory 2. That is, it is possible to execute high-speed computations where low-speed memory access does not become a bottleneck.

It is a block diagram in one embodiment of an arithmetic unit according to the present invention. It is a figure which shows the instruction cycle of the operation execution unit and fetch unit in one Embodiment of the arithmetic unit which concerns on this invention. It is a figure which shows the map of the instruction area of the main memory in one Embodiment of the arithmetic unit which concerns on this invention. It is a figure which shows the map of the operand area | region of the main memory in one Embodiment of the arithmetic unit which concerns on this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Processor, 2 ... Main memory, 3 ... Operation execution unit, 4 ... Fetch unit, 5 ... Register, 6 ... Internal memory, 7, 8 ... Instruction cycle, 10 ... Arithmetic unit, 21 ... Instruction area, 22 ... Operand area 61 ... Instruction area 62 ... Operand area

Claims (8)

In a processor that performs arithmetic processing based on instructions and operands stored in main memory,
Registers,
Internal memory,
A fetch unit that operates at a first operating clock to transfer and store instructions and operands from the main memory to the internal memory;
An operation execution unit that operates using a second operation clock different from the first operation clock and performs an operation using the register based on an instruction and an operand stored in the internal memory;
A processor characterized by comprising:   When the instruction transferred to and stored in the internal memory is a branch instruction, the fetch unit receives the instruction and the operand from the branch destination address indicated by the address when there is no branch and the branch instruction operand. 2. The processor according to claim 1, wherein the processor is transferred to and stored in a memory.   3. The processor according to claim 2, wherein the fetch unit converts an address of the main memory at a branch destination indicated by an operand of the branch instruction into an address of the internal memory.   4. The fetch unit according to claim 2, wherein when the operand of the branch instruction uses the register as an address, the fetch unit accesses the register to obtain an address of the branch destination main memory. The processor described in.   The fetch unit includes instruction fetch from the main memory and instruction transfer to the internal memory, instruction decode, operand address calculation, operand fetch from the main memory and operand transfer to the internal memory, and the internal 5. The processor according to claim 1, wherein the operation result stored in the memory is stored in the main memory by a pipeline. 6.   The processor according to any one of claims 1 to 5, wherein the fetch unit converts an operand address of the main memory into an operand address of the internal memory.   7. The fetch unit according to claim 1, wherein when the register is used as an operand address of the main memory, the fetch unit accesses the register and acquires the operand address of the main memory. The processor according to item 1. Main memory,
A register, an internal memory, a fetch unit that operates with a first operation clock to transfer instructions and operands from the main memory to the internal memory, and a second operation clock different from the first operation clock A processor comprising an operation execution unit that operates and performs an operation using the register based on instructions and operands stored in the internal memory;
An arithmetic device comprising:

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