JP2008172213A - Semiconductor module, method for manufacturing the same and mobile apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing technology capable of improving the reliability of a semiconductor module having a via contact connected to an electrode part of a semiconductor device. <P>SOLUTION: A conductive bump 5a is formed on an insulating layer 4 and arranged so that the tip part of the conductive bump 5a is in contact with the surface of an electrode 2 of a semiconductor substrate 1. By pressure-molding the arranged assembly by using a press machine, the semiconductor substrate 1, the conductive bump 5a and the insulating layer 4 are integrated. Thereby, the conductive bump 5a is allowed to embed itself in the insulating layer 4 while maintaining contact with the electrode 2. The insulating layer 4 is subjected to laser irradiation from above so as to form an aperture part 7 exposing the conductive bump 5a. Then, the upper surface of the insulating layer 4 and the inner surface of the aperture part 7 are plated with copper by an electroless plating method and an electroplating method to form a copper plating layer 8 on the insulating layer 4 and a via contact 8b is formed in the aperture part 7 so as to coat the inwall of the aperture part 7. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor module and a manufacturing method thereof.

In recent years, with the miniaturization and high functionality of electronic devices, there has been a demand for miniaturization of semiconductor elements used in electronic devices. To achieve this, it is essential to narrow the pitch between the external connection electrodes of the semiconductor element, but the size of the external connection electrodes is reduced due to the size of the solder bumps and the occurrence of bridges during soldering. There were limits. In recent years, in order to overcome such limitations, rearrangement of external connection electrodes has been performed by forming rewirings in semiconductor elements. In general, when such rewiring is formed in a semiconductor element, a signal from the semiconductor element in the semiconductor module is taken out to the outside through the electrode pad. Therefore, a via contact is made to the insulating resin layer provided on the electrode pad. An opening is formed. At this time, since the semiconductor element is arranged below the electrode pad, it is necessary to form such an opening without applying high heat. However, when the opening on the electrode pad is formed by conventional laser irradiation, damage to the semiconductor element through the electrode pad due to the heat of the laser and accompanying reliability deterioration of the semiconductor element become a problem. As a method for solving this, a method has been proposed in which an opening is processed in the insulating resin layer on the electrode pad by laser irradiation and subsequent dry etching (see Patent Document 1). In the method of forming an opening described in Patent Document 1, an opening is made with a laser to such a depth that the semiconductor element is not damaged, and then the opening is made by dry etching.
JP 2005-286041 A

  However, in the above method, although the influence of heat by laser irradiation can be suppressed, the electrode pad exposed at the final stage during dry etching is exposed to the plasma atmosphere, and the semiconductor element (transistor, etc.) connected thereto is exposed. Charge-up damage will be added. For this reason, the device characteristics are deteriorated along with this, and there is a concern that the reliability of the semiconductor element is lowered. In the future, in order to further reduce the size of the semiconductor module, when the size of the opening is reduced, the coverage of the via contact formed in the opening will deteriorate, resulting in a decrease in the reliability of the semiconductor module. Is a problem.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a manufacturing technique for improving the reliability of a semiconductor module having a via contact connected to an electrode portion of a semiconductor element. Another object of the present invention is to provide a semiconductor module having a via contact with good connection reliability with an electrode portion of a semiconductor element.

  One embodiment of the present invention is a semiconductor module. The semiconductor module includes a semiconductor element having an electrode portion provided on a mounting surface, an insulating layer provided on the mounting surface of the semiconductor element, a wiring layer formed on the insulating layer, and an electrode embedded in the insulating layer. A first conductor portion that is in contact with the portion, and a second conductor portion that is formed in an opening provided in the insulating layer above the first conductor portion and electrically connects the conductor portion and the wiring layer. It is characterized by providing.

  According to the above aspect, since the opening in which the second conductor is formed is formed on the first conductor embedded in the insulating layer, the opening is formed so as to be directly connected to the electrode. The depth is shallower than For this reason, the coverage of the 2nd conductor part formed in the opening part can be improved, and the connection reliability between the 1st conductor part and the 2nd conductor part can be improved.

  In the above aspect, the first conductor portion may be thinner as it approaches the contact surface with the electrode portion. Moreover, the said aspect WHEREIN: The conductor part may become thin as it approaches the contact surface with the said 2nd conductor part.

  Another aspect of the present invention is a method for manufacturing a semiconductor module. The manufacturing method of the semiconductor module includes a first step of preparing a substrate having an electrode on the surface, a second step of forming a first conductor portion on one surface of the insulating layer, an electrode, and a first step. A third step of embedding the first conductor portion in the insulating layer by pressing the insulating layer on the substrate in contact with the conductor portion, and the first conductor portion exposed from the other surface of the insulating layer And a fourth step of forming an opening in the second portion and a fifth step of forming a second conductor portion in the opening.

  According to this aspect, since the opening for forming the second conductor is formed on the first conductor embedded in the insulating layer, the opening is formed so as to be directly connected to the electrode. The depth can be reduced as compared with the case of doing so. For this reason, the coverage of the 2nd conductor part formed in an opening part can be improved, and the connection reliability between a 1st conductor part and a 2nd conductor part can be improved. In addition, the formation time of the opening can be shortened, and the throughput when manufacturing the semiconductor module can be improved.

  In the above aspect, in the second step, it is preferable that the first conductor portion is formed so as to have a side portion whose dimensions become narrower as it approaches a portion in contact with the insulating layer. By doing in this way, when embedding the 1st conductor part in an insulating layer in the state which contacted the electrode, the 1st conductor part can be smoothly embedded in an insulating layer. For this reason, the throughput of this process can be improved and the cost of the semiconductor module with improved reliability can be reduced.

  In the above aspect, the third step preferably includes a step of pressure-bonding the insulating layer to the substrate in a semi-cured state and a step of heating and curing the insulating layer. By doing in this way, it becomes possible to embed the first conductor portion in the insulating layer in a self-aligning manner and easily. For this reason, a semiconductor module with improved reliability can be manufactured at a lower cost.

  Another embodiment of the present invention is a portable device. The portable device is characterized by mounting any of the semiconductor modules described above.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing technique which makes the reliability of the semiconductor module which has a via contact connected with the electrode part of a semiconductor element favorable is provided.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, embodiments of the invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

(First embodiment)
FIG. 1 is a schematic cross-sectional view showing the configuration of the semiconductor module according to the first embodiment of the present invention. The semiconductor module according to the first embodiment will be described with reference to FIG.

  As the semiconductor substrate 1, a P-type silicon substrate or the like is adopted, and a predetermined semiconductor element (not shown) is formed on the surface S (upper surface side) by a well-known technique, and the surface S (particularly the peripheral portion) serving as a mounting surface. The electrode 2 of the semiconductor element is formed on the substrate. A protective film 3 is formed in a region on the surface of the semiconductor substrate 1 so that a predetermined region of the electrode 2 is exposed. On the surface S of the semiconductor substrate 1, an insulating layer 4 is formed on the electrode 2 and the protective film 3 and a rewiring pattern 8 a is formed thereon in order to increase the pitch of the electrodes 2. Here, the connection between the electrode 2 and the rewiring pattern 8a is made through a conductive bump 5a connected to the exposed surface of the electrode 2 and a via contact 8b connected to the conductive bump 5a. External connection electrodes (solder bumps) 9 are provided in a predetermined region of the rewiring pattern 8 a, and the other regions are covered with a solder resist layer 10. The semiconductor substrate 1 is the “substrate” according to the present invention, the electrode 2 is the “electrode” according to the present invention, the insulating layer 4 is the “insulating layer” according to the present invention, and the conductive bump 5 a is the “first conductor” according to the present invention. The via contact 8b is an example of the “second conductor portion” in the present invention.

Specifically, the insulating layer 4 is formed on the surface S (upper surface side) of the semiconductor substrate 1 and has a thickness of about 80 μm, for example. The insulating layer 4 is made of a material that causes plastic flow when pressed. An example of a material that causes plastic flow when pressed is an epoxy thermosetting resin. The epoxy thermosetting resin employed for the insulating layer 4 may be any material having a viscosity of 1 kPa · s under conditions of a temperature of 160 ° C. and a pressure of 8 MPa, for example. In addition, when the material is pressed at 15 MPa under the condition of a temperature of 160 ° C., the viscosity of the resin is reduced to about 1/8 as compared with the case where no pressure is applied. On the other hand, the B stage epoxy resin before thermosetting is not as viscous as when the resin is not pressurized under the condition of the glass transition temperature Tg or less, and no viscosity is produced even if it is pressurized. The epoxy thermosetting resin may be a film of a type in which a woven glass fiber is impregnated with a resin. Or 2 μm in the insulating layer
It may be a film to which a filler having a diameter of about 10 μm is added. Examples of the filler include alumina (Al ₂ O ₃ ), silica (SiO ₂ ), aluminum nitride (AlN), silicon nitride (SiN), and boron nitride (BN). Further, the weight filling rate of the filler is about 30% to 80%.

  The conductive bump 5a is made of metal such as copper (Cu) and is embedded in the insulating layer 4 so as to be in contact with the exposed surface of the electrode 2. The height of the conductive bump 5a is, for example, about 50 μm. The conductive bump 5a is provided in a truncated cone (the cross-sectional shape is trapezoidal), and the tip (parallel) to the contact surface with the electrode 2 of the semiconductor substrate 1 and the diameter (dimension) become narrower as the tip approaches. And a side surface portion 5a1 formed on the surface. The diameter of the tip and the base surface of the conductive bump 5a are about 80 μmφ and about 100 μmφ, respectively. The conductive bump 5 a is provided at a position corresponding to the electrode 2. The tip of the conductive bump 5 a is formed so as to be in direct contact with the electrode 2 of the semiconductor substrate 1.

  The rewiring pattern 8a is formed on the insulating layer 4 and has a thickness of about 20 μm, for example. The rewiring pattern 8a is made of, for example, a metal such as copper (Cu), and is electrically connected to the conductive bump 5a through the via contact 8b provided in the opening 7 of the insulating layer 4. Here, the via contact 8b is provided so as to cover the inner surface of the opening 7 (opening width: about 100 μm), and is formed integrally with the rewiring pattern 8a. Since the conductive bump 5a is interposed on the electrode 2, the depth of the via contact 8b (opening 7) is about 30 μm, and the via contact (opening) is formed directly on the electrode 2. The depth is shallow compared to.

As described above, in the first embodiment of the present invention, the rewiring pattern 8a is formed on the electrode 2 of the semiconductor substrate 1 via the conductive bumps 5a and the via contacts 8b, so that the signal from the semiconductor module is received. I try to take it out.
(Production method)
FIG. 2 is a schematic cross-sectional view for explaining a method for forming an insulating layer with conductive bumps according to the first embodiment, and FIG. 3 is a schematic cross-sectional view for explaining a manufacturing process of the semiconductor module according to the first embodiment. It is. Next, a manufacturing process of the semiconductor module according to the first embodiment will be described with reference to FIGS.

  First, as shown in FIG. 2A, an epoxy thermosetting resin is used, and a copper foil 5z having a thickness of about 3 μm is formed on the insulating layer 4 having a thickness of about 80 μm.

  As shown in FIG. 2B, copper is plated on the surface of the copper foil 5z using an electroless plating method and an electrolytic plating method. Thereby, the copper layer 5 having a thickness of about 50 μm is formed on the insulating layer 4.

  As shown in FIG. 2C, a resist mask 6 is formed in a conductive bump formation region on the copper layer 5 using a normal lithography method. Here, the conductive bump formation region corresponds to the position of the electrode 2 of the semiconductor substrate 1 shown in FIG.

  As shown in FIG. 2D, a wet bump process using a chemical solution is performed using the resist mask 6 as a mask to form a conductive bump 5a having a predetermined truncated cone pattern. At this time, the conductive bump 5a is formed to have a side surface portion 5a1 whose diameter (dimension) becomes narrower as it approaches the tip portion. Here, the height of the conductive bump 5a is about 50 μm, and the diameter of the tip and the base surface of the conductive bump 5a are about 80 μmφ and about 100 μmφ, respectively. Then, the resist mask 6 is removed. In the series of steps described above, the insulating layer 4 which is a thermosetting resin is not completely cured by heat so that the insulating layer 4 is not semi-cured (a state in which it easily flows). Like to maintain.

  The insulating layer 4 with the conductive bumps 5a manufactured in this way is prepared separately and used in the manufacturing process of the semiconductor module in the first embodiment described below.

First, as shown in FIG. 3A, a predetermined semiconductor element (not shown) and its peripheral portion are formed on the surface S (upper surface side) of the semiconductor substrate 1 such as a P-type silicon substrate by a well-known technique. Alternatively, the electrode 2 is formed on the top. Generally, a metal such as aluminum is adopted as the material of the electrode 2. An insulating protective film 3 for protecting the semiconductor substrate 1 is formed in a region on the surface S of the semiconductor substrate 1 so that a predetermined portion of the electrode 2 is exposed. As the protective film 3, a silicon oxide film (SiO ₂ ), a silicon nitride film (SiN), or the like is employed.

  As shown in FIG. 3B, the conductive bump 5a is disposed on the electrode 2 of the semiconductor substrate 1 so that the tip of the conductive bump 5a is in contact therewith. In addition, the formation method of the insulating layer 4 with the conductive bump 5a is as described above.

  As shown in FIG. 3C, the semiconductor substrate 1, the conductive bumps 5a, and the insulating layer 4 are integrated (press-fit) by arranging them as described above and press-molding them using a press device. Step). The pressure and temperature during pressing are about 5 MPa and 200 ° C., respectively. By this press working, the viscosity of the insulating layer 4 decreases, and the insulating layer 4 causes plastic flow. As a result, the conductive bump 5a is embedded in the insulating layer 4 in a self-aligning manner in contact with the electrode 2. Since the thickness of the insulating layer 4 is about 80 μm and the height of the conductive bump is about 50 μm, the conductive bump 5a is embedded without penetrating the insulating layer 4 during pressure shaping.

  Subsequently, heat treatment (150 ° C., 30 minutes) is applied to the insulating layer 4 to completely cure the insulating layer 4 (curing step). As a result, the insulating layer 4 is pressure-bonded and fixed on the semiconductor substrate 1, and the conductive bump 5 a is fixed in the insulating layer 4 in contact with the electrode 2.

  As shown in FIG. 3D, openings 7 are formed so that the conductive bumps 5a are exposed by irradiating laser from the upper surface of the insulating layer 4. Here, for the laser irradiation, for example, a carbon dioxide laser is employed, and irradiation is performed in two stages of a first condition and a second condition in which the pulse width is changed. A laser with a pulse period of 0.25 ms and an output of 1.0 W is used. As the first condition, for example, the pulse width can be 8 to 10 μs and the number of shots can be 1. As the second condition, for example, the pulse width can be 3 to 5 μs, the pulse interval can be 25 ms or more, and the number of shots can be 3. As a result, an opening 7 having a tapered sidewall whose diameter decreases from the surface of the insulating layer 4 toward the conductive bump 5a is formed.

  As shown in FIG. 3E, copper is plated to a thickness of about 20 μm on the upper surface of the insulating layer 4 and the inner surface of the opening 7 by using an electroless plating method and an electrolytic plating method. As a result, a copper plating layer 8 having a thickness of about 20 μm is formed on the insulating layer 4, and a via contact 8 b is formed in the opening 7 so as to cover the inner wall thereof.

  Finally, as shown in FIG. 1, the copper plating layer 8 is processed by using a normal lithography technique and an etching technique to pattern the rewiring pattern 8a having a predetermined line / space pattern. Then, the solder resist layer 10 is formed so as to cover the insulating layer 4 and the rewiring pattern 8a on the semiconductor substrate 1 and to have an opening in the electrode pad formation region of the rewiring pattern 8a. The solder resist layer 10 functions as a protective film for the rewiring pattern 8a. Note that an epoxy resin or the like is employed for the solder resist layer 10 and has a film thickness of, for example, about 40 μm. Then, using a solder printing method, external connection electrodes (solder balls) 9 that function as external connection terminals are formed on the portion of the rewiring pattern 8a exposed from the opening of the solder resist layer 10.

  Through these steps, the semiconductor module of the first embodiment shown in FIG. 1 is manufactured.

According to the semiconductor module and the manufacturing method thereof of the first embodiment, the following effects can be obtained.
(1) After forming the conductive bump 5a on the electrode 2 of the semiconductor substrate 1, the opening 7 is processed by laser irradiation, and the via contact 8b is formed inside the via contact portion (conductive bump 5a). And a via contact portion formed of the via contact 8b), the via contact portion can be formed on the electrode 2 without employing dry etching. For this reason, charge-up damage caused by dry etching as in the prior art is not applied to the semiconductor substrate via the electrodes, and a decrease in reliability of the semiconductor module can be suppressed. Further, if the via contact portion has the same depth, the formation time of the opening 7 by laser irradiation is shortened by interposing the conductive bump 5a, so that the influence of heat by laser irradiation can be reduced. . As a result, it is possible to improve the manufacturing stability (reliability) of the semiconductor module having via contact portions (conductive bumps 5a and via contacts 8b) connected to the electrodes 2 of the semiconductor substrate 1.
(2) Since the via contact 8b is formed on the conductive bump 5a, the via contact portion is directly connected to the electrode 2 as long as the via contact portion has the same depth. Since the depth of the corresponding opening can be reduced, the laser irradiation time (opening formation time) when forming the opening can be shortened, and the throughput when manufacturing the semiconductor module can be improved.
(3) Since the via contact 8b is formed on the conductive bump 5a, the via contact portion is directly connected to the electrode 2 if the via contact portion has the same depth. Since the depth of the corresponding opening can be reduced, the coverage of the copper plating layer 8 (via contact 8b) formed in the opening can be improved, and the via contact portion (conductive bump 5a and via contact) can be improved. The connection reliability of 8b) can be improved.
(4) Since the via contact 8b is formed on the conductive bump 5a, the via contact portion is directly connected to the electrode 2 as long as the via contact portion has the same depth. Since the corresponding opening has a shallow depth, the aspect ratio of the opening can be reduced. For this reason, manufacturing variations due to the opening depth during opening formation are reduced, and a highly reliable semiconductor module can be easily manufactured without introducing a high-performance device for forming the opening. Will be able to. Further, this can reduce the manufacturing cost of the semiconductor module.
(5) Since the via contact 8b is formed on the conductive bump 5a, the via contact portion is directly connected to the electrode 2 as long as the via contact portion has the same depth. The corresponding opening is shallower. On the other hand, in the opening portion 7 having the tapered side wall as shown in FIG. 1, when the opening size (area) of the bottom portion is the same at the same taper angle, the shallower opening portion has a tapered shape. The resulting opening dimension spread is reduced. For this reason, compared with the case where the opening part reaching the electrode 2 is formed, the opening dimension on the surface side of the insulating layer 4 can be narrowed. Furthermore, the conductive bumps 5a can be formed to be smaller than the resolution limit of the opening in the lithography technique by over-etching during etching. As a result, it is possible to reduce the size of a semiconductor module having a via contact portion in which both are stacked.
(6) Since the conductive bumps 5a are embedded in the insulating layer 4 by pressure bonding, a laser corresponding to the conductive bumps is formed in comparison with the case where the portions corresponding to the conductive bumps are formed using a technique such as laser irradiation or dry etching. The conductive bump 5 a can be formed on the electrode 2 without damage caused by irradiation or dry etching affecting the semiconductor substrate 1 via the electrode 2.

(Second Embodiment)
FIG. 4 is a schematic cross-sectional view showing the configuration of the semiconductor module according to the second embodiment of the present invention. The difference from the first embodiment is that the shape of the conductive bump 5b is reduced from the electrode 2 side to the via contact 8b, and the side surface portion 5b1 whose diameter (dimension) becomes narrower (the diameter (dimension as the via contact 8b side approaches the electrode 2). ) Is formed so as to have a side surface portion 5b1) that becomes thicker. The rest is the same as in the first embodiment.

Specifically, the conductive bump 5 b is made of metal such as copper (Cu), and is embedded in the insulating layer 4 so as to be in contact with the exposed surface of the electrode 2. The height of the conductive bump 5b is, for example, about 50 μm. The conductive bumps 5b are provided in an inverted truncated cone (in which the cross-sectional shape is an inverted trapezoidal shape), a tip portion parallel to the contact surface with the electrode 2 of the semiconductor substrate 1, and a diameter thereof from the tip portion toward the via contact 8b. And a side surface portion 5b1 formed so that (dimension) becomes thin. The diameters of the tips and base surfaces of the conductive bumps 5b are about 100 μmφ and about 80 μmφ, respectively. In addition, the conductive bump 5 b is provided at a position corresponding to the electrode 2. The tip of the conductive bump 5 b is formed so as to be in direct contact with the electrode 2 of the semiconductor substrate 1.
(Production method)
FIG. 5 is a schematic cross-sectional view for explaining a method for forming an insulating layer with conductive bumps according to the second embodiment, and FIG. 6 is a schematic cross-sectional view for explaining a manufacturing process of a semiconductor module according to the second embodiment. It is.

  First, as shown in FIG. 5A, an epoxy thermosetting resin is used, and a copper foil 5z having a thickness of about 3 μm is formed on the insulating layer 4 having a thickness of about 80 μm.

  As shown in FIG. 5B, a resist mask 6a is formed in a conductive bump formation region on the copper foil 5z by using a normal lithography method. Here, the conductive bump formation region corresponds to the position of the electrode 2 of the semiconductor substrate 1 shown in FIG.

  As shown in FIG. 5C, copper is plated on the surface of the copper foil 5z in the opening of the resist mask 6a by using an electrolytic plating method. Thus, a copper plating layer 5z1 having a thickness of about 50 μm is formed on the insulating layer 4.

  As shown in FIG. 5D, the resist mask 6a is removed. As a result, a copper plating layer 5z1 serving as a conductive bump is formed on the copper foil 5z.

  As shown in FIG. 5E, the entire surface is etched back using a chemical solution, and unnecessary copper foil 5z other than the conductive bump formation region (copper plating layer 5z1 portion) is removed. At this time, the conductive bump 5b is formed so as to have a side surface portion 5b1 whose diameter (dimension) becomes narrower as it approaches a portion in contact with the insulating layer 4. Here, the height of the conductive bump 5b is about 50 μm, and the diameter of the tip and the base surface of the conductive bump 5b are about 100 μmφ and about 80 μmφ, respectively. In the series of steps described above, the insulating layer 4 which is a thermosetting resin is not completely cured by heat so that the insulating layer 4 is not semi-cured (a state in which it easily flows). Like to maintain.

  The insulating layer 4 with the conductive bumps 5b manufactured in this way is prepared separately and used for the manufacturing process of the semiconductor module in the second embodiment described below.

  Next, as shown in FIG. 6 (A), a semiconductor substrate 1 having an electrode 2 on the surface is prepared, and insulation with conductive bumps 5b is made so that the tips of the conductive bumps 5b are in contact with the electrodes 2. Layer 4 is placed. The method for forming the insulating layer 4 with the conductive bumps 5b is as described above.

  As shown in FIG. 6 (B), the semiconductor substrate 1, the conductive bumps 5b, and the insulating layer 4 are integrated by pressure molding using a press apparatus after the arrangement as described above. The pressure and temperature during pressing are the same as in the first embodiment. As a result, the conductive bumps 5 b are embedded in the insulating layer 4 in contact with the electrodes 2. At this time, the conductive bump 5b is formed in the insulating layer 4 at the time of pressure bonding by having the side surface portion 5b1 formed so that the diameter (dimension) becomes smaller as the conductive bump 5b approaches the portion in contact with the insulating layer 4. Can be embedded smoothly.

  Thereafter, the semiconductor module of the second embodiment is manufactured through the steps described in FIGS. 3C, 3D, and 1 in the first embodiment.

According to the semiconductor module and the manufacturing method thereof of the second embodiment, the following effects can be obtained in addition to the effects (1) to (6).
(7) The side surface portion 5b1 is formed so that the diameter (dimension) becomes smaller as the conductive bump 5b approaches the portion in contact with the insulating layer 4, so that the conductive bump 5b is smoothly embedded in the insulating layer 4 at the time of pressure bonding. be able to. For this reason, the throughput of such a process can be improved and the cost reduction of the semiconductor module with improved manufacturing stability (reliability) can be achieved.

  The present invention is not limited to the above-described embodiments, and various modifications such as design changes can be added based on the knowledge of those skilled in the art. The form can also be included in the scope of the present invention. For example, you may combine the structure of each embodiment suitably.

  In the first embodiment, the example in which the conductive bump 5a having the truncated cone (the cross-sectional shape is trapezoidal) and having the side surface portion 5a1 having a predetermined taper angle is employed is shown, but the present invention is not limited to this. Further, it may be a cylindrical conductive bump having a predetermined diameter. Moreover, although the circular shape of a truncated cone was employ | adopted as a conductive bump, polygons, such as a rectangle, may be sufficient. Also in this case, at least the effects (1) to (6) can be enjoyed.

  In the first embodiment, an example in which the cross-sectional shape is a trapezoidal shape as the conductive bump 5a having the side surface portion 5a1 having a predetermined taper angle is shown. However, the present invention is not limited to this, and for example, a rectangular conductive property The tip of the bump 5a may be chamfered and only a part of the side surface may be tapered. Similarly, only the tip portion may be rounded.

  In the above embodiment, an example in which the via contact 8b is provided so as to cover the inside of the opening 7 has been shown. However, the present invention is not limited to this, for example, when the rewiring pattern 8a including the via contact 8b is formed, By narrowing the opening size of the opening 7 and adding an inhibitor and an accelerator to the plating solution, the via contact 8b may be formed so as to completely fill the opening 7 with copper plating. . In this case, the resistance of the via contact portion can be reduced.

  In the above embodiment, an example in which via contact portions (conductive bumps 5a, 5b and via contacts 8b) for connecting the electrodes 2 of the semiconductor substrate 1 and the rewiring pattern 8a are provided has been described. For example, the invention may be applied to a via contact portion for connecting a lower wiring layer and an upper wiring layer in a multilayer wiring board. According to this, the manufacturing stability of the multilayer wiring board can be improved, and the multilayer wiring board can be manufactured at low cost.

(Third embodiment)
Next, a portable device provided with the semiconductor module of the present invention will be described. In addition, although the example mounted in a mobile telephone is shown as a portable apparatus, electronic devices, such as a personal digital assistant (PDA), a digital video camera (DVC), and a digital still camera (DSC), may be sufficient, for example.

  FIG. 7 is a diagram showing a configuration of a mobile phone including the semiconductor module according to the embodiment of the present invention. The mobile phone 111 has a structure in which a first housing 112 and a second housing 114 are connected by a movable portion 120. The first housing 112 and the second housing 114 can be rotated about the movable portion 120 as an axis. The first housing 112 is provided with a display unit 118 and a speaker unit 124 that display information such as characters and images. The second housing 114 is provided with an operation unit 122 such as operation buttons and a microphone unit 126. The semiconductor module according to each embodiment of the present invention is mounted inside such a mobile phone 111.

  FIG. 8 is a partial cross-sectional view (cross-sectional view of the first casing 112) of the mobile phone shown in FIG. The semiconductor module 130 according to each embodiment of the present invention is mounted on the printed circuit board 128 via the external connection electrode 90 and is electrically connected to the display unit 118 and the like via the printed circuit board 128. Further, a heat radiating substrate 116 such as a metal substrate is provided on the back surface side of the semiconductor module 130 (the surface opposite to the external connection electrode 90). For example, the heat generated from the semiconductor module 130 is generated inside the first housing 112. The heat can be efficiently radiated to the outside of the first housing 112 without causing any trouble.

According to the mobile device including the semiconductor module according to the embodiment of the present invention, the following effects can be obtained.
(8) Since the connection reliability of the semiconductor module 130 is improved as described above, the reliability of the mobile device in which the semiconductor module 130 is mounted is improved.
(9) Since the manufacturing cost of the semiconductor module 130 is reduced, the manufacturing cost of a portable device equipped with such a semiconductor module 130 can be suppressed.
(10) Since the semiconductor module 130 manufactured by the manufacturing method shown in the above embodiment is thinned and miniaturized, a portable device equipped with such a semiconductor module 130 can be thinned and miniaturized.

It is a schematic sectional drawing which shows the structure of the semiconductor module which concerns on 1st Embodiment. 2A to 2D are schematic cross-sectional views for explaining a method for forming an insulating layer with conductive bumps in the first embodiment. 3A to 3E are schematic cross-sectional views for explaining the semiconductor module manufacturing process according to the first embodiment. It is a schematic sectional drawing which shows the structure of the semiconductor module which concerns on 2nd Embodiment. 5A to 5E are schematic cross-sectional views for explaining a method for forming an insulating layer with conductive bumps in the second embodiment. 6A and 6B are schematic cross-sectional views for explaining a semiconductor module manufacturing process according to the second embodiment. It is a figure which shows the structure of the mobile telephone provided with the semiconductor module based on Embodiment 3. FIG. FIG. 8 is a partial cross-sectional view (cross-sectional view of the first housing) of the mobile phone shown in FIG. 7.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Electrode, 3 ... Protective film, 5a ... Conductive bump, 5a1 ... Side surface part, 7 ... Opening part, 8a ... Rewiring pattern, 8b ... via contact, 9 ... external connection electrode (solder bump), 10 ... solder resist layer.

Claims (7)

A semiconductor element having an electrode portion on the mounting surface;
An insulating layer provided on the mounting surface of the semiconductor element;
A wiring layer formed on the insulating layer;
A first conductor portion embedded in the insulating layer and in contact with the electrode portion;
A second conductor portion formed in an opening provided in the insulating layer on the first conductor portion, and electrically connecting the conductor portion and the wiring layer;
A semiconductor module comprising:   2. The semiconductor module according to claim 1, wherein the first conductor portion becomes thinner as approaching a contact surface with the electrode portion.   2. The semiconductor module according to claim 1, wherein the first conductor portion becomes thinner as approaching a contact surface with the second conductor portion. A first step of preparing a substrate having an electrode on the surface;
A second step of forming a first conductor portion on one surface of the insulating layer;
A third step of embedding the first conductor portion in the insulating layer by pressure-bonding the insulating layer to the substrate in a state where the electrode and the first conductor portion are in contact with each other;
A fourth step of forming an opening so that the first conductor portion is exposed from the other surface of the insulating layer;
A fifth step of forming a second conductor portion in the opening;
A method for manufacturing a semiconductor module.   5. The method of manufacturing a semiconductor module according to claim 4, wherein, in the second step, the first conductor portion is formed to have a side surface portion whose dimensions become narrower as it approaches a portion in contact with the insulating layer. .   The semiconductor module according to claim 4, wherein the third step includes a step of pressure-bonding the insulating layer to the substrate in a semi-cured state and a step of heating and curing the insulating layer. Production method.   A portable device comprising the semiconductor module according to any one of claims 1 to 3.

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