JP2008172093A - Method and apparatus for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method capable of extremely raising positioning precision in pasting different kinds of substrates. <P>SOLUTION: The semiconductor device manufacturing method having a process for pasting the first and second substrates includes: a process for adjacently holding the substrates in a state where one surface of the first substrate faces one substrate of the second substrates; a process for performing positioning in an in-plane direction between one surfaces of the adjacently held first and second substrates; a process for measuring a position deviation distribution in the in-plane direction between one surfaces of the first and second substrates after positioning; a process for bonding one surfaces of the adjacent first and second substrates by pressurization from the other surface side of the first substrate; and a process for partially correcting the position deviation in the in-plane direction between one surfaces of the first and second substrates, based on the position deviation distribution in the in-plane direction in the pressurization state from the other surface side of the first substrate. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device manufacturing apparatus.

  In recent years, as the degree of integration of semiconductor devices has increased, the circuit patterns of LSI elements constituting the semiconductor devices have become increasingly finer. Along with the miniaturization of the pattern, the cross-sectional area of the wiring decreases, so that the wiring resistance increases and the wiring interval between adjacent wirings decreases. Therefore, it is inevitable that the capacitance between the wirings increases. . For this reason, the signal delay time proportional to the product of the electrical resistance and the capacitance of the wiring increases, and many difficulties are brought about in speeding up the circuit operation.

  Conventionally, in order to reduce the signal delay, a technique of reducing the signal delay by using multilayer wiring layers has been used. However, an increase in the total number of wiring layers means an increase in the lithography process. Lithography process costs account for a large part of the current mass production cost, so that increasing the number of wiring layers increases the product cost. In addition, when the power supply voltage is constant, reducing the wiring resistance means increasing the current, leading to an increase in power consumption, and there is a problem that requires another device for reducing power consumption. .

  On the other hand, as a technique for fundamentally solving such a wiring problem, an optical wiring technique that uses light instead of an electric signal to transmit a signal has been attracting attention. In optical wiring, instead of metal wiring, an optical waveguide is used for signal propagation. The speed of the signal propagating through the optical waveguide depends only on the refractive index of the optical waveguide, and is usually about 1/2 to 1/3 of the speed of light in vacuum. For this reason, optical wiring is particularly promising as a technique for replacing long-distance wiring. An opto-electric hybrid integrated circuit using such an optical wiring has been proposed (see, for example, Patent Document 1).

JP 2006-23777 A

  However, in the above conventional technique, the light emitting element and the light receiving element combined with the optical waveguide are made of a group III-V semiconductor, which is an atomic species different from silicon, which is a normal semiconductor element, and therefore, on the same substrate. In order to form the substrate, a step of bonding different substrates is required. Further, the alignment accuracy required between the optical elements is about 1/8 or less of the wavelength of the light to be used, which is extremely strict value for a normal bonding technique. In an integrated circuit (for example, refer to Patent Document 1), correspondence to such high-precision alignment has not been recognized as a problem.

  That is, in an opto-electric hybrid integrated circuit, a step of bonding different substrates is indispensable, but it is difficult to achieve the alignment accuracy required between the optical elements over the entire surface of the wafer. There is a concern that the in-plane distortion caused by the underlying pattern and the in-plane distortion induced by the deviation of the underlying substrate surface from the flat surface may be insignificant. Furthermore, silicon substrates with a 12-inch diameter are becoming the norm, but group III-V semiconductor substrates are only 4 inches in diameter at the maximum. With simple one-to-one bonding, photoelectric mixing is performed on the entire surface of the silicon wafer. There is a problem that it is difficult to form an integrated circuit. That is, at present, such a high-precision alignment technique in an opto-electric hybrid integrated circuit has not yet been established.

  The present invention has been made in view of the above, and an object of the present invention is to provide a semiconductor device manufacturing method and a semiconductor device manufacturing apparatus in which the alignment accuracy in bonding different substrates is greatly improved.

  In order to solve the above-described problems and achieve the object, a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device including a step of bonding a first substrate and a second substrate, A step of holding the first substrate and the second substrate close to each other in a state of facing each other, and an in-plane direction of the first substrate and the second substrate held close to each other A step of aligning, a step of measuring a positional displacement distribution in the in-plane direction between one surface of the first substrate and the one surface of the second substrate after the alignment, In a state in which one surface of the second substrate is pressed and bonded from the other surface side of the first substrate, and in a state of being pressed from the other surface side of the first substrate, based on the positional deviation distribution in the in-plane direction, Partially correcting the in-plane misalignment between one surface of the first substrate and one surface of the second substrate; Characterized in that it contains.

  A semiconductor device manufacturing apparatus according to the present invention is a semiconductor device manufacturing apparatus for bonding a first substrate and a second substrate, wherein one surface of the first substrate and one surface of the second substrate are opposed to each other. A holding unit that is held close to each other in a closed state, an alignment unit that performs in-plane alignment between one surface of the held first substrate and one surface of the second substrate, and the first substrate after alignment A misalignment distribution measuring unit for measuring a misalignment distribution in the in-plane direction between one surface of the first substrate and one surface of the second substrate, and one surface of the first substrate and one surface of the second substrate as the other surface of the first substrate. A pressure pressing unit that pressurizes and bonds from the side, and a surface of the first substrate and a second substrate based on the positional displacement distribution in the in-plane direction in a state where pressure is applied from the other surface side of the first substrate. And a correction unit that partially corrects the positional deviation in the in-plane direction with respect to the one surface.

  According to the present invention, when the one surface of the first substrate and the one surface of the second substrate are bonded together, the alignment accuracy between the one surface of the first substrate and the one surface of the second substrate is greatly improved. . Thus, a semiconductor device manufacturing method and a semiconductor device manufacturing apparatus that realize high-quality bonding with a very small positional deviation distribution of bonding positions between one surface of a first substrate and one surface of a second substrate are provided. There is an effect that it becomes possible.

  Exemplary embodiments of a semiconductor device manufacturing method and a semiconductor device manufacturing apparatus according to the present invention will be explained below in detail with reference to the accompanying drawings. In addition, this invention is not limited by the following description, In the range which does not deviate from the summary of this invention, it can change suitably.

  1 and 2 are block diagrams showing a schematic configuration of a semiconductor device manufacturing apparatus according to a first embodiment of the present invention. This semiconductor device manufacturing apparatus is a substrate bonding apparatus that realizes the semiconductor device manufacturing method according to the present invention. FIG. 1 shows a first substrate bonding used when bonding substrates (wafers) of different sizes. FIG. 2 shows a second substrate bonding apparatus used when bonding substrates (wafers) having substantially the same size. Note that the substrate in this embodiment basically means a substrate in which another layer such as an element layer is formed over the base substrate, but the method for manufacturing a semiconductor device and the semiconductor device described in this embodiment The manufacturing apparatus can also be applied to bonding of base substrates.

  As shown in FIG. 1, the first substrate bonding apparatus includes a wafer stage 3, a height adjustment unit 4, a control unit 5, a positional deviation distribution measurement unit 6, a calculation unit 7, and substrate peeling light irradiation. A unit 8, a pressure pressing unit 9, a wafer chuck 10, and a storage unit 11 are provided.

  In the first substrate bonding apparatus according to the present embodiment, the wafer 1 serving as the first substrate is held by the pressure pressing unit 9 by vacuum suction and is opposed to the wafer 2 serving as the second substrate. Arranged. The wafer 2 is held by a wafer chuck 10 and can move on the wafer stage 3 in the in-plane direction of the wafer stage 3. A height adjustment that allows the height of the wafer 2 to be partially adjusted in a lattice form at a portion corresponding to the element region of the wafer 2 between the wafer 2 held by the wafer chuck 10 and the wafer stage 3. Part 4 is provided. The height adjusting unit 4 is housed in the storage unit 11. The operation of the wafer stage 3 and the operation of the height adjustment unit 4 are controlled by the control unit 5.

  The pressure pressing unit 9 has a function of performing the operation of bringing the wafer 1 close to the wafer 2 and pressing the wafer 1. The operation of the pressure pressing unit 9 to bring the wafer 1 close to the wafer 2 is a first stage in which a gap of several tens of μm or less remains between the wafer 1 and the wafer 2 so as to approach the proximity state, and the wafer 1 And the wafer 2 can be divided into two stages, that is, a second stage in which the wafer 2 is in complete contact with no gap.

  In the first stage, the positional deviation distribution measurement unit 6 measures the relative positional deviation between the pattern on the wafer 1 and the pattern on the wafer 2 in a state where the wafer 1 is close to the wafer 2 by the pressure pressing unit 9. . The measurement result is converted into a control signal for the height adjustment unit 4 by the calculation unit 7 and sent to the control unit 5.

  Bonding of the wafer 1 and the wafer 2 is performed by direct bonding without using an adhesive or the like. In this method, the surfaces to be joined are polished flat and brought into contact with each other at room temperature, thereby joining the surfaces. Such direct bonding without using an adhesive or the like does not include a heating step, and therefore has a feature that high-precision bonding is possible even when different materials are used. Based on the signals from the control unit 5 and the calculation unit 7, the pressure pressing unit 9 presses the wafer 1 and the wafer 2 by performing pressure pressing when the alignment between the wafer 1 and the wafer 2 is completed. Abut and perform direct joining.

  The operation of the pressure pressing unit 9 is divided into two stages. When the wafer 1 and the wafer 2 are even in contact with each other, direct bonding is started at the contacted portion, and the relative in the in-plane direction between the wafer 1 and the wafer 2 is determined. This is because the movement is restricted and it is difficult to adjust the alignment in the in-plane direction. That is, after adjusting the alignment in the in-plane direction of the wafer 1 and the wafer 2 in the proximity state where the gap between the wafer 1 and the wafer 2 is several tens of μm or less, and confirming that the alignment is completed, By performing a two-stage pressure pressing operation to directly bond the wafer 1 and the wafer 2, bonding with high alignment accuracy can be performed.

  It is possible to prevent uneven bonding by releasing the vacuum suction of the bonded portion of the wafer 1 at the stage of pressing and pressing.

  The substrate peeling light irradiation unit 8 has a function of peeling the element layer and the substrate by irradiating light to a peeling layer described later. Usually, a release layer is provided in advance between the element layer of the wafer 2 and the substrate, light irradiation is performed after the bonding of the wafer 1 and the wafer 2, and the element layer of the wafer 2 is bonded to the wafer 1, The substrate of the wafer 2 is separated.

  As shown in FIG. 2, the second substrate bonding apparatus includes a wafer stage 23, a height adjustment unit 24, a control unit 25, a misalignment distribution measurement unit 26, a calculation unit 27, and substrate peeling light irradiation. A unit 28, a pressure pressing unit 29, a wafer chuck 30, and a storage unit 31 are provided.

  In such a second substrate bonding apparatus according to the present embodiment, the wafer 21 serving as the first substrate is held by the pressure pressing unit 29 by vacuum suction and is opposed to the wafer 22 serving as the second substrate. Arranged. The wafer 22 is held by a wafer chuck 30 and can move on the wafer stage 23 in the in-plane direction of the wafer stage 23.

  Between the wafer 22 held by the wafer chuck 30 and the wafer stage 23, there is provided a height adjusting unit 24 which can adjust the height of the wafer 22 in a lattice pattern. The height adjusting unit 24 covers almost the entire surface except for the outer peripheral portion 8 mm of the wafer 22. The height adjustment unit 24 is housed in the storage unit 31. The storage unit 31 for storing the height adjustment unit 24 may have a very small moving distance as compared with the case of the first substrate bonding apparatus of FIG. Absent. The operation of the wafer stage 23 and the operation of the height adjustment unit 24 are controlled by the control unit 25.

  The pressure pressing unit 29 has a function of pressing and pressing the wafer 21 close to the wafer 22. The operation of the pressure pressing unit 29 to bring the wafer 21 closer to the wafer 22 is a first stage in which a gap of several tens of μm or less remains between the wafer 21 and the wafer 22 so as to approach the proximity state, and the wafer 21. And the wafer 22 is divided into two stages, that is, a second stage in which the wafer 22 is completely in contact with no gap.

  In the first stage, the positional deviation distribution measuring unit 26 measures the relative positional deviation between the pattern on the wafer 21 and the pattern on the wafer 22 in a state where the wafer 21 is close to the wafer 22 by the pressure pressing unit 29. . The measurement result is converted into a control signal for the height adjustment unit 24 by the calculation unit 27 and sent to the control unit 25.

  Bonding of the wafer 21 and the wafer 22 is performed by direct bonding without using an adhesive or the like. In this method, the surfaces to be joined are polished flat and brought into contact with each other at room temperature, thereby joining the surfaces. Such direct bonding without using an adhesive or the like does not include a heating step, and therefore has a feature that high-precision bonding is possible even when different materials are used. The pressure pressing unit 29 presses the wafer 21 and the wafer 22 by performing pressure pressing when the alignment between the wafer 21 and the wafer 22 is completed based on the signals from the control unit 25 and the calculation unit 27. Abut and perform direct joining.

  The operation of the pressure pressing unit 29 is divided into two stages. When the wafer 21 and the wafer 22 are even in contact with each other, direct bonding is started at the contacted portion, and the relative relationship between the wafer 21 and the wafer 22 in the in-plane direction. This is because it is difficult to adjust the in-plane alignment where movement is restricted. That is, after adjusting the alignment in the in-plane direction of the wafer 21 and the wafer 22 in the proximity state where the gap between the wafer 21 and the wafer 22 is several tens of μm or less, and confirming that the alignment is completed, By performing a two-stage pressure pressing operation to directly bond the wafer 21 and the wafer 22, bonding with high alignment accuracy can be performed.

  In addition, it is possible to prevent uneven bonding by releasing the vacuum suction of the wafer 21 at the stage of pressing and pressing.

  The substrate peeling light irradiation unit 28 has a function of peeling the element layer and the substrate by irradiating light to a peeling layer described later. Usually, a release layer is provided in advance between the element layer of the wafer 21 and the substrate, light irradiation is performed after the wafer 21 and the wafer 22 are bonded, and the wafer 21 is bonded to the wafer 22 in a state where the element layer of the wafer 21 is bonded to the wafer 22. 21 substrates are separated.

  As described above, in order to explain that distortion correction in the in-plane direction of the substrate can be performed by the first substrate bonding apparatus and the second substrate bonding apparatus having the configuration shown in FIGS. First, the influence of the deformation in the height direction of the substrate on the alignment accuracy will be described with reference to FIGS. FIG. 3A is a schematic cross-sectional view of the wafer W for explaining the principle of correction in the semiconductor device manufacturing apparatus according to the present embodiment. FIG. 3B is an enlarged view of region A in FIG. 3-1.

  When the wafer is deformed in the height direction (the thickness direction of the wafer), the strain energy of the volume deformation is extremely large, and therefore, deformation with a constant volume usually occurs. For this reason, the central plane in the thickness direction (height direction) of the wafer is a neutral plane, and no displacement in the lateral direction (in-plane direction of the wafer) occurs before and after deformation on the central plane. Therefore, the lateral displacement generated between the neutral surface and the pattern surface gives a misalignment amount.

Here, for example, the shape of the neutral plane is described as h (x, y) using the horizontal coordinate (x, y). In this case, under the condition that h is not so large, as shown in FIG. 3-2, the misalignment amount is obtained by multiplying the gradient of h (x, y) by half the wafer thickness t _W and inverting the sign. Given by −t _W / 2 * grad (h). As an example, if there is a wafer having a thickness of 720 μm and the deformation amount of the height per 1 mm in the horizontal direction is 100 nm, in this case, a misalignment amount of 36 nm is generated.

  FIGS. 4-1 is a cross-sectional schematic diagram of the wafer 1 (21) and the wafer 2 (22) for demonstrating the principle of correction | amendment in the bonding apparatus concerning this Embodiment. FIG. 4B is an enlarged view of the region B in FIG. 4-1. In the first substrate bonding apparatus and the second substrate bonding apparatus shown in FIGS. 1 and 2, since the wafer 1 (21) is pressed against the wafer 2 (22), the surface of the wafer 1 (21) The shape follows the surface shape of the wafer 2 (22).

As described above, since the center plane in the thickness direction of both wafers is a neutral plane, the pattern deformation of the wafer 1 (21) and the pattern deformation of the wafer 2 (22) are combined. The misalignment amount is given by − (tw ₁ + tw ₂ ) / 2 * grad (h), where tw _{1 is} the thickness of the wafer 1 (21) and tw ₂ is the thickness of the wafer 2 (22). As an example, if the thickness of the wafer 1 (21) is 400 μm, the thickness of the wafer 2 (22) is 720 μm, and the deformation in the height direction is 100 nm per 1 mm in the lateral direction, a misalignment amount of 56 nm is brought about. .

  Therefore, by designing the adjustment function of the height adjustment mechanism with a performance capable of generating a small displacement of about ± 1 μm, it is possible to correct a partial misalignment of several tens of nanometers within the bonding region. . Generally, the allowable value of the misalignment amount is set to 1/8 or less of the wavelength of light used for signal transmission. Therefore, even when using light in the visible light band, it is possible to perform this degree of alignment correction. It is enough.

  In addition, pressure bonding is performed in bonding by direct bonding. For this reason, the height adjusting unit 4 (24) in the present embodiment only needs to have a force in the pushing-up direction, and can have a simple configuration and can be configured at low cost. is there. On the other hand, in bonding using an adhesive or the like without pressing and pressing, the height adjustment mechanism on the back surface of the wafer not only pushes up when it is necessary to form a concave surface, but requires a pulling operation. It is necessary to devise such as configuring a minute vacuum chuck.

  Next, an actual substrate bonding method using the bonding apparatus according to the present embodiment will be described below with reference to FIGS. 5A and 5B. FIGS. 5A and 5B are flowcharts for explaining the processing flow of the substrate bonding method according to the present embodiment. First, a pattern for detecting misalignment is previously formed on a release layer together with a light emitting element, a light receiving element, and a circuit pattern on a wafer 2 made of a III-V group substrate. A part of the circuit pattern may be used for misregistration detection.

The wafer 2 has a diameter of 3 inches and a thickness of 400 μm, and an element layer is removed by etching in a peripheral area where transfer is unnecessary. In addition, a glass substrate 1 having a diameter of 12 inches and a film thickness of 400 μm to be bonded is preliminarily formed with a ground pattern on another release layer, further formed with a SiO ₂ film, and the surface is polished. The base pattern includes an optical waveguide pattern and a pattern for detecting misalignment. In this case as well, a part of the optical waveguide pattern may be used for misalignment detection.

  The prepared wafer 1 is vacuum-adsorbed to the pressure pressing unit 9 after coarse adjustment (pre-alignment) of the horizontal position and rotation in the horizontal plane by a pre-alignment mechanism (not shown) (step S101). The Then, using the reference mark on the wafer stage 3, fine adjustment of the position in the horizontal direction and the rotation direction is performed (step S101). Similarly, the wafer 2 is also subjected to rough adjustment (pre-alignment) of the horizontal position and rotation in the horizontal plane with reference to the notch by a pre-alignment mechanism (not shown) (step S102), and then on the wafer stage 3. Fixed to the wafer chuck 10. The wafer 2 is fixed to the wafer chuck 10 by using a portion of the wafer 2 where the pattern of the peripheral portion of the wafer is not formed.

  Next, fine adjustment of the horizontal position and rotation direction of the wafer 2 is performed by detecting the rough alignment mark on the wafer 2 (step S102). At this stage, by detecting the fine alignment mark of the wafer 1, the position coordinates of the base pattern on the wafer 1 are recorded as values with respect to the wafer stage coordinates, and a so-called shot center map is created. This map is used as the value of the center coordinate at the time of pasting. Since the wafer 1 is made of glass, normal visible light can be used as the alignment light, and the alignment mark of the wafer 2 can be detected through the wafer 1.

  On the other hand, the height adjusting unit 4 is constituted by a piezoelectric element made of PZT (lead zirconate titanate) arranged in a grid pattern of 1 mm. Then, a total of 2809 pieces of 53 × 53 pieces are stored in the storage unit 11 corresponding to the region (50 mm × 50 m) where the element is formed on the wafer 1. As shown in FIG. 6A, the piezo element 12 which is a main part of the height adjusting unit 4 is disposed in a region C indicated by a dotted line of 52 mm square, and a wafer contact made of hard fluororesin is provided at the tip thereof. Part 13 is pasted. FIG. 6A is a perspective view illustrating the configuration of the height adjustment unit 4. The hard fluororesin is suitable as a member that comes into contact with the wafer because it is unlikely to be a source of contamination of metals or the like and is excellent in low dust generation.

  FIG. 6B is an enlarged view showing a region D in FIG. As shown in the enlarged view of FIG. 6B, each piezo element 12 has two connection terminals, one connected to a common potential line (ground potential line) 14a and the other connected to a control line 14b. . The common potential line 14a and the control line 14b are formed by two layers of printed wiring 14, and the common potential line 14a is configured closer to the piezo element 12 in order to suppress the influence of noise. The minimum wiring pitch of the control lines 14 b in the printed wiring 14 is 40 μm, and is connected to the wiring connector 15 on the opposite surface of the piezo element 12.

  The movable range of each piezo element is ± 1 μm, and a predetermined voltage is applied to each piezo element in accordance with a signal from the control unit 5 to form a desired height distribution. Specifically, the surface on which the wiring connector 15 is provided is provided with a memory that holds the applied voltage value to each control line 14b, and a digital signal sent from the control unit 5 is directly written therein. The total capacity of the memory is 64K bits, and a voltage applied to each control line is generated from a value on the memory by a 12-bit digital-analog converter (DA conversion amplifier) provided on the same surface.

  By adopting such a configuration, it is possible to greatly reduce the number of wirings connecting the wiring connector 15 and the control unit 5. That is, when all the voltages applied to each piezo element are generated by the control unit 5 and supplied by wiring, the number of piezo elements plus one wiring is required, but generated on the printed wiring board. In this case, since only address lines, data lines, power supply lines and the like necessary for writing to the memory are sufficient, the number of necessary wirings may be several tens at most. Further, the entire storage unit is configured to be movable in the vertical direction, and when the bonding is not performed, particularly when the wafer 2 is moved to the next bonding region by the operation of the wafer stage 3, the height adjusting unit 4 is moved. Can be evacuated.

  At the stage where the wafer 1 and the wafer 2 are placed in the predetermined state before the bonding described above, the wafer stage is moved to the position of the center coordinate of the first bonding position of the wafer 1, and the center of the first bonding position is determined. The coordinates and the center coordinates of the wafer 2 are aligned. Subsequently, the storage unit 11 is driven to bring the height adjustment unit 4 close to the back surface of the wafer 2 (the surface opposite to the bonding surface with the wafer 1). Further, the pressure pressing unit 9 is driven in the first stage to bring the wafer 1 close to the wafer 2 to a position of about 5 μm. Then, the alignment of the center coordinates of the first bonding location of the wafer 1 and the center coordinates of the wafer 2 is finely adjusted by fine movement of the wafer stage, and fine alignment between the wafers is performed (step S103).

In this state, the misalignment distribution measuring unit 6 is used to optically measure the misalignment amount between the misalignment detection pattern of the wafer 1 and the misalignment detection pattern of the wafer 2, and the misalignment is measured. Distribution is measured (step S104). If this measurement result is u (x, y) (where u is a two-dimensional vector quantity), h = 2 / (tw ₁ + tw ₂ ) ∫ using line integration from the obtained u (x, y). If udl is obtained, it is possible to cancel the misalignment u (x, y) according to the principle described above. Actually, since u (x, y) is not a continuous value but a discrete value, the integral is approximated by a sum, and the arithmetic unit 7 obtains an approximate value map h1 of h.

  In addition, the position of the misalignment detection pattern and the grid position of the height adjustment unit 4 are not always the same. For this reason, the calculation unit 7 further performs polynomial approximation on the approximate value map h1, and obtains each coefficient of the polynomial by the least square method. Then, the obtained polynomial coefficients are sent to the control unit 5 as data.

  The control unit 5 obtains height distribution information for correcting the displacement distribution using the polynomial coefficient received from the calculation unit 7, and obtains the corrected height distribution information h <b> 2 to be given to each lattice point of the height adjustment unit 4. Calculate (step S105). Then, the control unit 5 converts the calculated corrected height distribution information h2 into a voltage to be applied to each piezo element of the height adjustment unit 4, and applies the voltage to the piezo element to drive the piezo element. The height distribution in the surface of the transfer position is adjusted (step S106).

  In this state, the pressure pressing unit 9 is driven in the second stage to press the wafer 1 against the wafer 2, and the storage unit 11 is driven so that the height adjusting unit 4 is attached to the back surface of the wafer 2 (bonding with the wafer 1). At the same time, the vacuum suction of the bonded portion of the wafer 1 is released. Thus, the wafer 2 is directly bonded to a predetermined position on the wafer 1 in a state where the misalignment is canceled (step S107). Note that the wafer 1 may be pressed against the wafer 2 after the height adjusting unit 4 is brought into contact with the back surface of the wafer 2.

  In this state, the bonding state is confirmed using visible light from the back surface of the wafer 1 (the surface opposite to the bonding surface with the wafer 2), and it is confirmed that a direct bonding is formed (zero contact state). After confirmation, the wafer chuck 10 is released, the storage unit 11 is driven to retract the height adjustment mechanism, and the pressure pressing unit 9 is retracted by about 5 μm.

  Subsequently, pulse light in the infrared region is irradiated from the back surface of the wafer 2 (the surface opposite to the bonding surface with the wafer 1) using the substrate peeling light irradiation unit 8 (step S108), and the wafer 2 is peeled from the peeling layer on the wafer 2. The device regions are separated. That is, the wafer 1 and the substrate portion (base) of the wafer 2 are separated (step S109). In a state where the wafer 1 is vacuum-sucked, the separated substrate portion of the wafer 2 is again held by the wafer chuck 10, drives the wafer stage 3, and is carried out to an unload port (not shown).

  Next, the control unit 5 determines whether or not there is a next bonding position, that is, whether or not the bonding portion of the wafer 2 still remains on the wafer 1 (step S110). If it is determined that there is a next bonding position (Yes at Step S110), the process returns to Step 102, the next wafer 2 is loaded again, and the same process is repeated at the next bonding center coordinate. If it is determined that there is no next bonding position (No at step S110), the bonding process for all the bonding points on the wafer 1 has been completed, so the bonded wafer 1 is pressed and pressed. The wafer is removed from the unit 9 (step S111), and the process proceeds to the next wafer 1.

  Through the above-described series of steps, it is possible to form a bonded wafer 21 of light emitting elements / light receiving elements / circuit patterns and optical waveguide patterns, in which partial distortion is corrected and the positional deviation distribution is extremely small. If necessary, an optical waveguide layer can be further added on the bonded wafer 21.

  Next, a wafer 22 is prepared in which the electrical wiring portion of a normal CMOS (Complementary Metal Oxide Semiconductor) circuit is formed on a silicon substrate having a diameter of 12 inches and a thickness of 720 μm. Since the wafer 22 is processed in a normal CMOS circuit manufacturing process, naturally, a mark for normal alignment is already provided, but a pattern for detecting misalignment is further formed. A part of the circuit pattern may be used for misregistration detection.

After the SiO ₂ film is formed on the uppermost layer of the wafer 22, the surface is polished to prepare for direct bonding. Further, the surface of the bonded wafer 21 of the light emitting element / light receiving element / circuit pattern and the optical waveguide pattern described above is also subjected to a polishing process to prepare for direct bonding. As described above, since a pattern for detecting misalignment has already been formed on the bonded wafer 21, this is reused.

  The prepared wafer 21 is vacuum-adsorbed to the pressure pressing unit 29 after coarse adjustment (pre-alignment) of the horizontal position and rotation in the horizontal plane by a pre-alignment mechanism (not shown). Then, using the reference mark on the wafer stage 23, fine adjustment of the position in the horizontal direction and the rotation direction is performed (step S201).

  Similarly, the wafer 22 is also subjected to rough adjustment (pre-alignment) of the horizontal position and rotation in the horizontal plane with reference to the notch by a pre-alignment mechanism (not shown) (step S202), and then the wafer on the wafer stage 23. It is fixed to the chuck 30. The wafer 22 is fixed to the wafer chuck 30 by using a portion of the wafer 22 where patterning is not performed on the peripheral portion of the wafer.

  Next, fine adjustment of the horizontal position and rotation direction of the wafer 22 is performed by detecting the rough alignment mark on the wafer 22 (step S202). Since the wafer 21 is made of glass, normal visible light can be used as the alignment light, and the alignment mark of the wafer 22 can be detected through the wafer 21.

  On the other hand, the height adjusting unit 24 is configured by a piezoelectric element made of PZT arranged in a grid of 1 mm. A total of about 68,000 piezo elements are accommodated corresponding to the areas where the elements are formed on the wafers 21 and 22. As shown in FIG. 6-3, the piezo element 32, which is the main part of the height adjusting unit 24, is disposed in a region E having a diameter of 284 mmφ indicated by a dotted line, and a wafer contact made of hard fluororesin is disposed at the tip thereof. The part 33 is affixed. FIG. 6C is a perspective view illustrating the configuration of the height adjustment unit 24. The hard fluororesin is suitable as a member that comes into contact with the wafer because it is unlikely to be a source of contamination of metals or the like and is excellent in low dust generation.

  Similar to the enlarged view shown in FIG. 6B, each of the piezo elements 32 has two connection terminals, one connected to a common potential line (ground potential line) and the other connected to a control line. The common potential line and the control line are formed by nine layers of printed wiring, and the common potential line is closest to the piezo element 32 in order to suppress the influence of noise. The minimum wiring pitch of the control lines in the printed wiring is 50 μm, and is connected to the wiring connector 35 on the surface opposite to the piezoelectric element 22.

  The movable range of each piezo element is ± 1 μm, and a predetermined voltage is applied to each piezo element in accordance with a signal from the control unit 25 to form a desired height distribution. Specifically, the surface on which the wiring connector 35 is provided is provided with a memory that holds a voltage value applied to each control line, and a digital signal sent from the control unit 25 is directly written therein. The total capacity of the memory is 1 Mbit, and a voltage applied to each control line is generated from a value on the memory by a 12-bit digital-analog converter (DA conversion amplifier) provided on the same surface.

  By adopting such a configuration, it is possible to greatly reduce the number of wires connecting the wiring connector 35 and the control unit 25. That is, when all the voltages applied to each piezo element are generated by the control unit 25 and supplied by wiring, the number of piezo elements plus one wiring is required, whereas it is generated on the printed wiring board. In this case, since only address lines, data lines, power supply lines and the like necessary for writing to the memory are sufficient, the number of necessary wirings may be several tens at most. Further, the entire storage unit is configured to be movable in the vertical direction, and the height adjusting unit 24 can be retracted when bonding is not performed, particularly when the wafer 22 is moved by the operation of the wafer stage 23. .

  At the stage where the wafer 21 and the wafer 22 are placed in the predetermined state before bonding, the wafer stage 23 is moved to the position of the center coordinate of the bonding position of the wafer 21, and the center coordinate of the bonding position and the wafer 22 are moved. Align the center coordinates of. Subsequently, the storage unit 31 is driven to bring the height adjustment unit 24 close to the back surface of the wafer 22 (the surface opposite to the bonding surface with the wafer 21). Furthermore, the first-stage driving is performed on the pressure pressing unit 29 to bring the wafer 21 close to the wafer 22 to a position of about 5 μm. Then, the alignment of the center coordinates of the wafer 21 and the center coordinates of the wafer 22 is finely adjusted by fine movement of the wafer stage to perform precise alignment between the wafers (step S203).

In this state, the misalignment distribution measuring unit 26 is used to optically measure the misalignment amount between the misalignment detection pattern of the wafer 21 and the misalignment detection pattern of the wafer 22, and the misalignment is detected. Distribution is measured (step S204). If this measurement result is u (x, y) (where u is a two-dimensional vector quantity), h = 2 / (tw ₁ + tw ₂ ) ∫ using line integration from the obtained u (x, y). If udl is obtained, it is possible to cancel the misalignment u (x, y) according to the principle described above. Actually, since u (x, y) is not a continuous value but a discrete value, the integral is approximated by a sum, and the arithmetic unit 27 obtains an approximate value map h1 of h.

  In addition, the position of the misalignment detection pattern and the grid position of the height adjustment unit 24 are not always the same. For this reason, the calculation unit 27 further performs polynomial approximation on the approximate value map h1, and obtains each coefficient of the polynomial by the least square method. Then, the obtained polynomial coefficients are sent to the control unit 25 as data.

  The control unit 25 obtains height distribution information for correcting the displacement distribution using the polynomial coefficient received from the calculation unit 7, and obtains the corrected height distribution information h <b> 2 to be given to each lattice point of the height adjustment unit 4. Calculate (step S205). Then, the control unit 25 converts the calculated corrected height distribution information h2 into a voltage to be applied to each piezo element of the height adjustment unit 24 and applies the voltage to the piezo element to drive the piezo element. The height distribution in the surface of the transfer position is adjusted (step S206).

  In this state, the pressure pressing unit 29 is driven in the second stage to press the wafer 21 against the wafer 22, and the storage unit 31 is driven so that the height adjusting unit 24 is attached to the back surface of the wafer 22 (attachment to the wafer 21. At the same time, the vacuum suction of the bonded portion of the wafer 21 is released. Thereby, the wafer 2 is directly bonded to a predetermined position on the wafer 21 in a state where the misalignment is canceled (step S207). Note that the wafer 21 may be pressed against the wafer 22 after the height adjusting unit 24 is brought into contact with the back surface of the wafer 22.

  In this state, the bonding state is confirmed using visible light from the back surface of the wafer 21 (the surface opposite to the bonding surface with the wafer 22), and it is confirmed that a direct bonding is formed (zero contact state). After confirmation, the wafer chuck 30 is released, the storage unit 31 is driven to retract the height adjustment mechanism, and the pressure pressing unit 29 is further retracted by about 5 μm.

  Subsequently, pulse light having a wavelength region different from that of the substrate peeling light irradiation unit 8 is irradiated from the back surface of the wafer 21 (the surface opposite to the bonding surface with the wafer 22) using the substrate peeling light irradiation unit 28 (step S208). Then, the element region of the wafer 21 is separated from the release layer on the wafer 21. That is, the wafer 22 is separated from the substrate portion (base) of the wafer 21 (step S209). The whole substrate portion of the separated wafer 21 is again vacuum-sucked by the pressure pressing unit 29 and is carried out to an unload port (not shown).

  On the other hand, the bonded wafer 22 is held by the wafer chuck 30 again, the wafer stage 23 is driven, and it is carried out to another unloading port (not shown) (step S210), and the next wafer is processed. Transition. Through the above series of steps, the partial distortion is corrected, the positional deviation distribution is extremely small, and the light emitting element / light receiving element / circuit pattern / optical waveguide pattern bonded substrate 21 and the silicon CMOS circuit substrate 22 are bonded. A substrate can be formed. If necessary, an electric wiring layer can be further added on the bonded substrate.

  By performing a series of steps as described above using the bonding apparatus according to the present embodiment, partial distortion in the in-plane direction on the substrate is corrected, and the alignment accuracy between the substrate 121 and the substrate 122 is increased. It is possible to bond a high-quality substrate that is greatly improved and has a very small misalignment distribution.

  Next, a manufacturing method of the semiconductor device according to the present embodiment realized by using the first substrate bonding apparatus and the second substrate bonding apparatus according to the present embodiment described above will be described with reference to FIGS. This will be described with reference to 9-4. 7A to 9D are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the present embodiment.

  First, as shown in FIG. 7A, a gallium arsenide (GaAs) substrate 51 having a diameter of 3 inches is subjected to crystallinity recovery treatment by ion implantation and annealing of indium (In) and antimony (Sb), and GaAs A release layer 52 and a buffer layer 53 are formed in this order on one surface of the substrate 51. These can also be formed by a deposition method. Next, as shown in FIG. 7B, an optical element layer 54 including a GaInNAs light emitting layer, an InGaAs light receiving layer, and the like is formed on the buffer layer 53 by epitaxial growth of a group III-V semiconductor. Then, a lead wiring portion (not shown) is formed.

Subsequently, as shown in FIG. 7C, a buffer layer 55 made of silicon dioxide (SiO ₂ ) is formed on the optical element layer 54 by sputtering, and the uppermost portion is polished. Then, as shown in FIG. 7-4, unnecessary parts (buffer layer 53, optical element layer 54, buffer layer 55) including the peripheral part of the wafer are removed by a photolithography process and etching. The substrate thus obtained is called a substrate 102.

On the other hand, as shown in FIG. 8A, a thin film of, for example, chromium (Cr) -containing glass is formed on a glass substrate 61 having a diameter of 12 inches, and a release layer 62 is formed. Then, as shown in Figure 8-2, an optical waveguide layer 63 made of silicon dioxide silicon nitride (SiO ₂₎ is embedded in the membrane _{(Si 1-x N x)} , silicon dioxide (SiO ₂₎ film Polish the top. The substrate thus obtained is referred to as a substrate 101.

  Next, as shown in FIG. 8-3, the substrate 102 shown in FIG. 7-4 is used in an upside down state, and alignment correction is performed using the first substrate bonding apparatus described above. Paste. Next, as shown in FIG. 8-4, the substrate peeling light is applied from the back surface (the surface opposite to the bonding surface) of the substrate 51 by using the substrate peeling light irradiation device built in the first substrate bonding apparatus described above. For example, irradiation with pulsed light in the infrared region is performed to separate the substrate 51 from the release layer 52.

Next, as shown in FIG. 8-5, the substrate 102 shown in FIG. 7-4 is sequentially bonded to another desired position on the substrate 101 by using the first substrate bonding apparatus described above. Then, as shown in FIG. 8-6, a SiO ₂ film 64 is formed on the entire surface of the substrate by plasma CVD using tetraethoxysilane (TEOS), and the surface is polished and flattened. The substrate thus obtained is referred to as a substrate 121.

Further, as shown in FIG. 9A, a CMOS circuit layer 72 including an electric circuit wiring is formed on a silicon (Si) substrate 71 having a diameter of 12 inches by using a normal CMOS circuit manufacturing process. Next, as shown in FIG. 9B, a silicon dioxide (SiO ₂ ) film 73 is formed on the entire surface of the substrate by plasma CVD using TEOS, and the surface is polished and flattened. The substrate thus obtained is referred to as a substrate 122.

  Next, as shown in FIG. 9-3, the substrate 121 shown in FIG. 8-6 is used in an upside down state, and alignment correction is performed using the above-described second substrate bonding apparatus. Paste. Next, as shown in FIG. 9-4, using the substrate peeling light irradiation apparatus having a light source having a wavelength different from that of the first substrate bonding apparatus, which is built in the second substrate bonding apparatus described above, The substrate peeling light is irradiated from the back surface of the substrate 61 (the surface opposite to the bonding surface with the substrate 122), and the substrate 61 is separated from the peeling layer 62.

  Then, although not shown, a wiring layer forming process for connecting the element of the optical element layer 54 and the circuit of the CMOS circuit layer 72 is performed, and finally a normal semiconductor element manufacturing process such as final passivation formation and pad formation is performed. As a result, an opto-electric hybrid semiconductor element can be formed.

  By performing a series of steps as described above using the bonding apparatus according to the present embodiment, partial distortion in the in-plane direction on the substrate is corrected, and the alignment accuracy between the substrate 121 and the substrate 122 is increased. It is possible to form a high-quality opto-electric hybrid semiconductor element by attaching a high-quality substrate with extremely small positional deviation distribution, which is greatly improved.

(Modification)
In addition, this invention is not limited to each embodiment mentioned above. In the above-described embodiment, the direct bonding is used for bonding the substrates to each other. However, it is possible to further strengthen the bonding by performing a heat treatment after the direct bonding, and electric field application and heating are performed at the time of bonding. It is also possible to use anodic bonding. Furthermore, although PZT is used as the piezo element in the above-described embodiment, other materials such as lanthanum-doped lead zirconate titanate (PLZT) can be used. In the above-described embodiment, the light emitting element and the light receiving element are formed on the III-V group substrate. However, by using an external light source as the light source, the light emitting element is not formed, but instead light made of lithium niobate or the like. It is also possible to incorporate a modulation element in the waveguide. In addition, various modifications can be made without departing from the scope of the present invention.

  As described above, the method for manufacturing a semiconductor device according to the present invention is useful for a method for manufacturing a semiconductor device using an optical wiring, and is particularly suitable for manufacturing an opto-electric hybrid semiconductor element.

It is a manufacturing apparatus of the semiconductor device concerning an embodiment of the invention, and is a lineblock diagram of the 1st substrate bonding apparatus used when bonding substrates (wafers) from which size differs. It is a manufacturing apparatus of the semiconductor device concerning an embodiment of the invention, and is a lineblock diagram of the 2nd substrate pasting device used when pasting substrates (wafers) with the same size. It is a cross-sectional schematic diagram for demonstrating the principle of correction | amendment in the manufacturing apparatus of the semiconductor device concerning embodiment of this invention. It is a figure which expands and shows the area | region A in FIGS. It is a cross-sectional schematic diagram for demonstrating the principle of correction | amendment in the manufacturing apparatus of the semiconductor device concerning embodiment of this invention. It is a figure which expands and shows the area | region B in FIGS. It is a flowchart for demonstrating the processing flow of the bonding method of the board | substrate concerning embodiment of this invention. It is a flowchart for demonstrating the processing flow of the bonding method of the board | substrate concerning embodiment of this invention. It is a perspective view explaining the structure of the height adjustment part concerning embodiment of this invention. It is an enlarged view which expands and shows the area | region D in FIGS. It is a perspective view explaining the structure of the height adjustment part concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention.

Explanation of symbols

1, 2, 21, 22 Wafer 3, 23 Wafer stage 4, 24 Height adjustment unit 5, 25 Control unit 6, 26 Misalignment distribution measurement unit 7, 27 Calculation unit 8, 28 Substrate peeling light irradiation unit 9, 29 Addition Pressure pressing part 10, 30 Wafer chuck 11, 31 Storage part 12, 32 Piezo element 13, 33 Wafer contact part 14 Printed wiring 15, 35 Wiring connector 51 3-inch GaAs substrate 52, 62 Peeling layer 53, 55 Buffer layer 54 Optical element Layer 61 12-inch glass substrate 63 Optical waveguide layer 64, 73 SiO ₂ film 71 12-inch Si substrate 72 CMOS circuit layer 101, 102, 121, 122 substrate

Claims (12)

A method of manufacturing a semiconductor device including a step of attaching a first substrate and a second substrate,
Holding one surface of the first substrate and one surface of the second substrate in close proximity to each other;
Performing in-plane alignment of one surface of the first substrate and one surface of the second substrate held close to each other;
Measuring a positional deviation distribution in an in-plane direction between one surface of the first substrate and the one surface of the second substrate after the alignment;
Pressurizing and bonding the one surface of the first substrate and the one surface of the second substrate brought close together from the other surface side of the first substrate;
In a state where pressure is applied from the other surface side of the first substrate, based on the positional displacement distribution in the in-plane direction, the positional displacement in the in-plane direction between one surface of the first substrate and one surface of the second substrate is determined. Partially correcting, and
A method for manufacturing a semiconductor device, comprising: By partially adjusting the height of a part of the other surface of the second substrate based on the positional displacement distribution in the in-plane direction, distortion in the in-plane direction on one surface of the second substrate is partially adjusted. To partially correct the positional deviation in the in-plane direction on the one surface of the second substrate,
The method of manufacturing a semiconductor device according to claim 1. A step of converting an in-plane positional displacement distribution between one surface of the first substrate and one surface of the second substrate into a correction amount distribution in the height direction;
Partially adjusting the height of a part of the other surface of the second substrate based on the correction amount distribution in the height direction;
The method of manufacturing a semiconductor device according to claim 2. The second substrate is an element substrate in which an element layer in which an element is formed on one surface of a base substrate is formed via a release layer;
After correcting the positional deviation in the in-plane direction between the one surface of the first substrate and the one surface of the second substrate, the substrate peeling light for peeling the peeling layer is sent from the other surface side of the second substrate. Irradiating a second substrate to separate the base substrate and the element layer;
The method of manufacturing a semiconductor device according to claim 2. One of the first substrate and the second substrate is a substrate including an element made of a group IV semiconductor including electric wiring, and the other is a group III-V semiconductor including at least one of a light emitting element or a light receiving element. A substrate including an element,
The method of manufacturing a semiconductor device according to claim 1. In-plane alignment of one surface of the first substrate and one surface of the second substrate held close to each other is performed by alignment light,
Using a substrate that transmits the alignment light as the first substrate;
The method of manufacturing a semiconductor device according to claim 1. Bonding the first substrate to a third substrate that transmits the alignment light, and bonding and bonding the first substrate bonded to the third substrate to the second substrate;
The method of manufacturing a semiconductor device according to claim 1. After bonding and pasting a plurality of the first substrates to the third substrate, the plurality of first substrates bonded to the third substrate are bonded and pasted to the second substrate. thing,
A method for manufacturing a semiconductor device according to claim 7. The diameter of the second substrate is larger than the diameter of the first substrate, and the diameter of the second substrate and the diameter of the third substrate are substantially equal;
A method for manufacturing a semiconductor device according to claim 8. A semiconductor device manufacturing apparatus for attaching a first substrate and a second substrate,
A holding portion that holds the one surface of the first substrate and the one surface of the second substrate in close proximity to each other;
An alignment unit that performs in-plane alignment between one surface of the held first substrate and one surface of the second substrate;
A misalignment distribution measuring unit for measuring a misalignment distribution in an in-plane direction between the one surface of the first substrate and the one surface of the second substrate after the alignment;
A pressure pressing unit that pressurizes and bonds one surface of the first substrate and one surface of the second substrate from the other surface side of the first substrate;
In a state where pressure is applied from the other surface side of the first substrate, based on the positional displacement distribution in the in-plane direction, the positional displacement in the in-plane direction between one surface of the first substrate and one surface of the second substrate is determined. A correction unit that partially corrects;
An apparatus for manufacturing a semiconductor device, comprising: The correction unit partially adjusts the height of a part of the other surface of the second substrate based on the positional deviation distribution in the in-plane direction, so that the in-plane direction on the one surface of the second substrate. Partially adjusting the in-plane positional deviation on one surface of the second substrate by partially adjusting the distortion of the second substrate,
The apparatus for manufacturing a semiconductor device according to claim 10. The second substrate is an element substrate in which an element layer in which an element is formed on one surface of a base substrate is formed via a release layer;
Substrate peeling light for separating the base substrate and the element layer by peeling the peeling layer after correcting the positional deviation in the in-plane direction between the one surface of the first substrate and the one surface of the second substrate. Further comprising a substrate peeling light irradiating unit for irradiating from the other surface side of the second substrate,
The apparatus for manufacturing a semiconductor device according to claim 10.

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