JP2008160677A - Oscillation frequency control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an oscillation frequency control circuit capable of stably keeping an oscillation frequency by correcting its own frequency, even without inputting a highly stable reference signal and even during self-running. <P>SOLUTION: The oscillation frequency control circuit includes: a voltage controlled oscillator 15; a frequency divider 16; a phase comparator 12; a loop filter 14; a detection circuit 17 for detecting an external reference signal; a PWM circuit 22 which generates a pulse and outputs it to the loop filter 14 when pulse generation information is input; a memory 21 for storing pulse generation information corresponding to voltage information; a switch 13 for turning on/off the connection of the phase comparator 12 and the loop filter 14; and a CPU 20 which turns on the switch 13 when the level of the external reference signal detected by the detection circuit 17 is within a proper range, or turns off the switch 13 when the level is out of the proper range, and outputs to the PWM circuit 22 the pulse generation information stored in the memory 21. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an oscillation frequency control circuit of an oscillator, and more particularly to an oscillation frequency control circuit that can be synchronized with an output signal, correct its own frequency, and can be kept stable for a certain period even when there is no highly stable reference signal. .

In base stations such as next-generation mobile communication and digital terrestrial broadcasting, the required accuracy for frequency reference signals is increasing.
As a frequency reference signal, a cesium frequency reference oscillator, a rubidium frequency reference oscillator, a frequency-synchronized reference oscillator using a GPS signal, and the like are used in systems in the broadcasting and communication fields.

  However, since these oscillators are generally expensive, the reference signals from these oscillators are distributed and used as a reference signal source for the device.

The distributed reference signal is used as a reference clock for the communication system.
Specifically, reference signal for phase comparison of PLL (Phase Locked Loop) circuit, reference clock signal such as DSP (Digital Signal Processor), FPGA (Field Programmable Gate Array), DA (Digital / Analog) converter, AD (Analog) / Digital) Used as a sampling clock for the converter.

[Conventional PLL circuit: FIG. 6]
Next, a conventional PLL circuit will be described with reference to FIG. FIG. 6 is a configuration block diagram of a general PLL circuit.
As shown in FIG. 6, the PLL circuit compares an external reference signal (Fref) with a signal divided by 1 / N, and outputs a phase difference signal (Phase Comparator) 32 and pulses the phase difference. A charge pump 33 that outputs a voltage having a width, a loop filter 34 that smoothes the output voltage from the charge pump 33, and a frequency that is changed by a control voltage from the loop filter 34 is desired. A voltage controlled crystal oscillator (VCXO) 35 that oscillates and outputs a frequency (internal reference signal: Output Frequency), and a frequency divider that divides the output (internal reference signal) of the VCXO 35 by 1 / N. Divider) 36.
The internal reference signal is an N × Fref signal.

  The PLL circuit obtains an oscillator output synchronized with the reference signal by applying feedback control to the internal VCXO 35 so that the phase difference between the reference signal input from the outside and the internal VCXO 35 becomes constant.

Specifically, the phase comparator 32 compares the phase of the highly stable external reference signal and the output signal from the VCXO 35 whose frequency is controlled by the input voltage, and the DC voltage obtained by smoothing the phase comparison result is fed back to the VCXO 35. By performing the PLL control, high-accuracy signal generation is performed.
The PLL circuit is widely used in communication and broadcasting apparatuses.

  As prior arts related to an oscillation frequency control circuit in a conventional oscillator, there are JP-A-2000-083003 (Patent Document 1) and JP-A-2003-179489 (Patent Document 2).

  In Patent Document 1, a frequency counter performs a counting operation in synchronization with an output signal of a VCO (Voltage Controlled Oscillator) input within a time corresponding to a pulse width, and a count value corresponding to the oscillation frequency of the VCO is latched. A full-run frequency adjustment method is described in which, when the coefficient value is held in the circuit and the coefficient value is out of the predetermined range, the free-run frequency is adjusted to be within the predetermined range by changing the voltage applied to the VCO.

  Further, in Patent Document 2, the microcomputer counts the pulses of the output pulse signal of the VCO during a period in which the output of the phase comparator is at a predetermined level, and updates the control data according to the count value. A phase-locked loop circuit having a function of automatically adjusting the free-running frequency of a voltage-controlled oscillator that combines the data with a signal from an LPF (Low Pass Filter) as an analog signal by a DAC (Digital Analog Converter) to generate a VCO frequency control signal. Is described.

JP 2000-083003 A Japanese Patent Laid-Open No. 2003-179489

  However, in the above conventional PLL circuit, when no reference signal is input, phase comparison cannot be performed. Therefore, switching to another external reference signal is performed, or the voltage controlled oscillator is free-runned (self-running). Although it will operate, when switching to another external reference signal in the standby system, PLL control is performed again, so there is no problem because the deviation of the reference signal depends on the external reference signal, but when self-running There is a problem in that the frequency is excessively controlled by the phase comparison result at the time of switching, and the frequency shift increases due to sticking to the upper limit or lower limit frequency.

Even when self-running, as a short-term problem-solving, a temperature-compensated highly stable crystal oscillator (VC-TCXO) may be used as a voltage-controlled oscillator.
However, in this case, for example, although it operates with a frequency stability of ± 0.5 ppm, the performance cannot be satisfied for a long time due to aging.

  For example, since there is a fluctuation of about ± 1 ppm per year as the aging characteristic, a maximum frequency deviation of 0.5 ppm occurs after 10 years. If the carrier wave output frequency in communication is 800 MHz, a frequency deviation of 8.4 kHz occurs as in the case of the frequency deviation of the reference frequency. Such a frequency deviation is unacceptable as a system.

  In addition, even in the case of a highly stable system using a temperature controlled crystal oscillator (VC-OCXO) with a voltage control function, a frequency deviation occurs over a long period of time as an aging characteristic. There was a problem that the calibration work was troublesome.

  In Patent Documents 1 and 2, the output of the VCO is counted or the output of the phase comparator is counted to adjust the free-running frequency. It was not intended to make adjustments, and was not able to cope with aging.

[Control voltage characteristics of VCXO: FIG. 7]
The control voltage characteristics of VCXO are shown in FIG. FIG. 7 is a diagram illustrating an example of control voltage characteristics of a crystal oscillator with a voltage control function. In FIG. 7, the horizontal axis represents the control voltage, and the vertical axis represents the frequency deviation.
The VCXO in the example of FIG. 7 can operate when the control voltage is 0 to 4V, but cannot operate when the control voltage is 4V or higher.
Even in the case of VCXO, the frequency deviation increases with the passage of time, so that an appropriate control voltage changes.

  The present invention has been made in view of the above circumstances, and an oscillation frequency control circuit that corrects its own frequency, does not have a highly stable reference signal input, and can keep the oscillation frequency stable even when it is self-running. The purpose is to provide.

  The present invention for solving the problems of the above-described conventional example includes, in an oscillation frequency control circuit, a voltage controlled oscillator, a frequency divider that divides an output from the voltage controlled oscillator, an external reference signal, and a frequency divider. Phase comparator that outputs phase difference and outputs phase difference signal, loop filter that smoothes and outputs output from phase comparator, detector circuit that detects external reference signal, and pulse generation information are input ON / OFF of the connection between the pulse generation circuit that generates a pulse and outputs it to the loop filter, the memory that stores the specified voltage information and the corresponding pulse generation information, and the phase comparator and the loop filter When the level of the external reference signal detected by the switch and the detection circuit is within the proper range, the switch is turned on, and when the level is outside the proper range, the switch is turned off and stored in the memory. And having a control unit for outputting information of the pulse generator to the pulse generating circuit.

  The present invention is characterized in that, in the oscillation frequency control circuit, the specified voltage information stored in the memory is used as a central control voltage in a control voltage capable of controlling the voltage controlled oscillator.

  According to the present invention, in the oscillation frequency control circuit, instead of storing the prescribed voltage information and the corresponding pulse generation information in the memory, an appropriate control voltage for the aging time and the corresponding pulse generation information are stored. Stores the aging characteristics table, and the controller measures the time with an internal timer, and the time measured from the aging characteristics table of the memory when the level of the external reference signal is outside the proper range The control voltage is searched for, and information on pulse generation corresponding to the searched control voltage is read and output to the pulse generation circuit.

  The present invention provides a level detection circuit for detecting the voltage level of the output from the loop filter and outputting the latest voltage information to the control unit in the oscillation frequency control circuit. Instead of storing information on pulse generation to be performed, the latest voltage information, a plurality of voltage information and a voltage / pulse generation information table for storing information on pulse generation corresponding to the voltage information are stored, and the control unit is a level detection circuit The latest voltage information in the memory is updated with the latest voltage information input from the memory, and when the level of the external reference signal is outside the proper range, the latest voltage information is supported from the memory voltage / pulse generation information table. The pulse generation information is read and output to a pulse generation circuit.

  The present invention is characterized in that, in the oscillation frequency control circuit, a crystal oscillator with a voltage control function, a temperature compensation type crystal oscillator, or a thermostat crystal oscillator with a voltage control function is used instead of the voltage control oscillator.

  According to the present invention, in the oscillation frequency control circuit, the pulse generation circuit is a pulse width modulation circuit, and the pulse generation information output from the control unit is information of a pulse width modulation duty cycle.

  In the calibration method of the oscillation frequency control circuit according to the present invention, the control unit is configured so that the external reference signal is not input, the reference signal is input at a specific timing, and then the input of the reference signal is stopped. It is characterized by self-running control according to the control voltage and calibration.

  In the calibration method of the oscillation frequency control circuit according to the present invention, the control unit is configured so that the external reference signal is not input, the reference signal is input at a specific timing, and then the input of the reference signal is stopped. By referring to the change characteristic table, self-running control is performed according to the control voltage corresponding to the measured time, and calibration is performed.

  According to the present invention, the voltage-controlled oscillator, the frequency divider that divides the output from the voltage-controlled oscillator, the phase comparison that outputs the phase difference signal by comparing the phase of the output from the external reference signal and the frequency divider Generator, a loop filter that smoothes and outputs the output from the phase comparator, a detection circuit that detects an external reference signal, and a pulse generator that generates a pulse when information on pulse generation is input and outputs it to the loop filter The level of the external reference signal detected by the detector, the circuit, the memory for storing the prescribed voltage information and the corresponding pulse generation information, the switch for turning on / off the connection between the phase comparator and the loop filter, A control unit that turns on the switch if it is within the proper range and turns off the switch if the level is outside the proper range and outputs the pulse generation information stored in the memory to the pulse generation circuit. Since the oscillation frequency control circuit corrects the frequency of the self, no input of highly stable reference signal, an effect that can maintain the oscillation frequency stably even when the self-propelled.

  According to the present invention, since the above-mentioned oscillation frequency control circuit uses the specified voltage information stored in the memory as the central control voltage in the control voltage that can control the voltage controlled oscillator, the self-frequency is corrected and the oscillation frequency Has an effect that can be kept stable.

  According to the present invention, instead of storing the prescribed voltage information and the corresponding pulse generation information, the memory stores the appropriate control voltage with respect to the aging time and the corresponding pulse generation information. A characteristic table is stored, and the control unit has a timer inside to measure the time, and when the level of the external reference signal is outside the proper range, the control voltage corresponding to the time measured from the aging characteristic table of the memory Since the oscillation frequency control circuit reads the pulse generation information corresponding to the searched control voltage and outputs the information to the pulse generation circuit, the frequency correction can be adapted to the secular change.

  According to the present invention, a level detection circuit that detects the voltage level of the output from the loop filter and outputs the latest voltage information to the control unit is provided, and the memory includes prescribed voltage information and corresponding pulse generation information. Instead of storing the latest voltage information, a plurality of voltage information and a voltage / pulse generation information table for storing the corresponding pulse generation information, and the control unit receives the latest input from the level detection circuit. The latest voltage information of the memory is updated with the voltage information of the memory, and when the level of the external reference signal is out of the proper range, the pulse generation information corresponding to the latest voltage information is obtained from the memory voltage / pulse generation information table. Since the oscillation frequency control circuit reads and outputs to the pulse generation circuit, there is no input of the reference signal, and even if it is self-running, it will take over the previous state. The vibration frequency is effective can be kept stable.

  According to the present invention, the external reference signal is not input, the reference signal is input at a specific timing, and then the input of the reference signal is stopped, so that the control unit performs free-running control according to the center control voltage, Since the calibration method of the oscillation frequency control circuit that performs calibration is used, the calibration can be performed without using a special device.

  According to the present invention, the external reference signal is not input, the reference signal is input at a specific timing, and then the input of the reference signal is stopped, so that the control unit refers to the aging characteristic table and performs measurement. Since the oscillation frequency control circuit performs the calibration by performing self-running control according to the control voltage corresponding to the time, the calibration corresponding to the secular change can be performed without using a special device.

[Outline of the embodiment]
Embodiments of the present invention will be described with reference to the drawings.
The oscillation frequency control circuit according to the embodiment of the present invention compares the phase of the output from the voltage controlled oscillator, the frequency divider that divides the output from the voltage controlled oscillator, the external reference signal and the frequency divider, A phase comparator that outputs a phase difference signal, a loop filter that smoothes and outputs the output from the phase comparator, a detection circuit that detects an external reference signal, and a pulse when information on pulse generation is input Detecting with a pulse generation circuit that outputs to the loop filter, a memory that stores the specified voltage information and the corresponding pulse generation information, a switch that turns on / off the connection between the phase comparator and the loop filter, and a detection circuit If the level of the external reference signal is within the proper range, the switch is turned on, and if the level is outside the proper range, the switch is turned off and the pulse generation information stored in the memory is generated. Those having a control unit for outputting to the circuit, and corrects the frequency of the self, no input of highly stable reference signal, in which even can keep the oscillation frequency stability when the self-propelled.

  In addition, the oscillation frequency control circuit according to the embodiment of the present invention includes an aging characteristic table that stores an appropriate control voltage with respect to aging time and information on pulse generation corresponding to the aging time in the oscillation frequency control circuit. The control unit is equipped with an internal timer to measure time, and when the level of the external reference signal is outside the proper range, the control voltage corresponding to the measured time is retrieved from the aging characteristics table of the memory. The pulse generation information corresponding to the searched control voltage is read and output to the pulse generation circuit, and the frequency correction can be made to correspond to the secular change.

  In addition, the oscillation frequency control circuit according to the embodiment of the present invention includes a level detection circuit that detects the voltage level of the output from the loop filter and outputs the latest voltage information to the control unit in the oscillation frequency control circuit. The latest voltage information in the memory, a plurality of voltage information and a voltage / pulse generation information table for storing the corresponding pulse generation information are stored, and the control unit receives the latest voltage information input from the level detection circuit. To update the latest voltage information of the memory, and when the level of the external reference signal is outside the proper range, read the pulse generation information corresponding to the latest voltage information from the voltage / pulse generation information table of the memory. This is output to the generator circuit, and there is no reference signal input. Even when it is free-running, it can take over the previous state and keep the oscillation frequency stable. It is kill things.

[Oscillation frequency control circuit: Fig. 1]
An oscillation frequency control circuit according to an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing the configuration of an oscillation frequency control circuit according to an embodiment of the present invention.
As shown in FIG. 1, an oscillation frequency control circuit (this circuit) according to an embodiment of the present invention includes a filter 11, a phase comparator 12, a switch 13, a loop filter 14, a voltage controlled oscillator 15, Frequency divider 16, detector circuit 17, amplifier 18, CPU (Central Processing Unit) 20, memory 21, PWM (Pulse Width Modulation) circuit 22, level detection circuit 23, AD converter 24, AD And a converter 25.

[Each part of this circuit]
The filter 11 is a filter that limits the band of an external reference signal of 10 MHz, for example. Although not essential as a basic configuration, it functions to remove high-frequency components of the external reference signal.
The phase comparator 12 compares the phase of the reference signal output from the filter 11 and the signal divided by the frequency divider 16 and outputs a phase difference signal.
When the phase comparator 12 detects the synchronization (lock) by comparing the phases of the external reference signal and the divided signal, it outputs a lock detection signal to the CPU 20 and detects the asynchronous (unlock). Outputs an unlock detection signal to the CPU 20.

  The switch 13 switches on / off the connection between the phase comparator 12 and the loop filter 14 in accordance with a switching instruction from the CPU 20. That is, when an on instruction is input from the CPU 20, an output from the phase comparator 12 is supplied to the loop filter 14. When an off instruction is input from the CPU 20, the connection between the phase comparator 12 and the loop filter 14 is performed. It is a matter of disclaimer.

The loop filter 14 is a filter that smoothes the output voltage.
The voltage controlled oscillator 15 oscillates and outputs a desired frequency (internal reference signal) by changing the frequency according to the control voltage from the loop filter 14.
In place of the voltage controlled oscillator (VCO), a crystal oscillator with voltage control (VCXO), a thermostat crystal oscillator with voltage control function (VC-OCXO), or the like may be used.

The frequency divider 16 divides the internal reference signal output from the voltage controlled oscillator 15 by 1 / N.
The detection circuit 17 performs level detection of the output signal from the filter 11.
The amplifier 18 amplifies the signal detected by the detection circuit 17.

  The CPU 20 inputs the control voltage information from the AD converter 25 and stores it in the memory 21 as the latest control voltage information. Specifically, the CPU 20 always receives the control voltage information from the AD converter 25, and does not update the memory 21 if there is no change from the previously input control voltage information. If there is a change, the CPU 20 displays the control voltage information in the memory 21. Update.

  Further, the CPU 20 inputs the detected level of the external reference signal (external REF) from the AD converter 24, and receives an appropriate range (between the first threshold value and the second threshold value) stored in the memory 21. If it is within the proper range, an on instruction is output to the switch 13, and if it is outside the proper range, an off instruction is output to the switch 13.

  Further, if the detection level of the external REF is out of the proper range, the CPU 20 refers to the voltage / PWM duty cycle table stored in the memory 21 and refers to the PWM duty cycle based on the voltage information of the current (latest) control voltage. The pulse width information according to the above is output to the PWM circuit 22.

The memory 21 stores the latest control voltage information, the first threshold value and the second threshold value that are the reference of the appropriate range with respect to the detection level of the external REF, and the voltage / PWM duty cycle table. Yes.
The control voltage information is detected by the level detection circuit 23, and when it is changed, it is updated in the memory 21 and held as the latest value.

[Voltage / PWM duty cycle table: Fig. 2]
Here, the voltage / PWM duty cycle table will be described with reference to FIG. FIG. 2 is a schematic diagram of a voltage / PWM duty cycle table.
As shown in FIG. 2, the voltage / PWM duty cycle table stores a PWM duty cycle (%) for specifying a pulse width for voltage information.

Here, the voltage information is obtained by predetermining the PWM duty cycle of the pulse output from the PWM circuit 22 to the loop filter 14 in order to maintain the value of the control voltage from the loop filter 14 (control voltage information). It has become.
Accordingly, when the PWM duty cycle corresponding to the control voltage information detected by the level detection circuit 23 is read from the voltage / PWM duty cycle table and the pulse corresponding to the cycle is output to the loop filter 14, the loop filter 14 The same control voltage as before is output to the voltage controlled oscillator 15.

  The PWM circuit 22 performs pulse width modulation on the PWM duty cycle data input from the CPU 20 and outputs a desired pulse signal to the loop filter 14. If voltage information data is output from the CPU 20, a DA (Digital / Analog) converter can be used instead of the PWM circuit.

The level detection circuit 23 detects the DC voltage output from the loop filter 14 and outputs it to the AD converter 25 as control voltage information.
The AD converter 24 converts the detection level of the external REF output from the amplifier 18 from an analog signal to a digital signal and outputs it to the CPU 20.
The AD converter 25 converts the control voltage information from the level detection circuit 23 from an analog signal to a digital signal and inputs it to the CPU 20.

  In this circuit, the input abnormality of the external reference signal can be recognized by the CPU 20 based on the detection level of the external REF output from the detection circuit 17 and the amplifier 18, and therefore the unlock detection signal from the phase comparator 12 is used. Not.

[Operation of this circuit]
The operation in this circuit will be described.
In this circuit, when the switch is normal, the switch 13 is on and the phase comparator 12 and the loop filter 14 are connected. Then, the phase comparator 12 outputs the signal of the phase difference between the external reference signal and the signal from the frequency divider 16 to the voltage controlled oscillator 15 via the loop filter 14 and controls the oscillation frequency in the voltage controlled oscillator 15. ing. At this time, the level detection circuit 23 detects the latest control voltage and outputs it to the CPU 20 via the AD converter 25. The CPU 20 updates the latest control voltage information in the memory 21 if the control voltage information is changed. To do.

  In this circuit, the external reference signal is detected by the detection circuit 17, amplified by the amplifier 18, the level of the external REF is detected, and is output to the CPU 20 via the AD converter 24.

  The CPU 20 determines whether or not the input external REF detection level is within an appropriate range. Specifically, if there is a value of the detection level of the external REF between the first threshold value and the second threshold value indicating the appropriate range stored in the memory 21, it is determined that the value is within the appropriate range. If there is no external REF detection level value between the first threshold value and the second threshold value, it is determined that the value is outside the proper range.

  As a result of the determination, if the CPU 20 is within the proper range, the CPU 13 maintains the switch 13 in the normal state, and if it is outside the proper range, the CPU 20 turns off the switch 13 as the abnormal state, and the phase comparator 12 and the loop filter 14. Disconnect from the.

Further, in an abnormal state, the CPU 20 reads the latest control voltage information stored in the memory 21, reads the PMW duty cycle corresponding to the voltage information from the voltage / PMW duty cycle table, and outputs a pulse that becomes the PWM duty cycle. Information (data) for formation is output to the PWM circuit 22.
The PWM circuit 22 generates a pulse in accordance with the pulse formation information input from the CPU 20 and outputs a control voltage to the voltage controlled oscillator 15 via the loop filter 14.

As a result, when an abnormality occurs in the external reference signal, particularly when no external reference signal is input (in the case of self-running), the CPU 20 immediately detects the abnormality by the output from the detection circuit 17 and the amplifier 18. Then, the output of the phase comparator 12 is cut off, and a pulse similar to the control voltage that has been controlling the voltage controlled oscillator 15 so far is output from the PWM circuit 22.
That is, by using the output from the PWM circuit 22 instead of the output of the phase comparator 12, it is possible to take over the previous state and optimize the frequency oscillation in the voltage controlled oscillator 15.

[Another embodiment 1]
In the above example, the pulse output from the PWM circuit 22 is generated based on the latest control voltage information detected by the level detection circuit 23. However, the default voltage information is stored, and the default voltage information is stored. Information on pulse generation may be output based on the PWM duty cycle corresponding to the voltage information.

Specifically, in the control voltage for the voltage controlled oscillator 15, the memory 21 stores a center voltage value within an appropriate range, and the PWM duty cycle corresponding to the center voltage value is 50%. If the control voltage of 14 operates from 0 to 3.3V, the control voltage is set to 3.3 / 2V. Note that an arbitrary voltage value other than the center voltage value may be stored to set a corresponding control voltage.
If the default voltage information is used, the components of the level detection circuit 23 and the AD converter 25 and the voltage / PMW duty cycle table in the memory 21 can be eliminated.

[Proofreading]
Calibration in this circuit will be described with reference to FIG. FIG. 3 is a diagram showing characteristics at the time of calibration.
In this circuit, as shown in FIG. 3, when time passes without an external reference signal being input, the frequency deviation increases or decreases. The figure shows a rise. Therefore, when an appropriate reference signal is input at a specific timing and then the input of the reference signal is stopped, the frequency deviation returns to the center frequency by self-running control, and calibration is performed. In FIG. 3, the calibration is repeated twice.

In this calibration, frequency control is performed using the center voltage value within the control range of the control voltage for the voltage controlled oscillator 15.
According to this circuit, the calibration work can be performed without connecting a special circuit during calibration.

[Voltage characteristics of aging: Fig. 4]
Next, FIG. 4 shows an example of optimum control voltage characteristics with respect to secular change in this circuit. FIG. 4 is a diagram showing aging / control voltage characteristics.
As shown in FIG. 4, in this circuit, the optimum control voltage decreases with time (however, the case where the frequency deviation increases) is shown.

[Another embodiment 2]
Furthermore, as another embodiment (another embodiment 2), this circuit has a configuration corresponding to the above-mentioned secular change. Another embodiment 2 will be described with reference to FIG. FIG. 5 is a schematic diagram of an aging characteristic table.
In this circuit, the memory 21 stores a voltage / PMW duty cycle table. Instead of this table, the aging characteristic table of FIG. 5 is used.

The aging characteristic table of FIG. 5 further provides a time factor in the relationship between the voltage information and the PWM duty cycle.
Specifically, voltage information appropriate for the passage of time is set, and a PWM duty cycle is set corresponding to the voltage information and stored as a table.
The CPU 20 includes a timer inside and measures the passage of time.

  In another embodiment 2, when the detection level of the external reference signal is outside the proper range, the CPU 20 turns off the switch 13 and refers to the time measured by the internal timer, and corresponds to the time. The PWM duty cycle is searched from the voltage information, information for generating a pulse according to the PWM duty cycle is output to the PWM circuit 22, a desired pulse is generated by the PWM circuit 22, and the voltage is passed through the loop filter 14. A control voltage is output to the control oscillator 15.

  As a result, in another embodiment 2, the CPU 20 corrects the oscillation frequency by using the voltage information corresponding to the secular change when the external reference signal is abnormal and the pulse generated according to the PWM duty cycle corresponding thereto. There is an effect that the frequency control circuit can cope with the secular change.

Further, calibration may be performed in the circuit configuration according to the second embodiment.
In this case, the CPU 20 measures the passage of time, and performs frequency control using a voltage value corresponding to the passage of time with reference to an aging characteristic table during calibration work. Thereby, there is an effect that the calibration work can be made to correspond to the secular change of the frequency control circuit.

  The present invention is suitable for an oscillation frequency control circuit that corrects its own frequency, does not receive a highly stable reference signal, and can keep the oscillation frequency stable even when it is free-running.

It is a block diagram of the configuration of an oscillation frequency control circuit according to an embodiment of the present invention. It is the schematic of a voltage and PWM duty cycle table. It is a figure which shows the characteristic at the time of calibration. It is a figure which shows secular change and control voltage characteristics. It is the schematic of an aging characteristic table. It is a block diagram of a general PLL circuit. It is a figure which shows the example of a control voltage characteristic of the crystal oscillator with a voltage control function.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Filter, 12 ... Phase comparator, 13 ... Switch, 14 ... Loop filter, 15 ... Voltage controlled oscillator, 16 ... Frequency divider, 17 ... Detection circuit, 18 ... Amplifier, 20 ... CPU, 21 ... Memory, 22 ... PWM circuit, 23 ... Level detection circuit, 24 ... AD converter, 25 ... AD converter, 32 ... Phase comparator, 33 ... Charge pump, 34 ... Loop filter, 35 ... VCXO, 36 ... Frequency divider

Claims (8)

  A voltage-controlled oscillator, a frequency divider that divides the output from the voltage-controlled oscillator, a phase comparator that compares a phase of an output from the frequency divider and an external reference signal, and outputs a phase difference signal; A loop filter that smoothes and outputs the output from the phase comparator; a detection circuit that detects an external reference signal; and a pulse generation circuit that generates a pulse when pulse generation information is input and outputs the pulse to the loop filter; A memory for storing prescribed voltage information and corresponding pulse generation information, a switch for turning on / off the connection between the phase comparator and the loop filter, and the level of the external reference signal detected by the detection circuit If the value is within the proper range, the switch is turned on. If the level is outside the proper range, the switch is turned off and the pulse generation information stored in the memory is stored in the pulse. Oscillation frequency control circuit, characterized in that a control unit for outputting the raw circuit.   2. The oscillation frequency control circuit according to claim 1, wherein the prescribed voltage information stored in the memory is a central control voltage in a control voltage capable of controlling the voltage controlled oscillator. Instead of storing the prescribed voltage information and the corresponding pulse generation information, the memory stores an appropriate control voltage with respect to the time of aging and the aging characteristic table storing the corresponding pulse generation information,
The control unit is equipped with a timer to measure the time, and when the level of the external reference signal is outside the proper range, the control unit searches for a control voltage according to the measured time from the aging characteristic table of the memory, and searches 2. The oscillation frequency control circuit according to claim 1, wherein the pulse generation information corresponding to the control voltage is read and output to the pulse generation circuit. Provide a level detection circuit that detects the voltage level for the output from the loop filter and outputs the latest voltage information to the control unit,
Instead of storing prescribed voltage information and corresponding pulse generation information in the memory, the voltage / pulse generation information table stores the latest voltage information, a plurality of voltage information and corresponding pulse generation information. Remember
The control unit updates the latest voltage information of the memory with the latest voltage information input from the level detection circuit, and generates a voltage / pulse generation of the memory when the level of the external reference signal is out of an appropriate range. 2. The oscillation frequency control circuit according to claim 1, wherein pulse generation information corresponding to the latest voltage information is read from the information table and output to the pulse generation circuit.   5. The oscillation frequency control according to claim 1, wherein a crystal oscillator with a voltage control function, a temperature compensation type crystal oscillator, or a thermostatic chamber crystal oscillator with a voltage control function is used instead of the voltage control oscillator. circuit.   6. The oscillation frequency according to claim 1, wherein the pulse generation circuit is a pulse width modulation circuit, and the pulse generation information output from the control unit is information of a pulse width modulation duty cycle. Control circuit.   3. The calibration method for an oscillation frequency control circuit according to claim 2, wherein an external reference signal is not input, a reference signal is input at a specific timing, and then the input of the reference signal is stopped so that the control unit A calibration method for an oscillation frequency control circuit, wherein self-running control is performed according to a control voltage and calibration is performed.   4. The method of calibrating an oscillation frequency control circuit according to claim 3, wherein the control unit is configured so that the external reference signal is not input, the reference signal is input at a specific timing, and then the input of the reference signal is stopped. A method for calibrating an oscillation frequency control circuit, wherein a calibration is performed by referring to a change characteristic table and performing free-running control according to a control voltage corresponding to the measured time.

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