JP2008160450A - Phase synchronizing circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a control voltage recovery circuit being an auxiliary circuit for quickly attaining convergence only by a phase detector in a clock data recovery circuit using a broadband voltage controlled oscillator. <P>SOLUTION: A control voltage recovery circuit has a Schmidt trigger circuit SThigh for making control voltage Vctrl to be input voltage, and a Schmidt trigger circuit STlow for making the control voltage Vctrl to be input voltage, wherein a relation among a higher logic threshold Vt1, h and a lower logic threshold Vt1, l of the Schmidt trigger circuit SThigh, and a higher logic threshold Vt2, h and a lower logic threshold Vt2, l of the Schmidt trigger circuit STlow is Vt2, 1<Vt1, 1<Vt2, h<Vt1, h, control is disconnected when the control voltage exceeds Vt2, h from low to high, and the control is disconnected when the control voltage exceeds Vt1, l from high to low. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a phase locked loop for speeding up convergence of a phase locked loop and a clock and data recovery circuit (CDR).

  In recent years, as the demand for digital information has increased, the need for high-speed and large-capacity data transmission technology has rapidly increased. In response to such a demand, the communication system has shifted from the conventional parallel data transmission system to the serial data transmission system. In the high-speed serial data transmission system, a clock / data restoration circuit that restores a clock synchronized with received data is one of important circuit elements.

  The following Non-Patent Document 1 proposes a design technique for a clock / data restoration circuit in recent years. The clock and data recovery circuit discussed in this document uses a half-rate phase detector (PD) to reduce the burden on the voltage controlled oscillator (VCO), and uses a voltage controlled oscillator (PD). Coarse tuning is performed from outside the clock and data recovery circuit. Then, fine tuning is performed in the clock / data restoration circuit to extract a clock synchronized with the data.

In the following Non-Patent Document 2, a clock / data recovery circuit is configured by a phase detector and a frequency detector (FD). In order to use the frequency detector, the voltage controlled oscillator has a structure capable of generating a four-phase clock. Course tuning is realized by this frequency detector.
J. Savoj, B. Razavi “A 10-Gb / s CMOS clock and data recovery circuit with a half-rate linear phase detector” IEEE J. Solid-State Circuits, vol.36, no.5, pp.761-- 767, May. 2001. J. Savoj, B. Razavi “A 10-Gb / s CMOS clock and data recovery circuit with a half-rate binary phase / frequency detector“ IEEE J. Solid-State Circuits, vol.38, no.1, pp.13 --21, Jan. 2003.

The need for coarse tuning is based on the configuration of a phase detector that samples random data. The phase detector is a circuit that detects the phase difference between the input data and the recovered clock. When the data rate and the clock have the same frequency, the clock / data restoration circuit naturally converges, but otherwise it may not converge. For example, the following cases (1) and (2) can be considered.
(1) When the clock is earlier than the data rate When the clock is earlier than the data rate, the frequency component of the phase with respect to the data is increased and the frequency of the clock is lowered so as to correct it. . However, when the clock is a positive integer multiple with respect to the data rate, if random data is input, the loop of the clock / data recovery circuit may converge to this integer multiple frequency. This is called a pseudo lock.
(2) When the clock is slow with respect to the data rate As in the case of (1), the clock frequency is increased so as to correct the increase in the phase error component with respect to the data, and the convergence is attempted. The cut-off frequency of the loop filter of the clock / data restoration circuit needs to be set corresponding to random data, and is set in consideration of random data length, jitter, and the like. In other words, regarding the convergence when the data rate is low with respect to the clock, it is important to set the loop of the clock / data restoration circuit.

Further, the convergence of the clock / data restoration circuit largely depends on the frequency characteristics of the voltage controlled oscillator.
It is an object of the present invention to provide a voltage-controlled oscillator that uses a voltage-controlled oscillator, such as an initial voltage fluctuation or power supply fluctuation in the control voltage of the voltage-controlled oscillator. An object of the present invention is to provide a phase locked loop circuit that can perform coarse tuning for fast convergence without depending on frequency characteristics.

The phase synchronization circuit of the present invention includes a control voltage recovery circuit that controls (coarse tuning) the control voltage of the voltage controlled oscillator.
The control voltage recovery circuit includes a first Schmitt trigger circuit that uses the control voltage as an input voltage, and a second Schmitt trigger circuit that uses the control voltage as an input voltage, which is higher than the first Schmitt trigger circuit. The relationship between the lower logical threshold Vt1, h, the lower logical threshold Vt1, l, and the higher logical threshold Vt2, h and lower logical threshold Vt2, l of the second Schmitt trigger circuit is
Vt2, l <Vt1, l <Vt2, h <Vt1, h
Suppose that

The control voltage recovery circuit cuts off the control when the control voltage exceeds Vt2, h from the bottom to the top, and cuts off the control when the control voltage exceeds Vt1, l from the top to the bottom.
In the voltage controlled oscillator, when the relationship between the control voltage and the frequency is such that the higher the control voltage is, the lower the frequency is, and the frequency lock range is between Vt2, l and Vt1, l. In the voltage controlled oscillator, when the relationship between the control voltage and the frequency is such that the higher the control voltage is, the higher the frequency is, the range in which the frequency is locked is Vt2. , h and Vt1, h (claim 2).

  In the case of the configuration of claim 1, an image until convergence is shown in FIG. When the initial value of the control voltage Vctrl is significantly lower than the locked range, that is, the range where only fine tuning is performed (Vctrl <Vt2, l), the control voltage recovery circuit supplies current to the loop filter, and the control voltage Vctrl Pull up until Vt2, h exceeds the lockable range (I). When the control voltage Vctrl reaches Vt2, h, the control voltage recovery circuit cuts off the control. As a result, the clock / data recovery circuit CDR is disconnected. Thereafter, in order to minimize the phase difference between the input data and the recovered clock, feedback is applied to increase the clock frequency, and thus the voltage of Vctrl decreases. The data can be locked by normal fine tuning (II).

  When the initial value of the control voltage Vctrl is larger than the lock range (Vctrl> Vt1, h), the control voltage recovery circuit draws the current from the loop filter and Vt1 is in the range where the control voltage Vctrl can be locked , l until it reaches l (III). When the control voltage Vctrl reaches Vt1, l, the control voltage recovery circuit cuts off the control. After this, since feedback is applied to increase the clock frequency to minimize the phase difference between the input data and the recovered clock, the voltage of Vctrl drops and enters the data lockable range by normal fine tuning. (IV).

  In the case of the configuration of claim 2, FIG. 11 shows an image until convergence. When the initial value of the control voltage Vctrl is significantly lower than the locked range, that is, the range where only fine tuning is performed (Vctrl <Vt2, l), the control voltage recovery circuit supplies current to the loop filter, and the control voltage Vctrl Pull up until Vt2, h exceeds the lockable range (V). When the control voltage Vctrl reaches Vt2, h, the control voltage recovery circuit cuts off the control. As a result, the clock / data recovery circuit CDR is disconnected. After this, feedback is applied to increase the clock frequency in order to minimize the phase difference between the input data and the recovered clock, so the voltage of Vctrl rises, and the data can be locked within the normal fine tuning range. Enter (VI).

  When the initial value of the control voltage Vctrl is larger than the lock range (Vctrl> Vt1, h), the control voltage recovery circuit draws the current from the loop filter and is within the lockable range of the control voltage Vctrl. Pull down until Vt1, l is reached (VII). When the control voltage Vctrl reaches Vt1, l, the control voltage recovery circuit cuts off the control. After this, feedback is applied to increase the clock frequency to minimize the phase difference between the input data and the recovered clock, so the voltage of Vctrl rises and enters the data lockable range by normal fine tuning. (IV).

According to the present invention, it is possible to quickly converge the clock / data restoration circuit to a desired frequency and restore the desired clock. The control terminal of the voltage controlled oscillator can be reduced, and it functions as a frequency detector FD that determines the convergence range with a simple circuit configuration.
Even when the data rate changes, if the logic threshold is set below the control voltage of the voltage controlled oscillator that oscillates twice the assumed minimum data rate, the data rate will converge even if the data rate becomes variable.

  The present invention can be used as a receiving circuit for high-speed communication in the field of electronic circuits and communication circuits.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a block diagram showing the overall configuration of a clock and data recovery circuit (CDR) according to an embodiment of the present invention.
The clock and data recovery circuit includes a half-rate phase detector 2 (Charge Pump; CP), a voltage controlled oscillator 4 (Voltage Controlled Oscillator; VCO), and a loop filter 6 (Loop Filter; LF) and a multiplexer 5 (Multiplexer; MUX), and a control voltage recovery circuit 7 characteristic of the present invention.

  The output side of the half-rate phase detector 2 is connected to the charge pump 3, and the output terminal of the charge pump 3, the loop filter 6, the input terminal of the voltage controlled oscillator 4, and the control voltage recovery circuit 7 are connected by the wiring 8. The voltage of the connected wiring 8 is referred to as a control voltage Vctrl. The lock voltage is a control voltage (Vctrl) when the clock / data recovery circuit locks to the input data. The output clock signal of the voltage controlled oscillator 4 is extracted from the clock / data recovery circuit and input to the multiplexer 5.

  The half-rate phase detector 2 receives an input signal Din consisting of 1 and 0 of a pseudo random data stream using an LFSR (Linear Feedback Shift Register) or the like. The input signal speed is not limited, but is 1 to 40 Gbps, for example. A phase error signal is output from the half-rate phase detector 2 to the charge pump 3. The charge pump 3 is a circuit for performing fine tuning, and supplies electric charge to a loop filter 6 composed of a capacitor and a resistor in accordance with a phase error. The electric charge generates the control voltage Vctrl. The voltage controlled oscillator 4 is a circuit that generates a clock signal having a frequency corresponding to the control voltage Vctrl, and has two types according to the voltage-frequency pattern. This will be described later with reference to FIG. The multiplexer 5 is a circuit that samples an input signal based on a clock signal obtained from the voltage controlled oscillator 4.

  The control voltage recovery circuit 7 is directly connected to the wiring 8 and controls the control voltage Vctrl by supplying or extracting charges from the loop filter 6. The function of the control voltage recovery circuit 7 is referred to as “coarse tuning”. On the other hand, the control voltage control function of the charge pump 3 is referred to as “fine tuning”. The difference between course tuning and fine tuning is that course tuning supplies larger current and faster tuning speed than fine tuning.

The reason for performing the course tuning is to prevent pseudo-locking with a clock twice or more the data rate as described in the section “Problems to be solved by the invention”.
FIG. 2 shows a circuit diagram of the control voltage recovery circuit 7.
The control voltage recovery circuit 7 includes two types of Schmitt Trigger circuits SThigh and STlow having different logic threshold values, and has a total of four logic threshold values.

Here, the Schmitt trigger circuit is generally a circuit having a dead zone and having hysteresis characteristics at the input and output. When there is an input voltage between two logic thresholds, the logic when the previous logic threshold is exceeded is output.
The circuit configuration of the control voltage recovery circuit 7 includes a Schmitt trigger circuit SThigh that receives the control voltage Vctrl of the wiring 8 and a Schmitt trigger circuit STlow, a logic circuit composed of NAND and AND circuits, a first switch SW1, and the first switch SW1. The first current source 11, the second switch SW 2, and the second current source 12 connected thereto. That is, the trigger trigger signal is supplied to the first switch SW1 and the second switch SW2 via the logic circuit based on the outputs of the two Schmitt trigger circuits. The trigger voltages of the first switch SW1 and the second switch SW2 are indicated by “U1, U2”. A common connection portion of the first switch SW1 and the second switch SW2 is connected to the wiring 8.

  The operation of the first switch SW1 is off when the trigger voltage U1 is high (eg, 5V), and is on when the trigger voltage U1 is low (eg, 0V). The operation of the second switch SW2 is on when the trigger voltage U1 is high. When low, it is off. This relationship is shown in Table 1.

  When the first switch SW <b> 1 is on, electric charge is supplied from the first current source 11 to the wiring 8. When the second switch SW <b> 2 is on, charges are extracted from the wiring 8 to the second current source 12. Thereby, course tuning is performed. When both the first switch SW1 and the second switch SW2 are turned off, there is no charge in / out. In this case, fine tuning is performed by taking charge in and out from the charge pump 3. Fine tuning is also performed during course tuning. However, since the current value of the charge pump 3 of the control voltage recovery circuit 7 is smaller than the current values of the first current source 11 and the second current source 12, The effects of fine tuning during tuning can be ignored.

The relationship between the output voltages of the Schmitt trigger circuit SThigh and the Schmitt trigger circuit STlow and the operation states of the first switch SW1 and the second switch SW2 will be described later with reference to FIGS.
FIG. 3 shows the frequency characteristics of the voltage controlled oscillator 4. The voltage controlled oscillator 4 has two patterns in which the slope of the frequency versus the control voltage is positive and negative.

FIG. 3A shows the relationship between the control voltage Vctrl of the voltage controlled oscillator 4 and the frequency, and the frequency decreases as the control voltage increases. FIG. 3B shows the relationship between the control voltage Vctrl and the frequency of the voltage controlled oscillator 4, and the frequency increases as the control voltage increases.
In the present invention, two Schmitt trigger circuits are combined. That is, the high logic threshold of the Schmitt trigger circuit SThigh is written as Vt1, h, the low logic threshold is written as Vt1, l, the high logic threshold of the Schmitt trigger circuit STlow is written as Vt2, h, and the low logic threshold is written as Vt2, l. These are set so as to satisfy the relationship of the following expression.

Vt2, l <Vt1, l <Vt2, h <Vt1, h
The relationship between the four logical threshold values is illustrated in FIGS. 4 and 5.
When the voltage controlled oscillator 4 whose frequency decreases as the control voltage in FIG. 3A increases is used, the lock range is Vt2, l <Vctrl <Vt1, l as shown in FIG.
To be.

When the voltage controlled oscillator 4 having a higher frequency as the control voltage is higher in FIG. 3B is used, the lock range is as shown in FIG.
Vt2, h <Vctrl <Vt1, h
To be.
4 (a) and 5 (a) show a process in which the voltage is lower than the lock voltage and the voltage rises due to coarse tuning. 4 (b) and 5 (b) show a process in which the voltage is higher than the lock voltage and the voltage is lowered by coarse tuning.

  In the case of FIG. 4A, when the control voltage Vctrl reaches Vt2, h in the process of increasing the voltage, the output of the Schmitt trigger circuit becomes low. At this time, when the recovery circuit is turned OFF, the control voltage Vctrl is lowered to increase the clock frequency in order to minimize the phase difference between the input data and the recovered clock. , l and Vt1, l.

  However, when a large noise enters and the voltage becomes higher than the lock voltage, the control voltage Vctrl reaches Vt1, l in the process of decreasing the voltage as shown in FIG. 4 (b) (at this time, Vt2, h cannot be seen), and the output of the Schmitt trigger circuit goes high. At this time, the recovery circuit is turned off. The control voltage Vctrl can fall between Vt2, l and Vt1, l. Therefore, the locked state can be entered.

In the case of FIG. 5A, when the control voltage Vctrl reaches Vt2, h in the process of increasing the voltage, the output of the Schmitt trigger circuit becomes low. When the recovery circuit is turned off at this time, the control voltage Vctrl enters between Vt2, h and Vt1, h. Therefore, the locked state can be entered.
However, when a large noise or the like enters and the voltage becomes higher than the lock voltage, the control voltage Vctrl reaches Vt1, l as the voltage drops as shown in FIG. 5 (b) (at this time Vt2, h is The output of the Schmitt trigger circuit goes high. At this time, the recovery circuit is turned off. After that, the control voltage Vctrl is fed back so as to increase the frequency of the clock in order to minimize the phase difference between the input data and the recovered clock. , h and Vt1, h.
(A) Behavior of control voltage Vctrl (No.1)
Hereinafter, the voltage-controlled oscillator 4 in which the relationship between the voltage and the frequency of the voltage-controlled oscillator 4 in FIG. 3A is such that the higher the voltage is, the lower the frequency is. The behavior of the control voltage will be described assuming that it is set during l.

FIG. 6 is a graph showing the behavior (No. 1) of the control voltage Vctrl.
(A-1) Initial Vctrl <locked Vctrl (Fig. 6 (a))
The range that can be pseudo-locked is the range below Vt2, l. First, when the initial voltage Initial Vctrl of the control voltage Vctrl is sufficiently lower than Vt2,1, charge is supplied from the control voltage recovery circuit 7 to the loop filter 6 to raise the voltage in order to raise the control voltage Vctrl. This prevents false locks.

  FIG. 7 is an operation explanatory diagram of the control voltage recovery circuit 7 showing a state in which this electric charge is supplied. When the Schmitt trigger circuit is viewed from the input side, as shown in FIG. 7B, the logical thresholds are only visible as Vt2, h and Vt1, h. Therefore, the control voltage Vctrl is lower than any logic threshold value, and the outputs of the two Schmitt trigger circuits are both in the high state (solid line) as shown in FIG. Therefore, the trigger voltage supplied to the first switch SW1 and the trigger voltage supplied to the second switch SW2 are both low, the first switch SW1 is on, and the second switch SW2 is off. Accordingly, electric charges are supplied to the loop filter 6 and the voltage rises.

FIG. 8 shows a case where the control voltage Vctrl exceeds Vt2, h. At this time, the output of the Schmitt trigger circuit SThigh is in the high state (solid line), but the output of the Schmitt trigger circuit STlow is in the low state (broken line). Therefore, as shown in FIG. 8A, the trigger voltage supplied to the first switch SW1 is high, the trigger voltage supplied to the second switch SW2 is low, and the first switch SW1 is off. The second switch SW2 is also turned off (that is, the recovery circuit is shut off). The charge from the recovery circuit to the loop filter 6 is stopped. As a result, since the control voltage Vctrl is fed back to increase the clock frequency in order to minimize the phase difference between the input data and the recovered clock, the control voltage Vctrl falls and falls within the lock range Vt2, l <Vctrl. <Vt1, l
Only fine tuning by the charge pump 3 is performed.

(A-2) Initial Vctrl> locked Vctrl (Fig. 6 (b))
When the control voltage Vctrl is higher than Vt1, h, the recovery circuit pulls out the charge of the loop filter 6 in order to lower the control voltage Vctrl.
FIG. 9 is an operation explanatory diagram showing a state in which this electric charge is extracted. When the Schmitt trigger circuit is viewed from the input side, as shown in FIG. 9B, the logical thresholds are only visible as Vt2, l and Vt1, l. Therefore, the control voltage Vctrl is higher than any logic threshold value, and the outputs of the two Schmitt trigger circuits are in a low state (broken line). Therefore, the trigger voltage supplied to the first switch SW1 and the trigger voltage supplied to the second switch SW2 are both high, the first switch SW1 is off, and the second switch SW2 is on (FIG. 9 (a)). Accordingly, electric charges are extracted from the loop filter 6 and the voltage drops.

FIG. 10 shows a case where the control voltage Vctrl is lower than Vt1, l. At this time, the output of the Schmitt trigger circuit SThigh is in the high state (solid line), but the output of the Schmitt trigger circuit STlow is in the low state (broken line). Therefore, the trigger voltage supplied to the first switch SW1 is high, the trigger voltage supplied to the second switch SW2 is low, the first switch SW1 is off, and the second switch SW2 is off ( FIG. 10 (a)). The charge from the recovery circuit to the loop filter 6 is stopped. As a result, the control voltage Vctrl is Vt2, l <Vctrl <Vt1, l, which is the lock range, as indicated by IV in FIG.
, Enters a locked state, and only fine tuning by the charge pump 3 is performed.
(B) Behavior of control voltage Vctrl (No. 2)
Hereinafter, the voltage-controlled oscillator 4 shown in FIG. 3B has a relationship between the voltage and the frequency, and the higher the voltage, the higher the frequency, and the convergence range is Vt1, h. A description will be given assuming that it is set between Vt2 and h.

FIG. 11 is a graph showing the behavior (No. 2) of the control voltage Vctrl in this case.
(B-1) Initial Vctrl <locked Vctrl (Fig. 11 (a))
First, when the initial voltage Initial Vctrl of the control voltage Vctrl is lower than Vt2, h, charge is supplied from the control voltage recovery circuit 7 to the loop filter 6 to raise the voltage in order to raise the control voltage Vctrl.

The logic thresholds of the two Schmitt trigger circuits are only visible as Vt1, h and Vt2, h. Therefore, the logic circuit is set so that the recovery circuit is turned off at Vt2, h.
Specifically, when the control voltage Vctrl is lower than any logic threshold, the outputs of the two Schmitt trigger circuits of the control voltage recovery circuit 7 are set to the high state (FIG. 12). Therefore, the trigger voltage supplied to the first switch SW1 and the trigger voltage supplied to the second switch SW2 are both low, the first switch SW1 is on, and the second switch SW2 is off. Charge is supplied to the loop filter 6 and the voltage rises.

When the control voltage Vctrl exceeds Vt2, h, as shown in FIG. 13, the output of the Schmitt trigger circuit SThigh is in the high state, but the output of the Schmitt trigger circuit STlow is in the low state. Therefore, the trigger voltage supplied to the first switch SW1 is high, the trigger voltage supplied to the second switch SW2 is low, and both the first switch SW1 and the second switch SW2 are turned off. The charge from the recovery circuit to the loop filter 6 is stopped. As a result, the control voltage Vctrl is as shown by VI in FIG.
Vt2, h <Vctrl <Vt1, h
And is locked, and only fine tuning by the charge pump 3 is performed.

(B-2) Initial Vctrl> locked Vctrl (Figure 11 (b))
When the control voltage Vctrl is higher than Vt1, l, the recovery circuit extracts the charge of the loop filter 6 in order to lower the control voltage Vctrl.
FIG. 14B is a graph showing the behavior (No. 2) of the control voltage Vctrl in this case.
When the control voltage Vctrl is higher than Vt1, h, the voltage is lowered by the recovery circuit. However, the logic threshold values of the Schmitt trigger circuit are only Vt1, l and Vt2, l.

  Therefore, the control voltage Vctrl is higher than any logic threshold, and the outputs of the two Schmitt trigger circuits are in the low state. Therefore, the trigger voltage supplied to the first switch SW1 and the trigger voltage supplied to the second switch SW2 are both high, the first switch SW1 is off, and the second switch SW2 is on. Therefore, as shown in FIG. 14A, the recovery circuit draws out the charge of the loop filter 6 to lower the control voltage Vctrl, and the control voltage Vctrl falls.

When the control voltage Vctrl falls below Vt1, l (FIG. 15 (a)), the output of the Schmitt trigger circuit SThigh is in the high state, but the output of the Schmitt trigger circuit STlow remains in the low state (broken line). Therefore, the trigger voltage supplied to the first switch SW1 is high, the trigger voltage supplied to the second switch SW2 is low, the first switch SW1 is off, and the second switch SW2 is off ( FIG. 15 (a)). The charge from the recovery circuit to the loop filter 6 is stopped. As a result, the control voltage Vctrl rises because feedback is applied to increase the frequency of the clock in order to minimize the phase difference between the input data and the recovered clock, as indicated by VIII in FIG. Vt2, l <Vctrl <Vt1, l which is the lock range
, Enters a locked state, and only fine tuning by the charge pump 3 is performed.

  As described above, the four threshold values in the relationship of Vt2, l <Vt1, l <Vt2, h <Vt1, h and the lock range (between Vt2, l and Vt1, l or Vt2, h and Vt1, l The control of the control voltage recovery circuit can be cut off using the relationship between

1 is a block diagram showing an overall configuration of a clock and data recovery circuit according to an embodiment of the present invention. 3 is a circuit diagram of a control voltage recovery circuit 7. FIG. It is a figure which shows two patterns of the frequency characteristic of the voltage controlled oscillator. It is a figure which shows the relationship of the four logic threshold values of the two Schmitt trigger circuits corresponding to 1 pattern of the frequency characteristic of the voltage controlled oscillator. It is a figure which shows the relationship of the four logic threshold values of the two Schmitt trigger circuits corresponding to the other pattern of the frequency characteristic of the voltage controlled oscillator. 6 is a graph showing a behavior (No. 1) of a control voltage Vctrl corresponding to one pattern of frequency characteristics of the voltage controlled oscillator 4; 6 is an operation explanatory diagram of a control voltage recovery circuit corresponding to one pattern of frequency characteristics of the voltage controlled oscillator. FIG. 6 is an operation explanatory diagram of a control voltage recovery circuit corresponding to one pattern of frequency characteristics of the voltage controlled oscillator. FIG. 6 is an operation explanatory diagram of a control voltage recovery circuit corresponding to one pattern of frequency characteristics of the voltage controlled oscillator. FIG. 6 is an operation explanatory diagram of a control voltage recovery circuit corresponding to one pattern of frequency characteristics of the voltage controlled oscillator. FIG. 6 is a graph showing the behavior (No. 2) of a control voltage Vctrl corresponding to another pattern of frequency characteristics of the voltage controlled oscillator 4; FIG. 11 is an operation explanatory diagram of the control voltage recovery circuit 7 corresponding to another pattern of frequency characteristics of the voltage controlled oscillator 4. FIG. 11 is an operation explanatory diagram of the control voltage recovery circuit 7 corresponding to another pattern of frequency characteristics of the voltage controlled oscillator 4. FIG. 11 is an operation explanatory diagram of the control voltage recovery circuit 7 corresponding to another pattern of frequency characteristics of the voltage controlled oscillator 4. FIG. 11 is an operation explanatory diagram of the control voltage recovery circuit 7 corresponding to another pattern of frequency characteristics of the voltage controlled oscillator 4.

Explanation of symbols

2 Half-Rate Phase Detector
3 Charge Pump (CP)
4 Voltage Controlled Oscillator (VCO)
5 Multiplexer (MUX)
6 Loop Filter
7 Control voltage recovery circuit 11 1st current source 12 2nd current source SW1 1st switch SW2 2nd switch

Claims (2)

In a phase synchronization circuit comprising a phase detector and a voltage controlled oscillator,
A control voltage recovery circuit for controlling a control voltage of the voltage controlled oscillator;
The voltage-controlled oscillator has a relationship between the control voltage and the frequency, the higher the control voltage, the lower the frequency,
The control voltage recovery circuit includes:
A first Schmitt trigger circuit having a control voltage as an input voltage, and a second Schmitt trigger circuit having the control voltage as an input voltage,
The first Schmitt trigger circuit has a higher logic threshold Vt1, h, a lower logic threshold Vt1, l, a second Schmitt trigger circuit has a higher logic threshold Vt2, h, and a lower logic threshold Vt2, h. relationship with l
Vt2, l <Vt1, l <Vt2, h <Vt1, h
And
The frequency lock range is set between Vt2, l and Vt1, l,
The control voltage recovery circuit cuts off the control when the control voltage exceeds Vt2, h from the bottom to the top, and cuts off the control when the control voltage exceeds Vt1, l from the top to the bottom. A phase synchronization circuit characterized by the above. In a phase synchronization circuit comprising a phase detector and a voltage controlled oscillator,
A control voltage recovery circuit for controlling a control voltage of the voltage controlled oscillator;
The voltage-controlled oscillator has a relationship between the control voltage and the frequency, the higher the control voltage, the higher the frequency,
The control voltage recovery circuit includes:
A first Schmitt trigger circuit having a control voltage as an input voltage, and a second Schmitt trigger circuit having the control voltage as an input voltage,
The first Schmitt trigger circuit has a higher logic threshold Vt1, h, a lower logic threshold Vt1, l, a second Schmitt trigger circuit has a higher logic threshold Vt2, h, and a lower logic threshold Vt2, h. relationship with l
Vt2, l <Vt1, l <Vt2, h <Vt1, h
And
The frequency lock range is set between Vt2, h and Vt1, h.
The control voltage recovery circuit cuts off the control when the control voltage exceeds Vt2, h from the bottom to the top, and cuts off the control when the control voltage exceeds Vt1, l from the top to the bottom. A phase synchronization circuit characterized by the above.

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