JP2008160162A - Packaging structure of multilayer capacitor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer capacitor capable of increasing equivalent series resistance. <P>SOLUTION: A laminate 1 is composed by alternately laminating a plurality of dielectric layers 11-22 and first and second internal electrodes 31-34, 31-34. The first internal electrodes 31-34 are connected mutually and electrically via a first connection conductor 7. The first internal electrode 31 is connected to a first terminal electrode 3 electrically via an extraction conductor 37. Second internal electrodes 41-44 are connected mutually and electrically via a second connection conductor 9. The second internal electrode 44 is connected to a second terminal electrode 5 electrically via an extraction conductor 47. The first and second internal electrodes 31, 44 are arranged so that they are symmetric with respect to a center position M in the lamination direction of the laminate 1. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a multilayer capacitor mounting structure.

  As this type of multilayer capacitor, one having a multilayer body in which a plurality of dielectric layers and a plurality of internal electrodes are alternately stacked and a plurality of terminal electrodes formed in the multilayer body is known ( For example, see Patent Document 1).

  In a power supply for supplying power to a central processing unit (CPU) mounted on a digital electronic device, the load current is increasing while the voltage is lowered. Therefore, it has become very difficult to keep the fluctuation of the power supply voltage within an allowable value against a sudden change in the load current, so that a multilayer capacitor called a decoupling capacitor is connected to the power supply. A current is supplied from the multilayer capacitor to the CPU when the load current changes transiently to suppress fluctuations in the power supply voltage.

In recent years, as the operating frequency of CPUs has further increased, the load current has become higher at higher speeds. For multilayer capacitors used as decoupling capacitors, the equivalent series resistance (ESR) has been increased along with the increase in capacity. There is a demand to increase the size.
JP-A-9-148174

  However, the multilayer capacitor described in Patent Document 1 has not been studied for increasing the equivalent series resistance. Furthermore, in the multilayer capacitor described in Patent Document 1, all internal electrodes are directly connected to terminal electrodes. For this reason, in this multilayer capacitor, if the number of layers is increased and the capacitance is increased to cope with the increase in capacity, the equivalent series resistance is decreased.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a multilayer capacitor capable of increasing the equivalent series resistance.

  In order to achieve such an object, the present inventor has intensively studied a multilayer capacitor capable of increasing the equivalent series resistance. As a result, even if the number of stacked dielectric layers and internal electrodes is the same, the present inventor can provide an equivalent series by connecting internal electrodes with connection conductors and connecting only some internal electrodes to terminal electrodes with lead conductors. It came to find the new fact that it becomes possible to increase resistance.

  However, in such a multilayer capacitor in which only some of the internal electrodes are connected to the terminal electrode, there is a problem in which one of the two side surfaces facing the stacking direction of the multilayer body should be mounted facing the substrate or the like. End up. That is, the multilayer capacitor is mounted such that the terminal electrode is connected to the land pattern formed on the substrate. In the multilayer capacitor mounted on the substrate, a current path is formed between one land pattern and the other land pattern via an internal electrode connected to the terminal electrode. When current flows through this current path, inductance is generated in the multilayer capacitor. The magnitude of this inductance varies depending on the length of the current path formed between the land patterns. The length of the current path is determined by the distance between the internal electrode connected to the terminal electrode and the land pattern. Therefore, in a multilayer capacitor in which only some of the internal electrodes are connected to the terminal electrode, the internal electrode connected to the terminal electrode and the land pattern are generally determined depending on which side of the multilayer body is mounted facing the substrate. Therefore, the length of the current path changes depending on the mounting direction. As a result, there arises a problem that the equivalent series inductance depends on the mounting direction of the multilayer capacitor and causes variations.

  In view of this, the present inventor has conducted earnest research on a multilayer capacitor that can satisfy both the requirement to increase the equivalent series resistance and the requirement to suppress variations in equivalent series inductance. As a result, the inventor connects the internal electrodes with connection conductors and connects only some internal electrodes to the terminal electrodes with lead conductors, and laminates the positions of the internal electrodes connected to the terminal electrodes via the lead conductors. By making it symmetric in the body, the inventors have found a new fact that the equivalent series resistance can be increased while suppressing variations in equivalent series inductance. In particular, if the number of lead conductors or the position of the lead conductors in the stacking direction of the multilayer body can be changed, the equivalent series resistance can be adjusted to a desired value.

  Based on such research results, the multilayer capacitor according to the present invention is a multilayer capacitor including a multilayer body in which a plurality of dielectric layers and a plurality of internal electrodes are alternately stacked, and a plurality of terminal electrodes formed in the multilayer body. The capacitor includes a plurality of terminal electrodes including first and second terminal electrodes electrically insulated from each other, and the plurality of internal electrodes are a plurality of first and second internal electrodes arranged alternately. The plurality of first internal electrodes are electrically connected to each other via the connection conductor, and the plurality of second internal electrodes are electrically connected to each other via the connection conductor, Among the internal electrodes, one or more first internal electrodes less than the total number of the first internal electrodes are electrically connected to the first terminal electrode through the lead conductor, Total number of one or more second internal electrodes among the second internal electrodes The second internal electrode, which is less than one, is electrically connected to the second terminal electrode via the lead conductor, and is connected to the center position in the stacking direction of the multilayer body via the lead conductor. There is a second internal electrode electrically connected to the second terminal electrode through the lead conductor at a position symmetrical to each first internal electrode electrically connected to the one terminal electrode. , With respect to the center position in the stacking direction of the multilayer body, the first electrode is connected to the second inner electrode electrically connected to the second terminal electrode via the lead conductor. There is a first internal electrode electrically connected to one terminal electrode.

  The multilayer capacitor according to the present invention is a multilayer capacitor comprising a multilayer body in which a plurality of dielectric layers and a plurality of internal electrodes are alternately stacked, and a plurality of terminal electrodes formed in the multilayer body. The plurality of terminal electrodes include first and second terminal electrodes that are electrically insulated from each other, and the plurality of internal electrodes include a plurality of first and second internal electrodes that are alternately disposed, The first internal electrodes are electrically connected to each other via the connection conductor, and the plurality of second internal electrodes are electrically connected to each other via the connection conductor, One or more first internal electrodes that are one or more less than the total number of the first internal electrodes are electrically connected to the first terminal electrode through the lead conductor, and a plurality of second internal electrodes One or more of the electrodes, one less than the total number of the second internal electrodes The lower second internal electrode is electrically connected to the second terminal electrode via the lead conductor, and is electrically connected to the first terminal electrode via the lead conductor with respect to the center position in the stacking direction of the multilayer body. The first internal electrodes that are electrically connected to the first terminal electrodes via the lead conductors are present at positions symmetrical to the first internal electrodes that are connected to each other, and the stacking direction of the stacked body The second terminal electrode is electrically connected to the second terminal electrode via the lead conductor at a position symmetrical to each second internal electrode electrically connected to the second terminal electrode via the lead conductor with respect to the center position in FIG. There is a second internal electrode that is connected electrically.

  These multilayer capacitors have first and second internal electrodes that are not directly connected to the first and second terminal electrodes. By having such internal electrodes and connecting conductors that electrically connect them to each other, it is possible to increase the equivalent series resistance in these multilayer capacitors. In these multilayer capacitors, the first and second internal electrodes electrically connected to the first and second terminal electrodes via the lead conductors with respect to the center position in the stacking direction of the multilayer body, An internal electrode that is electrically connected to the terminal electrode through the lead conductor exists at a symmetrical position. Therefore, the length of the current path formed through the internal electrode between the land patterns on the substrate, even when the mounting is performed with any of the two side surfaces facing the stacking direction of the stack facing the substrate or the like. Is hard to change. Therefore, in these multilayer capacitors, variation in equivalent series inductance depending on the mounting direction is suppressed.

  The plurality of first internal electrodes are electrically connected to the connection conductor via the lead conductor, the plurality of second internal electrodes are electrically connected to the connection conductor via the lead conductor, and the connection conductor is laminated. It is preferably formed on the surface of the body. Or it is preferable that a connection conductor is a through-hole conductor provided in the lamination direction of the laminated body in the laminated body. In this case, the first and second internal electrodes are electrically connected to each other.

  In addition, a slit is formed in at least a part of the first and second internal electrodes among the plurality of first and second internal electrodes, and the slits are respectively the first and second internal electrodes in which the slit is formed. In this case, it is preferable that currents flow in opposite directions in regions facing each other with the slit interposed therebetween. In this case, the magnetic field generated due to the current is canceled out, and the equivalent series inductance can be reduced.

  Further, the laminate has a substantially rectangular parallelepiped shape, the first terminal electrode is formed on a side surface extending in the longitudinal direction among the side surfaces parallel to the stacking direction of the laminate, and the second terminal electrode is Of the side surfaces parallel to the stacking direction of the stacked body, it is preferably formed on the side surface extending in the longitudinal direction and facing the side surface on which the first terminal electrode is formed. Thereby, the length in which the first and second internal electrodes overlap is shortened along the direction from the first terminal electrode to the second terminal electrode. As a result, the magnetic field generated by the current flowing through the first and second internal electrodes can be reduced, and the equivalent series inductance can be reduced.

  The number of first internal electrodes electrically connected to the first terminal electrode via the lead conductor and the number of second internal electrodes electrically connected to the second terminal electrode via the lead conductor It is preferable that the equivalent series resistance is set to a desired value by adjusting each of the numbers.

  According to this multilayer capacitor, the number of first internal electrodes electrically connected to the first terminal electrode via the lead conductor and the second electrically connected to the second terminal electrode via the lead conductor. By adjusting the number of at least one of the two internal electrodes, the equivalent series resistance is set to a desired value, so that the equivalent series resistance can be controlled easily and accurately.

  Further, the position in the stacking direction of the laminate of the first internal electrodes that are electrically connected to the first terminal electrode via the lead conductor and the second terminal electrode are electrically connected via the lead conductor. It is preferable that the equivalent series resistance is set to a desired value by adjusting the position of the second internal electrode in the stacking direction of the stack.

  According to this multilayer capacitor, the position of the laminated body of the first internal electrode electrically connected to the first terminal electrode via the lead conductor and the second terminal electrode via the lead conductor The equivalent series resistance is set to a desired value by adjusting at least one position in the stacking direction of the stacked body of the second internal electrodes to be electrically connected. It can be performed easily and accurately.

  Further, by further adjusting the number of connection conductors that electrically connect the plurality of first internal electrodes and the number of connection conductors that electrically connect the plurality of second internal electrodes, respectively, The resistance is preferably set to a desired value. In this case, the equivalent series resistance can be controlled with higher accuracy.

  The plurality of first internal electrodes are preferably connected in parallel, and the plurality of second internal electrodes are preferably connected in parallel. In this case, even if the resistance value of each first internal electrode or each second internal electrode varies, there is little influence on the equivalent series resistance of the entire multilayer capacitor, and the deterioration of the control accuracy of the equivalent series resistance is suppressed. can do.

  According to the present invention, a multilayer capacitor capable of increasing the equivalent series resistance can be provided.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description, the same reference numerals are used for the same elements or elements having the same function, and redundant description is omitted. In the description, the terms “upper” and “lower” may be used, which correspond to the vertical direction of each figure.

(First embodiment)
With reference to FIG.1 and FIG.2, the structure of the multilayer capacitor C1 which concerns on 1st Embodiment is demonstrated. FIG. 1 is a perspective view of the multilayer capacitor in accordance with the first embodiment. FIG. 2 is an exploded perspective view of the multilayer body included in the multilayer capacitor in accordance with the first embodiment.

  As shown in FIG. 1, the multilayer capacitor C1 includes a multilayer body 1, first and second terminal electrodes 3, 5 formed on the multilayer body 1, and first and second connection conductors 7, 9. With.

  The first terminal electrode 3 is formed on the side surface 1 a extending in the longitudinal direction among the side surfaces parallel to the laminating direction described later of the multilayer body 1. The second terminal electrode 5 is formed on the side surface 1b that extends in the longitudinal direction and faces the side surface 1a on which the first terminal electrode 3 is formed, among the side surfaces parallel to the below-described stacking direction of the multilayer body 1. The first terminal electrode 3 and the second terminal electrode 5 are electrically insulated from each other.

  The first connection conductor 7 is formed on the surface of the multilayer body 1 so as to be positioned on the side surface 1 c side of the multilayer body 1. The second connection conductor 9 is formed on the surface of the multilayer body 1 so as to be positioned on the side surface 1 d side of the multilayer body 1. The first connection conductor 7 and the second connection conductor 9 are electrically insulated from each other.

  As shown in FIG. 2, the multilayer body 1 includes a plurality (9 layers in this embodiment) of dielectric layers 11 to 18 and 22, and a plurality (4 layers in this embodiment) of first and second layers. The second inner electrodes 31 to 34 and 41 to 44 are alternately stacked. Moreover, the laminated body 1 has the side surfaces 1e and 1f which mutually oppose in the lamination direction mentioned later. The actual multilayer capacitor C1 is integrated so that the boundaries between the dielectric layers 11 to 18 and 22 are not visible.

  Each of the first inner electrodes 31 to 34 has a substantially rectangular shape. The first internal electrodes 31 to 34 are located at a position having a predetermined interval from a side surface parallel to the stacking direction of the dielectric layers 11 to 18 and 22 in the stacked body 1 (hereinafter simply referred to as “stacking direction”). Each is formed. In each of the first inner electrodes 31 to 34, lead conductors 51 to 54 are formed so as to extend to the side surface 1 c of the multilayer body 1.

  The lead conductor 51 is formed integrally with the first internal electrode 31 and extends from the first internal electrode 31 so as to face the side surface 1 c of the multilayer body 1. The lead conductor 52 is formed integrally with the first internal electrode 32 and extends from the first internal electrode 32 so as to face the side surface 1 c of the multilayer body 1. The lead conductor 53 is formed integrally with the first internal electrode 33 and extends from the first internal electrode 33 so as to face the side surface 1 c of the multilayer body 1. The lead conductor 54 is formed integrally with the first internal electrode 34 and extends from the first internal electrode 34 so as to face the side surface 1 c of the multilayer body 1.

  The first inner electrodes 31 to 34 are electrically connected to the first connection conductor 7 via lead conductors 51 to 54, respectively. As a result, the first inner electrodes 31 to 34 are electrically connected to each other via the first connection conductor 7.

  A lead conductor 37 is formed integrally with the first internal electrode 31 in the first internal electrode 31 and extends from the first internal electrode 31 so as to face the side surface 1 a of the multilayer body 1. The first internal electrode 31 is electrically connected to the first terminal electrode 3 through the lead conductor 37. Since the first inner electrodes 31 to 34 are electrically connected to each other via the first connection conductor 7, the first inner electrodes 32 to 34 are also connected to the first terminal via the first connection conductor 7. It will be electrically connected to the electrode 3 and the first internal electrodes 31 to 34 will be connected in parallel. The first internal electrode 31 is adjacent to the side surface 1 e of the multilayer body 1 in the stacking direction via the dielectric layer 22.

  Each of the second inner electrodes 41 to 44 has a substantially rectangular shape. The second internal electrodes 41 to 44 are respectively formed at positions having a predetermined interval from the side surface parallel to the stacking direction in the stacked body 1. In each of the second inner electrodes 41 to 44, lead conductors 61 to 64 extending so as to be drawn to the side surface 1d of the multilayer body 1 are formed.

  The lead conductor 61 is formed integrally with the second internal electrode 41 and extends from the second internal electrode 41 so as to face the side surface 1 d of the multilayer body 1. The lead conductor 62 is formed integrally with the second internal electrode 42 and extends from the second internal electrode 42 so as to face the side surface 1 d of the multilayer body 1. The lead conductor 63 is formed integrally with the second internal electrode 43 and extends from the second internal electrode 43 so as to face the side surface 1 d of the multilayer body 1. The lead conductor 64 is formed integrally with the second internal electrode 44, and extends from the second internal electrode 44 so as to face the side surface 1 d of the multilayer body 1.

  The second inner electrodes 41 to 44 are electrically connected to the second connection conductor 9 via lead conductors 61 to 64, respectively. As a result, the second inner electrodes 41 to 44 are electrically connected to each other via the second connection conductor 9.

  A lead conductor 47 is formed integrally with the second internal electrode 44 in the second internal electrode 44, and extends from the second internal electrode 44 so as to face the side surface 1 b of the multilayer body 1. The second internal electrode 44 is electrically connected to the second terminal electrode 5 through the lead conductor 47. Since the second inner electrodes 41 to 44 are electrically connected to each other via the second connection conductor 9, the second inner electrodes 41 to 43 are also connected to the second terminal via the second connection conductor 9. It will be electrically connected to the electrode 5, and the second inner electrodes 41 to 44 will be connected in parallel. The second internal electrode 44 is adjacent to the side surface 1 f of the multilayer body 1 in the stacking direction via the dielectric layer 18.

  As described above, in the multilayer body 1, the central position M in the stacking direction is symmetrical to the first internal electrode 31 that is electrically connected to the first terminal electrode 3 via the lead conductor 37. There is a second internal electrode 44 that is electrically connected to the second terminal electrode 5 via the lead conductor 47. On the other hand, in the multilayer body 1, the extraction is performed at a position symmetrical to the second internal electrode 44 electrically connected to the second terminal electrode 5 via the extraction conductor 47 with respect to the center position M in the lamination direction. There is a first internal electrode 31 that is electrically connected to the first terminal electrode 3 via a conductor 37.

  In the multilayer capacitor C1, the number of the first internal electrodes 31 directly connected to the first terminal electrode 3 via the lead conductor 37 is one, and the total number of the first internal electrodes 31 to 34 (in this embodiment, 4). The number of second internal electrodes 44 directly connected to the second terminal electrode 5 via the lead conductor 47 is one, and the total number of second internal electrodes 41 to 44 (in this embodiment, four). ) Is less than. When attention is paid to the first terminal electrode 3, the resistance component of the first connecting conductor 7 is connected in series to the first terminal electrode 3. When attention is focused on the second terminal electrode 5, the resistance component of the second connection conductor 9 is connected in series to the second terminal electrode 5. As a result, the multilayer capacitor C1 has an equivalent series resistance greater than that of a conventional multilayer capacitor in which all internal electrodes are connected to corresponding terminal electrodes via lead conductors. In addition, since the equivalent series resistance is increased, a sudden drop in impedance at the resonance frequency can be prevented, and a wider band can be realized.

  Thus, according to the present embodiment, the number of first internal electrodes 31 that are electrically connected to the first terminal electrode 3 via the lead conductor 37 and the second terminal electrode via the lead conductor 47. By adjusting the number of second internal electrodes 44 electrically connected to each other, the equivalent series resistance of the multilayer capacitor C1 is set to a desired value, so that the equivalent series resistance can be controlled easily and It can be performed with high accuracy.

  In the present embodiment, the first inner electrodes 31 to 34 are connected in parallel, and the second inner electrodes 41 to 44 are connected in parallel. As a result, even if the resistance values of the first internal electrodes 31 to 34 and the second internal electrodes 41 to 44 vary, there is little influence on the equivalent series resistance of the entire multilayer capacitor C1, and the equivalent series resistance is reduced. It is possible to suppress a decrease in control accuracy.

  FIG. 3 is a diagram for explaining a state in which the multilayer capacitor C1 is mounted on the substrate 110. FIG. FIG. 3 shows a state where the first terminal electrode 3 is connected to the cathode land pattern 112 formed on the substrate 110 and the second terminal electrode 5 is connected to the anode land pattern 114.

  FIG. 4 is a diagram schematically showing a cross-sectional structure of the multilayer capacitor C1 mounted on the substrate 110. As shown in FIG. 4 shows a state in which the multilayer capacitor C1 is mounted so that the side surface 1f of the multilayer body 1 faces the substrate 110. FIG. FIG. 4 shows a state where the cathode land pattern 112 is connected to the wiring 116 and the anode land pattern 114 is connected to the wiring 118 in the substrate 110. As understood from FIG. 4, in the multilayer capacitor C1 mounted on the substrate 110, the first terminal electrode 3, the first internal electrode 31 connected to the first terminal electrode 3, from the cathode land pattern 112, A current path to the anode land pattern 114 is formed through the second internal electrode 44 connected to the second terminal electrode 5 and the second terminal electrode 5. In FIG. 4, hatching of regions corresponding to the dielectric layers 11 to 18 and 22 and the wirings 116 and 118 is omitted.

  When a current flows through the current path thus formed between the land patterns 112 and 114, an inductance is generated. The magnitude of this inductance varies depending on the length of the current path. In the multilayer capacitor C <b> 1, the internal electrodes 31 and 44 connected to the terminal electrodes 3 and 5 are disposed at positions that are symmetric with respect to the center position M in the stacking direction of the multilayer body 1. Therefore, even if the multilayer capacitor C1 is mounted so that the side surface 1e of the multilayer body 1 is opposed to the substrate 110 instead of the side surface 1f, the internal electrodes 31, 44 connected to the terminal electrodes 3, 5 and the land patterns 112, 114 are connected. The distance in the stacking direction is difficult to change. That is, in the multilayer capacitor C1, a change in the length of the current path formed between the land patterns depending on the mounting direction is suppressed. As a result, in the multilayer capacitor C1, the value of the equivalent series inductance does not depend on the mounting direction, and variation in the equivalent series inductance depending on the mounting direction can be suppressed.

  The first terminal electrode 3 is formed on the side surface 1 a extending in the longitudinal direction among the side surfaces parallel to the stacking direction of the rectangular parallelepiped stacked body 1, and the second terminal electrode 5 is formed in the stacking direction of the stacked body 1. Of the parallel side surfaces, the side surface 1b extends in the longitudinal direction and faces the side surface 1a on which the first terminal electrode 3 is formed. Accordingly, the length in which the first and second internal electrodes 31 to 34 and 41 to 44 overlap is shortened along the direction from the first terminal electrode 3 to the second terminal electrode 5. As a result, the magnetic field generated by the current flowing through the first and second internal electrodes 31 to 34 and 41 to 44 can be reduced, and the multilayer capacitor C1 can reduce the equivalent series inductance.

(Second Embodiment)
The configuration of the multilayer capacitor in accordance with the second embodiment will be described with reference to FIG. The multilayer capacitor in accordance with the second embodiment includes a first internal electrode 33 connected to the first terminal electrode 3 via the lead conductor 37 and a second terminal electrode 5 connected to the second terminal electrode 5 via the lead conductor 47. The second internal electrode 42 is different from the multilayer capacitor C1 according to the first embodiment in the position in the stacking direction. FIG. 5 is an exploded perspective view of the multilayer body included in the multilayer capacitor in accordance with the second embodiment.

  Although the multilayer capacitor according to the second embodiment is not illustrated, the multilayer capacitor 1 and the first terminal electrode 3 formed on the multilayer capacitor 1 are the same as the multilayer capacitor C1 according to the first embodiment. A second terminal electrode 5 formed on the multilayer body 1 and first and second connection conductors 7 and 9 are provided.

  In the multilayer capacitor in accordance with the second embodiment, as shown in FIG. 5, among the four first inner electrodes 31 to 34, the third inner electrode 33 that is the third from the top passes through the lead conductor 37. Are electrically connected to the first terminal electrode 3. As a result, the first inner electrodes 31, 32, and 34 are also electrically connected to the first terminal electrode 3, and the first inner electrodes 31 to 34 are connected in parallel. The lead conductor 37 is formed integrally with the first internal electrode 33 and extends from the first internal electrode 33 so as to face the side surface 1 a extending in the longitudinal direction among the side surfaces parallel to the stacking direction of the multilayer body 1. ing.

  In the multilayer capacitor in accordance with the second embodiment, as shown in FIG. 5, the second inner electrode 42 that is the second from the top among the four second inner electrodes 41 to 44 is provided via the lead conductor 47. Are electrically connected to the second terminal electrode 5. Accordingly, the second inner electrodes 41, 43, 44 are also electrically connected to the second terminal electrode 5, and the second inner electrodes 41 to 44 are connected in parallel. The lead conductor 47 is formed integrally with the second inner electrode 42 and extends in the longitudinal direction among the side surfaces parallel to the stacking direction of the multilayer body 1 and faces the side surface 1b facing the side surface 1a. The internal electrode 42 extends from the internal electrode 42.

  In the multilayer capacitor in accordance with the second embodiment, the number of first internal electrodes 33 directly connected to the first terminal electrode 3 via the lead conductor 37 is one, and the total number of first internal electrodes 31 to 34 is one. (In the present embodiment, the number is four). The number of second internal electrodes 42 directly connected to the second terminal electrode 5 via the lead conductor 47 is one, and the total number of second internal electrodes 41 to 44 (in this embodiment, four). ) Is less than. As a result, the multilayer capacitor according to the second embodiment has an equivalent series resistance greater than that of a conventional multilayer capacitor in which all internal electrodes are connected to corresponding terminal electrodes via lead conductors.

  By the way, paying attention to the first terminal electrode 3, the resistance component of the first connection conductor 7 is located on one side in the stacking direction from the first internal electrode 33 with the first internal electrode 33 as a boundary. The resistance component of the first connection conductor 7 is divided into the resistance component of the first connection conductor 7 located on the other side in the stacking direction from the first internal electrode 33. These resistance components are connected in parallel to the first terminal electrode 3. Focusing on the second terminal electrode 5, the resistance component of the second connection conductor 9 is located on one side in the stacking direction with respect to the second internal electrode 42 with respect to the second internal electrode 42. The resistance component of the second connection conductor 9 is divided into the resistance component of the second connection conductor 9 positioned on the other side in the stacking direction with respect to the second internal electrode 42. These resistance components are connected in parallel to the second terminal electrode 5.

  Therefore, due to the difference in resistance component between the first and second connection conductors 7 and 9, the multilayer capacitor according to the second embodiment has an equivalent series resistance compared to the multilayer capacitor C1 according to the first embodiment. Becomes smaller.

  As described above, according to the present embodiment, the position in the stacking direction of the first internal electrode 33 electrically connected to the first terminal electrode 3 through the lead conductor 37 and the lead conductor 47 are used. Since the equivalent series resistance of the multilayer capacitor is set to a desired value by adjusting the position of the second inner electrode 42 electrically connected to the second terminal electrode 5 in the lamination direction, the equivalent series resistance Can be controlled easily and accurately.

  In the multilayer body 1 of the multilayer capacitor in accordance with the second embodiment, the first internal electrode electrically connected to the first terminal electrode 3 via the lead conductor 37 with respect to the center position M in the lamination direction. A second internal electrode 42 that is electrically connected to the second terminal electrode 5 through the lead conductor 47 exists at a position that is symmetric with respect to 33. On the other hand, in the multilayer body 1 of the multilayer capacitor in accordance with the second embodiment, the second internal electrode electrically connected to the second terminal electrode 5 via the lead conductor 47 with respect to the center position M in the lamination direction. The first internal electrode 33 that is electrically connected to the first terminal electrode 3 through the lead conductor 37 exists at a position that is symmetrical with respect to 42. For this reason, even when mounting is performed with any one of the two side surfaces 1e and 1f facing the stacking direction of the stacked body 1 facing the substrate or the like, it is formed between the land patterns on the substrate or the like via the internal electrodes. The length of the current path is unlikely to change. Therefore, in the multilayer capacitor according to the second embodiment, the equivalent series inductance is prevented from varying depending on the mounting direction.

  The first terminal electrode 3 is formed on the side surface 1 a extending in the longitudinal direction among the side surfaces parallel to the stacking direction of the rectangular parallelepiped stacked body 1, and the second terminal electrode 5 is formed in the stacking direction of the stacked body 1. Of the parallel side surfaces, the side surface 1b extends in the longitudinal direction and faces the side surface 1a on which the first terminal electrode 3 is formed. Thereby, the magnetic field generated by the current flowing through the first and second internal electrodes 31 to 34 and 41 to 44 can be reduced, and the multilayer capacitor according to the second embodiment can reduce the equivalent series inductance. It becomes possible.

(Third embodiment)
With reference to FIG. 6, the structure of the multilayer capacitor in accordance with the third embodiment will be explained. The multilayer capacitor in accordance with the third embodiment is the first in terms of the number of first and second internal electrodes 31, 34, 41, 44 connected to the terminal electrodes 3, 5 via lead conductors 37, 47. This is different from the multilayer capacitor C1 according to the embodiment. FIG. 6 is an exploded perspective view of the multilayer body included in the multilayer capacitor in accordance with the third embodiment.

  Although the multilayer capacitor according to the third embodiment is not shown, the multilayer capacitor 1 and the first terminal electrode 3 formed in the multilayer capacitor 1 are the same as the multilayer capacitor C1 according to the first embodiment. A second terminal electrode 5 formed on the multilayer body 1 and first and second connection conductors 7 and 9 are provided.

  In the multilayer capacitor in accordance with the third embodiment, as shown in FIG. 6, two first inner electrodes 31, 34 out of the four first inner electrodes 31 to 34 are connected to the first via the lead conductor 37. The terminal electrode 3 is electrically connected. Since the first inner electrodes 31 to 34 are electrically connected to each other via the first connection conductor 7, the first inner electrodes 32 and 33 are also connected to the first terminal via the first connection conductor 7. It will be electrically connected to the electrode 3 and the first internal electrodes 31 to 34 will be connected in parallel. The lead conductor 37 is formed integrally with each of the first internal electrodes 31, 34, and the first internal electrode faces the side surface 1 a extending in the longitudinal direction among the side surfaces parallel to the stacking direction of the multilayer body 1. 31 and 34 respectively extend.

  Of the four second inner electrodes 41 to 44, two second inner electrodes 41, 44 are electrically connected to the second terminal electrode 5 via the lead conductor 47. Since the second inner electrodes 41 to 44 are electrically connected to each other via the second connection conductor 9, the second inner electrodes 42 and 43 are also connected to the second terminal via the second connection conductor 9. It will be electrically connected to the electrode 5, and the second inner electrodes 41 to 44 will be connected in parallel. The lead conductor 47 is formed integrally with each of the second inner electrodes 41 and 44, and extends in the longitudinal direction among the side surfaces parallel to the stacking direction of the multilayer body 1 and faces the side surface 1b facing the side surface 1a. , Extending from the second inner electrodes 41, 44, respectively.

  In the multilayer capacitor in accordance with the third embodiment, the number of first internal electrodes 31, 34 directly connected to the first terminal electrode 3 through the lead conductor 37 is two, and the first internal electrodes 31 to 34 are arranged. Has been less than the total number of. Further, the number of second internal electrodes 41 and 44 that are directly connected to the second terminal electrode 5 via the lead conductor 47 is two, which is smaller than the total number of the second internal electrodes 41 to 44. . Therefore, the multilayer capacitor according to the third embodiment has an equivalent series resistance that is greater than that of a conventional multilayer capacitor in which all internal electrodes are connected to corresponding terminal electrodes via lead conductors.

  The multilayer capacitor in accordance with the third embodiment has a larger number of first internal electrodes 31 and 34 that are directly connected to the first terminal electrode 3 via the lead conductor 37 than the multilayer capacitor C1. The lead conductor 37 is connected in parallel to the first terminal electrode 3. In addition, there are many second internal electrodes 41 and 44 that are directly connected to the second terminal electrode 5 through the lead conductor 47, and these lead conductors 47 are connected in parallel to the second terminal electrode 5. Therefore, the equivalent series resistance of the multilayer capacitor according to the third embodiment is smaller than the equivalent series resistance of the multilayer capacitor C1.

  As described above, according to the present embodiment, the number of first internal electrodes 31, 34 electrically connected to the first terminal electrode 3 through the lead conductor 37 and the second through the lead conductor 47. Since the equivalent series resistance of the multilayer capacitor in accordance with the third embodiment is set to a desired value by adjusting the number of second internal electrodes 41 and 44 that are electrically connected to the terminal electrode 5, respectively. Therefore, it is possible to easily and accurately control the equivalent series resistance.

  Further, in the multilayer body 1 of the multilayer capacitor in accordance with the third embodiment, the first internal electrode electrically connected to the first terminal electrode 3 via the lead conductor 37 with respect to the center position M in the lamination direction. A second internal electrode 44 that is electrically connected to the second terminal electrode 5 through the lead conductor 47 exists at a position that is symmetric with respect to 31. In the multilayer body 1, the lead conductor 47 is located at a position symmetrical to the first internal electrode 34 electrically connected to the first terminal electrode 3 via the lead conductor 37 with respect to the center position M in the stacking direction. There is a second internal electrode 41 that is electrically connected to the second terminal electrode 5 via the. On the other hand, in the multilayer body 1 of the multilayer capacitor in accordance with the third embodiment, the second internal electrode electrically connected to the second terminal electrode 5 through the lead conductor 47 with respect to the center position M in the lamination direction. The first internal electrode 34 that is electrically connected to the first terminal electrode 3 through the lead conductor 37 is present at a position that is symmetrical to 41. In the multilayer body 1, the lead conductor 37 is located at a position symmetrical to the second internal electrode 44 that is electrically connected to the second terminal electrode 5 via the lead conductor 47 with respect to the center position M in the stacking direction. There is a first internal electrode 31 that is electrically connected to the first terminal electrode 3 via the. For this reason, even when mounting is performed with any one of the two side surfaces 1e and 1f facing the stacking direction of the stacked body 1 facing the substrate or the like, it is formed between the land patterns on the substrate or the like via the internal electrodes. The length of the current path is unlikely to change. Therefore, in the multilayer capacitor in accordance with the third embodiment, the equivalent series inductance is prevented from varying depending on the mounting direction.

  The first terminal electrode 3 is formed on the side surface 1 a extending in the longitudinal direction among the side surfaces parallel to the stacking direction of the rectangular parallelepiped stacked body 1, and the second terminal electrode 5 is formed in the stacking direction of the stacked body 1. Of the parallel side surfaces, the side surface 1b extends in the longitudinal direction and faces the side surface 1a on which the first terminal electrode 3 is formed. As a result, the magnetic field generated by the current flowing through the first and second internal electrodes 31 to 34 and 41 to 44 can be reduced, and the multilayer capacitor according to the third embodiment can reduce the equivalent series inductance. It becomes possible.

(Fourth embodiment)
With reference to FIG. 7, the structure of the multilayer capacitor in accordance with the fourth embodiment will be explained. The multilayer capacitor in accordance with the fourth embodiment is different from the multilayer capacitor C1 in accordance with the first embodiment in that slits are formed in the first and second internal electrodes 32-34, 41-43. FIG. 7 is an exploded perspective view of the multilayer body included in the multilayer capacitor in accordance with the fourth embodiment.

  Although the multilayer capacitor according to the fourth embodiment is not shown, the multilayer body 1 and the first terminal electrode 3 formed on the multilayer body 1 are the same as the multilayer capacitor C1 according to the first embodiment. A second terminal electrode 5 formed on the multilayer body 1 and first and second connection conductors 7 and 9 are provided.

  In the first internal electrodes 32 to 34, slits S11 to S13 extend from the side of the connecting portion between the lead conductors 52 to 54 and the first internal electrodes 32 to 34 in the longitudinal direction of the first internal electrodes 32-34. Is formed. Accordingly, the slits S11 to S13 are formed in the first inner electrodes 32 to 34 such that currents flow in opposite directions in regions facing each other across the slits S11 to S13.

  In the second inner electrodes 41 to 43, the slits S21 to S23 extend from the side of the connecting portion between the lead conductors 61 to 63 and the second inner electrodes 41 to 43 in the longitudinal direction of the second inner electrodes 41 to 43. Is formed. Accordingly, the slits S21 to S23 are formed in the second internal electrodes 41 to 43 so that currents flow in opposite directions in regions facing each other across the slits S21 to S23.

  In the first and second internal electrodes 32 to 34 and 41 to 43 in which the slits S11 to S13 and S21 to S23 are formed, the currents are opposite to each other in regions facing each other with the slits S11 to S13 and S21 to S23 interposed therebetween. Therefore, the magnetic field generated due to the current is canceled out. In addition, the first internal electrodes 32 to 34 and the second internal electrodes 41 to 43 in which the slits are formed have the current flowing in the opposite direction when viewed in the stacking direction. Therefore, the magnetic field generated due to the current flowing through the first internal electrodes 32 to 34 and the magnetic field generated due to the current flowing through the second internal electrodes 41 to 43 are canceled out. For this reason, in the multilayer capacitor in accordance with the fourth embodiment, it is possible to reduce the equivalent series inductance.

  In the multilayer capacitor in accordance with the fourth embodiment, the number of first internal electrodes 31 directly connected to the first terminal electrode 3 via the lead conductor 37 is one, and the first internal electrodes 31 to 34 are provided. Is less than the total number (four in this embodiment). The number of second internal electrodes 44 directly connected to the second terminal electrode 5 via the lead conductor 47 is one, and the total number of second internal electrodes 41 to 44 (in this embodiment, four). ) Is less than. Accordingly, the multilayer capacitor according to the fourth embodiment has an equivalent series resistance that is higher than that of a conventional multilayer capacitor in which all internal electrodes are connected to corresponding terminal electrodes via lead conductors.

  As described above, according to the present embodiment, the number of first internal electrodes 31 that are electrically connected to the first terminal electrode 3 via the lead conductor 37 and the second terminal via the lead conductor 47. Since the equivalent series resistance of the multilayer capacitor according to the fourth embodiment is set to a desired value by adjusting the number of second internal electrodes 44 electrically connected to the electrode 5, the equivalent series resistance Can be controlled easily and accurately.

  Further, in the multilayer body 1 of the multilayer capacitor in accordance with the fourth embodiment, the first internal electrode electrically connected to the first terminal electrode 3 via the lead conductor 37 with respect to the center position M in the lamination direction. A second internal electrode 44 that is electrically connected to the second terminal electrode 5 through the lead conductor 47 exists at a position that is symmetric with respect to 31. On the other hand, in the multilayer body 1 of the multilayer capacitor in accordance with the fourth embodiment, the second internal electrode electrically connected to the second terminal electrode 5 through the lead conductor 47 with respect to the center position M in the lamination direction. The first internal electrode 31 that is electrically connected to the first terminal electrode 3 through the lead conductor 37 is present at a position that is symmetrical with respect to 44. For this reason, even when mounting is performed with any one of the two side surfaces 1e and 1f facing the stacking direction of the stacked body 1 facing the substrate or the like, it is formed between the land patterns on the substrate or the like via the internal electrodes. The length of the current path is unlikely to change. Therefore, in the multilayer capacitor in accordance with the fourth embodiment, the equivalent series inductance is suppressed from varying depending on the mounting direction.

  The first terminal electrode 3 is formed on the side surface 1 a extending in the longitudinal direction among the side surfaces parallel to the stacking direction of the rectangular parallelepiped stacked body 1, and the second terminal electrode 5 is formed in the stacking direction of the stacked body 1. Of the parallel side surfaces, the side surface 1b extends in the longitudinal direction and faces the side surface 1a on which the first terminal electrode 3 is formed. Thereby, the magnetic field generated by the current flowing through the first and second internal electrodes 31 to 34 and 41 to 44 can be reduced, and the multilayer capacitor according to the fourth embodiment can reduce the equivalent series inductance. It becomes possible.

  The internal electrodes in which the slits are formed are not limited to the first and second internal electrodes 32 to 34 and 41 to 43. That is, the slit may be formed in an internal electrode other than the first and second internal electrodes 32 to 34 and 41 to 43, for example, the first and second terminal electrodes 3 through the lead conductors 37 and 47, 5 may be formed on the first and second internal electrodes 31, 44 that are electrically connected to 5. As an example of this case, an exploded perspective view of a multilayer capacitor in which slits S11 to S14 and S21 to S24 are formed in the first and second internal electrodes 31 to 36, 41 to 45 is shown in FIG. By forming slits S11 and S24 in the first and second internal electrodes 31 and 44 that are electrically connected to the first and second terminal electrodes 3 and 5 through the lead conductors 37 and 47, these are provided. Also in the internal electrodes 31, 44, the magnetic field generated due to the current is canceled. Therefore, it is possible to further reduce the equivalent series inductance in the multilayer capacitor.

(Fifth embodiment)
With reference to FIG. 9, the structure of the multilayer capacitor in accordance with the fifth embodiment will be explained. In the multilayer capacitor in accordance with the fifth embodiment, the first internal electrode connected to the first terminal electrode and the internal electrode present at a position symmetrical to the center position in the stacking direction of the multilayer body are the first The internal electrode that is an internal electrode and exists at a position that is symmetrical with respect to the center position in the stacking direction of the stacked body and the second internal electrode that is connected to the second terminal electrode is the second internal electrode This is different from the multilayer capacitor C1 according to the first embodiment. FIG. 9 is an exploded perspective view of the multilayer body included in the multilayer capacitor in accordance with the fifth embodiment.

  Although the multilayer capacitor according to the fifth embodiment is not shown, the multilayer capacitor 1 and the first terminal electrode 3 formed on the multilayer substrate 1 are the same as the multilayer capacitor C1 according to the first embodiment. A second terminal electrode 5 formed on the multilayer body 1 and first and second connection conductors 7 and 9 are provided.

  As shown in FIG. 9, the stacked body 1 includes a plurality (12 layers in this embodiment) of dielectric layers 11 to 22 and a plurality (6 layers and 5 layers in this embodiment) of first and The second inner electrodes 31 to 36 and 41 to 45 are alternately stacked. In an actual multilayer capacitor, integration is performed so that the boundary between the dielectric layers 11 to 22 cannot be visually recognized.

  Each of the first inner electrodes 31 to 36 has a substantially rectangular shape. The first internal electrodes 31 to 36 are respectively formed at positions having a predetermined interval from a side surface parallel to the stacking direction of the dielectric layers 11 to 22 in the stacked body 1 (hereinafter simply referred to as “stacking direction”). Has been. In each of the first inner electrodes 31 to 36, lead conductors 51 to 56 extending so as to be drawn to the side surface 1c of the multilayer body 1 are formed.

  The lead conductor 51 is formed integrally with the first internal electrode 31 and extends from the first internal electrode 31 so as to face the side surface 1 c of the multilayer body 1. The lead conductor 52 is formed integrally with the first internal electrode 32 and extends from the first internal electrode 32 so as to face the side surface 1 c of the multilayer body 1. The lead conductor 53 is formed integrally with the first internal electrode 33 and extends from the first internal electrode 33 so as to face the side surface 1 c of the multilayer body 1. The lead conductor 54 is formed integrally with the first internal electrode 34 and extends from the first internal electrode 34 so as to face the side surface 1 c of the multilayer body 1. The lead conductor 55 is formed integrally with the first internal electrode 35, and extends from the first internal electrode 35 so as to face the side surface 1 c of the multilayer body 1. The lead conductor 56 is formed integrally with the first internal electrode 36 and extends from the first internal electrode 36 so as to face the side surface 1 c of the multilayer body 1.

  The first inner electrodes 31 to 36 are electrically connected to the first connection conductor 7 via lead conductors 51 to 56, respectively. As a result, the first inner electrodes 31 to 36 are electrically connected to each other via the first connection conductor 7.

  A lead conductor 37 is formed integrally with the first internal electrode 31 in the first internal electrode 31 and extends from the first internal electrode 31 so as to face the side surface 1 a of the multilayer body 1. The first internal electrode 31 is electrically connected to the first terminal electrode 3 through the lead conductor 37. A lead conductor 37 is formed integrally with the first internal electrode 36 on the first internal electrode 36, and extends from the first internal electrode 36 so as to face the side surface 1 a of the multilayer body 1. The first internal electrode 36 is electrically connected to the first terminal electrode 3 through the lead conductor 37. Since the first inner electrodes 31 to 36 are electrically connected to each other via the first connection conductor 7, the first inner electrodes 32 to 35 are also connected to the first terminal via the first connection conductor 7. It will be electrically connected to the electrode 3, and the first internal electrodes 31 to 36 will be connected in parallel. The first internal electrode 31 is adjacent to the side surface 1 e of the multilayer body 1 in the stacking direction via the dielectric layer 22. The first internal electrode 36 is adjacent to the side surface 1 f of the stacked body 1 in the stacking direction via the dielectric layer 21.

  Each of the second inner electrodes 41 to 45 has a substantially rectangular shape. The second internal electrodes 41 to 45 are respectively formed at positions having a predetermined interval from the side surface parallel to the stacking direction in the stacked body 1. In each of the second inner electrodes 41 to 45, lead conductors 61 to 65 extending so as to be drawn to the side surface 1d of the multilayer body 1 are formed.

  The lead conductor 61 is formed integrally with the second internal electrode 41 and extends from the second internal electrode 41 so as to face the side surface 1 d of the multilayer body 1. The lead conductor 62 is formed integrally with the second internal electrode 42 and extends from the second internal electrode 42 so as to face the side surface 1 d of the multilayer body 1. The lead conductor 63 is formed integrally with the second internal electrode 43 and extends from the second internal electrode 43 so as to face the side surface 1 d of the multilayer body 1. The lead conductor 64 is formed integrally with the second internal electrode 44, and extends from the second internal electrode 44 so as to face the side surface 1 d of the multilayer body 1. The lead conductor 65 is formed integrally with the second internal electrode 45 and extends from the second internal electrode 45 so as to face the side surface 1 d of the multilayer body 1.

  The second inner electrodes 41 to 45 are electrically connected to the second connection conductor 9 via lead conductors 61 to 65, respectively. As a result, the second inner electrodes 41 to 45 are electrically connected to each other through the second connection conductor 9.

  A lead conductor 47 is formed integrally with the second internal electrode 41 on the second internal electrode 41 and extends from the second internal electrode 41 so as to face the side surface 1 b of the multilayer body 1. The second internal electrode 41 is electrically connected to the second terminal electrode 5 through the lead conductor 47. A lead conductor 47 is formed integrally with the second internal electrode 45 in the second internal electrode 45, and extends from the second internal electrode 45 so as to face the side surface 1 b of the multilayer body 1. The second internal electrode 45 is electrically connected to the second terminal electrode 5 through the lead conductor 47. Since the second inner electrodes 41 to 45 are electrically connected to each other via the second connection conductor 9, the second inner electrodes 42 to 44 are also connected to the second terminal via the second connection conductor 9. It will be electrically connected to the electrode 5, and the second internal electrodes 41 to 45 will be connected in parallel.

  As described above, in the multilayer body 1, the central position M in the stacking direction is symmetrical to the first internal electrode 31 that is electrically connected to the first terminal electrode 3 via the lead conductor 37. There is a first internal electrode 36 that is electrically connected to the first terminal electrode 3 via the lead conductor 37. In the multilayer body 1, the lead conductor 37 is located at a position symmetrical to the first internal electrode 36 that is electrically connected to the first terminal electrode 3 via the lead conductor 37 with respect to the center position M in the stacking direction. There is a first internal electrode 31 that is electrically connected to the first terminal electrode 3 via the.

  On the other hand, in the multilayer body 1, with respect to the center position M in the stacking direction, the lead is placed at a position symmetrical to the second internal electrode 41 electrically connected to the second terminal electrode 5 via the lead conductor 47. There is a second internal electrode 45 that is electrically connected to the second terminal electrode 5 via the conductor 47. In the multilayer body 1, the lead conductor 47 is located at a position symmetrical to the second internal electrode 45 electrically connected to the second terminal electrode 5 via the lead conductor 47 with respect to the center position M in the stacking direction. There is a second internal electrode 41 that is electrically connected to the second terminal electrode 5 via the.

  In the multilayer capacitor in accordance with the fifth embodiment, the number of first internal electrodes 31, 36 directly connected to the first terminal electrode 3 via the lead conductor 37 is two, and the first internal electrodes 31 to 36 are used. Is less than the total number (six in this embodiment). In addition, the number of second internal electrodes 41 and 45 directly connected to the second terminal electrode 5 via the lead conductor 47 is two, and the total number of second internal electrodes 41 to 45 (in this embodiment, Less than 5). Therefore, the multilayer capacitor according to the fifth embodiment has an equivalent series resistance that is higher than that of a conventional multilayer capacitor in which all internal electrodes are connected to corresponding terminal electrodes via lead conductors. In addition, since the equivalent series resistance is increased, a sudden drop in impedance at the resonance frequency can be prevented, and a wider band can be realized.

  Thus, according to the present embodiment, the number of first internal electrodes 31, 36 electrically connected to the first terminal electrode 3 through the lead conductor 37 and the second through the lead conductor 47. Since the equivalent series resistance of the multilayer capacitor in accordance with the fifth embodiment is set to a desired value by adjusting the number of second internal electrodes 41 and 45 electrically connected to the terminal electrode 5, respectively. It is possible to easily and accurately control the equivalent series resistance.

  In the present embodiment, the first internal electrodes 31 to 36 are connected in parallel, and the second internal electrodes 41 to 45 are connected in parallel. As a result, even if the resistance values of the first internal electrodes 31 to 36 and the second internal electrodes 41 to 45 vary, there is an influence on the equivalent series resistance of the entire multilayer capacitor according to the fifth embodiment. Therefore, it is possible to suppress a decrease in accuracy of controlling the equivalent series resistance.

  FIG. 10 is a diagram schematically showing a cross-sectional structure of the multilayer capacitor in accordance with the fifth embodiment mounted on the substrate 110. FIG. 10 shows a state in which the multilayer capacitor according to the fifth embodiment is mounted so that the side surface 1 f of the multilayer body 1 faces the substrate 110. FIG. 10 shows a state in which the cathode land pattern 112 is connected to the wiring 116 and the anode land pattern 114 is connected to the wiring 118 in the substrate 110. As understood from FIG. 10, in the multilayer capacitor according to the fifth embodiment mounted on the substrate 110, the first terminal electrode 3 and the first terminal electrode 3 connected to the first terminal electrode 3 from the cathode land pattern 112. A current path to the anode land pattern 114 is formed through the internal electrodes 31 and 36, the second internal electrodes 41 and 45 connected to the second terminal electrode 5, and the second terminal electrode 5. In FIG. 10, hatching of regions corresponding to the dielectric layers 11 to 22 and the wirings 116 and 118 is omitted.

  When a current flows through the current path thus formed between the land patterns, an inductance is generated. The magnitude of this inductance varies depending on the length of the current path. In the multilayer capacitor in accordance with the fifth embodiment, the internal electrodes 31, 36, 41, 45 connected to the terminal electrodes 3, 5 are symmetrical with respect to the center position M in the stacking direction of the multilayer body 1. Internal electrodes 36, 31, 45, and 41 are respectively present. Therefore, even when the multilayer capacitor according to the fifth embodiment is mounted so that the side surface 1e of the multilayer body 1 is opposed to the substrate 110, the internal electrodes 31, 36, The distance in the stacking direction between 41 and 45 and the land patterns 112 and 114 is difficult to change. That is, in the multilayer capacitor in accordance with the fifth embodiment, a change in the length of the current path formed between the land patterns due to the mounting direction is suppressed. As a result, in the multilayer capacitor in accordance with the fifth embodiment, the value of the equivalent series inductance does not depend on the mounting direction, and variation in the equivalent series inductance can be suppressed depending on the mounting direction.

  The first terminal electrode 3 is formed on the side surface 1 a extending in the longitudinal direction among the side surfaces parallel to the stacking direction of the rectangular parallelepiped stacked body 1, and the second terminal electrode 5 is formed in the stacking direction of the stacked body 1. Of the parallel side surfaces, the side surface 1b extends in the longitudinal direction and faces the side surface 1a on which the first terminal electrode 3 is formed. Accordingly, the length in which the first and second internal electrodes 31 to 36 and 41 to 45 overlap is shortened along the direction from the first terminal electrode 3 to the second terminal electrode 5. As a result, the magnetic field generated by the current flowing through the first and second inner electrodes 31 to 36, 41 to 45 can be reduced, and the multilayer capacitor according to the fifth embodiment can reduce the equivalent series inductance. It becomes possible.

(Sixth embodiment)
With reference to FIG. 11, the structure of the multilayer capacitor in accordance with the sixth embodiment will be explained. The multilayer capacitor in accordance with the sixth embodiment is connected to the second terminal electrode 5 via the first internal electrodes 33, 34 connected to the first terminal electrode 3 via the lead conductor 37 and the lead conductor 47. This is different from the multilayer capacitor in accordance with the fifth embodiment in that the second internal electrodes 42 and 44 are positioned in the direction of lamination. FIG. 11 is an exploded perspective view of the multilayer body included in the multilayer capacitor in accordance with the sixth embodiment.

  Although the multilayer capacitor according to the sixth embodiment is not shown, the multilayer capacitor 1 and the first terminal electrode 3 formed on the multilayer capacitor 1 are the same as the multilayer capacitor C1 according to the first embodiment. A second terminal electrode 5 formed on the multilayer body 1 and first and second connection conductors 7 and 9 are provided.

  In the multilayer capacitor in accordance with the sixth embodiment, as shown in FIG. 11, among the six first internal electrodes 31 to 36, the first internal electrode 33 which is the third from the top, and the fourth from the top, The first inner electrode 34 is electrically connected to the first terminal electrode 3 through the lead conductor 37. As a result, the first inner electrodes 31, 32, 35, and 36 are also electrically connected to the first terminal electrode 3, and the first inner electrodes 31 to 36 are connected in parallel. The lead conductor 37 is formed integrally with the first inner electrodes 33, 34, and faces the side surface 1 a extending in the longitudinal direction among the side surfaces parallel to the stacking direction of the multilayer body 1. , 34.

  In the multilayer capacitor in accordance with the sixth embodiment, as shown in FIG. 11, the second internal electrode 42 that is the second from the top among the five second internal electrodes 41 to 45 and the fourth from the top, The second inner electrode 44 is electrically connected to the second terminal electrode 5 through the lead conductor 47. Accordingly, the second internal electrodes 41, 43, 45 are also electrically connected to the second terminal electrode 5, and the second internal electrodes 41 to 45 are connected in parallel. The lead conductor 47 is formed integrally with the second inner electrodes 42, 44, and extends in the longitudinal direction among the side surfaces parallel to the stacking direction of the multilayer body 1 and faces the side surface 1b facing the side surface 1a. Extending from the second internal electrodes 42, 44.

  In the multilayer capacitor in accordance with the sixth embodiment, the number of first internal electrodes 33 and 34 directly connected to the first terminal electrode 3 via the lead conductor 37 is two, and the first internal electrodes 31 to 36 are used. Is less than the total number (six in this embodiment). Further, the number of second internal electrodes 42 and 44 directly connected to the second terminal electrode 5 through the lead conductor 47 is two, and the total number of second internal electrodes 41 to 45 (in this embodiment, Less than 5). As a result, the multilayer capacitor according to the sixth embodiment has an equivalent series resistance greater than that of a conventional multilayer capacitor in which all internal electrodes are connected to corresponding terminal electrodes via lead conductors.

  By the way, paying attention to the first terminal electrode 3, the multilayer capacitor according to the sixth embodiment has a resistance component of the first connection conductor 7 as compared with the multilayer capacitor according to the fifth embodiment. The connection method is different. That is, in the multilayer capacitor in accordance with the fifth embodiment, the resistance component of the first connection conductor 7 is connected in series to each of the first internal electrodes 31 and 36. On the other hand, in the multilayer capacitor in accordance with the sixth embodiment, the resistance component of the first connection conductor 7 is divided with the first internal electrodes 33 and 34 as boundaries, and these resistance components are the first terminal electrodes. 3 are connected in parallel. Focusing on the second terminal electrode 5, the multilayer capacitor in accordance with the sixth embodiment has the second terminal electrode 5 having the resistance component of the second connection conductor 9 as compared with the multilayer capacitor in accordance with the fifth embodiment. The connection method is different. That is, in the multilayer capacitor in accordance with the fifth embodiment, the resistance component of the second connection conductor 9 is connected in series to each of the second internal electrodes 41 and 45. On the other hand, in the multilayer capacitor in accordance with the sixth embodiment, the resistance component of the second connection conductor 9 is divided with the second internal electrodes 42 and 44 as boundaries, and these resistance components are separated from the second terminal electrode. 5 are connected in parallel.

  Therefore, due to the difference in the resistance component between the first and second connecting conductors 7 and 9, the multilayer capacitor according to the sixth embodiment has an equivalent series resistance compared to the multilayer capacitor according to the fifth embodiment. Get smaller. (Please check the technical contents of paragraphs 0098 and 0099.)

  As described above, according to the present embodiment, the position of the first inner electrodes 33 and 34 in the stacking direction electrically connected to the first terminal electrode 3 via the lead conductor 37 and the lead conductor 47 are determined. The equivalent series resistance of the multilayer capacitor is set to a desired value by adjusting the position in the stacking direction of the second internal electrodes 42 and 44 electrically connected to the second terminal electrode 5 via Therefore, it is possible to easily and accurately control the equivalent series resistance.

  In the multilayer body 1 of the multilayer capacitor in accordance with the sixth embodiment, the first internal electrode electrically connected to the first terminal electrode 3 via the lead conductor 37 with respect to the center position M in the lamination direction. The first internal electrode 34 that is electrically connected to the first terminal electrode 3 through the lead conductor 37 is present at a position that is symmetrical to 33. In the multilayer body 1, the lead conductor 37 is located at a position symmetrical to the first internal electrode 34 electrically connected to the first terminal electrode 3 via the lead conductor 37 with respect to the center position M in the stacking direction. There is a first internal electrode 33 that is electrically connected to the first terminal electrode 3 via the. On the other hand, in the multilayer body 1 of the multilayer capacitor in accordance with the sixth embodiment, the second internal electrode electrically connected to the second terminal electrode 5 via the lead conductor 47 with respect to the center position M in the lamination direction. The second internal electrode 44 that is electrically connected to the second terminal electrode 5 through the lead conductor 47 exists at a position that is symmetric with respect to 42. In the multilayer body 1, the lead conductor 47 is located at a position symmetrical to the second internal electrode 44 that is electrically connected to the second terminal electrode 5 via the lead conductor 47 with respect to the center position M in the stacking direction. There is a second internal electrode 42 that is electrically connected to the second terminal electrode 5 via the. For this reason, even when mounting is performed with any one of the two side surfaces 1e and 1f facing the stacking direction of the stacked body 1 facing the substrate or the like, it is formed between the land patterns on the substrate or the like via the internal electrodes. The length of the current path is unlikely to change. Therefore, in the multilayer capacitor in accordance with the sixth embodiment, the equivalent series inductance is prevented from varying depending on the mounting direction.

  The first terminal electrode 3 is formed on the side surface 1 a extending in the longitudinal direction among the side surfaces parallel to the stacking direction of the rectangular parallelepiped stacked body 1, and the second terminal electrode 5 is formed in the stacking direction of the stacked body 1. Of the parallel side surfaces, the side surface 1b extends in the longitudinal direction and faces the side surface 1a on which the first terminal electrode 3 is formed. Thereby, the magnetic field generated by the current flowing through the first and second internal electrodes 31 to 36, 41 to 45 can be reduced, and the multilayer capacitor according to the sixth embodiment can reduce the equivalent series inductance. It becomes possible.

(Seventh embodiment)
With reference to FIG. 12, the structure of the multilayer capacitor in accordance with the seventh embodiment will be explained. The multilayer capacitor in accordance with the seventh embodiment includes first and second internal electrodes 31, 32, 35, 36, 41, 42, 44, 45 connected to the terminal electrodes 3, 5 through lead conductors 37, 47. This is different from the multilayer capacitor in accordance with the fifth embodiment in the number of points. FIG. 12 is an exploded perspective view of the multilayer body included in the multilayer capacitor in accordance with the seventh embodiment.

  Although not shown, the multilayer capacitor in accordance with the seventh embodiment is the same as the multilayer capacitor 1 and the first terminal electrode 3 formed in the multilayer body 1, as in the multilayer capacitor C1 in accordance with the first embodiment. A second terminal electrode 5 formed on the multilayer body 1 and first and second connection conductors 7 and 9 are provided.

  In the multilayer capacitor in accordance with the seventh embodiment, as shown in FIG. 12, four first inner electrodes 31, 32, 35, 36 out of the six first inner electrodes 31 to 36 are arranged via the lead conductor 37. Are electrically connected to the first terminal electrode 3. Since the first inner electrodes 31 to 36 are electrically connected to each other via the first connection conductor 7, the first inner electrodes 33 and 34 are also connected to the first terminal via the first connection conductor 7. It will be electrically connected to the electrode 3, and the first internal electrodes 31 to 36 will be connected in parallel. The lead conductor 37 is formed integrally with each of the first inner electrodes 31, 32, 35, 36, and faces the side surface 1 a extending in the longitudinal direction among the side surfaces parallel to the stacking direction of the multilayer body 1. 1 internal electrodes 31, 32, 35, and 36, respectively.

  Of the five second internal electrodes 41 to 45, four second internal electrodes 41, 42, 44, 45 are electrically connected to the second terminal electrode 5 through lead conductors 47. Since the second inner electrodes 41 to 45 are electrically connected to each other via the second connection conductor 9, the second inner electrode 43 is also connected to the second terminal electrode 5 via the second connection conductor 9. The second internal electrodes 41 to 45 are connected in parallel. The lead conductor 47 is formed integrally with each of the second inner electrodes 41, 42, 44, 45, and extends in the longitudinal direction among the side surfaces parallel to the stacking direction of the multilayer body 1 and faces the side surface 1 b. Extending from the second inner electrodes 41, 42, 44, 45, respectively.

  In the multilayer capacitor in accordance with the seventh embodiment, the number of first internal electrodes 31, 32, 35, 36 directly connected to the first terminal electrode 3 via the lead conductor 37 is four, and the first internal electrodes The total number of electrodes 31 to 36 is smaller. In addition, the number of second internal electrodes 41, 42, 44, 45 directly connected to the second terminal electrode 5 via the lead conductor 47 is four, which is larger than the total number of the second internal electrodes 41 to 45. It has been reduced. Therefore, the multilayer capacitor according to the seventh embodiment has an equivalent series resistance that is greater than that of a conventional multilayer capacitor in which all internal electrodes are connected to corresponding terminal electrodes via lead conductors.

  As compared with the multilayer capacitor according to the fifth embodiment, the multilayer capacitor according to the seventh embodiment includes first internal electrodes 31, 32, 35 that are directly connected to the first terminal electrode 3 via the lead conductor 37. , 36 are large, and these lead conductors 37 are connected in parallel to the first terminal electrode 3. In addition, there are many second internal electrodes 41, 42, 44, 45 that are directly connected to the second terminal electrode 5 as the lead conductor 47, and these lead conductors 47 are connected in parallel to the second terminal electrode 5. Is done. Therefore, the equivalent series resistance of the multilayer capacitor in accordance with the seventh embodiment is smaller than the equivalent series resistance of the multilayer capacitor in accordance with the fifth embodiment.

  As described above, according to the present embodiment, the number of the first inner electrodes 31, 32, 35, 36 that are electrically connected to the first terminal electrode 3 through the lead conductor 37 and the lead conductor 47 are set. By adjusting the number of second internal electrodes 41, 42, 44, 45 that are electrically connected to the second terminal electrode 5 via the respective terminals, the equivalent series resistance of the multilayer capacitor according to the seventh embodiment can be reduced. Since it is set to a desired value, the equivalent series resistance can be controlled easily and accurately.

  In the multilayer body 1 of the multilayer capacitor in accordance with the seventh embodiment, the first internal electrode that is electrically connected to the first terminal electrode 3 via the lead conductor 37 with respect to the center position M in the lamination direction. The first internal electrode 36 that is electrically connected to the first terminal electrode 3 through the lead conductor 37 is present at a position that is symmetrical to 31. In the multilayer body 1, the lead conductor 37 is located at a position symmetrical to the first internal electrode 32 electrically connected to the first terminal electrode 3 via the lead conductor 37 with respect to the center position M in the stacking direction. There is a first internal electrode 35 that is electrically connected to the first terminal electrode 3 via the. In the multilayer body 1, the lead conductor 37 is located at a position symmetrical to the first internal electrode 35 electrically connected to the first terminal electrode 3 via the lead conductor 37 with respect to the center position M in the stacking direction. There is a first internal electrode 32 that is electrically connected to the first terminal electrode 3 via the. In the multilayer body 1, the lead conductor 37 is located at a position symmetrical to the first internal electrode 36 that is electrically connected to the first terminal electrode 3 via the lead conductor 37 with respect to the center position M in the stacking direction. There is a first internal electrode 31 that is electrically connected to the first terminal electrode 3 via the.

  On the other hand, in the multilayer body 1 of the multilayer capacitor in accordance with the seventh embodiment, the second internal electrode electrically connected to the second terminal electrode 5 via the lead conductor 47 with respect to the center position M in the lamination direction. There is a second internal electrode 45 that is electrically connected to the second terminal electrode 5 via the lead conductor 47 at a position that is symmetric with respect to 41. In the multilayer body 1, the lead conductor 47 is located at a position symmetrical to the second internal electrode 42 electrically connected to the second terminal electrode 5 via the lead conductor 47 with respect to the center position M in the stacking direction. There is a second internal electrode 44 that is electrically connected to the second terminal electrode 5 via the. In the multilayer body 1, the lead conductor 47 is located at a position symmetrical to the second internal electrode 44 that is electrically connected to the second terminal electrode 5 via the lead conductor 47 with respect to the center position M in the stacking direction. There is a second internal electrode 42 that is electrically connected to the second terminal electrode 5 via the. In the multilayer body 1, the lead conductor 47 is located at a position symmetrical to the second internal electrode 45 electrically connected to the second terminal electrode 5 via the lead conductor 47 with respect to the center position M in the stacking direction. There is a second internal electrode 41 that is electrically connected to the second terminal electrode 5 via the.

  For this reason, even when mounting is performed with any one of the two side surfaces 1e and 1f facing the stacking direction of the stacked body 1 facing the substrate or the like, it is formed between the land patterns on the substrate or the like via the internal electrodes. The length of the current path is unlikely to change. Therefore, in the multilayer capacitor in accordance with the seventh embodiment, variation in equivalent series inductance depending on the mounting direction is suppressed.

  The first terminal electrode 3 is formed on the side surface 1 a extending in the longitudinal direction among the side surfaces parallel to the stacking direction of the rectangular parallelepiped stacked body 1, and the second terminal electrode 5 is formed in the stacking direction of the stacked body 1. Of the parallel side surfaces, the side surface 1b extends in the longitudinal direction and faces the side surface 1a on which the first terminal electrode 3 is formed. Thereby, the magnetic field generated by the current flowing through the first and second inner electrodes 31 to 36, 41 to 45 can be reduced, and the multilayer capacitor according to the seventh embodiment can reduce the equivalent series inductance. It becomes possible.

(Eighth embodiment)
A configuration of the multilayer capacitor in accordance with the eighth embodiment will be described with reference to FIG. The multilayer capacitor in accordance with the eighth embodiment is different from the multilayer capacitor in accordance with the fifth embodiment in that slits are formed in the first and second internal electrodes 31-36, 41-45. FIG. 13 is an exploded perspective view of the multilayer body included in the multilayer capacitor in accordance with the eighth embodiment.

  Although the multilayer capacitor according to the eighth embodiment is not shown, the multilayer capacitor 1 and the first terminal electrode 3 formed on the multilayer capacitor 1 are the same as the multilayer capacitor C1 according to the first embodiment. A second terminal electrode 5 formed on the multilayer body 1 and first and second connection conductors 7 and 9 are provided.

  In the first inner electrodes 31 to 36, slits S11 to S16 extend from the side of the connecting portion between the lead conductors 51 to 56 and the first inner electrodes 31 to 36 in the longitudinal direction of the first inner electrodes 31 to 36. Is formed. Accordingly, the slits S11 to S16 are formed in the first inner electrodes 31 to 36 such that currents flow in opposite directions in regions facing each other across the slits S11 to S16.

  In the second inner electrodes 41 to 45, slits S21 to S25 extend from the side of the connecting portion between the lead conductors 61 to 65 and the second inner electrodes 41 to 45 in the longitudinal direction of the second inner electrodes 41 to 45. Is formed. Accordingly, the slits S21 to S25 are formed in the second internal electrodes 41 to 45 so that currents flow in opposite directions in regions facing each other across the slits S21 to S25.

  In the first and second internal electrodes 31 to 36 and 41 to 45 in which the slits S11 to S16 and S21 to S25 are formed, the currents are opposite to each other in regions facing each other with the slits S11 to S16 and S21 to S25 interposed therebetween. Therefore, the magnetic field generated due to the current is canceled out. Also, the first internal electrodes 31 to 36 and the second internal electrodes 41 to 45 in which the slits are formed have the current flowing in the opposite direction when viewed in the stacking direction. Therefore, the magnetic field generated due to the current flowing through the first internal electrodes 31 to 36 and the magnetic field generated due to the current flowing through the second internal electrodes 41 to 45 are canceled out. For this reason, in the multilayer capacitor in accordance with the eighth embodiment, it is possible to reduce the equivalent series inductance.

  In the multilayer capacitor in accordance with the eighth embodiment, the number of first internal electrodes 31, 36 directly connected to the first terminal electrode 3 through the lead conductor 37 is two, and the first internal electrode 31 Is less than the total number of -36 (six in this embodiment). In addition, the number of second internal electrodes 41 and 45 directly connected to the second terminal electrode 5 via the lead conductor 47 is two, and the total number of second internal electrodes 41 to 45 (in this embodiment, Less than 5). As a result, the multilayer capacitor according to the eighth embodiment has an equivalent series resistance greater than that of a conventional multilayer capacitor in which all internal electrodes are connected to corresponding terminal electrodes via lead conductors.

  As described above, according to the present embodiment, the number of first internal electrodes 31, 36 electrically connected to the first terminal electrode 3 through the lead conductor 37 and the second through the lead conductor 47. Since the equivalent series resistance of the multilayer capacitor in accordance with the eighth embodiment is set to a desired value by adjusting the number of second internal electrodes 41 and 45 electrically connected to the terminal electrode 5, respectively. Therefore, it is possible to easily and accurately control the equivalent series resistance.

  Further, in the multilayer body 1 of the multilayer capacitor in accordance with the eighth embodiment, each first internal that is electrically connected to the first terminal electrode 3 via the lead conductor 37 with respect to the center position M in the lamination direction. First internal electrodes 36 and 31 that are electrically connected to the first terminal electrode 3 through lead conductors 37 are present at positions symmetrical to the electrodes 31 and 36, respectively. On the other hand, in the multilayer body 1 of the multilayer capacitor in accordance with the eighth embodiment, each second internal that is electrically connected to the second terminal electrode 5 via the lead conductor 47 with respect to the center position M in the lamination direction. Second internal electrodes 44 and 41 that are electrically connected to the second terminal electrode 5 through the lead conductor 47 are present at positions symmetrical to the electrodes 41 and 45, respectively. For this reason, even when mounting is performed with any one of the two side surfaces 1e and 1f facing the stacking direction of the stacked body 1 facing the substrate or the like, it is formed between the land patterns on the substrate or the like via the internal electrodes. The length of the current path is unlikely to change. Therefore, in the multilayer capacitor in accordance with the eighth embodiment, the equivalent series inductance is prevented from varying depending on the mounting direction.

  The first terminal electrode 3 is formed on the side surface 1 a extending in the longitudinal direction among the side surfaces parallel to the stacking direction of the rectangular parallelepiped stacked body 1, and the second terminal electrode 5 is formed in the stacking direction of the stacked body 1. Of the parallel side surfaces, the side surface 1b extends in the longitudinal direction and faces the side surface 1a on which the first terminal electrode 3 is formed. Thereby, the magnetic field generated by the current flowing through the first and second internal electrodes 31 to 36, 41 to 45 can be reduced, and the multilayer capacitor according to the eighth embodiment can reduce the equivalent series inductance. It becomes possible.

  Note that the slits do not have to be formed in all the internal electrodes. For example, the first and second electrodes electrically connected to the first and second terminal electrodes 3 and 5 through the lead conductors 37 and 47 are used. The internal electrodes 31, 36, 41, 45 may not be formed. However, by forming slits in the first and second internal electrodes 31, 36, 41, 45, magnetic fields generated due to current in these internal electrodes 31, 36, 41, 45 are canceled out. Therefore, it is possible to further reduce the equivalent series inductance in the multilayer capacitor.

(Ninth embodiment)
With reference to FIGS. 14 and 15, the structure of the multilayer capacitor C2 in accordance with the ninth embodiment will be explained. FIG. 14 is a perspective view of the multilayer capacitor in accordance with the ninth embodiment. FIG. 15 is an exploded perspective view of the multilayer body included in the multilayer capacitor in accordance with the ninth embodiment.

  As shown in FIG. 14, the multilayer capacitor C <b> 2 includes a multilayer body 1 and first and second terminal electrodes 3 and 5 formed on the multilayer body 1.

  The first terminal electrode 3 is formed on the side surface 1 a extending in the longitudinal direction among the side surfaces parallel to the laminating direction described later of the multilayer body 1. The second terminal electrode 5 is formed on the side surface 1b that extends in the longitudinal direction and faces the side surface 1a on which the first terminal electrode 3 is formed, among the side surfaces parallel to the below-described stacking direction of the multilayer body 1. The first terminal electrode 3 and the second terminal electrode 5 are electrically insulated from each other.

  As shown in FIG. 15, the multilayer body 1 includes a plurality (9 layers in this embodiment) of dielectric layers 11 to 18 and 22, and a plurality (4 layers in this embodiment) of first and second layers. The second inner electrodes 31 to 34 and 41 to 44 are alternately stacked. Moreover, the laminated body 1 has the side surfaces 1e and 1f which mutually oppose in the lamination direction mentioned later, and the side surfaces 1c and 1d extended in a transversal direction among the side surfaces parallel to the lamination direction. The actual multilayer capacitor C2 is integrated so that the boundaries between the dielectric layers 11 to 18 and 22 are not visible.

  Each of the first inner electrodes 31 to 34 has a substantially rectangular shape. The first internal electrodes 31 to 34 are located at a position having a predetermined interval from a side surface parallel to the stacking direction of the dielectric layers 11 to 18 and 22 in the stacked body 1 (hereinafter simply referred to as “stacking direction”). Each is formed. Openings 31 a to 34 a are formed in the first inner electrodes 31 to 34 so that the dielectric layers 11, 13, 15, and 17 are exposed. On each dielectric layer 11, 13, 15, 17, land-like internal conductors 71 to 74 are located in regions corresponding to the openings 31 a to 34 a formed in the first internal electrodes 31 to 34. . The first internal electrode 31 is adjacent to the side surface 1 e of the multilayer body 1 in the stacking direction via the dielectric layer 22.

  Each of the second inner electrodes 41 to 44 has a rectangular shape. The second internal electrodes 41 to 44 are respectively formed at positions having a predetermined interval from the side surface parallel to the stacking direction in the stacked body 1. Openings 41 a to 44 a are formed in the second inner electrodes 41 to 44 so that the dielectric layers 12, 14, 16, and 18 are exposed. On each dielectric layer 12, 14, 16, 18, land-like internal conductors 81 to 84 are located in regions corresponding to the openings 41 a to 44 a formed in the second internal electrodes 41 to 44. . The second internal electrode 44 is adjacent to the side surface 1 f of the multilayer body 1 in the stacking direction via the dielectric layer 18.

  Through-hole conductors 91a and 91b penetrating the dielectric layer 11 in the thickness direction are formed at positions corresponding to the inner conductor 81 and the inner conductor 71 in the dielectric layer 11, respectively. The through-hole conductor 91a is electrically connected to the first internal electrode 31. The through-hole conductor 91b is electrically connected to the internal conductor 71. The through-hole conductor 91a is electrically connected to the internal conductor 81 in a state where the dielectric layers 11 and 12 are laminated. The through-hole conductor 91b is electrically connected to the second internal electrode 41 in a state where the dielectric layers 11 and 12 are laminated.

  Through-hole conductors 92a and 92b penetrating the dielectric layer 12 in the thickness direction are formed at positions corresponding to the inner conductor 81 and the inner conductor 72 in the dielectric layer 12, respectively. The through-hole conductor 92a is electrically connected to the internal conductor 81. The through-hole conductor 92 b is electrically connected to the second internal electrode 41. The through-hole conductor 92a is electrically connected to the first internal electrode 32 in a state where the dielectric layers 12 and 13 are laminated. The through-hole conductor 92b is electrically connected to the internal conductor 72 in a state where the dielectric layers 12 and 13 are laminated.

  Through-hole conductors 93a and 93b penetrating the dielectric layer 13 in the thickness direction are formed at positions corresponding to the inner conductor 82 and the inner conductor 72 in the dielectric layer 13, respectively. The through-hole conductor 93a is electrically connected to the first internal electrode 32. The through-hole conductor 93 b is electrically connected to the inner conductor 72. The through-hole conductor 93a is electrically connected to the internal conductor 82 in a state where the dielectric layers 13 and 14 are laminated. The through-hole conductor 93b is electrically connected to the second internal electrode 42 in a state where the dielectric layers 13 and 14 are laminated.

  Through-hole conductors 94a and 94b penetrating the dielectric layer 14 in the thickness direction are formed at positions corresponding to the inner conductor 82 and the inner conductor 73 in the dielectric layer 14, respectively. The through-hole conductor 94a is electrically connected to the inner conductor 82. The through-hole conductor 94 b is electrically connected to the second internal electrode 42. The through-hole conductor 94a is electrically connected to the first internal electrode 33 in a state where the dielectric layers 14 and 15 are laminated. The through-hole conductor 94b is electrically connected to the internal conductor 73 in a state where the dielectric layers 14 and 15 are laminated.

  Through-hole conductors 95a and 95b penetrating the dielectric layer 15 in the thickness direction are formed at positions corresponding to the inner conductor 83 and the inner conductor 73 in the dielectric layer 15, respectively. The through-hole conductor 95a is electrically connected to the first internal electrode 33. The through-hole conductor 95b is electrically connected to the internal conductor 73. The through-hole conductor 95a is electrically connected to the internal conductor 83 in a state where the dielectric layers 15 and 16 are laminated. The through-hole conductor 95b is electrically connected to the second internal electrode 43 in a state where the dielectric layers 15 and 16 are laminated.

  Through-hole conductors 96a and 96b penetrating the dielectric layer 16 in the thickness direction are formed at positions corresponding to the inner conductor 83 and the inner conductor 74 in the dielectric layer 16, respectively. The through-hole conductor 96a is electrically connected to the inner conductor 83. The through-hole conductor 96 b is electrically connected to the second internal electrode 43. The through-hole conductor 96a is electrically connected to the first internal electrode 34 in a state where the dielectric layers 16 and 17 are laminated. The through-hole conductor 96b is electrically connected to the inner conductor 74 in a state where the dielectric layers 16 and 17 are laminated.

  Through-hole conductors 97a and 97b penetrating the dielectric layer 17 in the thickness direction are formed at positions corresponding to the inner conductor 84 and the inner conductor 74 in the dielectric layer 17, respectively. The through-hole conductor 97a is electrically connected to the first internal electrode 34. The through-hole conductor 97b is electrically connected to the inner conductor 74. The through-hole conductor 97a is electrically connected to the internal conductor 84 in a state where the dielectric layers 17 and 18 are laminated. The through-hole conductor 97b is electrically connected to the second internal electrode 44 in a state where the dielectric layers 17 and 18 are laminated.

  The through-hole conductors 91a to 97a are arranged in a substantially straight line in the laminating direction by laminating the dielectric layers 11 to 17 and are electrically connected to each other to constitute an energization path. The first inner electrodes 31 to 34 are electrically connected to each other through the through-hole conductors 91a to 97a and the inner conductors 81 to 84.

  The first internal electrode 31 is electrically connected to the first terminal electrode 3 through the lead conductor 37. As a result, the first inner electrodes 32 to 34 are also electrically connected to the first terminal electrode 3, and the first inner electrodes 31 to 34 are connected in parallel. The lead conductor 37 is formed integrally with the first internal electrode 31 and extends from the first internal electrode 31 so as to face the side surface 1 a extending in the longitudinal direction among the side surfaces parallel to the stacking direction of the multilayer body 1. ing.

  Similarly to the through-hole conductors 91a to 97a, the through-hole conductors 91b to 97b are arranged in a substantially straight line in the stacking direction and are electrically connected to each other by stacking the dielectric layers 11 to 17. The energization path is configured by The second inner electrodes 41 to 44 are electrically connected to each other through the through-hole conductors 91b to 97b and the inner conductors 71 to 74.

  The second internal electrode 44 is electrically connected to the second terminal electrode 5 through the lead conductor 47. Thereby, the second internal electrodes 41 to 43 are also electrically connected to the second terminal electrode 5, and the second internal electrodes 41 to 44 are connected in parallel. The lead conductor 47 is formed integrally with the second internal electrode 44 and extends in the longitudinal direction of the side surface parallel to the stacking direction of the multilayer body 1 and faces the side surface 1a on which the first terminal electrode 3 is formed. It extends from the second internal electrode 44 so as to face the side surface 1b.

  In the multilayer capacitor C2, the number of the first internal electrodes 31 directly connected to the first terminal electrode 3 via the lead conductor 37 is one, and the total number of the first internal electrodes 31 to 34 (in this embodiment, 4). The number of second internal electrodes 44 directly connected to the second terminal electrode 5 via the lead conductor 47 is one, and the total number of second internal electrodes 41 to 44 (in this embodiment, four). ) Is less than. Further, the through-hole conductors 91a to 97a are connected in series to the first terminal electrode 3, and the combined resistance component of the through-hole conductors 91a to 97a is relatively large. Further, the through-hole conductors 91b to 97b are also connected in series to the second terminal electrode 5, and the combined resistance component of the through-hole conductors 91b to 97b is relatively large. As a result, the multilayer capacitor C2 has a larger equivalent series resistance than a conventional multilayer capacitor in which all internal electrodes are connected to corresponding terminal electrodes via lead conductors.

  As described above, according to the present embodiment, the number of first internal electrodes 31 that are electrically connected to the first terminal electrode 3 via the lead conductor 37 and the second terminal via the lead conductor 47. By adjusting the number of second internal electrodes 44 electrically connected to the electrode 5, the equivalent series resistance of the multilayer capacitor C2 is set to a desired value, so that the equivalent series resistance can be easily controlled. And it can be performed with high accuracy.

  In the present embodiment, the first inner electrodes 31 to 34 are connected in parallel, and the second inner electrodes 41 to 44 are connected in parallel. As a result, even if the resistance values of the first internal electrodes 31 to 34 and the second internal electrodes 41 to 44 vary, there is little influence on the equivalent series resistance of the entire multilayer capacitor C2, and the equivalent series resistance It is possible to suppress a decrease in control accuracy.

  Further, in the multilayer body 1 of the multilayer capacitor C2, the first internal electrode 31 that is electrically connected to the first terminal electrode 3 via the lead conductor 37 is symmetric with respect to the center position M in the stacking direction. The second internal electrode 44 that is electrically connected to the second terminal electrode 5 through the lead conductor 47 exists at the position. On the other hand, in the multilayer body 1 of the multilayer capacitor C2, the second internal electrode 44 that is electrically connected to the second terminal electrode 5 via the lead conductor 47 is symmetric with respect to the center position M in the stacking direction. The first internal electrode 31 that is electrically connected to the first terminal electrode 3 via the lead conductor 37 exists at the position. For this reason, even when mounting is performed with any one of the two side surfaces 1e and 1f facing the stacking direction of the stacked body 1 facing the substrate or the like, it is formed between the land patterns on the substrate or the like via the internal electrodes. The length of the current path is unlikely to change. Therefore, in the multilayer capacitor C2 according to the ninth embodiment, variation in the equivalent series inductance depending on the mounting direction is suppressed.

  The first terminal electrode 3 is formed on the side surface 1 a extending in the longitudinal direction among the side surfaces parallel to the stacking direction of the rectangular parallelepiped stacked body 1, and the second terminal electrode 5 is formed in the stacking direction of the stacked body 1. Of the parallel side surfaces, the side surface 1b extends in the longitudinal direction and faces the side surface 1a on which the first terminal electrode 3 is formed. Thereby, the magnetic field generated by the current flowing through the first and second internal electrodes 31 to 34 and 41 to 44 can be reduced, and the multilayer capacitor C2 can reduce the equivalent series inductance.

(10th Embodiment)
A configuration of the multilayer capacitor in accordance with the tenth embodiment will be described with reference to FIG. The multilayer capacitor in accordance with the tenth embodiment is similar to the ninth embodiment in that the first and second internal electrodes 33, 42 connected to the terminal electrodes 3, 5 via lead conductors 37, 47 are positioned in the stacking direction. This is different from the multilayer capacitor C2 according to FIG. FIG. 16 is an exploded perspective view of the multilayer body included in the multilayer capacitor in accordance with the tenth embodiment.

  Although not shown, the multilayer capacitor in accordance with the tenth embodiment is the same as the multilayer capacitor 1 and the first terminal electrode 3 formed in the multilayer body 1, similar to the multilayer capacitor C2 according to the ninth embodiment. And a second terminal electrode 5 formed on the laminate 1.

  In the multilayer capacitor in accordance with the tenth embodiment, as shown in FIG. 16, the first inner electrode that is the third one counted down from the first inner electrode 31 among the four first inner electrodes 31 to 34. The electrode 33 is electrically connected to the first terminal electrode 3 through the lead conductor 37. As a result, the first internal electrodes 31, 32, and 34 are also electrically connected to the first terminal electrode 3, and the first internal electrodes 31 to 34 are connected in parallel. The lead conductor 37 is formed integrally with the first internal electrode 33 and extends from the first internal electrode 33 so as to face the side surface 1 a extending in the longitudinal direction among the side surfaces parallel to the stacking direction of the multilayer body 1. ing.

  Of the four second internal electrodes 41 to 44, the second second internal electrode 42 counting down from the second internal electrode 41 is electrically connected to the second terminal electrode 5 via the lead conductor 47. Connected. As a result, the second inner electrodes 41, 43, 44 are also electrically connected to the second terminal electrode 5, and the second inner electrodes 41-44 are connected in parallel. The lead conductor 47 is formed integrally with the second internal electrode 42, extends in the longitudinal direction among the side surfaces parallel to the stacking direction of the multilayer body 1, and the side surface 1 a on which the first terminal electrode 3 is formed. It extends from the second inner electrode 42 so as to face the opposing side surface 1b.

  In the multilayer capacitor in accordance with the tenth embodiment, the number of first internal electrodes 33 directly connected to the first terminal electrode 3 via the lead conductor 37 is one, and the total number of first internal electrodes 31 to 34 is one. (In the present embodiment, the number is four). The number of second internal electrodes 42 directly connected to the second terminal electrode 5 via the lead conductor 47 is one, and the total number of second internal electrodes 41 to 44 (in this embodiment, four). ) Is less than. As a result, the multilayer capacitor according to the tenth embodiment has a larger equivalent series resistance than a conventional multilayer capacitor in which all internal electrodes are connected to corresponding terminal electrodes via lead conductors.

  By the way, the resistance component of the through-hole conductors 91a to 97a is a combined resistance of the through-hole conductors 91a to 94a located on one side in the stacking direction from the first internal electrode 33 with the first internal electrode 33 as a boundary. And the combined resistance component of the through-hole conductors 95a to 97a located on the other side in the stacking direction from the first internal electrode 33. The combined resistance component of the through-hole conductors 91 a to 94 a and the combined resistance component of the through-hole conductors 95 a to 97 a are connected in parallel to the first terminal electrode 3. The resistance component of the through-hole conductors 91b to 97b is a combined resistance of the through-hole conductors 91b to 93b located on one side in the stacking direction with respect to the second internal electrode 42 with the second internal electrode 42 as a boundary. And the combined resistance component of the through-hole conductors 94b to 97b located on the other side in the stacking direction from the second internal electrode 42. The combined resistance component of the through-hole conductors 91 b to 93 b and the combined resistance component of the through-hole conductors 94 b to 97 b are connected in parallel to the second terminal electrode 5. Therefore, the multilayer capacitor according to the tenth embodiment has a lower equivalent series resistance than the multilayer capacitor C2 according to the ninth embodiment in which the through-hole conductors 91a to 97a and 91b to 97b are connected in series.

  As described above, according to the present embodiment, the position in the stacking direction of the first internal electrode 33 electrically connected to the first terminal electrode 3 via the lead conductor 37 and the lead conductor 47 are used. By adjusting the position of the second internal electrode 42 electrically connected to the second terminal electrode 5 in the stacking direction, the equivalent series resistance of the multilayer capacitor according to the tenth embodiment becomes a desired value. Since it is set, it is possible to easily and accurately control the equivalent series resistance.

  Further, in the multilayer body 1 of the multilayer capacitor in accordance with the tenth embodiment, the first internal electrode electrically connected to the first terminal electrode 3 via the lead conductor 37 with respect to the center position M in the lamination direction. A second internal electrode 42 that is electrically connected to the second terminal electrode 5 through the lead conductor 47 exists at a position that is symmetric with respect to 33. On the other hand, in the multilayer body 1 of the multilayer capacitor C2, the second internal electrode 42 that is electrically connected to the second terminal electrode 5 via the lead conductor 47 is symmetric with respect to the center position M in the stacking direction. The first internal electrode 33 that is electrically connected to the first terminal electrode 3 via the lead conductor 37 is present at the position. For this reason, even when mounting is performed with any one of the two side surfaces 1e and 1f facing the stacking direction of the stacked body 1 facing the substrate or the like, it is formed between the land patterns on the substrate or the like via the internal electrodes. The length of the current path is unlikely to change. Therefore, in the multilayer capacitor in accordance with the tenth embodiment, variation in equivalent series inductance depending on the mounting direction is suppressed.

  The first terminal electrode 3 is formed on the side surface 1 a extending in the longitudinal direction among the side surfaces parallel to the stacking direction of the rectangular parallelepiped stacked body 1, and the second terminal electrode 5 is formed in the stacking direction of the stacked body 1. Of the parallel side surfaces, the side surface 1b extends in the longitudinal direction and faces the side surface 1a on which the first terminal electrode 3 is formed. Thereby, the magnetic field generated by the current flowing through the first and second internal electrodes 31 to 34 and 41 to 44 can be reduced, and the multilayer capacitor according to the tenth embodiment can reduce the equivalent series inductance. It becomes possible.

(Eleventh embodiment)
With reference to FIG. 17, the structure of the multilayer capacitor in accordance with the eleventh embodiment will be explained. The multilayer capacitor in accordance with the eleventh embodiment is similar to the ninth embodiment in terms of the number of first and second internal electrodes 31, 34, 41, 44 connected to the terminal electrodes 3, 5 via lead conductors 37, 47. This is different from the multilayer capacitor C2 according to the embodiment. FIG. 17 is an exploded perspective view of the multilayer body included in the multilayer capacitor in accordance with the eleventh embodiment.

  Although not shown, the multilayer capacitor in accordance with the eleventh embodiment is the same as the multilayer capacitor 1 and the first terminal electrode 3 formed in the multilayer body 1 in the same manner as the multilayer capacitor C2 in accordance with the ninth embodiment. And a second terminal electrode 5 formed on the laminate 1.

  In the multilayer capacitor in accordance with the eleventh embodiment, as shown in FIG. 17, two first inner electrodes 31, 34 out of the four first inner electrodes 31 to 34 are first through the lead conductor 37. The terminal electrode 3 is electrically connected. As a result, the first internal electrodes 32 and 33 are also electrically connected to the first terminal electrode 3, and the first internal electrodes 31 to 34 are connected in parallel. The lead conductor 37 is formed integrally with each of the first internal electrodes 31, 34, and the first internal electrode faces the side surface 1 a extending in the longitudinal direction among the side surfaces parallel to the stacking direction of the multilayer body 1. 31 and 34 respectively extend.

  Of the four second inner electrodes 41 to 44, two second inner electrodes 41, 44 are electrically connected to the second terminal electrode 5 via the lead conductor 47. As a result, the second inner electrodes 42 and 43 are also electrically connected to the second terminal electrode 5, and the second inner electrodes 41 to 44 are connected in parallel. The lead conductor 47 is formed integrally with each of the second inner electrodes 41, 44, extends in the longitudinal direction on the side surface parallel to the stacking direction of the multilayer body 1, and the first terminal electrode 3 is formed. The second internal electrodes 41 and 44 extend from the side surface 1b facing the side surface 1a.

  In the multilayer capacitor in accordance with the eleventh embodiment, the number of first internal electrodes 31, 34 directly connected to the first terminal electrode 3 via the lead conductor 37 is two, and the first internal electrodes 31-34. Has been less than the total number of. Further, the number of second internal electrodes 41 and 44 that are directly connected to the second terminal electrode 5 via the lead conductor 47 is two, which is smaller than the total number of the second internal electrodes 41 to 44. . Therefore, the multilayer capacitor according to the eleventh embodiment has a larger equivalent series resistance than the conventional multilayer capacitor in which all the internal electrodes are connected to the corresponding terminal electrodes via the lead conductors.

  As compared with the multilayer capacitor C2 according to the ninth embodiment, the multilayer capacitor according to the eleventh embodiment includes the first internal electrodes 31 and 34 that are directly connected to the first terminal electrode 3 via the lead conductor 37. These lead conductors 37 are connected in parallel to the first terminal electrode 3. In addition, there are many second internal electrodes 41 and 44 that are directly connected to the second terminal electrode 5 via the lead conductor 47, and these lead conductors 47 are connected in parallel to the second terminal electrode 5. Therefore, the equivalent series resistance of the multilayer capacitor according to the eleventh embodiment is smaller than that of the multilayer capacitor C2 according to the ninth embodiment.

  As described above, according to the present embodiment, the number of first internal electrodes 31, 34 electrically connected to the first terminal electrode 3 through the lead conductor 37 and the second through the lead conductor 47. Since the equivalent series resistance of the multilayer capacitor in accordance with the eleventh embodiment is set to a desired value by adjusting the number of second internal electrodes 41 and 44 that are electrically connected to the terminal electrode 5, respectively. Therefore, it is possible to easily and accurately control the equivalent series resistance.

  Moreover, in the multilayer body 1 of the multilayer capacitor in accordance with the eleventh embodiment, the first internal electrode electrically connected to the first terminal electrode 3 via the lead conductor 37 with respect to the center position M in the lamination direction. A second internal electrode 44 that is electrically connected to the second terminal electrode 5 through the lead conductor 47 exists at a position that is symmetric with respect to 31. In the multilayer body 1, the lead conductor 47 is located at a position symmetrical to the first internal electrode 34 electrically connected to the first terminal electrode 3 via the lead conductor 37 with respect to the center position M in the stacking direction. There is a second internal electrode 41 that is electrically connected to the second terminal electrode 5 via the. On the other hand, in the multilayer body 1 of the multilayer capacitor C2, the second internal electrode 41 that is electrically connected to the second terminal electrode 5 via the lead conductor 47 is symmetric with respect to the center position M in the lamination direction. The first internal electrode 34 that is electrically connected to the first terminal electrode 3 through the lead conductor 37 exists at the position. In the multilayer body 1, the lead conductor 37 is located at a position symmetrical to the second internal electrode 44 that is electrically connected to the second terminal electrode 5 via the lead conductor 47 with respect to the center position M in the stacking direction. There is a first internal electrode 31 that is electrically connected to the first terminal electrode 3 via the. For this reason, even when mounting is performed with any one of the two side surfaces 1e and 1f facing the stacking direction of the stacked body 1 facing the substrate or the like, it is formed between the land patterns on the substrate or the like via the internal electrodes. The length of the current path is unlikely to change. Therefore, in the multilayer capacitor in accordance with the eleventh embodiment, the equivalent series inductance is prevented from varying depending on the mounting direction.

  The first terminal electrode 3 is formed on the side surface 1 a extending in the longitudinal direction among the side surfaces parallel to the stacking direction of the rectangular parallelepiped stacked body 1, and the second terminal electrode 5 is formed in the stacking direction of the stacked body 1. Of the parallel side surfaces, the side surface 1b extends in the longitudinal direction and faces the side surface 1a on which the first terminal electrode 3 is formed. Thereby, the magnetic field generated by the current flowing through the first and second inner electrodes 31 to 34 and 41 to 44 can be reduced, and the multilayer capacitor according to the eleventh embodiment can reduce the equivalent series inductance. It becomes possible.

(Twelfth embodiment)
With reference to FIG. 18, the structure of the multilayer capacitor in accordance with the twelfth embodiment will be explained. The multilayer capacitor in accordance with the twelfth embodiment differs from the multilayer capacitor C2 in accordance with the ninth embodiment in that slits are formed in the first and second internal electrodes 31-34, 41-45. FIG. 18 is an exploded perspective view of the multilayer body included in the multilayer capacitor in accordance with the twelfth embodiment.

  Although not shown, the multilayer capacitor in accordance with the twelfth embodiment is the same as the multilayer capacitor 1 and the first terminal electrode 3 formed in the multilayer body 1, similar to the multilayer capacitor C2 according to the ninth embodiment. And a second terminal electrode 5 formed on the laminate 1.

  In the first inner electrodes 31 to 34, through-hole conductors 91 a to 97 a and the first inner electrodes 31 to 34 are formed from the end sides of the first inner electrodes 31 to 34 facing the side surface 1 d of the multilayer body 1. Slits S11 to S14 are formed so as to extend to the side of the portion to which is connected. Accordingly, the slits S11 to S14 are formed in the first inner electrodes 31 to 34 so that currents flow in opposite directions in regions facing each other across the slits S11 to S14.

  In the second internal electrodes 41 to 44, through-hole conductors 91 b to 97 b and the second internal electrodes 41 to 44 are formed from the end sides of the second internal electrodes 41 to 44 facing the side surface 1 c of the multilayer body 1. Slits S21 to S24 are formed so as to extend to the side of the portion to which is connected. Therefore, the slits S21 to S24 are formed in the second inner electrodes 41 to 44 so that currents flow in opposite directions in regions facing each other across the slits S21 to S24.

  In the first and second inner electrodes 31 to 34 and 41 to 44 in which the slits S11 to S14 and S21 to S24 are formed, the currents are opposite to each other in regions facing each other with the slits S11 to S14 and S21 to S24 interposed therebetween. Therefore, the magnetic field generated due to the current is canceled out. In addition, the first internal electrodes 31 to 34 and the second internal electrodes 41 to 44 in which the slits are formed have the current flowing in the opposite direction when viewed in the stacking direction. Therefore, the magnetic field generated due to the current flowing through the first internal electrodes 31 to 34 and the magnetic field generated due to the current flowing through the second internal electrodes 41 to 44 are canceled out. For this reason, in the multilayer capacitor in accordance with the twelfth embodiment, the equivalent series inductance can be reduced.

  In the multilayer capacitor in accordance with the twelfth embodiment, the number of first internal electrodes 31 directly connected to the first terminal electrode 3 via the lead conductor 37 is one, and the first internal electrodes 31 to 34 are used. Is less than the total number (four in this embodiment). The number of second internal electrodes 44 directly connected to the second terminal electrode 5 via the lead conductor 47 is one, and the total number of second internal electrodes 41 to 44 (in this embodiment, four). ) Is less than. As a result, the multilayer capacitor according to the twelfth embodiment has an equivalent series resistance greater than that of a conventional multilayer capacitor in which all internal electrodes are connected to corresponding terminal electrodes via lead conductors.

  As described above, according to the present embodiment, the number of first internal electrodes 31 that are electrically connected to the first terminal electrode 3 via the lead conductor 37 and the second terminal via the lead conductor 47. Since the equivalent series resistance of the multilayer capacitor in accordance with the twelfth embodiment is set to a desired value by adjusting the number of second internal electrodes 44 electrically connected to the electrode 5, the equivalent series resistance Can be controlled easily and accurately.

  Further, in the multilayer body 1 of the multilayer capacitor in accordance with the twelfth embodiment, the first internal electrode electrically connected to the first terminal electrode 3 via the lead conductor 37 with respect to the center position M in the lamination direction. A second internal electrode 44 that is electrically connected to the second terminal electrode 5 through the lead conductor 47 exists at a position that is symmetric with respect to 31. On the other hand, in the multilayer body 1 of the multilayer capacitor in accordance with the twelfth embodiment, the second internal electrode electrically connected to the second terminal electrode 5 through the lead conductor 47 with respect to the center position M in the lamination direction. The first internal electrode 31 that is electrically connected to the first terminal electrode 3 through the lead conductor 37 is present at a position that is symmetrical with respect to 44. For this reason, even when mounting is performed with any one of the two side surfaces 1e and 1f facing the stacking direction of the stacked body 1 facing the substrate or the like, it is formed between the land patterns on the substrate or the like via the internal electrodes. The length of the current path is unlikely to change. Therefore, in the multilayer capacitor in accordance with the twelfth embodiment, variation in equivalent series inductance depending on the mounting direction is suppressed.

  The first terminal electrode 3 is formed on the side surface 1 a extending in the longitudinal direction among the side surfaces parallel to the stacking direction of the rectangular parallelepiped stacked body 1, and the second terminal electrode 5 is formed in the stacking direction of the stacked body 1. Of the parallel side surfaces, the side surface 1b extends in the longitudinal direction and faces the side surface 1a on which the first terminal electrode 3 is formed. Thereby, the magnetic field generated by the current flowing through the first and second internal electrodes 31 to 34 and 41 to 44 can be reduced, and the multilayer capacitor according to the twelfth embodiment can reduce the equivalent series inductance. It becomes possible.

  Note that the slits do not have to be formed in all the internal electrodes. For example, the first and second electrodes electrically connected to the first and second terminal electrodes 3 and 5 through the lead conductors 37 and 47 are used. The internal electrodes 31 and 44 may not be formed. However, by forming slits in the first and second internal electrodes 31 and 44, magnetic fields generated by currents in these internal electrodes 31 and 44 are canceled out. Therefore, it is possible to further reduce the equivalent series inductance in the multilayer capacitor.

(13th Embodiment)
The configuration of the multilayer capacitor in accordance with the thirteenth embodiment will be described with reference to FIG. In the multilayer capacitor in accordance with the thirteenth embodiment, the first internal electrode connected to the first terminal electrode and the internal electrode present at a position symmetrical with respect to the center position in the stacking direction of the multilayer body are the first The internal electrode that is an internal electrode and exists at a position that is symmetrical with respect to the center position in the stacking direction of the stacked body and the second internal electrode that is connected to the second terminal electrode is the second internal electrode This is different from the multilayer capacitor C2 according to the ninth embodiment. FIG. 19 is an exploded perspective view of the multilayer body included in the multilayer capacitor in accordance with the thirteenth embodiment.

  Although not shown, the multilayer capacitor in accordance with the thirteenth embodiment is the same as the multilayer capacitor 1 and the first terminal electrode 3 formed in the multilayer body 1, similar to the multilayer capacitor C2 according to the ninth embodiment. And a second terminal electrode 5 formed on the laminate 1.

  As shown in FIG. 19, the multilayer body 1 includes a plurality (12 layers in this embodiment) of dielectric layers 11 to 22 and a plurality (6 layers in this embodiment) of first internal electrodes 31. To 36 and a plurality of (in this embodiment, five layers) second internal electrodes 41 to 45 are alternately stacked. In an actual multilayer capacitor, integration is performed so that the boundary between the dielectric layers 11 to 22 cannot be visually recognized.

  Each of the first inner electrodes 31 to 36 has a substantially rectangular shape. The first internal electrodes 31 to 36 are respectively formed at positions having a predetermined interval from a side surface parallel to the stacking direction of the dielectric layers 11 to 22 in the stacked body 1 (hereinafter simply referred to as “stacking direction”). Has been. Openings 31 a to 36 a are formed in the first inner electrodes 31 to 36 so that the dielectric layers 11, 13, 15, 17, 19, and 21 are exposed. On each dielectric layer 11, 13, 15, 17, 19, 21, land-like inner conductors 71 to 76 are formed in regions corresponding to the openings 31 a to 36 a formed in the first inner electrodes 31 to 36. positioned. The first internal electrode 31 is adjacent to the side surface 1 e of the multilayer body 1 in the stacking direction via the dielectric layer 22. The first internal electrode 36 is adjacent to the side surface 1 f of the stacked body 1 in the stacking direction via the dielectric layer 21.

  Each of the second inner electrodes 41 to 45 has a rectangular shape. The second internal electrodes 41 to 45 are respectively formed at positions having a predetermined interval from the side surface parallel to the stacking direction in the stacked body 1. Openings 41 a to 45 a are formed in the second inner electrodes 41 to 45 so that the dielectric layers 12, 14, 16, 18, and 20 are exposed. On each dielectric layer 12, 14, 16, 18, 20, land-like internal conductors 81 to 85 are located in regions corresponding to the openings 41 a to 45 a formed in the second internal electrodes 41 to 45. ing.

  The through-hole conductors 91a to 97a are arranged substantially linearly in the stacking direction and are electrically connected to each other by stacking the dielectric layers 11 to 17 as in the multilayer capacitor C2 according to the ninth embodiment. Yes. The through-hole conductors 91b to 97b are also arranged substantially linearly in the stacking direction by the dielectric layers 11 to 17 being stacked, and are electrically connected to each other.

  Furthermore, in the multilayer capacitor in accordance with the thirteenth embodiment, dielectric layers 18 to 21 are laminated, and through-hole conductors 98a to 100a and 98b to 100b are provided on a substantially straight line.

  That is, through-hole conductors 98a and 98b penetrating the dielectric layer 18 in the thickness direction are formed at positions corresponding to the inner conductor 84 and the inner conductor 75 in the dielectric layer 18, respectively. The through-hole conductor 98a is electrically connected to the inner conductor 84. The through-hole conductor 98 b is electrically connected to the second internal electrode 44. The through-hole conductor 98a is electrically connected to the first internal electrode 35 in a state where the dielectric layers 18 and 19 are laminated. The through-hole conductor 98b is electrically connected to the inner conductor 75 in a state where the dielectric layers 18 and 19 are laminated.

  Through-hole conductors 99a and 99b penetrating the dielectric layer 19 in the thickness direction are formed at positions corresponding to the inner conductor 85 and the inner conductor 75 in the dielectric layer 19, respectively. The through-hole conductor 99a is electrically connected to the first internal electrode 35. The through-hole conductor 99b is electrically connected to the inner conductor 75. The through-hole conductor 99a is electrically connected to the internal conductor 85 in a state where the dielectric layers 19 and 20 are laminated. The through-hole conductor 99b is electrically connected to the second internal electrode 45 in a state where the dielectric layers 19 and 20 are laminated.

  Through-hole conductors 100a and 100b penetrating the dielectric layer 20 in the thickness direction are formed at positions corresponding to the inner conductor 85 and the inner conductor 76 in the dielectric layer 20, respectively. The through-hole conductor 100a is electrically connected to the internal conductor 85. The through-hole conductor 100b is electrically connected to the second internal electrode 45. The through-hole conductor 100a is electrically connected to the first internal electrode 36 in a state where the dielectric layers 20 and 21 are laminated. The through-hole conductor 100b is electrically connected to the inner conductor 76 in a state where the dielectric layers 20 and 21 are laminated.

  The through-hole conductors 91a to 100a are arranged in a substantially straight line in the stacking direction when the dielectric layers 11 to 20 are stacked, and are electrically connected to each other to form an energization path. The first inner electrodes 31 to 36 are electrically connected to each other through the through-hole conductors 91a to 100a and the inner conductors 81 to 85.

  The first inner electrodes 31 and 36 are electrically connected to the first terminal electrode 3 through the lead conductor 37. As a result, the first internal electrodes 32 to 35 are also electrically connected to the first terminal electrode 3, and the first internal electrodes 31 to 36 are connected in parallel. The lead conductor 37 is formed integrally with the first inner electrodes 31, 36, and faces the side surface 1 a extending in the longitudinal direction among the side surfaces parallel to the stacking direction of the multilayer body 1. , Extending from 36.

  Similarly to the through-hole conductors 91a to 100a, the through-hole conductors 91b to 100b are also arranged substantially linearly in the stacking direction by being laminated with the dielectric layers 11 to 20, and are electrically connected to each other. The energization path is configured by The second inner electrodes 41 to 45 are electrically connected to each other through the through-hole conductors 91b to 100b and the inner conductors 71 to 76.

  The second inner electrodes 41 and 45 are electrically connected to the second terminal electrode 5 through the lead conductor 47. Thereby, the second inner electrodes 42 to 44 are also electrically connected to the second terminal electrode 5, and the second inner electrodes 41 to 45 are connected in parallel. The lead conductor 47 is formed integrally with the second inner electrodes 41, 45, extends in the longitudinal direction among the side surfaces parallel to the stacking direction of the multilayer body 1, and the side surface 1 a on which the first terminal electrode 3 is formed. It extends from the second internal electrodes 41 and 45 so as to face the side surface 1b facing each other.

  In the multilayer capacitor in accordance with the thirteenth embodiment, the number of first internal electrodes 31, 36 that are directly connected to the first terminal electrode 3 via the lead conductor 37 is two, and the first internal electrodes 31-36. Is less than the total number (six in this embodiment). In addition, the number of second internal electrodes 41 and 45 directly connected to the second terminal electrode 5 via the lead conductor 47 is two, and the total number of second internal electrodes 41 to 45 (in this embodiment, Less than 5). Therefore, the multilayer capacitor according to the thirteenth embodiment has an equivalent series resistance that is greater than that of a conventional multilayer capacitor in which all internal electrodes are connected to corresponding terminal electrodes via lead conductors.

  As described above, according to the present embodiment, the number of first internal electrodes 31, 36 electrically connected to the first terminal electrode 3 through the lead conductor 37 and the second through the lead conductor 47. Since the equivalent series resistance of the multilayer capacitor in accordance with the thirteenth embodiment is set to a desired value by adjusting the number of second internal electrodes 41, 45 electrically connected to the terminal electrode 5, respectively. Therefore, it is possible to easily and accurately control the equivalent series resistance.

  In the present embodiment, the first internal electrodes 31 to 36 are connected in parallel, and the second internal electrodes 41 to 45 are connected in parallel. As a result, even if the resistance values of the first internal electrodes 31 to 36 and the second internal electrodes 41 to 45 vary, there is little influence on the equivalent series resistance of the entire multilayer capacitor according to the thirteenth embodiment. Therefore, it is possible to suppress a reduction in accuracy of control of the equivalent series resistance.

  Further, in the multilayer body 1 of the multilayer capacitor in accordance with the thirteenth embodiment, the first internal electrode electrically connected to the first terminal electrode 3 via the lead conductor 37 with respect to the center position M in the lamination direction. The first internal electrode 36 that is electrically connected to the first terminal electrode 3 through the lead conductor 37 is present at a position that is symmetrical to 31. In the multilayer body 1, the lead conductor 37 is located at a position symmetrical to the first internal electrode 36 that is electrically connected to the first terminal electrode 3 via the lead conductor 37 with respect to the center position M in the stacking direction. There is a first internal electrode 31 that is electrically connected to the first terminal electrode 3 via the. On the other hand, in the multilayer body 1 of the multilayer capacitor in accordance with the thirteenth embodiment, the second internal electrode electrically connected to the second terminal electrode 5 through the lead conductor 47 with respect to the center position M in the lamination direction. There is a second internal electrode 45 that is electrically connected to the second terminal electrode 5 via the lead conductor 47 at a position that is symmetric with respect to 41. In the multilayer body 1, the lead conductor 47 is located at a position symmetrical to the second internal electrode 45 electrically connected to the second terminal electrode 5 via the lead conductor 47 with respect to the center position M in the stacking direction. There is a second internal electrode 41 that is electrically connected to the second terminal electrode 5 via the. For this reason, even when mounting is performed with any one of the two side surfaces 1e and 1f facing the stacking direction of the stacked body 1 facing the substrate or the like, it is formed between the land patterns on the substrate or the like via the internal electrodes. The length of the current path is unlikely to change. Therefore, in the multilayer capacitor in accordance with the thirteenth embodiment, variation in equivalent series inductance depending on the mounting direction is suppressed.

  The first terminal electrode 3 is formed on the side surface 1 a extending in the longitudinal direction among the side surfaces parallel to the stacking direction of the rectangular parallelepiped stacked body 1, and the second terminal electrode 5 is formed in the stacking direction of the stacked body 1. Of the parallel side surfaces, the side surface 1b extends in the longitudinal direction and faces the side surface 1a on which the first terminal electrode 3 is formed. Thus, the magnetic field generated by the current flowing through the first and second internal electrodes 31 to 36, 41 to 45 can be reduced, and the multilayer capacitor according to the thirteenth embodiment can reduce the equivalent series inductance. It becomes possible.

(14th Embodiment)
A configuration of the multilayer capacitor in accordance with the fourteenth embodiment will be described with reference to FIG. The multilayer capacitor in accordance with the fourteenth embodiment is connected to the second terminal electrode 5 via the first inner electrodes 33 and 34 connected to the first terminal electrode 3 via the lead conductor 37 and the lead conductor 47. This is different from the multilayer capacitor in accordance with the thirteenth embodiment in that the second internal electrodes 42, 44 are positioned in the multilayer direction. FIG. 20 is an exploded perspective view of the multilayer body included in the multilayer capacitor in accordance with the fourteenth embodiment.

  Although not shown in the multilayer capacitor according to the fourteenth embodiment, the multilayer body 1 and the first terminal electrode 3 formed on the multilayer body 1 are the same as the multilayer capacitor C2 according to the ninth embodiment. And a second terminal electrode 5 formed on the laminate 1.

  In the multilayer capacitor in accordance with the fourteenth embodiment, as shown in FIG. 20, the first inner electrode 33, which is the third from the top among the six first inner electrodes 31 to 36, and the fourth from the top, The first inner electrode 34 is electrically connected to the first terminal electrode 3 through the lead conductor 37. As a result, the first inner electrodes 31, 32, 35, and 36 are also electrically connected to the first terminal electrode 3, and the first inner electrodes 31 to 36 are connected in parallel. The lead conductor 37 is formed integrally with the first inner electrodes 33, 34, and faces the side surface 1 a extending in the longitudinal direction among the side surfaces parallel to the stacking direction of the multilayer body 1. , 34.

  In the multilayer capacitor in accordance with the fourteenth embodiment, as shown in FIG. 20, the second internal electrode 42 that is the second from the top among the five second internal electrodes 41 to 45 and the fourth from the top, The second inner electrode 44 is electrically connected to the second terminal electrode 5 through the lead conductor 47. Accordingly, the second internal electrodes 41, 43, 45 are also electrically connected to the second terminal electrode 5, and the second internal electrodes 41 to 45 are connected in parallel. The lead conductor 47 is formed integrally with the second inner electrodes 42, 44, and extends in the longitudinal direction among the side surfaces parallel to the stacking direction of the multilayer body 1 and faces the side surface 1b facing the side surface 1a. Extending from the second internal electrodes 42, 44.

  In the multilayer capacitor in accordance with the fourteenth embodiment, the number of first internal electrodes 33, 34 that are directly connected to the first terminal electrode 3 via the lead conductor 37 is two, and the first internal electrodes 31-36. Is less than the total number (six in this embodiment). Further, the number of second internal electrodes 42 and 44 directly connected to the second terminal electrode 5 through the lead conductor 47 is two, and the total number of second internal electrodes 41 to 45 (in this embodiment, Less than 5). As a result, the multilayer capacitor according to the fourteenth embodiment has an equivalent series resistance greater than that of a conventional multilayer capacitor in which all internal electrodes are connected to corresponding terminal electrodes via lead conductors.

  By the way, paying attention to the first terminal electrode 3, the multilayer capacitor according to the fourteenth embodiment has a resistance component of the through-hole conductors 91a to 100a as compared with the multilayer capacitor according to the thirteenth embodiment. The connection method is different. That is, in the multilayer capacitor in accordance with the thirteenth embodiment, the resistance components of the through-hole conductors 91a to 100a are connected in series to the first internal electrodes 31 and 36, respectively. On the other hand, in the multilayer capacitor in accordance with the fourteenth embodiment, the resistance components of the through-hole conductors 91a to 100a are divided with respect to the first internal electrodes 33 and 34, respectively. 3 are connected in parallel. Focusing on the second terminal electrode 5, the multilayer capacitor according to the fourteenth embodiment has a resistance component of the through-hole conductors 91 b to 100 b as compared with the multilayer capacitor according to the thirteenth embodiment. The connection method is different. That is, in the multilayer capacitor in accordance with the thirteenth embodiment, the resistance components of the through-hole conductors 91b to 100b are connected in series to the second internal electrodes 41 and 45, respectively. On the other hand, in the multilayer capacitor in accordance with the fourteenth embodiment, the resistance components of the through-hole conductors 91b to 100b are divided with the second internal electrodes 42 and 44 as boundaries, and these resistance components are the second terminal electrodes. 5 are connected in parallel.

  Therefore, due to the difference in resistance components of the through-hole conductors 91a to 100a and 91b to 100b, the multilayer capacitor according to the fourteenth embodiment has a smaller equivalent series resistance than the multilayer capacitor according to the thirteenth embodiment. Become. (Please check the technical contents of paragraphs 0198 and 0199.)

  As described above, according to the present embodiment, the position of the first inner electrodes 33 and 34 in the stacking direction electrically connected to the first terminal electrode 3 via the lead conductor 37 and the lead conductor 47 are determined. The equivalent series resistance of the multilayer capacitor is set to a desired value by adjusting the position in the stacking direction of the second internal electrodes 42 and 44 electrically connected to the second terminal electrode 5 via Therefore, it is possible to easily and accurately control the equivalent series resistance.

  Further, in the multilayer body 1 of the multilayer capacitor in accordance with the fourteenth embodiment, the first internal electrode that is electrically connected to the first terminal electrode 3 via the lead conductor 37 with respect to the center position M in the stacking direction. The first internal electrode 34 that is electrically connected to the first terminal electrode 3 through the lead conductor 37 is present at a position that is symmetrical to 33. In the multilayer body 1, the lead conductor 37 is located at a position symmetrical to the first internal electrode 34 electrically connected to the first terminal electrode 3 via the lead conductor 37 with respect to the center position M in the stacking direction. There is a first internal electrode 33 that is electrically connected to the first terminal electrode 3 via the. On the other hand, in the multilayer body 1 of the multilayer capacitor in accordance with the fourteenth embodiment, the second internal electrode electrically connected to the second terminal electrode 5 through the lead conductor 47 with respect to the center position M in the lamination direction. The second internal electrode 44 that is electrically connected to the second terminal electrode 5 through the lead conductor 47 exists at a position that is symmetric with respect to 42. In the multilayer body 1, the lead conductor 47 is located at a position symmetrical to the second internal electrode 44 that is electrically connected to the second terminal electrode 5 via the lead conductor 47 with respect to the center position M in the stacking direction. There is a second internal electrode 42 that is electrically connected to the second terminal electrode 5 via the. For this reason, even when mounting is performed with any one of the two side surfaces 1e and 1f facing the stacking direction of the stacked body 1 facing the substrate or the like, it is formed between the land patterns on the substrate or the like via the internal electrodes. The length of the current path is unlikely to change. Therefore, in the multilayer capacitor in accordance with the fourteenth embodiment, variation in equivalent series inductance depending on the mounting direction is suppressed.

  The first terminal electrode 3 is formed on the side surface 1 a extending in the longitudinal direction among the side surfaces parallel to the stacking direction of the rectangular parallelepiped stacked body 1, and the second terminal electrode 5 is formed in the stacking direction of the stacked body 1. Of the parallel side surfaces, the side surface 1b extends in the longitudinal direction and faces the side surface 1a on which the first terminal electrode 3 is formed. Thereby, the magnetic field generated by the current flowing through the first and second internal electrodes 31 to 36, 41 to 45 can be reduced, and the multilayer capacitor according to the fourteenth embodiment can reduce the equivalent series inductance. It becomes possible.

(Fifteenth embodiment)
With reference to FIG. 21, the structure of the multilayer capacitor in accordance with the fifteenth embodiment will be explained. The multilayer capacitor in accordance with the fifteenth embodiment includes first and second internal electrodes 31, 32, 35, 36, 41, 42, 44, 45 connected to the terminal electrodes 3, 5 via lead conductors 37, 47. This differs from the multilayer capacitor in accordance with the thirteenth embodiment. FIG. 21 is an exploded perspective view of the multilayer body included in the multilayer capacitor in accordance with the fifteenth embodiment.

  Although not shown, the multilayer capacitor in accordance with the fifteenth embodiment is the same as the multilayer capacitor 1 and the first terminal electrode 3 formed in the multilayer body 1, similar to the multilayer capacitor C2 according to the ninth embodiment. And a second terminal electrode 5 formed on the laminate 1.

  In the multilayer capacitor in accordance with the fifteenth embodiment, as shown in FIG. 21, four first inner electrodes 31, 32, 35, 36 among the six first inner electrodes 31 to 36 are arranged via the lead conductor 37. Are electrically connected to the first terminal electrode 3. Since the first inner electrodes 31 to 36 are electrically connected to each other via the first connection conductor 7, the first inner electrodes 33 and 34 are also connected to the first terminal via the first connection conductor 7. It will be electrically connected to the electrode 3, and the first internal electrodes 31 to 36 will be connected in parallel. The lead conductor 37 is formed integrally with each of the first inner electrodes 31, 32, 35, 36, and faces the side surface 1 a extending in the longitudinal direction among the side surfaces parallel to the stacking direction of the multilayer body 1. 1 internal electrodes 31, 32, 35, and 36, respectively.

  Of the five second internal electrodes 41 to 45, four second internal electrodes 41, 42, 44, 45 are electrically connected to the second terminal electrode 5 through lead conductors 47. Since the second inner electrodes 41 to 45 are electrically connected to each other via the second connection conductor 9, the second inner electrode 43 is also connected to the second terminal electrode 5 via the second connection conductor 9. The second internal electrodes 41 to 45 are connected in parallel. The lead conductor 47 is formed integrally with each of the second inner electrodes 41, 42, 44, 45, and extends in the longitudinal direction among the side surfaces parallel to the stacking direction of the multilayer body 1 and faces the side surface 1 b. Extending from the second inner electrodes 41, 42, 44, 45, respectively.

  In the multilayer capacitor in accordance with the fifteenth embodiment, the number of first internal electrodes 31, 32, 35, 36 directly connected to the first terminal electrode 3 via the lead conductor 37 is four, and the first internal electrodes The total number of electrodes 31 to 36 is smaller. In addition, the number of second internal electrodes 41, 42, 44, 45 directly connected to the second terminal electrode 5 via the lead conductor 47 is four, which is larger than the total number of the second internal electrodes 41 to 45. It has been reduced. Therefore, the multilayer capacitor in accordance with the fifteenth embodiment has a larger equivalent series resistance than a conventional multilayer capacitor in which all internal electrodes are connected to corresponding terminal electrodes via lead conductors.

  The multilayer capacitor in accordance with the fifteenth embodiment is compared with the multilayer capacitor in accordance with the thirteenth embodiment with the first internal electrodes 31, 32, 35 connected directly to the first terminal electrode 3 via the lead conductor 37. , 36 are large, and these lead conductors 37 are connected in parallel to the first terminal electrode 3. Further, the multilayer capacitor in accordance with the fifteenth embodiment has the second internal electrodes 41, 42 that are directly connected to the second terminal electrode 5 through the lead conductor 47, as compared with the multilayer capacitor in accordance with the thirteenth embodiment. , 44, 45 are large, and these lead conductors 47 are connected in parallel to the second terminal electrode 5. Therefore, the equivalent series resistance of the multilayer capacitor in accordance with the fifteenth embodiment is smaller than the equivalent series resistance of the multilayer capacitor in accordance with the thirteenth embodiment.

  As described above, according to the present embodiment, the number of the first inner electrodes 31, 32, 35, 36 that are electrically connected to the first terminal electrode 3 through the lead conductor 37 and the lead conductor 47 are set. By adjusting the number of second internal electrodes 41, 42, 44, 45 that are electrically connected to the second terminal electrode 5 through the equivalent, the equivalent series resistance of the multilayer capacitor in accordance with the fifteenth embodiment is reduced. Since it is set to a desired value, the equivalent series resistance can be controlled easily and accurately.

  Further, in the multilayer body 1 of the multilayer capacitor in accordance with the fifteenth embodiment, the first internal electrode electrically connected to the first terminal electrode 3 via the lead conductor 37 with respect to the center position M in the lamination direction. The first internal electrode 36 that is electrically connected to the first terminal electrode 3 through the lead conductor 37 is present at a position that is symmetrical to 31. In the multilayer body 1, the lead conductor 37 is located at a position symmetrical to the first internal electrode 32 electrically connected to the first terminal electrode 3 via the lead conductor 37 with respect to the center position M in the stacking direction. There is a first internal electrode 35 that is electrically connected to the first terminal electrode 3 via the. In the multilayer body 1, the lead conductor 37 is located at a position symmetrical to the first internal electrode 35 electrically connected to the first terminal electrode 3 via the lead conductor 37 with respect to the center position M in the stacking direction. There is a first internal electrode 32 that is electrically connected to the first terminal electrode 3 via the. In the multilayer body 1, the lead conductor 37 is located at a position symmetrical to the first internal electrode 36 that is electrically connected to the first terminal electrode 3 via the lead conductor 37 with respect to the center position M in the stacking direction. There is a first internal electrode 31 that is electrically connected to the first terminal electrode 3 via the.

  On the other hand, in the multilayer body 1 of the multilayer capacitor in accordance with the fifteenth embodiment, the second internal electrode electrically connected to the second terminal electrode 5 through the lead conductor 47 with respect to the center position M in the lamination direction. There is a second internal electrode 45 that is electrically connected to the second terminal electrode 5 via the lead conductor 47 at a position that is symmetric with respect to 41. In the multilayer body 1, the lead conductor 47 is located at a position symmetrical to the second internal electrode 42 electrically connected to the second terminal electrode 5 via the lead conductor 47 with respect to the center position M in the stacking direction. There is a second internal electrode 44 that is electrically connected to the second terminal electrode 5 via the. In the multilayer body 1, the lead conductor 47 is located at a position symmetrical to the second internal electrode 44 that is electrically connected to the second terminal electrode 5 via the lead conductor 47 with respect to the center position M in the stacking direction. There is a second internal electrode 42 that is electrically connected to the second terminal electrode 5 via the. In the multilayer body 1, the lead conductor 47 is located at a position symmetrical to the second internal electrode 45 electrically connected to the second terminal electrode 5 via the lead conductor 47 with respect to the center position M in the stacking direction. There is a second internal electrode 41 that is electrically connected to the second terminal electrode 5 via the.

  For this reason, even when mounting is performed with any one of the two side surfaces 1e and 1f facing the stacking direction of the stacked body 1 facing the substrate or the like, it is formed between the land patterns on the substrate or the like via the internal electrodes. The length of the current path is unlikely to change. Therefore, in the multilayer capacitor in accordance with the fifteenth embodiment, variation in equivalent series inductance depending on the mounting direction is suppressed.

  The first terminal electrode 3 is formed on the side surface 1 a extending in the longitudinal direction among the side surfaces parallel to the stacking direction of the rectangular parallelepiped stacked body 1, and the second terminal electrode 5 is formed in the stacking direction of the stacked body 1. Of the parallel side surfaces, the side surface 1b extends in the longitudinal direction and faces the side surface 1a on which the first terminal electrode 3 is formed. Thereby, the magnetic field generated by the current flowing through the first and second internal electrodes 31 to 36, 41 to 45 can be reduced, and the multilayer capacitor according to the fifteenth embodiment can reduce the equivalent series inductance. It becomes possible.

(Sixteenth embodiment)
With reference to FIG. 22, the structure of the multilayer capacitor in accordance with the sixteenth embodiment will be explained. The multilayer capacitor in accordance with the sixteenth embodiment is different from the multilayer capacitor in accordance with the thirteenth embodiment in that slits are formed in the first and second internal electrodes 31-36, 41-45. FIG. 22 is an exploded perspective view of the multilayer body included in the multilayer capacitor in accordance with the sixteenth embodiment.

  Although the illustration of the multilayer capacitor in accordance with the sixteenth embodiment is omitted, the multilayer body 1 and the first terminal electrode 3 formed in the multilayer body 1 are the same as the multilayer capacitor C2 in accordance with the ninth embodiment. And a second terminal electrode 5 formed on the laminate 1.

  In the first internal electrodes 31 to 36, through-hole conductors 91 a to 100 a and the first internal electrodes 31 to 36 from the end sides of the first internal electrodes 31 to 36 facing the side surface 1 d of the multilayer body 1. Slits S11 to S16 are formed so as to extend to the side of the portion to which is connected. Accordingly, the slits S11 to S16 are formed in the first inner electrodes 31 to 36 such that currents flow in opposite directions in regions facing each other across the slits S11 to S16.

  In the second inner electrodes 41 to 45, through-hole conductors 91 b to 100 b and the second inner electrodes 41 to 45 are formed from the end sides of the second inner electrodes 41 to 45 facing the side surface 1 c of the multilayer body 1. Slits S21 to S25 are formed so as to extend to the side of the portion to be connected. Accordingly, the slits S21 to S25 are formed in the second internal electrodes 41 to 45 so that currents flow in opposite directions in regions facing each other across the slits S21 to S25.

  In the first and second internal electrodes 31 to 36 and 41 to 45 in which the slits S11 to S16 and S21 to S25 are formed, the currents are opposite to each other in regions facing each other with the slits S11 to S16 and S21 to S25 interposed therebetween. Therefore, the magnetic field generated due to the current is canceled out. Also, the first internal electrodes 31 to 36 and the second internal electrodes 41 to 45 in which the slits are formed have the current flowing in the opposite direction when viewed in the stacking direction. Therefore, the magnetic field generated due to the current flowing through the first internal electrodes 31 to 36 and the magnetic field generated due to the current flowing through the second internal electrodes 41 to 45 are canceled out. For this reason, in the multilayer capacitor in accordance with the sixteenth embodiment, it is possible to reduce the equivalent series inductance.

  In the multilayer capacitor in accordance with the sixteenth embodiment, the number of first internal electrodes 31, 36 directly connected to the first terminal electrode 3 through the lead conductor 37 is two, and the first internal electrode 31 Is less than the total number of -36 (six in this embodiment). In addition, the number of second internal electrodes 41 and 45 directly connected to the second terminal electrode 5 via the lead conductor 47 is two, and the total number of second internal electrodes 41 to 45 (in this embodiment, Less than 5). As a result, the multilayer capacitor according to the sixteenth embodiment has an equivalent series resistance greater than that of a conventional multilayer capacitor in which all internal electrodes are connected to corresponding terminal electrodes via lead conductors.

  As described above, according to the present embodiment, the number of first internal electrodes 31, 36 electrically connected to the first terminal electrode 3 through the lead conductor 37 and the second through the lead conductor 47. Since the equivalent series resistance of the multilayer capacitor in accordance with the sixteenth embodiment is set to a desired value by adjusting the number of second internal electrodes 41, 45 electrically connected to the terminal electrode 5, respectively. Therefore, it is possible to easily and accurately control the equivalent series resistance.

  Further, in the multilayer body 1 of the multilayer capacitor in accordance with the sixteenth embodiment, each first inner part electrically connected to the first terminal electrode 3 via the lead conductor 37 with respect to the center position M in the lamination direction. First internal electrodes 36 and 31 that are electrically connected to the first terminal electrode 3 through lead conductors 37 are present at positions symmetrical to the electrodes 31 and 36, respectively. On the other hand, in the multilayer body 1 of the multilayer capacitor in accordance with the sixteenth embodiment, each second internal electrode electrically connected to the second terminal electrode 5 via the lead conductor 47 with respect to the center position M in the lamination direction. Second internal electrodes 44 and 41 that are electrically connected to the second terminal electrode 5 through the lead conductor 47 are present at positions symmetrical to the electrodes 41 and 45, respectively. For this reason, even when mounting is performed with any one of the two side surfaces 1e and 1f facing the stacking direction of the stacked body 1 facing the substrate or the like, it is formed between the land patterns on the substrate or the like via the internal electrodes. The length of the current path is unlikely to change. Therefore, in the multilayer capacitor in accordance with the sixteenth embodiment, variation in equivalent series inductance depending on the mounting direction is suppressed.

  The first terminal electrode 3 is formed on the side surface 1 a extending in the longitudinal direction among the side surfaces parallel to the stacking direction of the rectangular parallelepiped stacked body 1, and the second terminal electrode 5 is formed in the stacking direction of the stacked body 1. Of the parallel side surfaces, the side surface 1b extends in the longitudinal direction and faces the side surface 1a on which the first terminal electrode 3 is formed. Thereby, the magnetic field generated by the current flowing through the first and second internal electrodes 31 to 36, 41 to 45 can be reduced, and the multilayer capacitor according to the sixteenth embodiment can reduce the equivalent series inductance. It becomes possible.

  Note that the slits do not have to be formed in all the internal electrodes. For example, the first and second electrodes electrically connected to the first and second terminal electrodes 3 and 5 through the lead conductors 37 and 47 are used. The internal electrodes 31, 36, 41, 45 may not be formed. However, by forming slits in the first and second internal electrodes 31, 36, 41, 45, magnetic fields generated due to current in these internal electrodes 31, 36, 41, 45 are canceled out. Therefore, it is possible to further reduce the equivalent series inductance in the multilayer capacitor.

  In the first to sixteenth embodiments, by adjusting at least one of the number of internal electrodes directly connected to the terminal electrodes 3 and 5 via the lead conductors 37 and 47 and the position in the stacking direction, The equivalent series resistance of the multilayer capacitor is set to a desired value. As a result, it is possible to easily and accurately control the equivalent series resistance of each multilayer capacitor.

  The adjustment of the number of the first internal electrodes 31 to 36 described above can be performed within a range of one or more and one or less than the total number of the first internal electrodes 31 to 36. The adjustment of the number of the second inner electrodes 41 to 45 described above can be performed in a range of one or more and one or less than the total number of the second inner electrodes 41 to 45. The number of first internal electrodes directly connected to the terminal electrode 3 via the lead conductor 37 and the number of second internal electrodes directly connected to the terminal electrode 5 via the lead conductor 47 may be different. Good.

  Furthermore, the number of the connecting conductors 7 and 9 or the through-hole conductors 91a to 100a and 91b to 100b may be adjusted so that the equivalent series resistance of each multilayer capacitor is set to a desired value. In this case, the equivalent series resistance of each multilayer capacitor can be controlled with higher accuracy.

  An example of adjusting the number of connection conductors 7 and 9 is shown in FIGS. In the multilayer capacitor shown in FIG. 23 and FIG. 24, the number of the first and second connection conductors 7 and 9 in the multilayer capacitor according to the first embodiment is set to two, so that the equivalent series resistance is desired. Is set to the value of FIG. 23 is a perspective view of a modification of the multilayer capacitor in accordance with the first embodiment. FIG. 24 is an exploded perspective view of the multilayer body included in the modification of the multilayer capacitor in accordance with the first embodiment. As shown in FIG. 23, the modification of the multilayer capacitor in accordance with the first embodiment includes two first and second connection conductors 7 and 9, respectively. As shown in FIG. 24, the first inner electrodes 31 to 34 each have two lead conductors 51 to 54 connected to the connection conductor 7. Therefore, the first inner electrodes 31 to 34 are electrically connected to each other through the two energization paths, and the second inner electrodes 41 to 45 are also electrically connected to each other through the two energization paths. .

  A plurality of connection conductors 7 and 9 in the multilayer capacitors according to the second to eighth embodiments other than the multilayer capacitor according to the first embodiment may be set. FIG. 25 is an exploded perspective view of a modification of the multilayer capacitor in accordance with the fifth embodiment. In the modification of the multilayer capacitor in accordance with the fifth embodiment shown in FIG. 25, the number of first and second connection conductors 7 and 9 is set to two.

  Although the preferred embodiments of the present invention have been described in detail above, the present invention is not limited to the above-described embodiments and modifications. For example, the number of stacked dielectric layers 11 to 22 and the number of stacked first and second internal electrodes 31 to 36 and 41 to 45 are not limited to the numbers described in the above-described embodiments. Further, the number of internal electrodes directly connected to the terminal electrodes 3 and 5 via the lead conductors 37 and 47 and the positions in the stacking direction are not limited to the numbers and positions described in the above-described embodiments. The first and second internal electrodes may be directly connected to the first and second connection conductors without passing through the lead conductor.

1 is a perspective view of a multilayer capacitor according to a first embodiment. FIG. 3 is an exploded perspective view of the multilayer body included in the multilayer capacitor in accordance with the first embodiment. It is a figure for demonstrating the state which mounts the multilayer capacitor which concerns on 1st Embodiment on a board | substrate. It is the figure which represented typically the cross-sectional structure of the multilayer capacitor based on 1st Embodiment mounted in the board | substrate. It is a disassembled perspective view of the laminated body contained in the multilayer capacitor which concerns on 2nd Embodiment. It is a disassembled perspective view of the laminated body contained in the multilayer capacitor which concerns on 3rd Embodiment. It is a disassembled perspective view of the laminated body contained in the multilayer capacitor which concerns on 4th Embodiment. It is a disassembled perspective view of the multilayer body contained in the modification of the multilayer capacitor which concerns on 4th Embodiment. It is a disassembled perspective view of the multilayer body included in the multilayer capacitor in accordance with the fifth embodiment. It is the figure which represented typically the cross-sectional structure of the multilayer capacitor based on 5th Embodiment mounted in the board | substrate. It is a disassembled perspective view of the multilayer body included in the multilayer capacitor in accordance with the sixth embodiment. It is a disassembled perspective view of the multilayer body included in the multilayer capacitor in accordance with the seventh embodiment. It is a disassembled perspective view of the multilayer body included in the multilayer capacitor in accordance with the eighth embodiment. It is a perspective view of the multilayer capacitor concerning a 9th embodiment. It is a disassembled perspective view of the multilayer body included in the multilayer capacitor in accordance with the ninth embodiment. It is a disassembled perspective view of the multilayer body included in the multilayer capacitor in accordance with the tenth embodiment. It is a disassembled perspective view of the multilayer body included in the multilayer capacitor in accordance with the eleventh embodiment. It is a disassembled perspective view of the laminated body contained in the multilayer capacitor which concerns on 12th Embodiment. It is a disassembled perspective view of the multilayer body included in the multilayer capacitor in accordance with the thirteenth embodiment. It is a disassembled perspective view of the multilayer body included in the multilayer capacitor in accordance with the fourteenth embodiment. It is a disassembled perspective view of the multilayer body included in the multilayer capacitor in accordance with the fifteenth embodiment. It is a disassembled perspective view of the multilayer body included in the multilayer capacitor in accordance with the sixteenth embodiment. It is a perspective view of the modification of the multilayer capacitor concerning a 1st embodiment. It is a disassembled perspective view of the multilayer body contained in the modification of the multilayer capacitor which concerns on 1st Embodiment. The disassembled perspective view of the modification of the multilayer capacitor which concerns on 5th Embodiment is shown.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Laminated body, 1a-1f ... Side surface, 3 ... 1st terminal electrode, 5 ... 2nd terminal electrode, 7 ... 1st connection conductor, 9 ... 2nd connection conductor, 11-22 ... Dielectric layer 31-36 ... 1st internal electrode, 41-45 ... 2nd internal electrode, 51-56, 61-65, 37, 47 ... Lead-out conductor, 71-76, 81-85 ... Internal conductor, 91a-100a , 91b to 100b... Through-hole conductors, 110 to substrate, 112 to cathode land pattern, 114 to anode land pattern, 116 and 118 to wiring, S11 to S16, S21 to S25 to slit, C1 and C2 to multilayer capacitor.

Claims (10)

A multilayer capacitor including a multilayer body in which a plurality of dielectric layers and a plurality of internal electrodes are alternately stacked; and a plurality of terminal electrodes formed in the multilayer body;
A circuit board having first and second land electrodes formed on the mounting surface,
The plurality of terminal electrodes include first and second terminal electrodes that are electrically insulated from each other;
The plurality of internal electrodes include a plurality of first and second internal electrodes arranged alternately,
The plurality of first internal electrodes are electrically connected to each other via a connection conductor,
The plurality of second internal electrodes are electrically connected to each other via a connection conductor,
Among the plurality of first internal electrodes, one or more first internal electrodes less than the total number of the first internal electrodes are electrically connected to the first terminal electrode via a lead conductor. Connected,
Among the plurality of second internal electrodes, one or more second internal electrodes less than the total number of the second internal electrodes are electrically connected to the second terminal electrode via a lead conductor. Connected,
The lead conductor is located at a position symmetrical to the first internal electrode electrically connected to the first terminal electrode via the lead conductor with respect to the center position in the stacking direction of the multilayer body. There is the second internal electrode electrically connected to the second terminal electrode via
The lead conductor is located at a position symmetrical to each second internal electrode electrically connected to the second terminal electrode via the lead conductor with respect to the center position in the stacking direction of the multilayer body. There is the first internal electrode electrically connected to the first terminal electrode via
The first terminal electrode is connected to the first land electrode formed on the circuit board,
The second terminal electrode is connected to the second land electrode formed on the circuit board,
2. The multilayer capacitor mounting structure according to claim 1, wherein none of the connection conductors is connected to any of the first and second land electrodes formed on the circuit board. A multilayer capacitor including a multilayer body in which a plurality of dielectric layers and a plurality of internal electrodes are alternately stacked; and a plurality of terminal electrodes formed in the multilayer body;
A circuit board having first and second land electrodes formed on the mounting surface,
The plurality of terminal electrodes include first and second terminal electrodes that are electrically insulated from each other;
The plurality of internal electrodes include a plurality of first and second internal electrodes arranged alternately,
The plurality of first internal electrodes are electrically connected to each other via a connection conductor,
The plurality of second internal electrodes are electrically connected to each other via a connection conductor,
Among the plurality of first internal electrodes, one or more first internal electrodes less than the total number of the first internal electrodes are electrically connected to the first terminal electrode via a lead conductor. Connected,
Among the plurality of second internal electrodes, one or more second internal electrodes less than the total number of the second internal electrodes are electrically connected to the second terminal electrode via a lead conductor. Connected,
The lead conductor is located at a position symmetrical to the first internal electrode electrically connected to the first terminal electrode via the lead conductor with respect to the center position in the stacking direction of the multilayer body. There is the first internal electrode electrically connected to the first terminal electrode via
The lead conductor is located at a position symmetrical to each second internal electrode electrically connected to the second terminal electrode via the lead conductor with respect to the center position in the stacking direction of the multilayer body. There is the second internal electrode electrically connected to the second terminal electrode via
The first terminal electrode is connected to the first land electrode formed on the circuit board,
The second terminal electrode is connected to the second land electrode formed on the circuit board,
2. The multilayer capacitor mounting structure according to claim 1, wherein none of the connection conductors is connected to any of the first and second land electrodes formed on the circuit board. The plurality of first internal electrodes are electrically connected to the connection conductor via lead conductors,
The plurality of second internal electrodes are electrically connected to the connection conductor via lead conductors,
The multilayer capacitor mounting structure according to claim 1, wherein the connection conductor is formed on a surface of the multilayer body.   4. The multilayer capacitor mounting structure according to claim 1, wherein the connection conductor is a through-hole conductor provided in the multilayer body in a stacking direction of the multilayer body. 5. A slit is formed in at least some of the first and second internal electrodes among the plurality of first and second internal electrodes,
The slit is formed in each of the first and second internal electrodes in which the slit is formed so that currents flow in opposite directions through regions facing each other with the slit interposed therebetween. Item 5. The multilayer capacitor mounting structure according to any one of Items 1 to 4. The laminate has a substantially rectangular parallelepiped shape,
The first terminal electrode is formed on a side surface extending in a longitudinal direction among side surfaces parallel to the stacking direction of the stacked body,
The second terminal electrode is formed on a side surface extending in a longitudinal direction among side surfaces parallel to the stacking direction of the multilayer body and facing the side surface on which the first terminal electrode is formed. The multilayer capacitor mounting structure according to any one of claims 1 to 5.   The number of the first internal electrodes electrically connected to the first terminal electrode via the lead conductor and the second electrically connected to the second terminal electrode via the lead conductor. The multilayer capacitor mounting structure according to claim 1, wherein the equivalent series resistance is set to a desired value by adjusting the number of internal electrodes of the multilayer capacitor.   The position of the first internal electrode electrically connected to the first terminal electrode via the lead conductor in the stacking direction of the laminate and the second terminal electrode via the lead conductor The equivalent series resistance is set to a desired value by adjusting the position in the stacking direction of the stacked body of the second internal electrodes connected to each other. 7. The multilayer capacitor mounting structure according to any one of 6 above.   By further adjusting the number of the connection conductors that electrically connect the plurality of first internal electrodes and the number of the connection conductors that electrically connect the plurality of second internal electrodes, respectively, 9. The multilayer capacitor mounting structure according to claim 7, wherein the equivalent series resistance is set to a desired value. The plurality of first internal electrodes are connected in parallel,
The multilayer capacitor mounting structure according to any one of claims 7 to 9, wherein the plurality of second internal electrodes are connected in parallel.

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