JP2008159923A - Mask for vapor deposition for manufacturing organic thin film transistor, method of manufacturing organic thin film transistor using the same, and organic thin film transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a mask for vapor deposition for manufacturing an organic TFT which makes it possible to form a high accurate patterning. <P>SOLUTION: The mask for the vapor deposition for manufacturing the organic TFT according to this invention is used in case of carrying out the vapor deposition of at least one patterning out of source and drain electrodes of the organic TFT, an organic semiconductor layer and a gate electrode. The mask for the vapor deposition is provided with a primary front surface suitable for a vapor-deposited substrate side and a secondary front surface suitable for a vapor deposition supply side. The primary front surface has a first opened window with at least one opening for forming the pattern and the secondary front surface has a second opened window with a substantially same shape as a shape consisting of the shortest outer line surrounding all openings of the first opened window. A distance D between the primary front surface and the secondary front surface and an opening width H in the channel length direction of the second opened window have the following relation: D>H. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an evaporation mask for manufacturing an organic thin film transistor (hereinafter referred to as “organic TFT”), a method for manufacturing an organic TFT using the same, and an organic TFT.

  In recent years, organic electronics has attracted attention. A major reason why organic electronics is attracting attention is that various devices can be fabricated and designed by utilizing the diversity of organic materials and abundant molecular design. Inorganic materials play a central role in the current semiconductor field, but it is not easy to incorporate new elements in materials having an inorganic hard crystal structure.

  In the case of organic, depending on the design of the molecule, not only the properties of each molecule can be changed, but also the integration state between the molecules can be controlled, and material properties corresponding to the application can be created by a bottom-up method. It is considered possible to do. Therefore, it may be possible to rationally add properties such as multi-functionality, flexibility, moldability, etc., which were difficult to realize with only inorganic materials centering on conventional silicon, by incorporating organic materials, The expansion of application development is expected by taking advantage of the merits of organic materials.

  The functionality of such organic materials has already been applied and developed in a wide variety of fields, and some mobile applications such as displays using organic electroluminescence elements have already been put into practical use. However, there are still many unknown areas regarding the characteristics of organic materials, and there are parts that have not been established technically, and there are many problems including reliability evaluation to realize various applications. It is.

In these organic electronics fields, thin film transistors (TFTs) using organic semiconductor layers are one of the objects that have been actively researched in recent years, and device characteristics have improved dramatically in recent years and have made remarkable progress. . For example, many TFTs using a pentacene vapor-deposited film as an organic semiconductor layer have been studied. However, a field effect mobility exceeding 1 cm ² / Vs is often reported, and reliability such as operational stability still remains. However, there are many problems to be solved in this field, but the device characteristic level is reached to the level of amorphous silicon.

  Those having such good characteristics are mainly realized by TFTs having a top contact type structure. A top contact type TFT is formed by forming an organic semiconductor layer on a gate insulating film and then forming source and drain electrodes, so that the organic semiconductor layer is positioned between the gate insulating film and the source and drain electrodes. Such a laminated structure.

  In general, a TFT with a top contact structure has better mobility than a TFT with a bottom contact structure in which an organic semiconductor layer is formed on a source and drain electrode formed on a gate insulating film. Therefore, a top contact type structure is often used in order to extract high mobility, but there is a limit to the process for manufacturing a TFT having this structure. This is because the electrode must be prepared after the organic semiconductor layer, and therefore the patterning of the source and drain electrodes cannot be performed by a method including a photolithography process, and the evaporation mask is used for the source and drain electrodes. It is necessary to form a pattern by vacuum deposition. In vacuum deposition, the accuracy of the channel shape and the element characteristics are affected by the accuracy of the mask deposition process.

  In general, an electrode pattern is formed by a lift-off method using a photolithography process for manufacturing a transistor element having a channel length of about several μ to several tens μm. The process will be briefly described. First, a photoresist is spin-coated on a substrate to form a film. A photomask is arranged on the photoresist film, and the pattern is transferred to the photoresist by an exposure process of irradiating photosensitive light from the photomask side.

  Thereafter, by immersing in a developing solution, in the case of a positive resist, the exposed portion is dissolved in the developing solution, and the shape of the unexposed portion is formed as a resist pattern. After this, after depositing the metal for the electrode, the remaining resist film and the metal deposited on it are peeled off together, so that the metal remains only in the part where the resist film is finally removed by exposure, An electrode pattern shape can be produced.

  The pattern forming method using the photolithography technique uses a developer or an organic solvent in the development or peeling process of the photoresist, and therefore the range of use is limited in the manufacturing process of an organic TFT including an organic thin film having low resistance to the solvent. As described above, when photolithography technology cannot be applied, pattern formation is performed by a vapor deposition method using a mask without a solvent treatment step.

  In recent years, miniaturization and integration of elements have become more and more important technologies, and a fine pattern formation method using a photolithography process is indispensable. However, in the formation of organic TFT electrodes and organic film formation, it is still a mask. Pattern formation by vapor deposition using is also an effective method.

  Pattern formation using a mask is often used in the formation of organic EL and liquid crystal elements, and various masks are used for the mask used so that high-definition pixels can be formed, such as color mixing suppression and film thickness uniformity. Is given. In general, the thinner the deposition mask for organic EL or liquid crystal, the better the thinner the deposition pattern is. This is because if the deposition mask is thick, the deposition material flying from the deposition source has a large shadow on the surface of the deposition substrate depending on the positional relationship between the mask opening window and the deposition source. In particular, it becomes a hindrance to reaching the edge corresponding to the edge of the pattern shape. As a result, the non-uniformity of the film thickness around the vapor deposition film becomes prominent, and the fineness of the vapor deposition pattern is adversely affected. Is essential. However, when the thickness of the evaporation mask is simply reduced, its mechanical strength is reduced.

  In general, since the mask thickness needs to be equal to or less than the opening width, there is a limit to miniaturization of the mask. For example, when applied to an opening window of 10 μm, the maximum thickness of the metal mask is 10 μm. In this case, however, the strength of the metal mask cannot be maintained, and distortion occurs. An adverse effect occurs.

  Therefore, in Patent Document 1, by using a mask having an EL element pattern opening window and a large opening window communicating with the periphery of the EL element pattern, the pattern opening window is made thin while ensuring the mask strength. By providing the material layer, it is said that a fine pattern can be formed with high accuracy by fixing with a magnet from the back surface and not generating a gap.

Further, in Patent Document 2, by using a mask pattern having a mask opening having a shape in which the opening width increases toward the vapor deposition source side, the film thickness becomes thin at the edge portion of the vapor deposition film corresponding to the end of the mask opening. This reduces the non-uniformity of the thickness of the deposited film.
JP 2002-47560 A JP 2002-220656 A

  In pattern formation using a vapor deposition mask in the production of organic TFTs, the vapor deposition material reaches the edge part of the mask opening window at the time of element formation in the same manner as the organic EL element pattern formation described above, and the entire film In addition, it is important to ensure that the edge state of a predetermined electrode shape or organic film shape can be formed without variation.

  This is because the state of the contact interface between the electrode and the organic film layer has a great influence on the device characteristics. In particular, since the source and drain electrodes are formed with a carrier conduction channel between the two electrodes, the state of the edge shape along the channel greatly affects the characteristics. When the channel length is as wide as about 100 μm, even if there is some dispersion, it can be regarded as a slight error. However, when the channel length is narrowed, the effect becomes increasingly serious and may cause deterioration of characteristics.

  However, in the conventional mask vapor deposition, the vapor deposition material wraps around the edge of the opening window of the mask. This is because the vapor deposition material that has come from the vapor deposition source is incident on the mask plane obliquely with respect to the mask plane and passes therethrough. There arises a problem that unnecessary deposition material adheres or the edge shape varies and a pattern is formed.

  In order to suppress excessive wraparound adhesion and variations on the back of the mask as much as possible, it is considered effective to bring the substrate and the mask as close as possible. However, if the substrate and the mask are brought into contact with each other, the surface of the soft organic film will be damaged or contaminated, which adversely affects the film surface state. A gap of about 10 μm is required. For this reason, if the small channel length is formed only by reducing the distance between the substrate and the mask, sufficient pattern definition cannot be obtained.

  This invention is made | formed in view of such a situation, and provides the vapor deposition mask for organic TFT manufacture which enables highly accurate pattern formation.

Means for Solving the Problems and Effects of the Invention

  The deposition mask for manufacturing an organic TFT according to the present invention has a source and drain electrodes spaced apart, an organic semiconductor layer providing a channel between the source and drain electrodes, and an electric field applied to the organic semiconductor layer. In the manufacture of an organic TFT comprising a gate electrode disposed on a gate electrode, and a gate insulating layer between the organic semiconductor layer and the gate electrode, the source and drain electrodes, the organic semiconductor layer, and the gate electrode A mask for vapor deposition for manufacturing an organic TFT used when forming at least one pattern of the above by vapor deposition, wherein the vapor deposition mask is directed to a first surface facing the substrate to be deposited and to a deposition source side. A first surface having a first opening window having at least one opening for forming the pattern, and the second surface has a first opening. A second opening window having substantially the same shape as the shape of the shortest outline that surrounds all the openings, a distance D between the first surface and the second surface, and a channel of the second opening window The opening width H in the long direction is characterized in that D> H.

  By using the vapor deposition mask having a thickness according to the present invention, when the vapor deposition material flying from the vapor deposition source passes through the opening window, the vapor deposition material incident obliquely with respect to the mask plane can be limited. It is possible to suppress the vapor deposition material from going around to the back and adhering to the deposition target substrate. Thereby, in particular, the variation of the edge portion of the pattern shape can be reduced, and a high-definition pattern can be formed.

  In addition, in an organic TFT manufactured using such a mask, the operation characteristics can be stabilized and improved. Such an effect can be obtained in the same manner with either a top contact type organic TFT or a bottom contact type organic TFT. However, since the top contact type organic TFT is limited in pattern formation by photolithography, the present invention is applied. The benefits are particularly great.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The configurations shown in the drawings and the following description are merely examples, and the scope of the present invention is not limited to those shown in the drawings and the following description.

  An evaporation mask for manufacturing an organic TFT according to an embodiment of the present invention includes a source and drain electrodes arranged at intervals, an organic semiconductor layer providing a channel between the source and drain electrodes, and an organic semiconductor layer In the manufacture of an organic TFT comprising a gate electrode arranged to apply an electric field, and a gate insulating layer between the organic semiconductor layer and the gate electrode, the source and drain electrodes, the organic semiconductor layer, An evaporation mask for manufacturing an organic TFT used for forming at least one pattern of a gate electrode by vapor deposition, wherein the vapor deposition mask includes a first surface facing a substrate to be deposited, a vapor deposition source A second surface directed to the side, the first surface having a first opening window having at least one opening for forming the pattern, the second surface A second opening window having substantially the same shape as the shape of the shortest outline surrounding all the openings of the first opening window, and a distance D between the first surface and the second surface; The opening width H in the channel length direction of the two opening windows is characterized in that D> H.

  Hereinafter, related matters will be described.

1. Organic TFT
First, an example of an organic TFT manufactured using the vapor deposition mask of this embodiment will be described with reference to FIG. FIG. 1 is a cross-sectional view showing an example of the structure of an organic TFT. Here, description will be given by taking a top contact type organic TFT as an example, but the vapor deposition mask of this embodiment can also be used for manufacturing a bottom contact type organic TFT.

  As shown in FIG. 1, the organic TFT includes source and drain electrodes 1 and 3 that are spaced apart from each other, an organic semiconductor layer 5 that provides a channel between the source and drain electrodes 1 and 3, and an organic semiconductor layer 5. A gate electrode 7 disposed so as to apply an electric field to the gate electrode 7 and a gate insulating layer 9 between the organic semiconductor layer 5 and the gate electrode 7. The gate electrode 7 is formed on the substrate 11, and the gate insulating layer 9 is formed so as to cover the gate electrode 7.

At least one pattern of the source and drain electrodes 1, 3, the organic semiconductor layer 5, and the gate electrode 7 is formed by vapor deposition using the vapor deposition mask of this embodiment. In addition, when vapor deposition is performed using the vapor deposition mask of the present embodiment, the pattern can be formed with high accuracy. Therefore, the vapor deposition mask of the present embodiment requires the high accuracy of the source and drain electrodes 1. , 3 is preferably used to form the pattern.
A method for manufacturing the organic TFT will be described later.

2. 2. Deposition mask 2-1. Next, the configuration of the vapor deposition mask of this embodiment will be described. Here, two configuration examples are shown using FIGS. 2A and 2B and FIGS. 3A and 3B. FIG. 2A is a perspective view showing the vapor deposition mask of the first configuration example, and FIG. 2B is a cross-sectional view taken along the line II in FIG. Fig.3 (a) is a perspective view which shows the mask for vapor deposition of the 2nd structural example, FIG.3 (b) is II sectional drawing in Fig.3 (a). It is a 1st and 2nd structural example, Comprising: You may comprise the mask for vapor deposition of this embodiment by another method.

(1) Evaporation Mask of First Configuration Example First, the deposition mask of the first configuration example will be described with reference to FIGS. 2 (a) and 2 (b). The vapor deposition mask of this configuration example has a first surface 13 facing the deposition target substrate side and a second surface 15 facing the vapor deposition source side, and the first surface 13 is at least for forming a pattern. The second opening 15 has a first opening window 19 having one opening, and the second surface 15 has substantially the same shape as the shape of the shortest outline that surrounds all the openings of the first opening window 19. The distance D between the first surface 13 and the second surface 15 having the window 21 and the opening width H in the channel length direction of the second opening window 21 have a relationship of D> H.

  The vapor deposition mask of this configuration example is assumed to be used for pattern formation of the source and drain electrodes 1 and 3, and the first opening window 19 has a pair of openings 19 a and 19 b arranged at intervals. Have The size of each opening is, for example, 1.0 mm × 0.5 mm. The space | interval between a pair of opening part 19a, 19b is 100 micrometers or less in an example. The distance between the pair of openings 19a and 19b is substantially equal to the channel length of the organic TFT to be manufactured. If this distance is short, the pattern of the source and drain electrodes 1 and 3 can be made with high accuracy. Since formation is required, the merit of applying the present invention is great. In this configuration example, “all the openings of the first opening window 19” is a pair of openings 19a and 19b.

  The vapor deposition mask of this configuration example includes a first mask 23 having a first surface 13, a second mask 25 having a second surface 15, and an intermediate in which the first mask 13 and the second mask 15 are spaced apart in parallel. And a support layer 27. The intermediate support layer 27 has a third opening window 29 that is larger than the second opening window 21. The size of the third opening window 29 may be approximately the same as that of the second opening window 21.

  Here, although the case where the evaporation mask of the present embodiment is configured by three layers of the first mask 23, the second mask 25, and the intermediate support layer 27 is shown as an example, the evaporation mask of the present embodiment is shown. May have a two-layer structure or a one-layer structure.

(2) Vapor Deposition Mask of Second Configuration Example Next, the vapor deposition mask of the second configuration example will be described with reference to FIGS. This configuration example is similar to the first configuration example, but the configuration of the first opening window 19 is different.

  The vapor deposition mask of this configuration example is assumed to be used for pattern formation of the organic semiconductor layer 5 or the gate electrode 7, and the first opening window 19 includes only one opening. Therefore, in this configuration example, “all the openings of the first opening window 19” is one opening.

2-2. Next, a method for manufacturing the vapor deposition mask of the first configuration example will be described with reference to FIGS. 4 (a) to 4 (d). 4A is a cross-sectional view of the vapor deposition mask of the first configuration example, and FIGS. 4B to 4D are configurations of the first mask 23, the second mask 25, and the intermediate support layer 27. FIG. FIG. The vapor deposition mask of the second configuration example can be manufactured by the same method.

(1) Manufacturing process of first mask and second mask The first mask 23 performs laser processing or etching processing on a thin plate made of a metal such as Fe, Ni, Cr, Co or an alloy thereof (for example, SUS material). It can produce by performing and forming the 1st opening window 19 which consists of a pair of opening part 19a, 19b. The thickness of the first mask 23 may be equal to or greater than a thickness that maintains the minimum strength, but is preferably equal to or less than the opening width of the pattern shape in order to increase the processing accuracy. Specifically, the thickness of the first mask 23 is preferably 20 to 1000 μm. The interval between the openings 19a and 19b is preferably 40 μm or more in order to increase the processing accuracy.

  The second mask 25 can also be formed by the same method as the first mask 23. However, the second mask 25 is manufactured by forming the second opening window 21 in a thin plate.

(2) Production process of intermediate support layer The intermediate support layer 27 is made of a metal such as Fe, Ni, Cr, Co or their alloys (for example, SUS material), a thin plate made of a material having a low thermal expansion coefficient such as glass or a silicon substrate Then, the third opening window 29 is formed by performing laser processing or etching processing. The third opening window 29 is preferably formed to be slightly larger than the second opening window 21. The thickness of the intermediate support layer 27 is not particularly limited, but the relationship between the distance D between the first surface 13 and the second surface 15 and the opening width H in the channel length direction of the second opening window 21 is D> H. It sets suitably so that.

(3) Connecting Step In the connecting step, the first mask 23, the intermediate support layer 27, and the second mask 25 produced in the above steps are connected to each other in this order. These connections are made so that the central axes of the first opening window 19 and the second opening window 21 coincide as shown in FIG. Further, since the third opening window 29 is formed larger than the second opening window 21, the central axis of the third opening window 29 may be slightly shifted from the first opening window 19 and the second opening window 21. Good. However, it is preferable that the central axis of the third opening window 29 also coincides with the central axes of the first opening window 19 and the second opening window 21.

  The connection method is not particularly limited, and an appropriate method is selected according to the material and the like. The connection method is, for example, a method such as thermocompression bonding or diffusion bonding, or a method of bonding using a double-sided tape for a vacuum device.

3. Next, an example of a method for manufacturing an organic TFT will be described. Here, an example of a method for manufacturing an organic TFT as shown in FIG. 1 will be described.

3-1. Overview of Organic TFT Manufacturing Method First, an evaporation mask having a first opening window 19 as shown in FIGS. 3A and 3B is parallel to the surface of the substrate 11 with a slight gap. The gate electrode 7 is patterned by depositing the gate electrode material in this state.

  The vapor deposition mask is parallel to the surface of the substrate 11 with a slight gap (for example, 20 to 100 μm) from the substrate 11 by, for example, a method of sandwiching a buffer material in a portion other than the first opening window 19. Deploy. The same applies hereinafter.

  Next, an insulating layer 9 is formed so as to cover the gate electrode 7 using a spin coating method or the like.

  Next, a vapor deposition mask having a first opening window 19 as shown in FIGS. 3A and 3B (however, the size of the first opening window 19 is different from that for pattern formation of the gate electrode 7). Are arranged so as to be parallel to the surface of the insulating layer 9 with a slight gap from the insulating layer 9, and the organic semiconductor layer material is vapor-deposited in this state, whereby the pattern of the organic semiconductor layer 5 is changed. Make it. For example, the organic semiconductor layer 5 is formed with a thickness of about 50 to 100 nm.

  Next, an evaporation mask having a first opening window 19 composed of a pair of openings 19a and 19b as shown in FIGS. 2A and 2B is separated from the organic semiconductor layer 5 by a slight gap. A pattern of the source and drain electrodes 1 and 3 is formed by depositing the source and drain electrode materials in this state so as to be parallel to the surface of the layer 5, and the structure shown in FIG.

  Here, an example is shown in which pattern formation is performed on the gate electrode 7, the organic semiconductor layer 5, and the source and drain electrodes 1 and 3 using the vapor deposition mask of the present embodiment. It is only necessary to use the vapor deposition mask of the present embodiment for the other, and for others, pattern formation may be performed by vapor deposition using a conventional metal mask or the like. Pattern formation may be performed by a method in which the solution containing the solution is applied only to a necessary portion and dried.

3-2. Details of the Deposition Process By the way, in the deposition process, the film thickness distribution on the deposition surface varies depending on the shape and structure of the deposition source of the deposition apparatus. In the case of a point evaporation source simply from a single crucible, the evaporation material flies radially from a certain point, so that the incident angle of the evaporation material can be limited by using a thick mask as in this embodiment, A sufficiently uniform film thickness cannot be obtained in a portion that is behind the mask edge.

  Therefore, in the vapor deposition using the vapor deposition mask of this embodiment, it is preferable to employ a vapor deposition method in which the vapor deposition material flies from multiple directions so that the thickness of the vapor deposition film is uniform. Such vapor deposition methods include, for example, the following two methods.

(1) Method of performing vapor deposition while rotating or rotating the deposition target substrate A method of performing deposition while rotating or rotating the deposition target substrate 31 will be described with reference to FIGS. 5 and 6 are cross-sectional views showing a state in which vapor deposition is performed on the deposition target substrate 31 using the vapor deposition mask 33 of the present embodiment.

  As shown in FIG. 5, the deposition substrate 31 is installed in the substrate installation unit 35, and the deposition mask 33 is parallel to the deposition substrate 31 surface with a slight gap from the deposition substrate 31. Is arranged. The substrate installation unit 35 is configured to rotate about the rotation axis X, and the deposition target substrate 31 and the deposition mask 33 also rotate together with the substrate installation unit 35. A vapor deposition source 37 is disposed at a position shifted from the rotation axis X of the substrate installation unit 35. The vapor deposition source 37 is configured such that the vapor deposition material 39 is heated in the crucible 41 to evaporate.

  In the arrangement as shown in FIG. 5, when the substrate setting portion 35 rotates, the angle at which the vapor deposition material 39 passes through the first opening window 19 of the vapor deposition mask 33 changes, so that vapor deposition is performed while rotating the vapor deposition substrate 31. If it carries out, it will become possible to form a vapor deposition film with uniform thickness.

  Further, as shown in FIG. 6, the deposition target substrate 31 and the deposition mask 33 can be installed at a position shifted from the rotation axis X of the substrate installation unit 35. In this case, the substrate installation unit 35 is installed at the rotation axis X. Is rotated about the rotation axis X, the substrate 31 for vapor deposition and the mask 33 for vapor deposition rotate. Even with such an arrangement, the deposited film can be formed with a uniform thickness according to the same principle as in FIG.

(2) Method of performing vapor deposition using planar vapor deposition source or multipoint or multiple vapor deposition source A method of performing vapor deposition using a planar vapor deposition source or a multipoint or multiple vapor deposition source will be described with reference to FIGS. 7 and 8 are cross-sectional views showing a state in which vapor deposition is performed on the deposition target substrate 31 using the vapor deposition mask 33 of the present embodiment.

  As shown in FIG. 7, the deposition substrate 31 is installed in the substrate installation unit 35, and the deposition mask 33 is parallel to the deposition substrate 31 surface with a slight gap from the deposition substrate 31. Is arranged. The flat deposition source 43 is disposed at a position away from the deposition mask 33 in a direction perpendicular to the surface of the deposition mask 33 so as to face the deposition mask 33. The flat evaporation source 43 is configured such that the evaporation material 39 is heated in the dish-shaped crucible 41 to evaporate.

  In the arrangement as shown in FIG. 7, since the vapor deposition material 39 evaporates from the dish-shaped crucible 45, the vapor deposition material 39 passes through the first opening window 19 of the vapor deposition mask 33 at various angles. When vapor deposition is performed using the flat vapor deposition source 43, a vapor deposition film can be formed with a uniform thickness.

  Further, instead of using the flat vapor deposition source 43, even if vapor deposition is performed using a multipoint vapor deposition source 45 in which the vapor deposition material 39 evaporates from many points as shown in FIG. It becomes possible to form the deposited film with a uniform thickness. The same applies when a large number of vapor deposition sources are used instead of the multipoint vapor deposition source 45.

  The deposition may be performed using a planar deposition source or a multipoint or multiple deposition source while rotating or rotating the deposition target substrate 31 and the deposition mask 33.

3-3. Effect of Deposition Mask Thickness and Second Opening Window Width on Pattern Accuracy Using FIG. 9, the thickness of the deposition mask 33 (distance D between the first surface 13 and the second surface 15) and the first The influence of the width of the two opening window 21 (the opening width H of the second opening window 21 in the channel length direction) on the pattern accuracy will be described. Here, the description will be given taking the vapor deposition mask shown in FIG. 2 as an example. FIG. 9 is a cross-sectional view showing a state in which a vapor deposition mask 33 is arranged in parallel to the surface of the vapor deposition substrate 31 with a gap d from the vapor deposition substrate 31.

In the arrangement of FIG. 9, it was examined how the maximum incident angle θ and the wraparound distance Δx change when the opening width H is 1 mm and the distance D and the gap d are changed. The results are shown in Table 1.

  Referring to Table 1, it can be seen that as the distance D corresponding to the thickness of the vapor deposition mask 33 increases, the maximum incident angle θ decreases and the wraparound distance Δx decreases. It can also be seen that the greater the gap d between the deposition substrate 31 and the deposition mask 33, the greater the wraparound distance Δx.

Also, referring to Table 1, when D ≦ H, the wraparound distance Δx is a relatively large value, but when D> H, the wraparound distance Δx is a relatively small value. I understand that

Further, when D ≧ 2H, the wraparound distance Δx is a smaller value. Also,
It can be seen that when the value of D is increased and D = 5H is reached, the wraparound distance Δx is sufficiently small, and it is not necessary to increase D further. Therefore, the relationship between D and H is preferably 2H ≦ H ≦ 5H.

Further, in order to suppress θ to about 10 ° or less, D may be 2.5 times or more of H. As a result, Δx can be reduced to 10 μm or less, which is considered effective when a channel length of about several tens of μm is formed.

  Various features shown in the above embodiments can be combined with each other. In the case where a plurality of features are included in one embodiment, one or a plurality of features can be appropriately extracted and used alone or in combination in the present invention.

  Hereinafter, a method for producing a vapor deposition mask of the present invention, a method for producing a pentacene TFT using the vapor deposition mask, evaluation of the accuracy of pattern formation by vapor deposition, and characteristic evaluation of the produced pentacene TFT are described below. Based on the explanation.

1. Preparation of evaporation mask An evaporation mask for forming the pattern of the source and drain electrodes having the structure as shown in FIGS. 2A and 2B was prepared.

  First, an etching process was performed on a thin SUS material plate having a thickness of 0.05 mm, and a pair of openings 19 a and 19 b each having a length of 1 mm and a width of 0.4 mm were arranged side by side at an interval of 50 μm. A first mask 23 was produced by forming a first opening window 19.

  Next, etching was performed on a SUS thin plate having a thickness of 0.05 mm to form a second mask 25 by forming a second opening window 21 having an opening of 1 mm in length × 0.8 mm in width. .

  Next, an intermediate support layer 27 was produced by etching a thin SUS material plate having a thickness of 1.5 mm to form a third opening window 29 having an opening of length 1.2 mm × width 1 mm. .

  Next, align the center position of each open window so that the open windows of the three processed SUS plates coincide when viewed from directly above, and perform diffusion bonding (heating and pressing under vacuum). Thus, a deposition mask for pattern formation of the source and drain electrodes having a thickness of 1.6 mm and an opening width of 0.8 mm was produced.

2. Next, a pentacene TFT was fabricated by the following method.
First, the silicon substrate with a 300 nm thermal oxide film was washed and dried. Specifically, the substrate was washed and dried by the following method. First, the substrate was immersed in acetone and subjected to ultrasonic cleaning for 10 minutes, and then immersed in isopropyl alcohol and further subjected to ultrasonic cleaning for 10 minutes. Then, after taking out and drying with a nitrogen flow, it was immersed in ultrapure water, subjected to ultrasonic cleaning for 10 minutes, taken out and dried with a nitrogen flow, and then dried in an oven at about 120 ° C. for 10 minutes.
A relatively highly doped silicon substrate was used so that the silicon substrate itself could be used as a gate electrode. The thermal oxide film is used as a gate insulating film.

  Next, a metal mask for pattern formation of the pentacene layer (a SUS material having a plate thickness of 0.05 mm and having an opening window of 1 mm in length and 0.5 mm in width) is used as an adhesive gel film (thickness of 100 to 100 mm). It was fixedly attached at about 200 μm and introduced and installed in a chamber for pentacene deposition, and pentacene was deposited in the chamber to form a pattern of the pentacene layer.

Pentacene was deposited using a multipoint deposition source 45 in the arrangement shown in FIG. A crucible 41 having a diameter of about 4 cm was used, and the crucible 41 was arranged at a position shifted by about 5 cm from the center of the substrate. The crucible 41 was arranged at a position about 30 cm away from the substrate installation part 35 in the direction perpendicular to the surface of the substrate installation part 35. After increasing the degree of vacuum in the chamber to 5 × 10 ⁻⁵ Pa, the crucible 41 was heated to about 200 to 230 ° C., and pentacene was deposited to a thickness of 100 nm at a deposition rate of 0.5 Å / s. .

  Next, the metal mask was removed from the silicon substrate.

  Next, the deposition mask for pattern formation of the source and drain electrodes prepared and prepared in advance is similarly fixed with an adhesive gel film, introduced and installed in a gold deposition chamber, and gold is deposited in the chamber. Thus, the pattern of the source and drain electrodes was formed.

Gold deposition was performed using a planar deposition source 43 in an arrangement as shown in FIG. A crucible 41 having a diameter of about 4 cm was used, and the crucible 41 was arranged at a position substantially coaxial with the center of the substrate. The crucible 41 was arranged at a position about 30 cm away from the substrate installation part 35. The substrate placement unit 35 was rotated at 10 seconds / rotation. After raising the degree of vacuum in the chamber to 5 × 10 ⁻⁵ Pa, the gold in the crucible 41 is heated and evaporated using an electron beam so that the thickness becomes 100 nm at a deposition rate of 2.0 Å / s. Gold was evaporated.

  After vapor deposition, the vapor deposition mask was removed from the silicon substrate to complete the production of a top contact type pentacene TFT. This TFT is hereinafter referred to as “Example TFT”.

  Further, instead of the thick deposition mask according to the embodiment of the present invention, a metal mask having the same material, plate thickness, and opening window as the first mask 23 is used as the deposition mask. Prepared a pentacene TFT by the same method as described above. This TFT is hereinafter referred to as “comparative TFT”.

3. Evaluation of pattern formation accuracy With the TFT of the example and the TFT of the comparative example, the state of the edge of the source and drain electrodes in the vicinity of the channel is observed by an optical microscope, a scanning electron microscope (SEM), and visual observation. The formation accuracy was evaluated.

  As a result, in the TFT of the comparative example, the change of the electrode film thickness is gradually observed over a width of about 10 μm, and the extra gold is formed up to the position of 20 μm at the maximum from the end of the uniform electrode film thickness formation of 100 nm. Particle adhesion was confirmed. On the other hand, in the TFT of the example, the width of the electrode film thickness change can be reduced to about 5 μm, and the distribution of the scattered gold particles is reduced.

  As a result, it was found that the accuracy of pattern formation can be improved by performing vapor deposition using the vapor deposition mask of the example of the present invention.

（但し、Ｌはチャネル長、Ｗはチャネル幅、Ｃ _i はＳｉＯ₂層の静電容量である。） 4). Evaluation of Characteristics of Pentacene TFT Five TFTs of Examples and Comparative Examples were manufactured, and field effect mobility (hereinafter referred to as “mobility”) was measured. Mobility μ measures the source-drain current I _D with respect to the modulation of the gate voltage V _G, was calculated from the slope of (I _D) ^1/2 -V _G characteristics in the saturation region using the following formula. The voltage condition was a drain voltage V _D = −50V, and V _G was swept from 50V to −50V.

(However, L is the channel length, W is the channel width, and C _i is the capacitance of the SiO ₂ layer.)

The obtained results are shown in Table 2.

  Referring to Table 2, it can be seen that the mobility of the TFT of the comparative example is larger than that of the TFT of the example. This result shows that it is possible to achieve a high definition pattern according to the present invention, which is effective in suppressing variation in device characteristics.

FIG. 1 is a cross-sectional view showing an example of the structure of an organic TFT manufactured using a vapor deposition mask according to an embodiment of the present invention. (A) is a perspective view which shows the mask for vapor deposition of the 1st structural example of one Embodiment of this invention, (b) is II sectional drawing in (a). (A) is a perspective view which shows the mask for vapor deposition of the 2nd structural example of one Embodiment of this invention, (b) is II sectional drawing in (a). (A) is sectional drawing of the mask for vapor deposition of the 1st structural example of one Embodiment of this invention, (b)-(d) is respectively the 1st mask 23, the 2nd mask 25, and intermediate | middle. 3 is a plan view showing a configuration of a support layer 27. FIG. It is sectional drawing which shows the state which has vapor-deposited to the to-be-deposited substrate 31 using the mask 33 for vapor deposition of one Embodiment of this invention. It is sectional drawing which shows the state which has vapor-deposited to the to-be-deposited substrate 31 using the mask 33 for vapor deposition of one Embodiment of this invention. It is sectional drawing which shows the state which has vapor-deposited to the to-be-deposited substrate 31 using the mask 33 for vapor deposition of one Embodiment of this invention. It is sectional drawing which shows the state which has vapor-deposited to the to-be-deposited substrate 31 using the mask 33 for vapor deposition of one Embodiment of this invention. 1 is a cross-sectional view showing a state in which a vapor deposition mask 33 according to an embodiment of the present invention is arranged in parallel to the surface of a vapor deposition substrate 31 with a gap d from the vapor deposition substrate 31. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,3: A pair of source and drain electrodes 5 Organic-semiconductor layer: 7: Gate electrode 9: Gate insulating layer 11: Substrate 13: 1st surface 15: 2nd surface 19: 1st opening window 19a, 19b: A pair of opening Part 21: Second opening window 23: First mask 25: Second mask 25 27: Intermediate support layer 29: Third opening window 31: Substrate to be deposited 33: Mask for deposition 35: Substrate installation part 37: Deposition source 39: Vapor deposition material 41: crucible 43: planar vapor deposition source 45: multi-point vapor deposition source

Claims (10)

Source and drain electrodes arranged at intervals, an organic semiconductor layer providing a channel between the source and drain electrodes, a gate electrode arranged to apply an electric field to the organic semiconductor layer, and the organic semiconductor layer And forming a pattern of at least one of the source and drain electrodes, the organic semiconductor layer, and the gate electrode by vapor deposition in the manufacture of an organic thin film transistor comprising a gate insulating layer between the gate electrode and the gate insulating layer A mask for vapor deposition for producing an organic thin film transistor used for
The deposition mask has a first surface facing the deposition substrate side and a second surface facing the deposition source side,
The first surface has a first opening window having at least one opening for forming the pattern, and the second surface is composed of a shortest outline line surrounding all the openings of the first opening window. A second opening window having substantially the same shape as the shape;
An evaporation mask for manufacturing an organic thin film transistor, wherein the distance D between the first surface and the second surface and the opening width H in the channel length direction of the second opening window satisfy a relationship of D> H. The mask according to claim 1, wherein the distance D and the opening width H have a relationship of 2H ≦ D ≦ 5H. The said mask for vapor deposition is provided with the 1st mask which has a 1st surface, the 2nd mask which has a 2nd surface, and the intermediate | middle support layer which arrange | positions a 1st mask and a 2nd mask spaced apart in parallel. 2. The mask according to 2. The mask according to claim 3, wherein the intermediate support layer has a third opening window larger than the second opening window. 5. The mask according to claim 1, wherein the first opening window has a pair of openings that are spaced from each other for pattern formation of the source and drain electrodes. The mask according to claim 5, wherein an interval between the pair of openings is 100 μm or less. A method for manufacturing an organic thin film transistor, comprising: forming at least one pattern of the source and drain electrodes, the organic semiconductor layer, and the gate electrode by vapor deposition using the mask according to claim 1. A method for producing an organic thin film transistor, comprising a step of forming a pattern of the source and drain electrodes by vapor deposition using the mask according to claim 5. The method according to claim 7 or 8, wherein the deposition is performed while rotating or rotating the deposition target substrate, or using a planar deposition source or a multi-point or multiple deposition source. The organic thin-film transistor manufactured by the method as described in any one of Claims 7-9.

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