JP2008158566A - Simulation device, simulation program, recording medium with simulation program stored therein and simulation method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a simulation device for efficiently analyzing a place where any noise problem is caused in a circuit board in which at least one of a signal line and a power source line strides over layers. <P>SOLUTION: This simulation device is provided with: a model preparation part 321 for preparing an analytic model for the circuit board based on board design data; an analyzing part 322 for executing electromagnetic field analysis to the analytic model; and an analytic result evaluation part 330 for calculating first currents flowing through the first via of a signal line or a power source and second currents flowing through a predetermined second via from an analytic result 390 of the electromagnetic field analysis, and for comparing the first currents with the second currents, and for extracting the bypass of return currents and the occurrence place of cross talk. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a multilayer printed circuit board.

  With the recent increase in operating frequency of digital equipment, noise problems such as equipment malfunction due to unnecessary radiation, power supply quality and signal quality deterioration have become apparent. This is because the electromagnetic influence due to the three-dimensional shape of the transmission path including the printed circuit board has increased with the increase in the operating frequency.

  One of the causes of noise problems is that a sufficient path for the feedback current (hereinafter referred to as “return current”) flowing through the high-speed signal line and / or power supply line is not secured, resulting in unnecessary radiation and crosstalk. There is a problem.

  For the purpose of securing the return current path, various inventions have been made so far as printed circuit boards and design devices thereof. For example, Patent Document 1 discloses an invention relating to a design apparatus for using a power source or a ground layer provided immediately below or directly above a signal line as a return current path.

  FIG. 10 is a diagram showing a structural example of a four-layer wiring board 50 designed by the design apparatus according to Patent Document 1. As shown in FIG. FIG. 11 is a diagram illustrating an example of the internal structure of the four-layer wiring board 50. With reference to FIG. 10 and FIG. 11, the path | route of the return current which concerns on patent document 1 is demonstrated.

  As shown in FIG. 10, the four-layer wiring board 50 includes a signal layer 51, a ground layer (ground) 52, a power supply layer 53, and a signal layer 54. A transmission IC (Integrated Circuit) 56 that is an example of a signal source is mounted on the four-layer wiring board 50, and a reception IC 57 that is an example of a load circuit is mounted on the substrate. The transmitting IC 56 is connected to the output terminal 13 and the ground terminal 14, and the receiving IC 57 is connected to the input terminal 15 and the ground terminal 16. The output terminal 13 and the input terminal 15 are connected by a signal line 55 that forms a signal layer 51. Further, in this example, the ground terminal 14 and the ground terminal 16 are connected to the ground layer 52.

  FIG. 11 shows an internal structure of a region I surrounded by a broken line in FIG. 10, and each layer is insulated by an insulator (dielectric) such as a prepreg resin. In each of these layers, contact holes (openings) 17 and 18 are provided, penetrating while maintaining insulation from the ground layer 52 and the power supply layer 53, and connecting the signal layers 51 and 54 between the upper part and the lower part. Used for.

  When a current flows through the signal line 55, a return current path 59 as shown by a broken line in the figure is induced in the ground layer 52. In this way, the return current path 59 outputs the output of the transmission IC 56 so as to minimize the signal (current) loop that is the forward path from the transmission IC 56 to the reception IC 57 and the return path from the reception IC 57 to the transmission IC 56. It is guided to a position directly below the signal line 55 in the signal layer 51 between the terminal 13 and the input terminal 15 of the receiving IC 57.

  As described above, the invention disclosed in Patent Document 1 is effective when the signal line is wired in a single layer, but the path of the return current when the signal line crosses the layers is not considered. .

  On the other hand, Patent Document 2 discloses a technique related to a printed circuit board wiring structure for ensuring a return current path when a signal line straddles a layer. According to the technique disclosed in Patent Document 2, when a signal line and / or a power supply line straddles a layer, a layer is formed by disposing a through hole that connects the ground layers in the vicinity of the through hole that connects the layers. Secure a return current path when straddling.

  Next, the background art of the three-dimensional electromagnetic field analysis for the printed circuit board, which forms the core of the present invention, will be described. The three-dimensional electromagnetic field analysis for the printed circuit board can analyze in detail the electromagnetic influence caused by the structure of the printed circuit board. For this reason, it is very effective in clarifying the mechanism of the noise problem. However, when a fine structure such as a multilayer printed circuit board is used as a target, there is a problem that the time required for calculation becomes enormous.

However, actual examples of three-dimensional electromagnetic field analysis for multilayer printed circuit boards have been reported due to recent improvements in the functions of electronic computers and parallel processing of three-dimensional electromagnetic field analysis. As an example, Non-Patent Document 1 describes an example of dealing with noise problems on a printed circuit board by performing parallel processing of electromagnetic field analysis and circuit analysis by FDTD (Finite Difference Time Domain) method using a plurality of computers. Yes.
JP 2004-252743 A JP-A-11-330703 Published by Nikkei BP, Nikkei Electronics, January 31, 2005, p. 117-130 Uno Satoshi, "Electromagnetic field and antenna analysis by FDTD method", Corona, 1st edition, 1998

  In the multilayer printed board, a via structure is used as a structure for electrically connecting the conductor layers. In the via structure, vias can be arbitrarily arranged for each conductor layer, so that the wiring density can be increased as compared with the multilayer printed board having the through-hole structure described in Patent Document 2.

FIG. 12 is a diagram in which a wiring layer that is an example of an inner layer of a multilayer printed board is extracted.
Referring to FIG. 12, a case is considered where a signal line and / or a power supply line via is a first via in a multilayer printed board using a via structure. In this case, a problem that occurs when determining whether the return current path for the first via is properly arranged based on the distance between the first via and the via serving as a return path such as the ground will be described.

  As shown in FIG. 12, the wiring layer 900 includes signal line and / or power supply line vias (hereinafter referred to as “first vias”) 902 connected to adjacent upper and lower wiring layers. The ground 910 through which the signal return current path is induced is electrically connected to the ground of the wiring layer immediately above by the ground via 912 due to restrictions on the wiring of the signal line group 930. Similarly, the ground via 914 is also electrically connected to the ground of the wiring layer immediately below.

  A case will be described in which a current flows in the first via 902 from the wiring layer immediately above to the wiring layer immediately below, and the return current flows from the ground directly above to the wiring layer 900 through the ground via 912. In this case, the return current passes through the ground via 912 in the vicinity of the first via 902. Then, it is considered that the current flows from the ground via 912 to the wiring layer immediately below through the ground via 914 through a route indicated by an arrow 940 due to restrictions on wiring. In the structural example shown in FIG. 11, a return current path is induced through the minimum loop area. In this way, in the wiring layer 900, the ground that returns through the minimum loop area is limited due to restrictions on the wiring. The return current is largely bypassed as indicated by arrow 940. For this reason, an induced current flows in another signal line (for example, signal line group 930) existing in the magnetic field due to the bypassed return current, and a further induced current is generated in another signal line by the magnetic field due to the induced current. That is, bypassing the return current causes noise problems such as crosstalk and signal reflection.

  As described above, it is not sufficient to compare the return current path with the distance between the first via and the via serving as the return current path with respect to the current flowing through the first via. It is also necessary to consider the wiring structure such as the ground that becomes the path of the above.

  However, in the multilayer printed board with an actual via structure, since the complexity of the wiring shape is multilayered, the return current when the signal line and / or the power line in the multilayer printed board crosses between layers is bypassed based on the geometric information of the wiring structure Therefore, it is difficult to extract a portion where crosstalk to other signal lines and / or power supply lines occurs.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a simulation apparatus that efficiently analyzes a location that causes a noise problem.

  According to one aspect of the present invention, in a circuit board in which at least one of a signal line or a power supply line straddles an interlayer, a current of a first via of a signal line or a power supply line that is a preset noise source, A simulation apparatus for performing analysis processing on a current flowing through a predetermined second via corresponding to a current of a first via, and a model for creating an analysis model for a circuit board based on board design data And a first current flowing in the first via and a second current flowing in the second via based on the result of the electromagnetic field analysis. The current calculation means for obtaining the current is compared with the first current and the second current, and the first via current and the second via flow corresponding to the first via current. To analyze the current and And a analysis result evaluation means.

  Preferably, the second via is at least one via existing within a predetermined radius centered on the first via, and the current calculation means uses the sum of the currents flowing through the second via as the second current. Ask.

  Preferably, the analysis result evaluating means compares the transient response value of the first current and the transient response value of the second current.

  Preferably, the analysis result evaluating means has an absolute value of the transient response value of the second current that is equal to or smaller than a predetermined ratio with respect to an absolute value of the transient response value of the first current, and the first current and the second current. The first via is identified as a return current bypass occurrence location corresponding to the first via in response to the determination that the polarity of the current is reversed.

  Preferably, the analysis result evaluating means compares the first current and the second current by the frequency response of the first current and the second current.

  Preferably, the analysis result evaluating means is configured such that the amplitude width of the second current is equal to or smaller than a predetermined ratio with respect to the amplitude width of the first current, and the phase difference between the first current and the second current is predetermined. The second via is specified as a return current detour occurrence location in response to the determination that it is within the range.

  Preferably, the analysis result evaluating means compares the transient response value of the first current and the transient response value of the second current.

  Preferably, the analysis result evaluating means determines whether the absolute value of the transient response value of the second current is greater than or equal to a predetermined ratio with respect to the absolute value of the transient response value of the first current. Are identified as crosstalk locations.

  Preferably, the analysis result evaluating means compares the first current and the second current by the frequency response of the first current and the second current.

  Preferably, the analysis result evaluating means determines that the second via is set as the crosstalk occurrence location in response to the determination that the amplitude width of the second current is greater than or equal to a predetermined ratio with respect to the amplitude width of the first current. Identify.

  Preferably, the means for performing the electromagnetic field analysis performs the electromagnetic field analysis by a finite time difference domain method.

  According to another aspect of the present invention, in a circuit board in which at least one of a signal line or a power supply line straddles an interlayer, a first signal line or power supply line that becomes a preset noise source is connected to a computer having an arithmetic unit. A simulation program for executing an analysis process for a current of a via and a current flowing through a predetermined second via corresponding to the current of the first via, the arithmetic unit based on the board design data, A step of creating an analysis model for the circuit board, a step of the operation unit executing an electromagnetic field analysis on the analysis model, and a calculation unit that performs a first flow through the first via from the result of the electromagnetic field analysis The step of calculating the current of the first via and the second current flowing through the second via, and the operation unit compares the first current and the second current to determine the current of the first via and the first via Current of And a step of analyzing the current flowing through the second via and response.

  According to still another aspect of the present invention, a computer readable recording medium storing the simulation program is provided.

  According to still another aspect of the present invention, in the circuit board in which at least one of the signal line or the power supply line straddles the interlayer, the current of the first via of the signal line or the power supply line that becomes a preset noise source, A simulation method for analyzing a current flowing through a predetermined second via corresponding to a current of a first via, the step of creating an analysis model for a circuit board based on board design data, and an analysis model Performing an electromagnetic field analysis on the first, a first current flowing through the first via and a second current flowing through the second via from the result of the electromagnetic field analysis, and the first current; Comparing the second current and analyzing the current of the first via and the current flowing through the second via corresponding to the current of the first via.

  According to the present invention, it is possible to efficiently analyze a portion that causes a noise problem. Thereby, a high-quality electronic circuit with less noise can be provided.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same parts are denoted by the same reference numerals. Their names and functions are also the same. Therefore, detailed description thereof will not be repeated.

  According to the simulation apparatus of the present embodiment, when designing a circuit board in which at least one of a signal line or a power supply line straddles between layers, a current flowing through each via is calculated by electromagnetic field analysis. Then, by comparing the values of currents flowing through the predetermined vias, return current detours and crosstalk occurrence points are specified. As a result, it is possible to provide a high-quality electronic circuit with less noise without actually creating a trial product.

  FIG. 1 is a block diagram showing the configuration of a simulation apparatus 100 according to the present invention.

The configuration of the simulation apparatus 100 will be described with reference to FIG.
The simulation apparatus 100 includes a computer main body 102, an FD drive 106 for reading and writing information on a flexible disk (hereinafter referred to as “FD”) 116 connected to the computer main body 102 via a bus 105, a CD An optical disc drive 108 for reading information on an optical disc such as a ROM (Compact Disc Read-Only Memory) 118, a communication interface 128 for exchanging data with the outside, a monitor 104 as a display device, and an input device As a keyboard 110 and a mouse 112. The computer main body 102 includes a CPU (Central Processing Unit) 120 connected to the bus 105, a memory 122 including a ROM (Read Only Memory) and a RAM (Random Access Memory), and a direct access memory device, for example, a hard disk 124.

  The hard disk 124 includes a substrate CAD data 350 in which parameters representing physical properties such as the shape of the printed circuit board to be designed and the dielectric constant of the medium constituting the substrate are stored, and the components arranged on the circuit board A model database (hereinafter referred to as “model DB”) 360 that stores an equivalent circuit model corresponding to, a program 160 that executes electromagnetic field analysis, a program 161 that evaluates an analysis result, and a condition for the analysis are A stored analysis condition 370, an analysis model 380 of a printed circuit board to be designed, and an analysis result 390 for storing the analysis result are included.

  Here, for example, the substrate CAD data 350, the model DB 360, and the analysis condition 370 may be supplied from an external database via the communication interface 128. The program for performing the simulation according to the present invention may be supplied by a storage medium such as the FD 116 or the CD-ROM 118, or may be supplied by another computer via a communication line. The electromagnetic field analysis may be executed by an external computer via the communication interface 128 and the result may be stored in the hard disk 124.

  The CPU 120 functioning as an arithmetic processing unit executes processing corresponding to each program described above using the memory 122 as a working memory.

  The CD-ROM 118 may be another medium, such as a DVD-ROM (Digital Versatile Disc) or a memory card, as long as it can record information such as a program installed in the computer main body. In this case, the computer main body 102 is provided with a drive device that can read these media. The bus 105 may be connected to a magnetic tape device that is detachably loaded with a cassette type magnetic tape.

  The program for performing the simulation according to the present invention is software executed by the CPU 120 as described above. Generally, such software is stored and distributed in a storage medium such as the CD-ROM 118 and the FD 116, read from the storage medium by the optical disk drive 108 or the FD drive 106, and temporarily stored in the hard disk 124. Alternatively, when the simulation apparatus 100 is connected to the network, it is temporarily copied from the server on the network to the hard disk 124. Then, the data is further read from the hard disk 124 to the RAM in the memory 122 and executed by the CPU 120. In the case of network connection, the program may be directly loaded into the RAM and executed without being stored in the hard disk 124.

  The computer hardware itself shown in FIG. 1 and its operating principle are general. Therefore, an essential part for realizing the functions of the present invention is software stored in a storage medium such as the FD 116, the CD-ROM 118, and the hard disk 124.

FIG. 2 is a block diagram illustrating a functional configuration of the CPU 120.
The functional configuration of the CPU 120 will be described with reference to FIG.

  The CPU 120 performs an electromagnetic field analysis unit 320 that performs electromagnetic field analysis according to a program 160 that executes electromagnetic field analysis, an analysis result evaluation unit 330, an electromagnetic field analysis unit 320, and an analysis result evaluation unit 330 according to a program 161 that evaluates the analysis result. And a control unit 310 for controlling the above.

  The electromagnetic field analysis unit 320 includes a model creation unit 321 that creates an analysis model to be designed and an analysis unit 322 that performs electromagnetic field analysis.

  The model creation unit 321 extracts, from the board CAD data 350, the shape information of each component of the printed circuit board to be designed and the physical property values of permittivity, permeability, and conductivity necessary for electromagnetic field analysis, and the analysis conditions An analysis model of the multilayer printed board is created according to the conditions given at 370. For example, when performing electromagnetic field analysis using the FDTD method, the target multilayer printed circuit board is divided by a grid called a cell, and an analysis model is created in which physical properties are given to each cell according to the material to be filled. To do.

  When analyzing including the influence of the circuit elements mounted on the multilayer printed circuit board, information identifying the type of the component is read from the board CAD data 350, and equivalent circuit information corresponding to the component is read from the model DB 360. For example, an analysis model of a circuit based on the current source method or the voltage source method described in Non-Patent Document 2 is created. The circuit analysis model includes via position information for storing the current value of the via used in the analysis result evaluation unit 330. The via position information includes position information in the substrate CAD data 350, position information in the analysis model 380, and signal information with respect to the via of the signal specified by the analysis condition 370.

  The model creation unit 321 writes the created analysis model into the analysis model 380 in the hard disk 124.

  The analysis unit 322 reads the analysis model 380 and executes analysis according to the analysis condition 370. Then, the analysis result is written in the analysis result 390. For example, when electromagnetic field analysis is performed by the FDTD method, the analysis condition 370 includes the size of the lattice cell, the time step of FDTD analysis, and the like. In the following description, the electromagnetic field analysis is described by the FDTD method, but the electromagnetic field analysis may be performed by other methods.

  Here, the FDTD method will be briefly described. In the FDTD method, analysis is performed using a structure called a Yee lattice in which a lattice in which an unknown electric field is arranged and a lattice in which an unknown magnetic field is arranged are shifted by half the width of the lattice. The FDTD method derives a relational expression that works between these unknown electric field and magnetic field and the adjacent unknown magnetic field and electric field by differentiating Maxwell's electromagnetic field equation, and based on that, the unknown electric field and magnetic field are converted to a certain time. This is an analysis method for obtaining the entire electromagnetic field behavior by updating the steps in units. According to this analysis method, the electric field and the magnetic field can be obtained alternately by updating the electric field at a certain time step, updating the magnetic field after ½ time step, and updating the electric field after one time step. .

  In general, in the three-dimensional electromagnetic field analysis, analysis is performed using one or a plurality of elements of an electric field or a magnetic field in the analysis region as a wave source. In the present embodiment, analysis is performed by setting a wave source between a signal that functions as a noise source and a signal through which a return current flows, which is specified by the analysis condition 370. The analysis unit 322 writes the analysis result in the analysis result 390. In the analysis result 390, the current flowing through each via corresponding to the via position information included in the analysis model 380 is stored.

  The wave source set between the signal acting as the noise source and the signal through which the return current flows may be given in advance as an analysis condition, or the wave source may be provided in advance from a noise source and a terminal through which the return current flows. It may be set. These terminals are extracted by the model creation unit 321 when modeling the board.

  FIG. 3 is a diagram for explaining a method of setting a wave source between two terminals. 3A is a diagram of the substrate 10 viewed from the Z-axis direction, and FIG. 3B is a diagram of the substrate 10 viewed from the Y-axis direction.

  With reference to FIG. 3, an example of a method of setting a wave source between a signal serving as a noise source and a signal through which a return current flows will be described.

  As shown in FIG. 3A, the substrate 10 includes a noise source terminal 11, a return current terminal 12, and other terminals 13. A shaded portion indicates a conductor on the substrate 10.

  When a wave source is set in a layer in which the noise source terminal 11 and the return current terminal 12 are set, when the wave source and a terminal for setting the wave source are connected by a conductor, they are connected to other terminals 13. A malfunction occurs.

  Therefore, as shown in FIG. 3B, a minute resistor 22 is provided for the layer shifted by one in the Z-axis direction from the layer where the terminal is set, and is connected to the wave source 21.

  Thereby, the wave source can be set between the terminals without overlapping the other signal lines.

  Returning to FIG. 2, the analysis result evaluation unit 330 performs the return current bypass when the signal line and / or the power supply line straddles the layers based on the analysis result 390, the analysis model 380, the analysis condition 370, and the substrate CAD data 350. The location where crosstalk to other signal lines and / or power supply lines occurs is extracted. Here, a signal that is given in advance by the analysis condition 370, a signal that causes a return current, a signal through which a return current flows, a signal that impairs the original function when noise enters, or a signal that is greatly affected by noise (hereinafter referred to as “noise resistance”). And a via position information indicating the position of each via given in advance by the analysis model 380, the current flowing through each via is obtained from the analysis result 390. Then, the current flowing through the via of the signal serving as the noise source is compared with the current flowing through the via of the other signal to extract the detour of the return current and the occurrence of the crosstalk.

  A specific method for extracting a return current detour and a crosstalk occurrence point will be described below.

(1. Method to extract return current bypass from transient response)
Here, a method for extracting the return current detour from the transient response will be described.

  As described above, the current (hereinafter referred to as “first current”) that flows through the via of the signal serving as the noise source is calculated from the analysis condition 370, the analysis model 380, and the analysis result 390. The analysis condition 370 is provided with a maximum allowable return current via distance in advance, and a via for a signal through which a return current exists within the maximum allowable return current via centered on a via for a signal that is a noise source. To extract. Then, the sum of the currents flowing through the extracted vias (hereinafter referred to as “second current”) is calculated.

  Here, when the designed current does not flow in the via designed for the return current in advance, the absolute value of the transient response value of the second current is smaller than the absolute value of the transient response value of the first current. Conceivable. Therefore, for example, when the following formulas (1) and (2) are simultaneously satisfied, it is assumed that the first via is specified and a return current bypass corresponding to the first via occurs.

However, the transient response values of the first current and the second current are I _1t and I _2t respectively, and the return current transient allowable ratio given in advance under the analysis condition 370 is r _rt . The current value may be a time integral or an average value, or may be a peak value of a transient response.

(2. Method of extracting return current detour in frequency domain)
Here, a method for extracting a return current bypass in the frequency domain will be described.

  Similar to the method of extracting the return current detour from the transient response, when the designed current does not flow in the via designed for the return current in advance, the amplitude width of the frequency response of the second current is the first This is considered to be smaller than the amplitude width of the frequency response of the current. Therefore, for example, when the following expressions (3) and (4) are simultaneously satisfied, it is assumed that the first via is specified and a return current bypass corresponding to the first via occurs.

However, the amplitude widths of the frequency responses of the first current and the second current are I _1f and I _2f , the phases are ∠I _1f and ∠I _2f , respectively, and the return current frequency allowable ratio given in advance under the analysis condition 370 is r _rf and the upper limit and the lower limit of the return current phase allowable range are a _l and a _h , respectively.

(3. Method of extracting crosstalk occurrence location from transient response)
Here, a method of extracting a portion where crosstalk from a transient response to a signal line and / or a power supply line with low noise resistance occurs will be described.

  As described above, from the analysis condition 370, the analysis model 380, and the analysis result 390, the current (hereinafter referred to as “third current”) that flows through the via of the signal line and / or the power supply line with low noise resistance is calculated. .

  Here, when crosstalk occurs from the first current to the signal having low noise resistance and / or the power supply line, the absolute value of the transient response value of the third current is larger than that in the case of flowing into the via as designed. Is also expected to grow. Thus, for example, when the following equation (5) is satisfied, a via through which the third current flows is specified and crosstalk is generated.

However, the transient response value of the third current is I _3t , and the crosstalk current transient allowable ratio given in advance under the analysis condition 370 is r _ct .

(4. Method of extracting crosstalk occurrence location in frequency domain)
Here, a description will be given of a method of extracting a portion where crosstalk to a signal line and / or a power supply line with low noise resistance occurs in the frequency domain.

  Similar to the method of extracting the crosstalk from the transient response to the signal line and / or power supply line having low noise resistance, from the first current to the signal line and / or power supply line having low noise resistance. When crosstalk occurs, the amplitude width of the frequency response of the third current is considered to be larger than when the current flows in the via as designed. Therefore, for example, when the following equation (6) is satisfied, a via through which the third current flows is specified and crosstalk is generated.

However, the amplitude width of the frequency response of the third current is I _3f , and the crosstalk current frequency allowable ratio given in advance under the analysis condition 370 is r _cf.

  As described above, return current detours and crosstalk occurrence points are extracted. As an example of the transient response value, a value at an arbitrary time of the transient response, a maximum value in the transient response, or the like is used.

Below, the process which the simulation apparatus 100 of the structure mentioned above performs is demonstrated.
FIG. 4 is a flowchart showing an outline of processing performed by the simulation apparatus 100.

  A process performed by the simulation apparatus 100 will be described with reference to FIG. First, the outline of the entire process will be described, and then the details of each process of step S12, step S18, and step S24 will be described.

  In step S <b> 10, the control unit 310 writes analysis conditions necessary for creating an analysis model, electromagnetic field analysis, and evaluation of analysis results in the analysis conditions 370 in the hard disk 124 in cooperation with the substrate CAD data 350. .

  Next, in step S12, the control unit 310 activates the model creation unit 321. Processing performed by the model creation unit 321 will be described later.

  Subsequently, in step S <b> 14, the control unit 310 confirms reception of a message notified from the model creation unit 321 that the model creation has been completed.

  In step S16, control unit 310 determines whether a message has been received in step S14. If it is determined that no message has been received (NO in step S16), the process returns to step S14.

  On the other hand, if it is determined that a message has been received (YES in step S16), in step S18, control unit 310 activates analysis unit 322 and executes electromagnetic field analysis. Processing performed by the analysis unit 322 will be described later.

  Next, in step S20, the control unit 310 confirms reception of a message notified from the analysis unit 322 that the electromagnetic field analysis is completed.

  Subsequently, in step S22, control unit 310 determines whether a message has been received in step S20. If it is determined that no message has been received (NO in step S22), the process returns to step S20.

  On the other hand, if it is determined that a message has been received (YES in step S22), in step S24, control unit 310 activates analysis result evaluation unit 330 and executes analysis result evaluation. Processing performed by the analysis result evaluation unit 330 will be described later.

  In step S <b> 26, the control unit 310 confirms reception of a message notified from the analysis result evaluation unit 330 that the evaluation of the analysis result is completed.

  Subsequently, in step S28, control unit 310 determines whether a message has been received in step S26. If it is determined that no message has been received (NO in step S28), the process returns to step S26.

  Next, in step S30, the control unit 310 uses the information extracted by the analysis result evaluation unit 330 to specify the return current bypass and crosstalk occurrence location on the screen of the monitor 104, for example. Is output to the substrate CAD or the like so that the result can be confirmed, and the process ends.

FIG. 5 is a flowchart showing processing performed by the model creation unit 321.
With reference to FIG. 5, the process performed in step S12 of FIG. 4 will be described.

  In step S <b> 40, the model creation unit 321 reads the analysis condition 370 and develops it on the memory 122.

  Next, in step S <b> 42, the model creation unit 321 reads the substrate CAD data 350 and develops it on the memory 122.

  In step S44, the model creation unit 321 divides the structure of the substrate CAD data read in step S42 by the cell size given by the analysis condition.

  Subsequently, in step S46, when the model creation unit 321 is set to analyze including the elements mounted on the printed circuit board under the analysis conditions, an equivalent circuit of the corresponding element is obtained from the model DB 360. Read.

  Next, in step S <b> 48, the model creation unit 321 models the analysis target substrate so that an electromagnetic field analysis can be performed based on the data read above, and writes the model into the analysis model 380. For example, the structure information or physical property value of the component to be analyzed is written. At this time, by referring to the analysis condition 370, for example, the file name is managed so that the created analysis model can be identified.

  Finally, in step S50, the model creation unit 321 transmits a message to the effect that model creation has been completed to the control unit 310.

As described above, the model creation unit 321 creates an analysis model.
FIG. 6 is a flowchart showing processing performed by the analysis unit 322.

With reference to FIG. 6, the process performed in step S18 of FIG. 4 will be described.
In step S52, the analysis unit 322 reads the analysis condition 370.

  Next, in step S <b> 54, the analysis unit 322 reads the analysis model 380. At this time, the analysis model specified by the analysis conditions is read.

  Subsequently, in step S56, the analysis unit 322 performs electromagnetic field analysis according to the analysis conditions.

  In step S58, the analysis unit 322 writes the current flowing through each via specified by the via position information in the analysis model in the analysis result 390 after the analysis is completed. In this embodiment, it is assumed that the analysis result 390 is written after the analysis is completed. However, the analysis result 390 may be written during the execution of the analysis.

  In step S <b> 60, the analysis unit 322 transmits a message indicating that the electromagnetic field analysis is completed to the control unit 310.

As described above, the analysis unit 322 performs electromagnetic field analysis.
FIG. 7 is a flowchart showing processing performed by the analysis result evaluation unit 330.

With reference to FIG. 7, the process performed in step 24 of FIG. 4 will be described.
In step S62, the analysis result evaluating unit 330 reads the analysis condition 370.

  Next, in step S64, the analysis result evaluation unit 330 reads the analysis result 390.

  Subsequently, in step S66, the analysis result evaluation unit 330 calculates a first current value that flows through each via of a signal that is a noise source, which is specified by the analysis condition. In addition, the calculated current value may be converted into frequency domain data using a technique such as discrete Fourier transform.

  In step S68, the analysis result evaluation unit 330 calculates the second current value of the sum of the currents flowing through the vias within the maximum allowable return current via distance for each via of the signal serving as the noise source. . In addition, the calculated current value may be converted into frequency domain data using a technique such as discrete Fourier transform.

  Further, in step S70, the analysis result evaluation unit 330 calculates a current value flowing through each via of a signal with low noise resistance specified by the analysis condition. In addition, the calculated current value may be converted into frequency domain data using a technique such as discrete Fourier transform.

  Next, in step S72, the analysis result evaluation unit 330 identifies the via according to the formula (1) and the formula (2) or the formula (3) and the formula (4), and extracts a place where the return current is bypassed. To do.

  Subsequently, in step S74, the analysis result evaluating unit 330 specifies a via according to the equation (5) or the equation (6), and extracts a crosstalk occurrence location.

  In step S76, the analysis result evaluation unit 330 outputs a location where return current detouring occurs and a location where crosstalk occurs. At this time, since the coordinate position of each via is known from the information of the analysis model, the location where the return current is bypassed and the location where the crosstalk is generated may be output to the substrate CAD or the like.

  Finally, in step S78, the analysis result evaluation unit 330 transmits a message to the control unit 310 indicating that the analysis evaluation has been completed.

As described above, the analysis result evaluation unit 330 evaluates the analysis result.
FIG. 8 is a wiring diagram of the inner layer of the multilayer printed circuit board to be analyzed.

  An application example of the simulation method according to the present embodiment will be described with reference to FIG.

  In FIG. 8, a white portion of the substrate 700 indicates a portion formed of a conductor, and a circle indicated by a black line in the conductor indicates a position of a via connected to adjacent upper and lower layers. The position coordinates are given to these vias according to the analysis conditions and the analysis model.

  For example, if the via allowable maximum distance for return current is 12 mm as an analysis condition for the via 710 of the signal line that works as a noise source, vias 720 to 725 existing within a radius of 12 mm centering on the via 710 are returned. This is a current via. The current flowing through the via 710 is the first current, and the sum of the current flowing through the vias 720 to 725 is the second current.

FIG. 9 is a diagram showing transient response current waveforms of the first current and the second current.
Referring to FIG. 9, the amplitude value (I _1t ) at point 800 where the maximum amplitude value of the transient response of the first current is taken is −10.4 mA, and the maximum amplitude value of the transient response of the second current is taken. The amplitude value (I _2t ) at 802 is 3.53 mA.

Here, when the return current transient allowable ratio r _rt is 0.4, the above values satisfy the expressions (1) and (2) at the same time. Therefore, the via 710 is specified as the corresponding return current bypass occurrence location.

  As described above, according to the simulation apparatus according to the present embodiment, in the circuit board in which the signal line and / or the power supply line straddles the interlayer, the return current is bypassed and another signal line and / or the power supply line is routed. It is possible to extract a portion where crosstalk occurs. Thereby, the user can design the circuit board while confirming the detour of the return current and the occurrence of the crosstalk on the display and confirming the display. Therefore, a high-quality electronic circuit with less noise can be provided.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a block diagram showing a configuration of a simulation apparatus 100 according to the present invention. 2 is a block diagram showing a functional configuration of a CPU 120. FIG. 3 is a flowchart showing an outline of processing performed by a simulation apparatus 100. 3 is a flowchart showing an outline of processing performed by a simulation apparatus 100. It is the flowchart shown about the process which the model preparation part 321 performs. It is the flowchart shown about the process which the analysis part 322 performs. It is the flowchart shown about the process which the analysis result evaluation part 330 performs. It is a wiring diagram of the inner layer of the multilayer printed circuit board used as analysis object. It is a figure which shows the transient response current waveform of a 1st electric current and a 2nd electric current. It is a figure which shows the structural example of the 4-layer wiring board 50 designed by the design apparatus which concerns on patent document 1. FIG. 3 is a diagram showing an example of the internal structure of a four-layer wiring board 50. FIG. It is the figure which extracted the wiring layer which is an example of the inner layer of a multilayer printed circuit board.

Explanation of symbols

  50 4-layer wiring board, 51 signal layer, 52 ground layer, 53 power supply layer, 54 signal layer, 55 signal line, 56 transmitting IC, 57 receiving IC, 59 return current path, 100 simulation device, 102 computer main body, 104 Monitor, 105 bus, 106 FD drive, 108 optical disk drive, 110 keyboard, 112 mouse, 116 FD, 118 CD-ROM, 120 CPU, 122 memory, 124 hard disk, 128 communication interface, 160 program for performing electromagnetic field analysis, 161 Program for evaluating analysis results, 310 control unit, 320 electromagnetic field analysis unit, 321 model creation unit, 322 analysis unit, 330 analysis result evaluation unit, 350 substrate CAD data, 360 model DB, 370 analysis condition, 3 0 analysis model, 390 analysis results.

Claims (14)

Corresponding to the current of the first via of the signal line or the power supply line and the current of the first via, which is a preset noise source, in a circuit board in which at least one of the signal line or the power supply line straddles the layer A simulation apparatus for performing an analysis process on a current flowing through a predetermined second via,
Model creation means for creating an analysis model for the circuit board based on the board design data;
Electromagnetic field analysis means for performing electromagnetic field analysis on the analysis model;
A current calculation means for obtaining a first current flowing through the first via and a second current flowing through the second via from the result of the electromagnetic field analysis;
Comparing the first current and the second current to analyze the current of the first via and the current flowing through the second via corresponding to the current of the first via A simulation apparatus comprising the analysis result evaluation means. The second via is at least one via existing within a predetermined radius around the first via,
The simulation apparatus according to claim 1, wherein the current calculation unit obtains a sum of currents flowing through the second vias as the second current.   The simulation apparatus according to claim 2, wherein the analysis result evaluation unit compares the transient response value of the first current and the transient response value of the second current.   The analysis result evaluating means has an absolute value of a transient response value of the second current that is equal to or smaller than a predetermined ratio with respect to an absolute value of the transient response value of the first current, and the first current and the The simulation apparatus according to claim 3, wherein the first via is specified as a return current detour generation location corresponding to the first via in response to the determination that the polarity of the second current is reversed.   The simulation apparatus according to claim 2, wherein the analysis result evaluation unit compares the first current and the second current based on a frequency response of the first current and the second current.   The analysis result evaluation unit is configured such that the amplitude width of the second current is equal to or less than a predetermined ratio with respect to the amplitude width of the first current, and the phase difference between the first current and the second current is The simulation apparatus according to claim 5, wherein the first via is specified as a return current detour generation location corresponding to the first via in response to a determination that it is within a predetermined range.   The simulation apparatus according to claim 1, wherein the analysis result evaluation unit compares a transient response value of the first current and a transient response value of the second current.   The analysis result evaluation means determines that the absolute value of the transient response value of the second current is greater than or equal to a predetermined ratio with respect to the absolute value of the transient response value of the first current. The simulation device according to claim 7, wherein the two vias are specified as a crosstalk occurrence location.   The simulation apparatus according to claim 1, wherein the analysis result evaluation unit compares the first current and the second current based on frequency responses of the first current and the second current.   The analysis result evaluating means determines that the second via is located at a location where the crosstalk occurs in response to a determination that the amplitude width of the second current is greater than or equal to a predetermined ratio with respect to the amplitude width of the first current. The simulation device according to claim 9, specified as:   The simulation apparatus according to claim 1, wherein the means for performing the electromagnetic field analysis performs the electromagnetic field analysis by a finite time difference domain method. In a circuit board in which at least one of a signal line or a power supply line straddles an interlayer, a current of the first via of the signal line or the power supply line, which is a preset noise source, A simulation program for executing an analysis process on a current flowing through a predetermined second via corresponding to a current of one via,
The arithmetic unit creating an analysis model for the circuit board based on the board design data;
The arithmetic unit performing an electromagnetic field analysis on the analysis model;
The operation unit obtains a first current flowing through the first via and a second current flowing through the second via from the result of the electromagnetic field analysis;
The arithmetic unit compares the first current and the second current, the first via current, and the current flowing through the second via corresponding to the first via current. And a step of analyzing the simulation program.   A computer-readable recording medium storing the simulation program according to claim 12. Corresponding to the current of the first via of the signal line or the power supply line and the current of the first via, which is a preset noise source, in a circuit board in which at least one of the signal line or the power supply line straddles the layer A simulation method for analyzing a current flowing through a predetermined second via,
Creating an analysis model for the circuit board based on the board design data;
Performing electromagnetic field analysis on the analysis model;
Obtaining a first current flowing through the first via and a second current flowing through the second via from the result of the electromagnetic field analysis;
Comparing the first current and the second current and analyzing the current of the first via and the current flowing through the second via corresponding to the current of the first via; A simulation method comprising:

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