JP2008157917A - Circuit for detecting capacity difference - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit for detecting capacity difference capable of detecting fine capacity variability with higher speed and high precise, while reducing consumption current. <P>SOLUTION: A timing generator 14 of the capacity difference detecting circuit 100 outputs current change-over pulse signal controlling switching operation of a current change-over switch circuit 6, outputs gate pulse signal controlling chopper-type amplifier 7, during charging period when a first and a second charging voltages are charged into a first and a second variable capacity capacitors 2 and 3, so as to detect the first and the second charging voltages, outputs a first sample pulse signal controlling a first sample-and-hold circuit 8 so as to sample-hold the output signal of the chopper-type amplifier 7 during the period detecting the first charging voltage, and outputs a second sample pulse signal controlling a second sample holding circuit 9 so as to sample-hold the output signal of the chopper-type amplifier 7 during the period detecting the second charging voltage. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a capacitance difference detection circuit that detects a minute capacitance change of a MEMS (Micro Electro Mechanical Systems) sensor.

  As a capacitance difference detection circuit for detecting a minute capacitance change of a conventional MEMS sensor, for example, two LC oscillation circuits using the sensor capacitance, a mixer circuit for generating the difference frequency, and the frequency of the output of the mixer circuit as a voltage An F / V conversion (for example, PLL) circuit for conversion is provided (for example, see Patent Document 1).

  Since the conventional capacitance difference detection circuit uses, for example, a PLL circuit, there is a problem that the configuration is complicated and the power consumption is large.

  Another conventional capacitance difference detection circuit includes a main amplifier, a compensation voltage generation circuit, and a sample hold circuit to constitute a minute capacitance detection circuit. The two variable capacitors of the MEMS sensor are set in a discharge clear state, and in this state, the switched capacitor circuit outputs an offset voltage. A compensation voltage generation circuit detects the offset voltage via the main amplifier and generates a compensation voltage that makes the offset voltage zero, and a sample hold circuit samples and holds the compensation voltage. Next, the capacitance difference voltage in which noise and drift are suppressed by converting the capacitance difference between the two variable capacitance capacitors into a voltage and removing the offset voltage component of the capacitance difference voltage with the compensation voltage from the switched capacitor circuit. Amplified and output (for example, see Patent Document 2).

  In the above-described conventional capacitance difference detection circuit, the detection gain in the switched capacitor circuit varies depending on the gain and the value of the feedback capacitance on the detection circuit side, and the variation in the feedback capacitance becomes the detection gain variation.

  In the conventional capacitance difference detection circuit, the common terminal of the variable capacitor needs to be connected to an inverting input terminal (virtual ground point) that is very sensitive to the operation of the switched capacitor amplifier. Usually, since the wiring from the sensor to the inverting input terminal is long, it is extremely affected by disturbance. Further, the amplifier may oscillate due to the parasitic capacitance of the wiring, and detection may be impossible.

In the conventional capacitance difference detection circuit, many switch parts are arranged on the sensor input side in order to reduce the offset due to the parasitic capacitance of the feedback path switch of the switched capacitor amplifier. For this reason, variation in on-resistance of the switch and variation in switching time may cause a large offset.
JP 2005-326285 A Japanese Patent Laid-Open No. 9-72757

  An object of the present invention is to provide a capacitance difference detection circuit capable of detecting a minute capacitance change at higher speed and higher accuracy while reducing current consumption.

A capacitance difference detection circuit according to an embodiment of one aspect of the present invention includes:
Capacitors for detecting the voltages charged to the first variable capacitor and the second variable capacitor whose sum of the capacitance values is constant, and outputting signals corresponding to these voltages to the output terminals, respectively. A difference detection circuit,
A current source for supplying a charging current to the first and second variable capacitors;
The current source is connected between the current source and the first and second variable capacitors, and the current output from the current source is supplied complementarily to the first variable capacitor and the second variable capacitor. A current changeover switch circuit that performs a changeover operation to
A chopper type amplifier for detecting a first charging voltage charged in the first variable capacitor and a second charging voltage charged in the second variable capacitor;
A first sample-and-hold circuit connected to the output of the chopper-type amplifier and sampling and holding an output signal of the chopper-type amplifier corresponding to the first charging voltage;
A second sample and hold circuit connected to the output of the chopper type amplifier and sampling and holding the output signal of the chopper type amplifier corresponding to the second charging voltage;
A differential amplifying circuit in which an output of the first sample and hold circuit is input to an inverting input terminal, an output of the second sample and hold circuit is input to a non-inverting input terminal, and a signal is output to the output terminal; ,
A timing generator that outputs a signal based on an input clock signal,
The timing generator is
Outputting a current switching pulse signal for controlling the switching operation of the current switching circuit;
The first charging voltage is detected while the first variable capacitor is charged with the first charging voltage, and the second charging capacitor is charged with the second charging voltage. Outputting a gate pulse signal for controlling the chopper amplifier so as to detect the second charging voltage during a period of time,
Outputting a first sample pulse signal for controlling the first sample and hold circuit so as to sample and hold the output signal of the chopper amplifier during a period of detecting the first charging voltage;
A second sample pulse signal for controlling the second sample and hold circuit is output so as to sample and hold the output signal of the chopper amplifier during a period of detecting the second charging voltage. .

A capacitance difference detection circuit according to an embodiment according to another aspect of the present invention includes:
The respective voltages charged to the first variable capacitor and the second variable capacitor whose sum of the capacitance values is constant are detected, and a differential signal corresponding to these voltages is output to the first output terminal. A capacitance difference detection circuit that outputs to each of the second output terminals,
A current source for supplying current to the first and second variable capacitors;
The current source is connected between the current source and the first and second variable capacitors, and the current output from the current source is supplied complementarily to the first variable capacitor and the second variable capacitor. A current changeover switch circuit that performs a changeover operation to
A chopper type amplifier for detecting a first charging voltage charged in the first variable capacitor and a second charging voltage charged in the second variable capacitor;
A first sample-and-hold switch circuit having one end connected to the output of the chopper type amplifier, and a first capacitor connected between the other end of the first chopper switch circuit and the ground. A first sample-and-hold circuit that samples and holds the output of the chopper amplifier corresponding to the first charging voltage by charging the first capacitor as a voltage;
A second sample-and-hold switch circuit having one end connected to the output of the chopper-type amplifier, and a second capacitor connected between the other end of the second sample-and-hold switch circuit and the ground. A second sample-and-hold circuit that samples and holds the output of the chopper amplifier corresponding to the second charging voltage by charging the second capacitor as a voltage;
A first differential amplifier circuit in which a voltage of the first capacitor is input to a non-inverting input terminal and a signal is output to the first output terminal;
A second differential amplifier circuit in which a voltage of the second capacitor is input to a non-inverting input terminal and a signal is output to the second output terminal;
A first resistor connected between an output of the first differential amplifier circuit and an inverting input terminal;
A second resistor having one end connected to the inverting input terminal of the first differential amplifier circuit;
A third resistor connected between an output of the second differential amplifier circuit and an inverting input terminal and having the same resistance value as the first resistor;
A fourth resistor connected between the inverting input terminal of the second differential amplifier circuit and the other end of the second resistor, and having the same resistance value as the second resistor;
A timing generator that outputs a signal based on an input clock signal;
A control amplifier for controlling the current source by integrating and amplifying the voltage between the second resistor and the fourth resistor;
With
The timing generator is
Outputting a current switching pulse signal for controlling the switching operation of the current switching circuit;
The first charging voltage is detected while the first variable capacitor is charged with the first charging voltage, and the second charging capacitor is charged with the second charging voltage. Outputting a gate pulse signal for controlling the chopper amplifier so as to detect the second charging voltage during a period of time,
A first sample pulse for controlling a first sample and hold switch circuit of the first sample and hold circuit so as to sample and hold an output signal of the chopper amplifier during a period of detecting the first charging voltage. Output signal,
A second sample pulse for controlling a second sample and hold switch circuit of the second sample and hold circuit so as to sample and hold the output signal of the chopper amplifier during a period of detecting the second charging voltage; Output signal,
The control amplifier is
The charging current of the current source is controlled so that a voltage between the second resistor and the fourth resistor becomes a constant reference value.

A capacitance difference detection circuit according to an embodiment according to still another aspect of the present invention includes:
Capacitors for detecting the voltages charged to the first variable capacitor and the second variable capacitor whose sum of the capacitance values is constant, and outputting signals corresponding to these voltages to the output terminals, respectively. A difference detection circuit,
A current source for supplying a charging current to the first and second variable capacitors;
The current source is connected between the current source and the first and second variable capacitors, and the current output from the current source is supplied complementarily to the first variable capacitor and the second variable capacitor. A current changeover switch circuit that performs a changeover operation to
A first sample-and-hold circuit that samples and holds a signal corresponding to the first charging voltage;
A second sample and hold circuit that samples and holds a signal corresponding to the second charging voltage;
A differential amplifying circuit in which an output of the first sample and hold circuit is input to an inverting input terminal, an output of the second sample and hold circuit is input to a non-inverting input terminal, and a signal is output to the output terminal; ,
A timing generator that outputs a signal based on an input clock signal;
A summing amplifier for adding the output of the first sample and hold circuit and the output of the second sample and hold circuit and amplifying the addition result;
A control amplifier for controlling the charging current by outputting a control voltage obtained by integrating and amplifying the output of the summing amplifier to the current source so that the output of the summing amplifier becomes a constant reference value;
The timing generator is
Outputting a current switching pulse signal for controlling the switching operation of the current switching circuit;
Controlling the first sample and hold circuit so as to sample and hold a signal corresponding to the first charging voltage during a period in which the first charging capacitor is charged with the first charging voltage; Outputting a first sample pulse signal;
Controlling the second sample and hold circuit so as to sample and hold a signal corresponding to the second charging voltage during a period in which the second charging capacitor is charged in the second variable capacitor; A second sample pulse signal is output.

  According to the capacitance difference detection circuit of the present invention, it is possible to detect a minute capacitance change at higher speed and higher accuracy while reducing current consumption.

  Embodiments according to the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram illustrating a configuration of a main part of a capacitance difference detection circuit according to a first embodiment which is an aspect of the present invention.

  As shown in FIG. 1, the capacitance difference detection circuit 100 is charged to the first variable capacitor 2 and the second variable capacitor 3 that constitute the MEMS sensor 1 and whose sum of capacitance values is constant. Detect each voltage. Then, the capacitance difference detection circuit 100 outputs signals corresponding to the detected voltages to the output terminals 4 respectively.

  The capacitance difference detection circuit 100 includes a current source 5 that supplies a charging current to the first and second variable capacitors 2 and 3, and the current source 5 and the first and second variable capacitors 2 and 3. A current changeover switch circuit 6 connected therebetween.

  Here, the current source 5 is a constant current source.

  The current selector switch circuit 6 performs a switching operation for supplying the charging current Ic output from the current source 5 to the first variable capacitor 2 and the second variable capacitor 3 in a complementary manner.

  Further, the capacitance difference detection circuit 100 detects a first charging voltage V1 charged in the first variable capacitor 2 and a second charging voltage V2 charged in the second variable capacitor 3. An amplifier 7, a first sample and hold circuit 8 connected to the output of the chopper type amplifier 7, and a second sample and hold circuit 9 connected to the output of the chopper type amplifier 7 are provided.

  The chopper type amplifier 7 includes a first chopper switch circuit 7a having one end connected to the first variable capacitor 2, a second chopper switch circuit 7b connected to the second variable capacitor 3, Have

  Further, the chopper amplifier 7 has inputs connected to the other end of the first chopper switch circuit 7a and the other end of the second chopper switch circuit 7b, amplifies the input signal, and receives the first sample hold. An operational amplifier circuit 7 c that outputs to the circuit 8 and the second sample and hold circuit 9 is provided.

  Here, it is assumed that the gain of the operational amplifier circuit 7c is K0.

  The first sample and hold circuit 8 samples and holds the output signal of the chopper type amplifier 7 corresponding to the first charging voltage V1.

That is, the first sample and hold circuit 8 holds the peak voltage Vp1 (first charging voltage V1) expressed by the equation (1). It is assumed that the output current of the current source is Io, the charging period of the first and second variable capacitors is To, the normal capacity is Co, and the slight change in this capacity is ΔC. In the equation (1), ΔP = ΔC / Co and ΔP << 1 are approximated.
Vp1 (V1) = IcTo / (Co + ΔC) ≈IcTo (1−ΔP) / Co (1)

  The second sample and hold circuit 9 samples and holds the output signal of the chopper type amplifier 7 corresponding to the second charging voltage V2.

That is, the second sample and hold circuit 9 holds the peak voltage Vp2 (second charge voltage V2) expressed by the equation (2). In the equation (2), ΔP = ΔC / Co and ΔP << 1 as in the case of the equation (1).
Vp2 (V2) = IcTo / (Co−ΔC) ≈IcTo (1 + ΔP) / Co (2)

  Further, in the capacitance difference detection circuit 100, the output of the first sample hold circuit 8 is input to the inverting input terminal, the output of the second sample hold circuit 9 is input to the non-inverting input terminal, and the signal is output to the output terminal. 4 is provided.

  The capacitance difference detection circuit 100 is connected between the first reset switch circuit 11 connected between the first variable capacitor 2 and the ground, and between the second variable capacitor 3 and the ground. A second reset switch circuit 12.

Here, the gain of the differential amplifier circuit 10 is assumed to be K1. The output of the differential amplifier circuit 10 (that is, the output Vo of the capacitance difference detection circuit 100) is expressed as Expression (3) from Expression (1) and Expression (2).
Vo = K0K1 (−V1 + V2) ≈2IcToΔPK0K1 / Co Equation (3)

  When the first reset switch circuit 11 is turned on, the first variable capacitor 2 is electrically connected to the ground, and the electric charge charged in the first variable capacitor 2 is discharged. .

  When the second reset switch circuit 12 is turned on, the second variable capacitor 3 and the ground are brought into conduction, and the charge charged in the second variable capacitor 3 is discharged. .

  Further, the capacitance difference detection circuit 100 includes a timing generator 14 that outputs a signal for controlling each circuit configuration based on a clock signal input via the clock signal input terminal 13.

  The timing generator 14 outputs a current switching pulse signal P1 that controls the switching operation of the current selector switch circuit 6.

  Further, the timing generator 14 controls the chopper amplifier 7 so as to detect the first charging voltage V1 while the first variable capacitor 2 is charged with the first charging voltage V1. A pulse signal P4 is output. That is, the timing generator 14 controls the first chopper switch circuit 7a to turn on during the period when the first charging capacitor V1 is charged in the first variable capacitor 2. The signal P4 is output.

  Further, the timing generator 14 controls the chopper amplifier 7 so as to detect the second charging voltage V2 while the second variable capacitor 3 is charged with the second charging voltage V2. A pulse signal P5 is output. That is, the timing generator 14 controls to turn on the second chopper switch circuit 7b while the second variable capacitor 2 is charged with the second charging voltage V2. The signal P5 is output.

  In addition, the timing generator 14 controls the first sample and hold circuit 8 so as to sample and hold the output signal of the chopper type amplifier 7 during the period in which the first charging voltage V1 is detected. P6 is output.

  Further, the timing generator 14 controls the second sample and hold circuit 9 so as to sample and hold the output signal of the chopper type amplifier 7 during the period when the second charging voltage V2 is detected. Is output.

  Here, the operation of the capacitance difference detection circuit 100 having the above configuration will be described.

  FIG. 2 is a diagram showing an example of the waveform of the pulse signal output from the timing generator of FIG. 1 and the waveform of the voltage of the first and second variable capacitors.

  As shown in FIG. 2, at time t <b> 1, the current switching pulse signal P <b> 1 changes from “Low” to “High”, the current switching switch circuit 6 is switched, and the charging current Ic flows through the first variable capacitor 2. Further, the first reset pulse signal P2 changes from “High” to “Low”, and the first reset switch circuit 11 is turned off. As a result, charging of the first variable capacitor 2 is started and the terminal voltage of the first variable capacitor 2 is increased.

  At time t1, the second gate pulse signal P5 changes from “Low” to “High”, the second chopper switch circuit 7b is turned on, and the second charging voltage V2 is supplied to the operational amplifier circuit 7c. Is done. Then, when the second sample pulse signal P7 changes from “Low” to “High”, the second sample hold circuit 9 samples and holds the second charge voltage V2.

  Next, at time t2, the second reset pulse signal P3 changes from “Low” to “High”, and the second reset switch circuit 12 is turned on. As a result, the second variable capacitor 3 is discharged, and the terminal voltage of the second variable capacitor 3 becomes the ground VSS.

  Further, at time t2, the second gate pulse signal P5 changes from “High” to “Low”, and the second chopper switch circuit 7b is turned off. Further, the second sample pulse signal P7 changes from “High” to “Low”, and the sample hold of the second charging voltage V2 is completed.

  Next, at time t 3, the current switching pulse signal P 1 changes from “High” to “Low”, the current switching circuit 6 is switched, and the charging current Ic flows through the second variable capacitor 3. Further, the second reset pulse signal P3 changes from “High” to “Low”, and the second reset switch circuit 12 is turned off. As a result, charging of the second variable capacitor 3 is started and the terminal voltage of the second variable capacitor 3 rises.

  At time t3, the first gate pulse signal P4 changes from “Low” to “High”, the first chopper switch circuit 7a is turned on, and the first charging voltage V1 is supplied to the operational amplifier circuit 7c. Is done. Then, when the first sample pulse signal P6 changes from “Low” to “High”, the first sample hold circuit 8 samples and holds the first charge voltage V1.

  Next, at time t4, the first reset pulse signal P2 changes from “Low” to “High”, and the first reset switch circuit 11 is turned on. As a result, the first variable capacitor 2 is discharged, and the terminal voltage of the first variable capacitor 2 becomes the ground VSS.

  At time t4, the first gate pulse signal P4 changes from “High” to “Low”, and the first chopper switch circuit 7a is turned off. Further, the first sample pulse signal P6 changes from “High” to “Low”, and the sample hold of the first charging voltage V1 is completed.

  After the next time t5, the same operation as that after time t1 is performed.

  The timing generator 14 supplies the charging current Ic from the current source 5 to charge the first variable capacitor 2 (time t1 to time t3), and supplies the charging current Ic from the current source 5 for the first time. The current switching pulse signal P1 is output to the current switching circuit 6 so that the period (time t3 to time t5) for charging the two variable capacitors 3 is the same.

  In this way, charging and discharging are performed with a minute current alternately for a desired period of time on the differentially configured variable capacitor. Then, a sawtooth wave is generated at each terminal of the variable capacitor, and the peak value is alternately sampled and amplified by the same amplifier. After that, signals are alternately detected by the two sample hold circuits alternately from the amplified output, and the difference is calculated. Thereby, a minute capacitance change is converted into a voltage.

  By sharing the first stage operational amplifier circuit, the offset of the detection output can be removed.

  As described above, according to the capacitance difference detection circuit according to the present embodiment, a minute capacitance change can be detected at higher speed and with higher accuracy.

  The first gate pulse signal P4 and the first sample pulse signal P6 may be the same signal. Similarly, the second gate pulse signal P5 and the first sample pulse signal P7 may be the same signal.

  In the first embodiment, the current source that supplies current to the variable capacitor is described as a constant current source.

  In the present embodiment, a configuration for adjusting the current of the current source so that the output of the capacitance difference detection circuit becomes a constant reference value will be described.

  FIG. 3 is a diagram illustrating a configuration of a main part of the capacitance difference detection circuit according to the second embodiment which is an aspect of the present invention. In the figure, the same reference numerals as those in FIG. 1 of the first embodiment denote the same structures as in the first embodiment.

  As shown in FIG. 3, the capacitance difference detection circuit 200 adds the output of the first sample hold circuit 8 and the output of the second sample hold circuit 9 as compared with the first embodiment, and uses this added value. A control amplifier 15 that further integrates and amplifies and outputs the control voltage Vcnt to the current source 25 is further provided. Here, the current source 25 is a variable current source.

  The control amplifier 15 is operated so that the sum of the sample hold output V1 ′ and the sample hold output V2 ′ becomes a constant reference value (because the calculation is performed based on the reference voltage Vr as described below, the sum value is The charging current Ic of the current source 25 is controlled so that it becomes the reference voltage Vr. Here, the reference voltage Vr is set to zero.

Here, the 1st charging voltage V1 is represented by Formula (4).
V1 = Vr−ΔPVr (4)

In addition, the second charging voltage V2 is expressed by Expression (5).
V2 = Vr + ΔPVr (5)

Therefore, the output Vo of the capacitance difference detection circuit 200 is expressed by Expression (6).
Vo = K0K1 (−V1 + V2) = 2K0K1ΔPVr (6)

  Thus, the capacitance difference detection circuit 200 corrects the output variation caused by the MEMS sensor by controlling the charging current Ic so that the added value of the output becomes a constant value.

  Further, by controlling the added value to a constant value, the minute change rate is normalized, and the variation of the MEMS sensor is automatically corrected.

  The operation of the capacitance difference detection circuit 200 is the same as that of the first embodiment except for the operation of controlling the charging current Ic by the added value.

  As described above, according to the capacitance difference detection circuit according to the present embodiment, it is possible to detect a minute capacitance change at higher speed and higher accuracy while automatically correcting variations in output.

  In the second embodiment, an example of the configuration for adjusting the current of the current source so that the output of the capacitance difference detection circuit becomes a constant reference value has been described.

  In this embodiment, another configuration for adjusting the current of the current source so that the output of the capacitance difference detection circuit becomes a constant reference value will be described.

  FIG. 4 is a diagram illustrating the configuration of the main part of the capacitance difference detection circuit according to the third embodiment which is an aspect of the present invention. In the capacitance difference detection circuit 300 shown in FIG. 4, the configurations corresponding to the first and second sample and hold circuits, the operational amplifier circuit, and the control amplifier which are different from the capacitance difference detection circuit 200 of FIG. Since other than that is the same, it is omitted.

  As shown in FIG. 4, the capacitance difference detection circuit 300 is charged to the first variable capacitor 2 and the second variable capacitor 3 with which the sum of the capacitance values is constant. 2 charging voltages V1 and V2 are detected, and differential signals Vo and -Vo corresponding to the first and second charging voltages V1 and V2 are supplied to the first output terminal 34a and the second output terminal 34b, respectively. Output.

  The capacitance difference detection circuit 300 includes a first sample hold circuit 28, a second sample hold 29, and a control amplifier 215 in addition to the configuration described above that is omitted in FIG.

  The first sample-and-hold circuit 28 includes a first sample-and-hold switch circuit 28a having one end connected to the output of the chopper type amplifier 7, and the other end of the first sample-and-hold switch circuit 28a and the ground VSS. And a first capacitor 28b connected therebetween.

  The first sample hold circuit 28 samples and holds the output of the chopper amplifier 7 corresponding to the first charge voltage V1 by charging the first capacitor 28b as a voltage.

  The second sample and hold circuit 29 includes a second sample and hold switch circuit 29a having one end connected to the output of the chopper type amplifier 7, and the other end of the second sample and hold switch circuit 29a and the ground VSS. And a second capacitor 29b connected therebetween.

  The second sample and hold circuit 29 samples and holds the output of the chopper type amplifier 7 corresponding to the second charging voltage V2 by charging the second capacitor 29b as a voltage.

  The capacitance difference detection circuit 300 includes a first differential amplifier circuit 16a that receives the voltage of the first capacitor 28b at the non-inverting input terminal and outputs the signal Vo to the first output terminal 34a; And a second differential amplifier circuit 16b that inputs a voltage of the capacitor 29b to the non-inverting input terminal and outputs a signal to the second output terminal 34b.

  In addition, the capacitance difference detection circuit 300 has a first resistor 17 connected between the output of the first differential amplifier circuit 16a and the inverting input terminal, and an inverting input terminal of the first differential amplifier circuit 16a. A second resistor 18 having one end connected thereto, and a third resistor 19 connected between the output of the second differential amplifier circuit 16b and the inverting input terminal and having the same resistance value R2 as the first resistor 17 And a fourth resistor 20 connected between the inverting input terminal of the second differential amplifier circuit 16b and the other end of the second resistor 18 and having the same resistance value R1 as the second resistor 18. Prepare.

  The timing generator 14 (similar to that shown in FIG. 3) sets the first sample and hold switch circuit 28a so as to sample and hold the output signal of the chopper type amplifier 7 during the period of detecting the first charging voltage V1. A first sample pulse signal P6 to be controlled is output.

  Further, the timing generator 14 controls the second sample and hold switch circuit 29a so as to sample and hold the output signal of the chopper type amplifier 7 during the period of detecting the second charging voltage V2. The signal P7 is output.

  Here, the control amplifier 215 controls the current source 25 by integrating and amplifying the voltage between the second resistor 18 and the fourth resistor 20. This control amplifier 215 is calculated so that the sum of the sample hold output V1 ′ and the sample hold output V2 ′ becomes a constant reference value (here, zero), that is, the calculation is performed with reference to the reference voltage Vr. The charging current Ic of the current source 25 is controlled so that the value becomes the reference voltage Vr.

Here, the output Vo of the capacitance difference detection circuit 300 is expressed by Expression (7).
Vo = R2 / R1 (Vp1-Vp2) (7)

  As described above, the capacitance difference detection circuit 300 has the configuration including the operational amplifier circuit as the instrumentation amplifier configuration, so that the first and second sample and hold circuits 28 and 29 have the first and second samples. The holding switch circuits 28a and 29a and the first and second capacitors can be used alone. That is, the configuration of the sample and hold circuit can be simplified.

  The operation of the capacitance difference detection circuit 300 is the same as that of the second embodiment.

  As described above, according to the capacitance difference detection circuit according to the present embodiment, it is possible to detect a minute capacitance change at higher speed and higher accuracy while correcting output variations.

  In the second embodiment, the configuration in which the current of the current source is adjusted so that the output of the capacitance difference detection circuit becomes a constant reference value has been described.

  In the fourth embodiment, another configuration example for adjusting the current of the current source so as to improve the linearity of the output change of the capacitance difference detection circuit with respect to the capacitance change of the MEMS sensor will be described.

  FIG. 5 is a diagram illustrating the configuration of the main part of the capacitance difference detection circuit according to the fourth embodiment which is an aspect of the present invention. In the drawing, the same reference numerals as those in FIG. 2 of the second embodiment denote the same structures as in the second embodiment.

  As shown in FIG. 5, the capacitance difference detection circuit 400 is charged to the first variable capacitor 2 and the second variable capacitor 3 that constitute the MEMS sensor 1 and whose sum of capacitance values is constant. Detect each voltage. Then, the capacitance difference detection circuit 400 outputs signals corresponding to the detected voltages to the output terminals 4 respectively.

  The capacitance difference detection circuit 400 includes a current source 25 that supplies a charging current Ic to the first and second variable capacitance capacitors 2 and 3, and the current source 25 and the first and second variable capacitance capacitors 2 and 3. And a current changeover switch circuit 6 connected between the two.

  Here, the current source 25 is a variable current source.

  The current selector switch circuit 6 performs a switching operation for supplying the charging current Ic output from the current source 25 to the first variable capacitor 2 and the second variable capacitor 3 in a complementary manner.

  The capacitance difference detection circuit 400 includes a first sample and hold circuit 8 having an input connected to the first variable capacitor 2. The first sample and hold circuit 8 samples and holds the first charging voltage V1 charged in the first variable capacitor 2 in accordance with the first sample pulse signal P6.

  Further, the capacitance difference detection circuit 400 includes a second sample and hold circuit 9 whose input is connected to the second variable capacitor 3. The second sample and hold circuit 9 samples and holds the second charging voltage V2 charged in the second variable capacitor 2 in accordance with the second sample pulse signal P7.

  As described above, the first sample hold circuit 8 samples and holds a signal corresponding to the first charge voltage V1. That is, the first sample and hold circuit 8 holds the peak voltage Vp1 (first charging voltage V1) expressed by the above-described equation (1).

  The second sample and hold circuit 9 samples and holds a signal corresponding to the second charging voltage V2. That is, the second sample and hold circuit 9 holds the peak voltage Vp2 (second charge voltage V2) expressed by the above-described equation (2).

  Further, in the capacitance difference detection circuit 400, the output of the first sample hold circuit 8 is input to the inverting input terminal, the output of the second sample hold circuit 9 is input to the non-inverting input terminal, and the signal is output to the output terminal. 4 is provided.

Here, the gain of the differential amplifier circuit 10 is assumed to be K1. The output of the differential amplifier circuit 10 (that is, the output Vo of the capacitance difference detection circuit 400) is expressed as Expression (8).
Vo = K1 (−V1 + V2) (8)

  The capacitance difference detection circuit 400 is connected between the first reset switch circuit 11 connected between the first variable capacitor 2 and the ground, and between the second variable capacitor 3 and the ground. A second reset switch circuit 12.

  When the first reset switch circuit 11 is turned on, the first variable capacitor 2 is electrically connected to the ground, and the electric charge charged in the first variable capacitor 2 is discharged. .

  When the second reset switch circuit 12 is turned on, the second variable capacitor 3 and the ground are brought into conduction, and the charge charged in the second variable capacitor 3 is discharged. .

  Further, the capacitance difference detection circuit 400 includes a timing generator 14 that outputs a signal for controlling each circuit configuration based on a clock signal input via the clock signal input terminal 13.

  The timing generator 14 outputs a current switching pulse signal P1 that controls the switching operation of the current selector switch circuit 6.

  In addition, the timing generator 14 samples and holds the signal corresponding to the first charging voltage V1 during the period when the first charging capacitor V1 is charged in the first variable capacitor 2. The first sample pulse signal P6 for controlling the sample hold circuit 8 is output.

  Further, the timing generator 14 samples and holds the signal corresponding to the second charging voltage V2 during the period in which the second charging capacitor V2 is charged in the second variable capacitor 3. A second sample pulse signal P7 for controlling the sample hold circuit 9 is output.

  Further, the capacitance difference detection circuit 400 adds the output of the first sample hold circuit 8 and the output of the second sample hold circuit 9, and further adds an addition amplifier 401 that amplifies the added value and outputs the voltage Vc. Prepare. Here, the gain K2 of the summing amplifier 401 is set to 0.5, for example.

  The capacitance difference detection circuit 400 includes a control amplifier 415 that compares the voltage Vc output from the addition amplifier 401 with the set voltage Vs and controls the current source 25 so that the voltage Vc and the set voltage Vs are equal.

  In this control amplifier 415, the sum value (output of the summing amplifier 401) of the sample hold output V1 ′ (first charging voltage V1) and the sample hold output V2 ′ (second charging voltage V2) becomes a constant reference value. Thus, the control voltage Vcnt obtained by integrating and amplifying the output of the summing amplifier 401 is output to the current source 25. Thereby, the control amplifier 415 controls the charging current Ic. Here, for example, the control amplifier 415 controls the charging current Ic of the current source so that ½ of the added value becomes the set voltage Vs.

  Here, the operation of the capacitance difference detection circuit 400 having the above configuration will be described.

  FIG. 6 is a diagram illustrating an example of the waveform of the pulse signal output from the timing generator of FIG. 5 and the waveform of the voltage of the first and second variable capacitors.

  As shown in FIG. 6, at time t <b> 1, the current switching pulse signal P <b> 1 changes from “Low” to “High” and the current switching circuit 6 is switched, and the charging current Ic flows through the first variable capacitor 2. Further, the first reset pulse signal P2 changes from “High” to “Low”, and the first reset switch circuit 11 is turned off. As a result, charging of the first variable capacitor 2 is started and the terminal voltage of the first variable capacitor 2 is increased.

  At time t1, the second sample pulse signal P7 changes from “Low” to “High”, so that the second sample hold circuit 9 samples and holds the second charge voltage V2.

  Next, at time t2, the second reset pulse signal P3 changes from “Low” to “High”, and the second reset switch circuit 12 is turned on. As a result, the second variable capacitor 3 is discharged, and the terminal voltage of the second variable capacitor 3 becomes the ground VSS.

  Further, at time t2, the second sample pulse signal P7 changes from “High” to “Low”, and the sampling and holding of the second charging voltage V2 is completed.

  Next, at time t 3, the current switching pulse signal P 1 changes from “High” to “Low”, the current switching circuit 6 is switched, and the charging current Ic flows through the second variable capacitor 3. Further, the second reset pulse signal P3 changes from “High” to “Low”, and the second reset switch circuit 12 is turned off. As a result, charging of the second variable capacitor 3 is started and the terminal voltage of the second variable capacitor 3 rises.

  At time t3, the first sample pulse signal P6 changes from “Low” to “High”, so that the first sample hold circuit 8 samples and holds the first charging voltage V1.

  Next, at time t4, the first reset pulse signal P2 changes from “Low” to “High”, and the first reset switch circuit 11 is turned on. As a result, the first variable capacitor 2 is discharged, and the terminal voltage of the first variable capacitor 2 becomes the ground VSS.

  Further, at time t4, the first sample pulse signal P6 changes from “High” to “Low”, and the sampling and holding of the first charging voltage V1 is completed.

  After the next time t5, the same operation as that after time t1 is performed.

  The timing generator 14 supplies the charging current Ic from the current source 25 to charge the first variable capacitor 2 (time t1 to time t3), and supplies the charging current Ic from the current source 25 for the first time. The current switching pulse signal P1 is output to the current switching circuit 6 so that the period (time t3 to time t5) for charging the two variable capacitors 3 is the same.

  In this way, charging and discharging are performed with a minute current alternately for a desired period of time on the differentially configured variable capacitor. Then, a sawtooth wave is generated at each terminal of the variable capacitor, and the peak value is alternately sampled and amplified by the same amplifier. After that, signals are alternately detected by the two sample hold circuits alternately from the amplified output, and the difference is calculated. Thereby, a minute capacitance change is converted into a voltage.

  Here, the characteristics of the capacitance difference detection circuit 400 having the configuration and functions as described above will be examined.

  First, for comparison, the characteristics of a conventional capacitance difference detection circuit are examined. Note that the current source that supplies the charging current of the conventional capacitance difference detection circuit is a constant current source.

  FIG. 7 is a diagram showing the relationship between each voltage of the conventional capacitance difference detection circuit and the capacitance change rate of the variable capacitance capacitor of the MEMS sensor. As shown in FIG. 7, since the charging current is constant, when the capacitance change rate of the variable capacitor increases, nonlinearity becomes significant between the charging voltages V1 and V2 of the capacitance difference detection circuit and the output Vo.

  That is, in the conventional capacitance difference detection circuit, when the capacitance change of the variable capacitor increases, it becomes difficult to accurately detect the capacitance difference.

  Next, the characteristics of the capacitance difference detection circuit 400 according to the present embodiment will be examined. FIG. 8 is a diagram illustrating a relationship between each voltage of the capacitance difference detection circuit and the capacitance change rate of the variable capacitor of the MEMS sensor.

Assuming that the charging current is Ic and the charging period is Tc, each detection voltage is V1 = IcTc / (9)
V2 = IcTc / (C−ΔC) (10)
The added voltage Vc is
Vc = K2 (V1 + V2)
= 2K2IcTcC / ((C + ΔC) (C−ΔC))

As described above, if Vc = Vs is maintained by the control of the charging current Ic of the control amplifier 415, the output Vc of the adding amplifier 401 satisfies Expression (9).
Vs = Vc = 2K2IcTcC / ((C + ΔC) (C−ΔC)) (11)
The charging current Ic to be controlled is assumed that Vs = 1 and K2 = 0.5. Ic = − ((C + ΔC) (C−ΔC) / TcC) (12)
The detection voltage V1 is expressed by Expression (13) from Expressions (9) and (12).
V1 = (C−ΔC) / C (13)
The detection voltage V2 is expressed by Expression (14) from Expressions (10) and (12).
V2 = (C + ΔC) / C (14)

Therefore, the output Vo of the capacitance difference detection circuit 400 is a voltage output proportional to ΔC expressed by the equation (15) from the equations (13) and (14).
Vo = V1 + V2
= -2ΔC Expression (15)

  That is, if Vc = Vs is maintained by controlling the charging current Ic of the control amplifier 415, linearity between the output Vo of the capacitance difference detection circuit 400 and the charging voltages V1 and V2 is realized.

  In this way, the capacitance difference detection circuit 400 controls the charging current Ic so that the added value of the sample hold output becomes a constant value, and the linearity between the output Vo and the charging voltages V1 and V2 is improved.

  Therefore, the capacitance difference detection circuit 400 according to the present embodiment can detect the capacitance difference more accurately even when the capacitance change of the variable capacitance capacitor becomes larger than that of the conventional capacitance difference detection circuit.

  As described above, according to the capacitance difference detection circuit according to the present embodiment, the capacitance change can be detected at higher speed and with higher accuracy.

  Note that the chopper type amplifier shown in the first and second embodiments may be applied to the present embodiment. In this case, it is also possible to apply the instrumentation amplifier configuration shown in the third embodiment.

It is a figure which shows the structure of the principal part of the capacity | capacitance difference detection circuit based on Example 1 which is 1 aspect of this invention. FIG. 3 is a diagram illustrating an example of a waveform of a pulse signal output from the timing generator of FIG. 1 and a waveform of a voltage of first and second variable capacitors. It is a figure which shows the structure of the principal part of the capacity | capacitance difference detection circuit based on Example 2 which is 1 aspect of this invention. It is a figure which shows the structure of the principal part of the capacity | capacitance difference detection circuit based on Example 3 which is 1 aspect of this invention. It is a figure which shows the structure of the principal part of the capacity | capacitance difference detection circuit based on Example 4 which is 1 aspect of this invention. It is a figure which shows an example of the waveform of the pulse signal which the timing generator of FIG. 5 outputs, and the waveform of the voltage of the 1st, 2nd variable capacitance capacitor. It is a figure which shows the relationship between each voltage of the conventional capacitance difference detection circuit, and the capacitance change rate of the variable capacitor of a MEMS sensor. It is a figure which shows the relationship between each voltage of a capacity | capacitance difference detection circuit, and the capacitance change rate of the variable capacitor of a MEMS sensor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 MEMS sensor 2 1st variable capacitance capacitor 3 2nd variable capacitance capacitor 4 Output terminals 5, 25 Current source 6 Current changeover switch circuit 7 Chopper type amplifier 7a First chopper switch circuit 7b Second chopper switch circuit 7c Operational amplifier circuits 8, 28 First sample hold circuit 9, 29 Second sample hold circuit 10 Differential amplifier circuit 11 First reset switch circuit 12 Second reset switch circuit 13 Clock signal input terminal 14 Timing Generator 15, 215, 415 Control amplifier 16a First differential amplifier circuit 16b Second differential amplifier circuit 17 First resistor 18 Second resistor 19 Third resistor 20 Fourth resistor 28a First sample and hold Switch circuit 28b first capacitor 29a second sample and hold switch circuit 29b second capacitor 34a the first output terminal 34b second output terminals 100, 200, 300 capacitance difference detecting circuit 401 summing amplifier

Claims (7)

Capacitors for detecting the voltages charged to the first variable capacitor and the second variable capacitor whose sum of the capacitance values is constant, and outputting signals corresponding to these voltages to the output terminals, respectively. A difference detection circuit,
A current source for supplying a charging current to the first and second variable capacitors;
The current source is connected between the current source and the first and second variable capacitors, and the current output from the current source is supplied complementarily to the first variable capacitor and the second variable capacitor. A current changeover switch circuit that performs a changeover operation to
A chopper type amplifier for detecting a first charging voltage charged in the first variable capacitor and a second charging voltage charged in the second variable capacitor;
A first sample-and-hold circuit connected to the output of the chopper-type amplifier and sampling and holding an output signal of the chopper-type amplifier corresponding to the first charging voltage;
A second sample and hold circuit connected to the output of the chopper type amplifier and sampling and holding the output signal of the chopper type amplifier corresponding to the second charging voltage;
A differential amplifying circuit in which an output of the first sample and hold circuit is input to an inverting input terminal, an output of the second sample and hold circuit is input to a non-inverting input terminal, and a signal is output to the output terminal; ,
A timing generator that outputs a signal based on an input clock signal,
The timing generator is
Outputting a current switching pulse signal for controlling the switching operation of the current switching circuit;
The first charging voltage is detected while the first variable capacitor is charged with the first charging voltage, and the second charging capacitor is charged with the second charging voltage. Outputting a gate pulse signal for controlling the chopper amplifier so as to detect the second charging voltage during a period of time,
Outputting a first sample pulse signal for controlling the first sample and hold circuit so as to sample and hold the output signal of the chopper amplifier during a period of detecting the first charging voltage;
Outputting a second sample pulse signal for controlling the second sample and hold circuit so as to sample and hold the output signal of the chopper type amplifier during a period of detecting the second charge voltage. Capacitance difference detection circuit. A control amplifier for adding the output of the first sample and hold circuit and the output of the second sample and hold circuit, and integrating and amplifying the added value to control the current source;
The capacity difference detection circuit according to claim 1, wherein the current source controls the charging current so that the added value becomes a constant reference value. The timing generator supplies the charging current from the current source to charge the first variable capacitor, and supplies the charging current from the current source to charge the second variable capacitor. The capacitance difference detection circuit according to claim 2, wherein a current switching pulse signal is output to the current switching circuit so that the period is the same. The chopper amplifier is
A first chopper switch circuit having one end connected to the first variable capacitor and controlled by the timing generator;
A second chopper switch circuit connected to the second variable capacitor and controlled by the timing generator; the other end of the first chopper switch circuit; and the other end of the second chopper switch circuit And an operational amplifier circuit that amplifies the input signal and outputs the amplified signal to the first sample hold circuit and the second sample hold circuit,
The timing generator is
Outputting a first gate pulse signal for turning on the first chopper switch circuit during a period when the first charging voltage is charged in the first variable capacitor;
The second gate pulse signal for turning on the second chopper switch circuit is output during a period when the second charging voltage is charged in the second variable capacitor. 4. The capacitance difference detection circuit according to any one of 1 to 3. The respective voltages charged to the first variable capacitor and the second variable capacitor whose sum of the capacitance values is constant are detected, and a differential signal corresponding to these voltages is output to the first output terminal. A capacitance difference detection circuit that outputs to each of the second output terminals,
A current source for supplying current to the first and second variable capacitors;
The current source is connected between the current source and the first and second variable capacitors, and the current output from the current source is supplied complementarily to the first variable capacitor and the second variable capacitor. A current changeover switch circuit that performs a changeover operation to
A chopper type amplifier for detecting a first charging voltage charged in the first variable capacitor and a second charging voltage charged in the second variable capacitor;
A first sample-and-hold switch circuit having one end connected to the output of the chopper type amplifier, and a first capacitor connected between the other end of the first chopper switch circuit and the ground. A first sample-and-hold circuit that samples and holds the output of the chopper amplifier corresponding to the first charging voltage by charging the first capacitor as a voltage;
A second sample-and-hold switch circuit having one end connected to the output of the chopper-type amplifier, and a second capacitor connected between the other end of the second sample-and-hold switch circuit and the ground. A second sample-and-hold circuit that samples and holds the output of the chopper amplifier corresponding to the second charging voltage by charging the second capacitor as a voltage;
A first differential amplifier circuit in which a voltage of the first capacitor is input to a non-inverting input terminal and a signal is output to the first output terminal;
A second differential amplifier circuit in which a voltage of the second capacitor is input to a non-inverting input terminal and a signal is output to the second output terminal;
A first resistor connected between an output of the first differential amplifier circuit and an inverting input terminal;
A second resistor having one end connected to the inverting input terminal of the first differential amplifier circuit;
A third resistor connected between an output of the second differential amplifier circuit and an inverting input terminal and having the same resistance value as the first resistor;
A fourth resistor connected between the inverting input terminal of the second differential amplifier circuit and the other end of the second resistor, and having the same resistance value as the second resistor;
A timing generator that outputs a signal based on an input clock signal;
A control amplifier for controlling the current source by integrating and amplifying the voltage between the second resistor and the fourth resistor;
With
The timing generator is
Outputting a current switching pulse signal for controlling the switching operation of the current switching circuit;
The first charging voltage is detected while the first variable capacitor is charged with the first charging voltage, and the second charging capacitor is charged with the second charging voltage. Outputting a gate pulse signal for controlling the chopper amplifier so as to detect the second charging voltage during a period of time,
A first sample pulse for controlling a first sample and hold switch circuit of the first sample and hold circuit so as to sample and hold an output signal of the chopper amplifier during a period of detecting the first charging voltage. Output signal,
A second sample pulse for controlling a second sample and hold switch circuit of the second sample and hold circuit so as to sample and hold the output signal of the chopper amplifier during a period of detecting the second charging voltage; Output signal,
The control amplifier is
The capacitance difference detection circuit characterized by controlling the charging current of the current source so that a voltage between the second resistor and the fourth resistor becomes a constant reference value. Capacitors for detecting the voltages charged to the first variable capacitor and the second variable capacitor whose sum of the capacitance values is constant, and outputting signals corresponding to these voltages to the output terminals, respectively. A difference detection circuit,
A current source for supplying a charging current to the first and second variable capacitors;
The current source is connected between the current source and the first and second variable capacitors, and the current output from the current source is supplied complementarily to the first variable capacitor and the second variable capacitor. A current changeover switch circuit that performs a changeover operation to
A first sample-and-hold circuit that samples and holds a signal corresponding to the first charging voltage;
A second sample and hold circuit that samples and holds a signal corresponding to the second charging voltage;
A differential amplifying circuit in which an output of the first sample and hold circuit is input to an inverting input terminal, an output of the second sample and hold circuit is input to a non-inverting input terminal, and a signal is output to the output terminal; ,
A timing generator that outputs a signal based on an input clock signal;
A summing amplifier for adding the output of the first sample and hold circuit and the output of the second sample and hold circuit and amplifying the addition result;
A control amplifier for controlling the charging current by outputting a control voltage obtained by integrating and amplifying the output of the summing amplifier to the current source so that the output of the summing amplifier becomes a constant reference value;
The timing generator is
Outputting a current switching pulse signal for controlling the switching operation of the current switching circuit;
Controlling the first sample and hold circuit so as to sample and hold a signal corresponding to the first charging voltage during a period in which the first charging capacitor is charged with the first charging voltage; Outputting a first sample pulse signal;
Controlling the second sample and hold circuit so as to sample and hold a signal corresponding to the second charging voltage during a period in which the second charging capacitor is charged in the second variable capacitor; A capacitance difference detection circuit characterized by outputting a second sample pulse signal. The capacitance difference detection circuit according to claim 1, wherein the first variable capacitor and the second variable capacitor constitute a MEMS sensor.

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