JP2008152176A - Display device drive circuit, display device, electronic equipment, display device driving method, and computer program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that a cost and power consumption are increased while rise and fall properties can be improved when it is a conventional method arranging drivers on both the sides of a data line. <P>SOLUTION: A display device drive circuit for driving an active matrix drive type display device includes a scanning line drive part for controlling all switching elements in an off state in a first period in the head of each horizontal scanning period by controlling all switching elements for controlling writing of signal voltage to corresponding pixels, and controlling all the switching elements in an on state in a second period subsequent to the first period positioned; and a data line drive part for applying the signal voltage of each horizontal scanning period to the corresponding data line during the first and second periods. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The invention described in this specification relates to a driving technique of an active matrix driving type display device. Note that the present invention has aspects as a display device driving circuit, a display device, an electronic apparatus, a display device driving method, and a computer program.

  The trend toward larger screens and higher definition of flat panel display devices is increasing. Along with this, signal delay with respect to the driving frequency of the panel display element and deterioration of the rising / falling characteristics (frequency characteristics) of the driving signal have become problems.

  FIG. 1 shows an example of drive signals of an active matrix drive type display device. FIG. 1 shows an example of a drive signal when the data line is driven from one side. As shown in FIG. 1, writing of the signal voltage Vin (FIG. 1A) to each pixel is performed by a write signal WS (FIG. 1B to FIG. 1) synchronized with the horizontal synchronization signal HS (FIG. 1E). (D)) are executed in sequence with the rise.

  By the way, in this driving method, the waveform of the signal voltage Vin becomes dull as the writing frequency increases (indicated by a broken line in FIG. 1A). For this reason, it is difficult to accurately write the signal voltage Vin to the capacitor in the display element.

Therefore, a method of driving the drive line from both sides has been proposed for the purpose of improving the rise / fall characteristics with respect to the drive frequency.
FIG. 2 shows a screen configuration example of the display device 1. As shown in FIG. 2, two data line drivers 5 are arranged on both upper and lower sides of the display panel 3.

The selection of the pixel 11 to which the signal voltage Vin is to be written is performed by the scanning line driver 7 that outputs the write signal WS.
JP 2005-345910 A

  However, the method of driving the data lines from the both sides by the two data line drivers 5 has a positive aspect that can improve the rising and falling characteristics, but has a negative aspect that increases the manufacturing cost and power consumption. Moreover, there is a negative aspect that the power consumption tends to increase as the drive frequency increases. Accordingly, there is a need for a proposal of a technology that is excellent in balance between improvement of various characteristics and cost.

  Therefore, the inventor has, as a display device driving circuit for driving an active matrix driving type display device, (a) a switch for controlling writing of a signal voltage to a corresponding pixel in a first period located at the head of each horizontal scanning period. A scanning line driver that controls the elements all at once and controls the switch elements all at once in a second period following the first period; and (b) during the first and second periods, A device having a data line driving section for applying a signal voltage in each horizontal scanning period to a corresponding data line is proposed.

  In the case of the invention proposed by the inventor, a first period (a period during which the capacitance component in the pixel is not visible from the data line side) in which the switch element for controlling writing of the signal voltage to each pixel is controlled to be off is the horizontal scanning period. The signal voltage is applied to the data line from this period.

Of course, the application of the signal voltage is continued after the switch element for controlling the writing of the signal voltage is turned on.
That is, in the invention proposed by the inventor, the potential of the data line can be made as close as possible to the signal voltage within the leading period with a small time constant.

  As a result, the voltage change of the data line to be driven by the data line driver becomes small during the second period (the period after the switch element is turned on) where the capacitance seen from the data line driver becomes large. For this reason, if the voltage change to the target potential is small, the potential of the data line can be driven to the signal voltage within a short time even if the time constant is large. Therefore, improvement of the rising and falling characteristics of the signal voltage with respect to the driving frequency is realized.

Hereinafter, an example of drive control suitable when the invention is applied to an active matrix drive type organic EL display device will be described.
In addition, the well-known or well-known technique of the said technical field is applied to the part which is not illustrated or described in particular in this specification.
Moreover, the form example demonstrated below is one form example of invention, Comprising: It is not limited to these.

(A) Form example 1
(A-1) Overall Configuration of Organic EL Display Device FIG. 3 shows the main components of the organic EL display device 21. The organic EL display device 21 includes an organic EL panel 23, a data line driver 25, a scanning line driver 27, and a timing generator 29 as main components.

(A-2) Configuration of Each Part The organic EL panel 23 is a self-luminous display panel in which the pixels 31 are arranged in a matrix according to the panel resolution. In the case of this embodiment, the organic EL panel 23 is for color display, and the pixels 31 are arranged for each emission color. However, in the case where the pixel 31 is an organic EL element having a structure in which a plurality of light emitting layers are stacked, one pixel 31 corresponds to a plurality of light emitting colors.

FIG. 4 shows a connection relationship between the pixel 31 formed at the intersection of the data line DL and the scanning line WL and the driving circuit.
The pixel 31 includes a switch element T1, a capacitor C, a current drive element T2, and an organic EL element D.

  The switch element T1 is a transistor that controls writing of the signal voltage applied to the data line DL to the capacitor C. The write signal WS is supplied from the scanning line driver 27 to each switch element T1 through the scanning line WL.

  The capacitor C is a storage element that holds the written signal voltage Vin for one frame. By using the capacitor C, even when the signal voltage Vin is written line-sequentially, the same light emission mode as that in the case of writing by the frame sequential scanning method is realized.

  The current drive element T2 is a transistor that supplies a drive current corresponding to the signal voltage Vin held in the capacitor C to the organic EL element D. The drive current value here is determined by the voltage Vgs applied between the gate and source of the current drive element T2.

The data line driver 25 is a circuit device that drives the data line DL of the organic EL panel 23. FIG. 5 shows an internal configuration example of the data line driver 25.
The data line driver 25 includes a shift register unit 251, a latch unit 253, a D / A conversion unit 255, and a latch unit 257.

  The shift register unit 251 executes a process of sequentially shifting the gradation values (signal values) Din that are sequentially input in the horizontal direction and outputting them to the latch unit 253 in units of one scanning line. The latch unit 253 executes a process of outputting the gradation value (signal value) Din read out in units of pixels to the D / A conversion unit 255. The signal voltage Vin after D / A conversion is output to the latch unit 257 for each corresponding data line DL.

  The scanning line driver 27 is a circuit device that provides a write timing of the signal voltage Vin. The scanning line driver 27 controls one scanning line to be selectively writable every time the horizontal synchronization signal HS is input.

  This control signal is the write signal WS. However, the scanning line driver 27 used in this embodiment applies the ON potential to the switch element T1 for a period Tb shorter than the horizontal scanning period T0 (corresponding to the “second period” in the claims).

  Note that a period Ta (corresponding to a “first period” in the claims) for turning off the switch element T1 is disposed at the head of the horizontal scanning period T0. This period Ta corresponds to a period in which the pixel 31 is disconnected from the data line DL. Therefore, as shown in FIG. 6A, only the data line DL is driven by the data line driver 25.

  By the way, the wiring capacity of the data line DL is considerably smaller than the total capacity Ctotal in the pixel circuit (capacitor C for storing the signal voltage and parasitic capacity in the pixel circuit). For this reason, the rising / falling characteristics with respect to the driving frequency in the head period Ta are improved. For reference, FIG. 7 shows various capacitance components existing in the pixel circuit.

  On the other hand, during the period Tb (the ON period of the switch element T1), the pixel 31 is connected to the data line DL. Therefore, as shown in FIG. 6B, it appears that the data line DL and the total capacity Ctotal in the pixel circuit are connected to the data line driver 25.

The total capacity Ctotal is considerably larger than the wiring capacity CL. Accordingly, the rising / falling characteristics with respect to the driving frequency in the period Tb are deteriorated.
However, the potential VD of the data line DL is driven to a potential close to the signal voltage Vin to be written. Therefore, the data line driver 25 only needs to drive the voltage difference ΔV between the potential VD and the signal voltage Vin immediately before switching the switch element T1 to the on state.

  Since the difference voltage ΔV is generally small, the potential of the data line DL can be driven to the signal voltage V in a short time. As a result, even if the horizontal scanning period is shortened by improving the resolution or the like (that is, even when the driving frequency is increased), the potential VD of the data line can be driven to the signal voltage Vin in a short time, It becomes possible to reliably write the signal voltage Vin.

FIG. 8 shows an internal configuration example of the scanning line driver 27 that enables the above-described writing. FIG. 9 shows an internal signal example of the scanning line driver 27.
The scanning line driver 27 includes a shift register 271, a latch 273, an AND circuit 275, and a buffer circuit 277.
The shift register 271 includes register stages having stages corresponding to the vertical resolution.

A write signal WS (FIG. 9A) is inputted to the register stage at the head position at the head of each frame. The signal width T0 of the write signal WS is the same as the horizontal scanning period.
The write signal WS is sequentially output to the next stage with a clock (FIG. 9B) synchronized with the horizontal synchronization signal HS (FIG. 9F), and is output to the latch 273 as the write signal WS corresponding to each scanning line DL. Is done. The latch 273 adjusts the timing of the write signal WS.

  The logical product circuit 275 calculates the logical product of the write signal WS (FIG. 9A) and the write enable signal WSenable (FIG. 9C). For example, the write enable signal WSenable is generated by logically inverting a pulse having a pulse width corresponding to the first period Ta.

FIG. 9D shows a write signal WS (I) used for selecting the I-th scanning line DL, and FIG. 9E shows a write signal WS (I + 1) used for selecting the I + 1-th scanning line DL. ).
Incidentally, the rising start time of the write enable signal WSenable is set in consideration of the rising time of the data line DL.

  In this embodiment, the ratio of the period Ta corresponding to the OFF period of the switch element T1 and the period Tb corresponding to the ON period of the switch element T1 is determined so as to satisfy Ta: Tb = K · CLi: Ctotal. .

  CLi in the previous equation is the capacity of the data line portion when driving the i-th scanning line WL. The coefficient K is a coefficient for ensuring the period Ta as a minimum. Incidentally, if the manufacturing error is ignored, the total capacity Ctotal of each pixel is basically the same.

  Generally, as the distance from the data line driver 25 increases, the wiring capacitance CLi increases. Therefore, as shown in FIG. 10, the ratio of the period Ta to be secured at the head portion of the horizontal scanning period increases as the pixel 31 located farther from the data line driver 25 is driven.

  The timing generator 29 is a processing device that generates various timing signals based on the data signal Din. In addition to the clock signal, a write enable signal WSenable and the like are also generated.

(A-3) Drive Operation FIG. 11 shows a signal waveform example for explaining the drive operation of the organic EL display device 21.
FIG. 11A shows a change in the potential VD by driving the data line DL. 11B and 11C show the write signal WS supplied from the scanning line driver 27. FIG.

  11B shows a write signal WS applied to the I-th scanning line WL, and FIG. 11C shows a write signal WS applied to the (I + 1) -th scanning line WL. is there. FIG. 11D shows the horizontal synchronization signal HS.

As shown in FIG. 11, simultaneously with the start of the horizontal scanning period, the potential VD of the data line DL changes rapidly so as to approach the applied signal voltage Vin.
At this time, the capacitance viewed from the data line driver 25 looks much smaller than that when the switch element T1 is ON-controlled.

That is, the time constant looks small. For this reason, the potential VD of the data line DL rises sharply.
Eventually, when this period Ta ends, the write signal WS switches from the L level to the H level.

After this timing, the switch element T1 is controlled to be in an ON state, and writing of the signal voltage Vin to the capacitor C in the pixel is started through the switch element T1.
Note that the writing potential here is a difference between the signal voltage Vin which is the final attained potential and the potential reached by driving the period Ta.

  Therefore, although the load capacity to be driven by the data line driver 25 increases, the potential of the data line DL can be driven to the signal voltage Vin in a short time. FIG. 11A shows this operation as a two-stage transition waveform.

The power consumption W is C · V ² · f
(C: capacity, V: voltage, f: frequency). For the driving method of this embodiment, the load capacity of the period Ta, requires only the wiring capacitance C _L. Therefore, the power consumption is greatly reduced as compared to the case where the switch element T1 is controlled to be in the ON state from the beginning of the horizontal drive period as in the conventional method.

  Incidentally, after the end of the period Ta, it is necessary to drive the same load capacity as in the conventional method, but this time the voltage to be driven is significantly reduced. Therefore, the power consumption W when writing the signal voltage Vin to the pixel 31 is significantly smaller than that of the conventional method.

(A-4) Effect of Embodiment As a result, the total time until the signal voltage Vin rises is significantly shortened as compared with the case of driving only with the existing driving method. Therefore, even when the resolution and driving frequency of the organic EL panel 23 are high, it is possible to ensure a sufficient writing time without increasing the number of special wiring patterns and driving circuits.

That is, the potential of the data line DL changes to the signal voltage Vin leaving sufficient time to write the potential to the capacitor C. As a result, the signal voltage Vin can be written faithfully in the capacitor C, and the image quality can be improved.
In addition, the power consumed by writing the signal voltage Vin is smaller than that of the existing driving method.

  Further, in the case of this embodiment, even when the total capacity Ctotal in the pixel cannot be ignored with respect to the capacity and resistance of the data line DL, the driving frequency can be simply and at low cost without increasing the write voltage (overdrive). It is possible to follow the increase in speed.

(B) Other Embodiments (B-1) Automatic Adjustment of Period Ta In the embodiment described above, the period Ta is fixed according to the distance (wiring length) from the data line driver 25 to the pixel column to be written. The case where it is set automatically has been described.

  However, in reality, there is a possibility that the expected characteristics cannot be obtained in the set period due to the influence of manufacturing variations and the like. That is, the potential change of the data line DL may be too small or too large.

Therefore, it is desirable that the head period length can be automatically adjusted so as to obtain appropriate characteristics.
FIG. 12 shows the main components of the organic EL display device 21 equipped with an automatic adjustment function for the period Ta.

FIG. 12 shows only the relationship between one data line DL and one pixel 31, but actually this connection relationship is prepared for all the data lines DL.
The write enable signal width adjustment unit 41 that realizes the automatic adjustment function for the period Ta is arranged inside the timing generator 29.

  The write enable signal width adjustment unit 41 monitors the change in the data line potential input through the feedback line drawn from the position farthest from the data line driver 25, and based on whether the change matches the reference characteristic. The signal width of the write enable signal WSenable is increased or decreased.

FIG. 13 shows an internal configuration example of the write enable signal width adjustment unit 41.
The write enable signal width adjustment unit 41 includes an A / D converter 43, a signal width control unit 45, a reference characteristic storage unit 47, and a write enable signal generation unit 49.

  The A / D converter 43 executes processing for converting an analog potential input through a feedback line into digital data. The analog potential to be converted is a change in potential that appears on the farthest end side of the data line DL when a test signal is applied to the data line DL.

  The signal width control unit 45 compares the rising / falling characteristic waveform specific to the data line DL detected through the feedback line with the reference characteristic stored in the reference characteristic storage unit 47, and determines the head portion according to the comparison result. Outputs a control signal that specifies the period length. The control signal is given to the write enable signal generator 47.

  The write enable signal generator 49 is a processing device that generates a write enable signal WSenable for controlling the switch element T1 to be turned off by a period length given by the control signal of the signal width controller 45.

  FIG. 14 shows an internal circuit example of the write enable signal generator 49. The enable signal generator 49 generates, for example, a pulse width modulation circuit 491 that generates a pulse that rises from the beginning of each horizontal scanning period to the H level for the length of the start period specified by the control signal, and a pulse that is output from the pulse width modulation circuit 491. And an inverter 493 that logically inverts. The output of the inverter 493 is a write enable signal WSenable.

  Incidentally, it is desirable that this head period length adjustment function (application of a test signal to the data line DL) is executed periodically as a correction function for a pre-shipment test or a secular change.

(B-2) Other Pixel Structures In the above-described embodiment, the case where the switch element T1 is composed of an N channel FET and the current drive element T2 is composed of a P channel FET has been described.
However, this combination is not necessarily required depending on the manufacturing process.

  For example, both the switch element T1 and the current drive element T2 may be constituted by N-channel FETs. FIG. 15 shows an equivalent circuit of a pixel corresponding to this case. In this case, one electrode of the capacitor C is connected to the gate terminal of the current driver element T2, and the other electrode is connected to the drain terminal.

  Further, for example, the switch element T1 may be configured with a P-channel FET, and the current drive element T2 may be configured with an N-channel FET. Further, for example, both the switch element T1 and the current drive element T2 may be constituted by P-channel FETs.

(B-3) Product example (a) Drive IC
The organic EL panel 23, the data line driver 25, and the scanning line driver 27 constituting the organic EL display device 21 can all be formed on one panel, but the driver and the pixel matrix are separately manufactured and distributed. You can also

  For example, the data line driver 25 and the scanning line driver 27 can be manufactured as independent drive ICs (integrated circuits) and can be distributed independently of the organic EL panel 23.

(B) Display module The organic EL display device 21 in the embodiment described above can also be distributed in the form of a display module which is an intermediate product.

  FIG. 16 shows an appearance example of the display module 51. The display module 51 has a structure in which a facing portion 53 is bonded to the surface of the support substrate 55. The facing portion 53 is made of glass or other transparent member as a base material, and a color filter, a protective film, a light shielding film, and the like are disposed on the surface thereof.

  The display module 51 may be provided with an FPC (flexible printed circuit) 57 and the like for inputting and outputting signals and the like to the support substrate 55 from the outside.

(C) Electronic device The organic EL display device 21 in the embodiment described above is also distributed in a product form mounted on an electronic device.
FIG. 17 shows a conceptual configuration example of the electronic device 61. The electronic device 61 includes the organic EL display device 21 and the system control unit 63 described above. The processing content executed by the system control unit 63 differs depending on the product form of the electronic device 61.

Note that the electronic device 61 is not limited to a device in a specific field as long as it has a function of displaying an image or video generated in the device or input from the outside.
As this type of electronic apparatus 61, for example, a television receiver is assumed. FIG. 18 shows an example of the appearance of the television receiver 71.

  A display screen 77 including a front panel 73, a filter glass 75, and the like is disposed on the front surface of the television receiver 71. The portion of the display screen 77 corresponds to the organic EL display device 21 described in the embodiment.

  Also, for example, a digital camera is assumed as this type of electronic device 61. FIG. 19 shows an appearance example of the digital camera 81. FIG. 19A shows an example of the appearance on the front side (subject side), and FIG. 19B shows an example of the appearance on the back side (photographer side).

  The digital camera 81 has an imaging lens (FIG. 19 shows the state in which the protective cover 83 is closed, so it is disposed on the back side of the protective cover 83), a flash light emitting unit 85, a display screen 87, a control switch 89, and a shutter. It consists of buttons 91. Among these, the display screen 87 corresponds to the organic EL display device 21 described in the embodiment.

For example, a video camera is assumed as this type of electronic device 61. FIG. 20 shows an example of the appearance of the video camera 101.
The video camera 101 includes an imaging lens 105 that images a subject in front of a main body 103, a shooting start / stop switch 107, and a display screen 109. Among these, the display screen 109 corresponds to the organic EL display device 21 described in the embodiment.

  Further, for example, a portable terminal device is assumed as this type of electronic device 61. FIG. 21 shows an example of the appearance of a mobile phone 111 as a mobile terminal device. A cellular phone 111 illustrated in FIG. 21 is a foldable type, and FIG. 21A illustrates an appearance example in a state where the housing is opened, and FIG. 21B illustrates an appearance example in a state where the housing is folded.

  The mobile phone 111 includes an upper housing 113, a lower housing 115, a connecting portion (in this example, a hinge portion) 117, a display screen 119, an auxiliary display screen 121, a picture light 123, and an imaging lens 125. Among these, the display screen 119 and the auxiliary display screen 121 correspond to the organic EL display device 21 described in the embodiment.

Further, for example, a computer is assumed as this type of electronic device 61. FIG. 22 shows an example of the appearance of the notebook computer 131.
The notebook computer 131 includes a lower casing 133, an upper casing 135, a keyboard 137, and a display screen 139. Of these, the display screen 139 corresponds to the organic EL display device 21 described in the embodiment.

  In addition to these, the electronic device 61 may be an audio playback device, a game machine, an electronic book, an electronic dictionary, or the like.

(B-4) Other Display Device Examples In the description of the embodiments, the case where the display device is the organic EL display device 21 has been described.
However, the data line driver 25 and the scanning line driver 27 can also be applied to other self-luminous display devices. For example, the present invention can be applied to an inorganic EL display device, a display device in which LEDs are arranged, an FED display device, a PDP display device, and the like.

The data line driver 25 and the scanning line driver 27 can also be applied to non-self light emitting display devices such as liquid crystal display devices.
FIG. 23 shows a connection relationship between the pixel 141 formed at the intersection of the data line DL and the scanning line WL and the driver circuit.

  As shown in FIG. 23, the equivalent circuit of the pixel 141 can be expressed as a switch element T1 and a capacitor C1. The capacitor C1 corresponds to the liquid crystal sandwiched between the pixel electrode and the counter electrode. Even when the driving method proposed by the inventor is applied to a liquid crystal display device, the signal voltage writing characteristics can be improved. Therefore, the image quality can be improved without increasing the cost.

(B-5) Control Device Configuration In the above description, the case where the drive timing of the data line driver 25 and the drive timing of the scanning line driver 27 are controlled by hardware has been described.
However, these control timings may be controlled through software processing.

(B-6) Others Various modifications can be considered for the above-described embodiments within the scope of the invention. Various modifications and applications created or combined based on the description of the present specification are also conceivable.

It is a figure which shows the example of a conventional drive. It is a figure which shows the prior art example of a display device. It is a figure which shows the structural example of a display device. It is a figure which shows the structural example of a pixel. It is a figure which shows the structural example of a data line driver. It is a figure which shows the load capacity seen from a data line driver. It is a figure explaining the capacitive component in a pixel. It is a figure which shows the structural example of a scanning line driver. It is a figure which shows the example of a drive of a scanning line driver. It is a figure which shows the write signal according to the positional relationship of a scanning line and a data line driver. It is a figure which shows the example of a drive of a display device. It is a figure which shows the display device structure with the automatic adjustment of the period length ensured at the head part. It is a figure which shows the internal structural example of an enable signal part. It is a figure which shows the internal structural example of an enable signal generation part. It is a figure which shows the other structural example of a pixel. It is a figure which shows the structural example of a display module. It is a figure which shows the function structural example of an electronic device. It is a figure which shows the example of goods of an electronic device. It is a figure which shows the example of goods of an electronic device. It is a figure which shows the example of goods of an electronic device. It is a figure which shows the example of goods of an electronic device. It is a figure which shows the example of goods of an electronic device. It is a figure which shows the pixel structure of a liquid crystal display device.

Explanation of symbols

21 Organic EL Display Device 23 Organic EL Panel 25 Data Line Driver 27 Scan Line Driver 29 Timing Generator 41 Write Enable Signal Width Adjusting Unit 61 Electronic Device

Claims (9)

In a display device drive circuit for driving an active matrix drive type display device,
In the first period positioned at the beginning of each horizontal scanning period, the switch elements that control the writing of the signal voltage to the corresponding pixels are simultaneously controlled to be in the OFF state, and the second period following the first period, the switch A scanning line drive unit that controls the elements to the on state all at once;
And a data line driving section for applying a signal voltage of each horizontal scanning period to a corresponding data line during the first and second periods. The display device driving circuit according to claim 1,
The length of the first period is individually set according to the length of a data line connecting a pixel column to which a signal voltage is written and a data line driver. The display device driving circuit according to claim 2,
A ratio between the length Ta of the first period and the length Tb of the second period is set by the following equation.
Ta: Tb = K · C _Li : C _total
K is a coefficient C _Li for ensuring the first period at a minimum, C is a capacity of the data line portion from the data line driver to the pixel column to which the signal voltage is written, C _total is a total capacity in the pixel A display region having an active matrix drive type pixel structure;
In the first period positioned at the beginning of each horizontal scanning period, the switch elements that control the writing of the signal voltage to the corresponding pixels are simultaneously controlled to be in the OFF state, and the second period following the first period, the switch A scanning line drive unit that controls the elements to the on state all at once;
An active matrix drive type display device, comprising: a data line driving unit that applies a signal voltage of each horizontal scanning period to a corresponding data line during the first and second periods. The display device according to claim 4.
A display device, wherein each pixel is composed of an electroluminescence element. The display device according to claim 4.
A display device in which each pixel is composed of a liquid crystal. A display region having an active matrix drive type pixel structure;
In the first period positioned at the beginning of each horizontal scanning period, the switch elements that control the writing of the signal voltage to the corresponding pixels are simultaneously controlled to be in the OFF state, and the second period following the first period, the switch A scanning line drive unit that controls the elements to the on state all at once;
A data line driver that applies a signal voltage of each horizontal scanning period to a corresponding data line during the first and second periods;
An electronic device comprising: a system control unit. In a display device driving method for driving an active matrix drive type display device,
In the first period positioned at the beginning of each horizontal scanning period, the switch elements that control the writing of the signal voltage to the corresponding pixels are simultaneously controlled to be in the OFF state, and the second period following the first period, the switch A process of controlling the elements to the ON state all at once,
A display device driving method comprising: applying a signal voltage of each horizontal scanning period to a corresponding data line during the first and second periods. In a computer that controls the drive timing of an active matrix drive type display device,
In the first period positioned at the beginning of each horizontal scanning period, the switch elements that control the writing of the signal voltage to the corresponding pixels are simultaneously controlled to be in the OFF state, and the second period following the first period, the switch A process of controlling the elements to the ON state all at once,
And a process of applying a signal voltage of each horizontal scanning period to a corresponding data line during the first and second periods.

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