JP2008148104A - Power semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power semiconductor device which is capable of continuously limiting electrification even when power supply is cut off, if abnormality is once detected. <P>SOLUTION: A semiconductor device 1 includes an external control terminal 8 to which a control signal is inputted, two external output terminals 3 and 4 into or from each of which an output current flows, and a power semiconductor element 2 which controls the output current. The semiconductor device comprises: an operating state detection circuit 6 which outputs an electric signal corresponding to an operating state of the power semiconductor element 2; a nonvolatile state holding circuit 7 to which an output of the operating state detection circuit 6 is inputted, and which is turned into a predetermined output state when the output of the operating state detection circuit 6 becomes a value indicating abnormality of the power semiconductor element 2, and continuously holds the predetermined output state even when power supply is cut off; and a control circuit 5 which limits the output of the power semiconductor element 2 in accordance with the control signal and the output of the state holding circuit. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a power semiconductor device, and more particularly to a power semiconductor device including a protection circuit.

  Some power semiconductor devices including power switching semiconductor elements such as IGBTs and MOSFETs include a protection circuit that detects an abnormal state such as overheating of the power switching element in the package and cuts off the current.

  For example, there is a 3-pin power semiconductor device in which when a device detects temperature and detects an overheat state, the state is held in a latch, and the power MOSFET is shut off by short-circuiting the source and gate of the power MOSFET. Normally, the power supply for the protection circuit of such a power semiconductor device uses a gate-source voltage, and when the gate input voltage becomes 0 V, the latch state is released.

  In Patent Document 1, as shown in FIG. 10, in order to control the power MOSFET 41, the state of the power MOSFET 41 is detected by the operation state detection circuit 42, and the output of the operation state detection circuit 42 is changed to a value indicating abnormality. When the output state of the latch circuit 43 is an abnormal value, the control circuit 44 reduces the gate voltage of the power MOSFET 41 to the LO level and outputs the output of the power MOSFET 41. A power semiconductor device in which a diode 45 is provided in the latch circuit 43 in a configuration for interrupting the above is disclosed.

  In the power semiconductor device of Patent Document 1, since the diode 45 is provided in the latch circuit 43, the electric charge held in the parasitic gate capacitance C of the latch circuit 43 is not easily discharged even when 0 V is applied to the external gate terminal 46. For a short time, an output state indicating an abnormality of the power MOSFET 41 can be maintained.

  However, also in the power semiconductor device of FIG. 10, when 0 V is applied to the external gate input terminal 46 for a long time or when the power semiconductor device is removed from the circuit and the external gate input terminal 46 is left in a floating state for a long time, The charge held in the parasitic gate capacitance C is discharged, and the state cannot be held.

In a power semiconductor device that switches a large current, when an abnormal state of the power MOSFET 41 is detected even once, an abnormality may have occurred in the power semiconductor device or the surrounding system. Therefore, when the signal applied to the external gate terminal 46 is turned off and then turned on again, if the control circuit applies a gate voltage to the power MOSFET 41 and energizes a large current, the power MOSFET 41 and the surrounding system There is a risk of further damage such as the above and system malfunctions associated therewith leading to serious accidents and fires.
Japanese Patent No. 3169723 Japanese Patent No. 2522208 JP 2005-150762 A

  In view of the above problems, an object of the present invention is to provide a power semiconductor device capable of continuously restricting energization even if the power is turned off once an abnormality is detected.

  In order to solve the above problems, a power semiconductor according to the present invention includes an external control terminal to which a control signal is input, two external output terminals to which an output current flows in or out, and a power semiconductor element that controls the output current. An operation state detection circuit that outputs an electrical signal corresponding to an operation state of the power semiconductor element; and an output of the operation state detection circuit is input, and the output of the operation state detection circuit is a value indicating an abnormality of the power semiconductor element A non-volatile state holding circuit that continues to hold the predetermined output state even when the power is cut off, and the control signal and the output of the state holding circuit according to the output of the power semiconductor element. And a control circuit for limiting the output.

  According to this configuration, since the nonvolatile state holding circuit continues to hold the operating state of the power semiconductor element even when the power is cut off, if there is an abnormality in the power semiconductor element before the power is cut off, Even when the power source is connected again, the output of the power semiconductor element can be continuously limited, and the power semiconductor device and the surrounding system can be destroyed and the system malfunction associated therewith can be prevented.

  In the power semiconductor device of the present invention, the control signal input to the external control terminal may be used as a power source for the operation state detection circuit and the state holding circuit.

  According to this configuration, it is not necessary to provide a power supply terminal for supplying power to the operation state detection circuit and the state holding circuit, and wiring for using the power semiconductor element is simplified.

  The state holding circuit may include a nonvolatile memory, and data indicating that the output of the operation state detection circuit has a value indicating an abnormality of the power semiconductor element may be recorded in the nonvolatile memory.

  According to this configuration, even if the power is cut off, it is possible to continue to hold information on whether or not there is an abnormality in the power semiconductor element.

  The power semiconductor device of the present invention may further include a reset circuit that initializes data recorded in the nonvolatile memory.

  According to this configuration, when it is confirmed that once the operation of the power semiconductor element is restricted, it is not necessary to restrict the operation, the output of the power semiconductor element is initialized by initializing the recording in the nonvolatile memory. The restriction can be lifted and the power semiconductor device can be used again at maximum capacity.

  The reset circuit may initialize data recorded in the non-volatile memory when the voltage of the control signal reaches a predetermined value, and a reset signal is input to an external reset terminal further provided in the power semiconductor device When recorded, the data recorded in the non-volatile memory may be initialized.

  According to this configuration, the user can artificially reset the state holding circuit.

  In the power semiconductor device of the present invention, the state holding circuit may include a fuse, and the fuse may be blown when an output of the operation state detection circuit becomes a value indicating an abnormality of the power semiconductor element. .

  This configuration can also prevent the power semiconductor device and the surrounding system from being destroyed or malfunctioning.

  The fuse may be embedded in the package of the semiconductor device so as not to be replaceable, or may be detachably mounted. Moreover, it is preferable that the said fuse is exposed and arrange | positioned so that the presence or absence of fusing can be visually observed.

  In the power semiconductor device of the present invention, the state holding circuit may include a latch-type switch that is stable in a conductive state or a cut-off state, and may hold the predetermined output state by the conduction or cut-off of the latch-type switch. .

  This configuration can also prevent the power semiconductor device and the surrounding system from being destroyed or malfunctioning.

  The latch-type switch may include reset means for setting one of the conduction state and the cutoff state as an initial state, the other state indicating the predetermined output state, and returning to the initial state. The reset means is an operation member that selects the conduction state or the cutoff state by a mechanical operation, and resets the latch-type switch to the initial state by an electric signal input from the outside. May be.

  In the power semiconductor device of the present invention, the operating state detection circuit may be a temperature detection circuit that detects the temperature of the power semiconductor element.

  According to this configuration, the power semiconductor element can be prevented from being damaged due to overheating.

  The power semiconductor device of the present invention may further include a status terminal for leading the output of the state holding circuit or the control circuit to the outside.

  According to this configuration, it is possible to monitor whether the power semiconductor device detects an abnormality and restricts the output.

  According to the present invention, the nonvolatile state holding circuit continues to hold the operating state of the power semiconductor element even when the power is turned off. Therefore, after detecting an abnormality in the power semiconductor element, the power supply is temporarily turned off. However, by limiting the output (including shutting down), it is possible to prevent damage to the power semiconductor element and destruction or malfunction of the surrounding system.

Embodiments of the present invention will now be described with reference to the drawings.
FIG. 1 shows a power semiconductor device 1 according to a first embodiment of the present invention. The power semiconductor device 1 includes a power MOSFET (field effect transistor) 2 that is one of power semiconductor elements, and external output terminals 3 and 4 connected to the source and drain (output current input / output electrodes) of the power MOSFET 2, respectively. A control circuit 5 capable of applying a voltage to the gate electrode of the power MOSFET 2, an operation state detection circuit 6 for detecting the operation state of the power MOSFET 2, and a nonvolatile state holding circuit 7 for holding the output state of the operation state detection circuit 6. The operation state detection circuit 6, the nonvolatile state holding circuit 7, and the control circuit 5 have an external control terminal 8 for applying a control signal that also serves as a power source.

  The operation state detection circuit 6 outputs a voltage according to the operation state of the power MOSFET 2 such as temperature. The nonvolatile body holding circuit 7 is a latch circuit that holds the output state when the output of the operation state detection circuit 6 becomes a value indicating an abnormality of the power semiconductor device 1, and is supplied from the external control terminal 8. Even when the power is shut off, the output state can be maintained. Only when the power is supplied from the external control terminal 8 and the output of the nonvolatile state holding circuit 7 is a predetermined value indicating that no abnormality is recognized in the power semiconductor device 1, the control circuit 5 is the power MOSFET 2. A predetermined voltage is applied to the gate electrode so that a current can flow between the source and drain, that is, between the external output terminals 3-4.

  For example, when the operation state detection circuit 6 detects an abnormality in the power semiconductor device 1, the operation state detection circuit 6 outputs a voltage signal at the HI level. The nonvolatile state holding circuit 7 to which this voltage signal is input outputs a voltage signal at the HI level and latches (self-holds) the output state. When the HI level voltage signal is input from the nonvolatile state holding circuit 7, the control circuit 5 prevents the input from the external control terminal 8 from applying a voltage to the gate of the power MOSFET 2. As a result, the power MOSFET 2 is turned off and the drain current is cut off.

  Even when the voltage applied to the external control terminal 8 is set to 0V, the output state held in the nonvolatile state holding circuit 7 is not reset but is held. Thereafter, even if a control signal is applied to the external control terminal 8 again, if the operation state detection circuit 6 has detected an abnormal state in the past, an output state indicating that the nonvolatile state holding circuit 7 has detected an abnormality. Is maintained, the control circuit 5 continues to cut off the drain current without turning on the power MOSFET 2.

  Even if the entire power semiconductor device 1 is removed from the system and the external control terminal 8 and the external output terminals 3 and 4 are in a floating state, the operation state detection circuit 6 has detected an abnormal state of the power semiconductor device 1 in the past. If so, the power MOSET 2 is not turned on because the nonvolatile state holding circuit 7 holds the output state indicating abnormality.

  That is, in the power semiconductor device 1, once the power MOSFET 2 is in an abnormal state, the current is not output again even if the power is turned off. For this reason, since the system incorporating the power semiconductor device 1 cannot be restarted unless the power semiconductor device 1 is repaired or replaced, the safety confirmation of the system is ensured.

  FIG. 2 shows a power semiconductor device 1 according to the second embodiment of the present invention. In the following description, the same components as those described above are denoted by the same reference numerals and description thereof is omitted.

  The nonvolatile state holding circuit 7 of the power semiconductor device 1 of this embodiment includes a nonvolatile memory 9, a write state determination circuit 10, and a write pulse generation circuit 11. The write state determination circuit 10 generates write data based on the output of the operation state detection circuit 6. The write pulse generation circuit 11 detects a rising edge at which the output of the operation state detection circuit 6 changes from LO to HI, and generates a write pulse. When the write pulse is input, the nonvolatile memory 9 records the value of the write data at that time in the internal nonvolatile memory cell. The data recorded in the nonvolatile memory 9 is always read and output to the control circuit 5.

  When the write pulse generation circuit 11 extracts the rising edge of the output of the operation state detection circuit 6, the write data is always HI. That is, once data indicating the HI signal is recorded in the nonvolatile memory 9, the data in the nonvolatile memory 9 is not rewritten to a value indicating LO. Therefore, when the operation state detection circuit 6 detects an abnormality of the power semiconductor device 1 even once, the control circuit 5 thereafter turns off the power MOSFET 2 so that the external output terminals 3 and 4 are not energized. For this reason, the power semiconductor device 1 according to the present embodiment needs to be replaced in order to restart the system once the abnormality of the power semiconductor device 1 is detected.

  FIG. 3 shows a power semiconductor device 1 according to a third embodiment of the present invention. The power semiconductor device 1 of the present embodiment includes a reset circuit 12 that outputs a signal for writing LO data in the nonvolatile memory 9 and an external reset for inputting a trigger signal for causing the reset circuit 12 to output a signal. The terminal 13 has an external power supply terminal 14 and an external ground terminal 15 provided for supplying power to the operation state detection circuit 6, the nonvolatile state holding circuit 7 and the control circuit 5.

  When the write pulse generation circuit 11 detects the rise of the output of the operation state detection circuit 6 or the rise of the output of the reset circuit 12, the write pulse generation circuit 11 outputs a write pulse that causes the nonvolatile memory 9 to rewrite data. However, even when the write pulse generation circuit 11 detects the rising edge of the output of the operation state detection circuit 6, the write pulse generation circuit 11 does not generate a write pulse if the output of the reset circuit 12 is HI.

  The write state determination circuit 10 outputs a logical product of the output of the operation state detection circuit 6 and the inverted value of the output of the reset circuit 12. That is, HI is output only when the output of the reset circuit 12 is LO and the output of the operation state detection circuit 6 is HI, and LO is output otherwise.

  When the operation state detection circuit 6 detects an abnormality in the power semiconductor device 1, the power semiconductor device 1 according to the present embodiment records the data of the output HI in the nonvolatile memory 9. Is turned off so that no current is applied between the external output terminals 3 and 4. However, by inputting a signal to the external reset terminal 13, the data of the output LO is recorded in the nonvolatile memory 9, the output restriction of the power MOSFET 2 is released, and the power is again supplied between the external output terminals 3 and 4. Can be made possible.

  FIG. 4 shows a power semiconductor device 1 according to the fourth embodiment of the present invention. The nonvolatile state holding circuit 7 of the power semiconductor device 1 of this embodiment includes a fuse 16 between an external control terminal 8 that is a power source and an external output terminal 3 on the source side of the power MOSFET 2 that is a common (reference potential). A resistor 17 is connected in series to output a potential between the fuse 16 and the resistor 17. The nonvolatile state holding circuit 7 includes a fusing transistor 18 connected in parallel with the resistor 17. The fusing transistor 18 is turned on when the output of the operation state detection circuit 6 becomes HI, and bypasses the resistor 17. The fuse 16 is directly connected to the external output terminal 3. Thereby, an excessive current flows through the fuse 16 and the fuse 16 can be blown.

  Until the fuse 16 is blown, the output of the nonvolatile state holding circuit 7 has the same potential as that of the external control terminal 8, but when the fuse 16 is blown, it becomes the same potential as that of the external output terminal 3. As a result, the power semiconductor device 1 of the present embodiment limits the output of the power MOSFET 2 when the fuse 16 is blown.

  In addition, since these components are housed in the mold package 19, if the fuse 16 is melted, the power semiconductor device 1 cannot be energized unless the entire power semiconductor device 1 is replaced.

  Therefore, like the power semiconductor device 1 according to the fifth embodiment of the present invention shown in FIG. 5, the fuse 16 is detachably disposed on the surface of the mold package 19, and the power MOSFET 2 is replaced by replacing the fuse 16. You may enable it to cancel the restriction | limiting of an output.

  Further, it is preferable that the fuse 16 is arranged so as to be exposed on the surface of the mold package 19 so that it can be visually confirmed whether or not it is blown.

  FIG. 6 shows a power semiconductor device 1 according to a sixth embodiment of the present invention. The power semiconductor device 1 of the present embodiment is obtained by replacing the fuse 16 of the fourth embodiment with a breaker switch 20. The breaker switch 20 is a known no-fuse breaker, and is a latch-type switch that can be switched between a conductive state and a cut-off state by the operation member 21 and is cut off when a current exceeding a predetermined current value flows. .

  In the present embodiment, the output limit of the power MOSFET 2 can be easily released simply by operating the operation member 21 using the operation member 21 as a reset means.

  FIG. 7 shows a power semiconductor device 1 according to a seventh embodiment of the present invention. The nonvolatile state holding circuit 7 of the power semiconductor device 1 of the present embodiment has a latch type relay switch 22. The latch-type relay switch 22 includes a contact 23, a closing coil 24 that closes the contact 23 when energized and energized, and an open coil 25 that opens the contact 23 when energized and energized. Even when the coil 25 is not energized, the bistable relay maintains the open state or the closed state of the contact 23.

  The nonvolatile state holding circuit 7 is energized and opened when the output of the operation state detection circuit 6 becomes HI and energized to apply a current to the closing coil 24, and when the output of the reset circuit 12 becomes HI. And an open transistor 27 for applying a current to the coil 25.

  The latch-type relay switch 22 is in a state where the contact 23 is closed in the initial state. Thus, the power semiconductor device 1 applies a voltage to the gate of the power MOSFET 2 when a predetermined voltage is applied to the external control terminal 8 until the operation state detection circuit 6 detects an abnormality of the power semiconductor device 1. It is possible to energize between the source and the drain. However, once the operation state detection circuit 6 detects an abnormality in the power semiconductor device 1, the contact 23 is held open, and an electric signal is input to the external reset terminal 13 until the contact 23 is closed. Disable output.

  In the present embodiment, the reset circuit 12, the open transistor 27, and the open coil 25 function as reset means for returning the operation state detection circuit 6 to the initial state.

  FIG. 8 shows a power semiconductor device 1 according to an eighth embodiment of the present invention. The power semiconductor device 1 of the present embodiment has a status terminal 28 that branches the output of the nonvolatile state holding circuit 7 and leads it to the outside.

  In the present embodiment, it is possible to monitor from the outside whether the operation state detection circuit 6 detects an abnormality of the power semiconductor device 1 and stops the output of the power MOSFET 2 by the status terminal 28.

  In addition to branching the output of the nonvolatile state holding circuit 7, the status terminal 28 can check whether or not an abnormality has been detected in the power semiconductor device 1 even if the output of the control circuit 5 is branched.

  Further, the operation state detection circuit 6 of the present embodiment is a temperature detection circuit including a plurality of diodes 29 for temperature detection formed in the vicinity of the power MOSFET 2. The temperature detection circuit 6 generates a constant voltage by the constant voltage circuit 30 using the external control terminal 8 as a power source, divides the output voltage of the constant voltage circuit 30 by a diode 29 connected in series with the voltage dividing resistor 31, The voltage is applied to the gate of an output transistor 33 having a limiting resistor 32 connected to the drain.

  In the temperature detection circuit 6, the voltage drop across the diode 29, which is the gate voltage of the output transistor 33, is a voltage sufficient to cause conduction between the source and drain at room temperature, but the resistance of the diode 29 increases due to the temperature rise of the power MOSFET 2. As the value decreases, the source and drain of the output transistor 33 cannot be made conductive. That is, the output of the temperature detection circuit 6 is normally HI, and the output becomes LO only when the temperature rise of the power semiconductor device 1 is detected.

  In the present embodiment, when an abnormality such as a temperature rise of the power semiconductor device 1 is detected, the output of the power MOSFET 2 is stopped. At this time, since the nonvolatile state holding circuit 7 holds the abnormality detection state, the function of the power semiconductor device 1 cannot be recovered only by stopping the input of the control signal to the external control terminal 8 even if the temperature falls. . For this reason, even if a failure occurs in the surrounding wiring or the like when the temperature rises, it is possible to prevent an accident in which the damaged wiring is ignited by turning on the power MOSFET 2 and flowing a large current without overlooking it.

  FIG. 9 shows a power semiconductor device 1 according to the ninth embodiment of the present invention. The power semiconductor device 1 of the present embodiment includes a reset circuit 12 that outputs a signal for writing LO data to the nonvolatile memory 9, a high voltage detection circuit 34 that detects a high voltage applied to the external control terminal 8, and have.

  In the high voltage detection circuit 34, the voltage of the external control terminal 8 is applied to the drains of the inverter element 36 and the MOSFET 37 via the limiting resistor 35. The voltage of the external control terminal 8 is connected to the source of the MOSFET 37 through the Zener diode 38 and the detection resistor 39 connected in series, and the connection point of the Zener diode 38 and the detection resistor 39 is connected to the gate of the MOSFET 37. Has been.

  In this embodiment, at a normal input voltage, the Zener diode 38 is non-conductive, the gate voltage of the MOSFET 37 becomes 0 V, and the MOSFET 37 is turned off.

  However, when a positive voltage considerably higher than usual is applied to the external control terminal 8, the Zener diode 38 becomes conductive, a potential difference is generated in the detection resistor 39, and the MOSFET 37 is turned on by increasing the gate voltage. . Accordingly, since the input of the inverter element 36 is at the LO level, the inverter element 36 outputs HI. That is, the output of the high voltage detection circuit 34 is normally LO, and the output becomes HI only when a positive voltage considerably higher than the normal input voltage is applied to the external control terminal 8.

  When the output of the high voltage detection circuit 34 becomes HI, the reset circuit 12 outputs HI.

  When the write pulse generation circuit 11 detects the rise of the output of the operation state detection circuit 6 or the rise of the output of the reset circuit 12, the write pulse generation circuit 11 outputs a write pulse that causes the nonvolatile memory 9 to rewrite data. However, even when the write pulse generation circuit 11 detects the rising edge of the output of the operation state detection circuit 6, the write pulse generation circuit 11 does not generate a write pulse if the output of the reset circuit 12 is HI.

  The write state determination circuit 10 outputs a logical product of the output of the operation state detection circuit 6 and the inverted value of the output of the reset circuit 12. That is, HI is output only when the output of the reset circuit 12 is LO and the output of the operation state detection circuit 6 is HI, and LO is output otherwise.

  When the operation state detection circuit 6 detects an abnormality in the power semiconductor device 1, the power semiconductor device 1 according to the present embodiment records the data of the output HI in the nonvolatile memory 9. Is turned off so that no current is applied between the external output terminals 3 and 4. However, by applying a positive voltage considerably higher than the normal input voltage to the external control terminal 8, the data of the output LO is recorded in the nonvolatile memory 9, the output limitation of the power MOSFET 2 is released, and the external output terminal It is possible to energize again between 3 and 4.

  In the above embodiment, the power switching semiconductor device having the power MOSFET 2 that performs on / off control of the current has been described. However, the power switching semiconductor device can also be applied to a power semiconductor device that performs linear control of the output. You may make it restrict | limit to below a predetermined value, ie, accept | permit conduction of a constant current.

1 is a schematic configuration diagram of a power semiconductor device according to a first embodiment of the present invention. The schematic block diagram of the power semiconductor device of 2nd Embodiment of this invention. The schematic block diagram of the power semiconductor device of 3rd Embodiment of this invention. The schematic block diagram of the power semiconductor device of 4th Embodiment of this invention. The schematic block diagram of the power semiconductor device of 5th Embodiment of this invention. The schematic block diagram of the power semiconductor device of 6th Embodiment of this invention. The schematic block diagram of the power semiconductor device of 7th Embodiment of this invention. The schematic block diagram of the power semiconductor device of 8th Embodiment of this invention. The schematic block diagram of the power semiconductor device of 9th Embodiment of this invention. The schematic block diagram of the conventional power semiconductor device.

Explanation of symbols

1 Power Semiconductor Device 2 Power MOSFET (Power Semiconductor Device)
3 External output terminal (source)
4 External output terminal (drain)
DESCRIPTION OF SYMBOLS 5 Control circuit 6 Operation | movement state detection circuit 7 Nonvolatile state holding circuit 8 External control terminal 9 Nonvolatile memory 10 Write state determination circuit 11 Write pulse generation circuit 12 Reset circuit 13 External reset terminal 16 Fuse 19 Mold package 20 Breaker switch ( (Latch type switch)
21 Operation member 22 Latch type relay switch 23 Contact 34 High voltage detection circuit

Claims (17)

An external control terminal to which a control signal is input;
Two external output terminals through which the output current flows in and out;
A power semiconductor element for controlling the output current;
An operation state detection circuit for outputting an electrical signal corresponding to the operation state of the power semiconductor element;
When the output of the operation state detection circuit is input and the output of the operation state detection circuit reaches a value indicating an abnormality of the power semiconductor element, the output state is a predetermined output state, and the predetermined output state is maintained even when the power is cut off. A non-volatile state holding circuit that continues;
A power semiconductor device comprising: a control circuit that limits the output of the power semiconductor element in accordance with the control signal and the output of the state holding circuit.   The power semiconductor device according to claim 1, wherein the control signal input to the external control terminal is used as a power source for the operation state detection circuit and the state holding circuit.   The state holding circuit includes a nonvolatile memory, and records data indicating that an output of the operation state detection circuit has a value indicating an abnormality of the power semiconductor element in the nonvolatile memory. 3. The power semiconductor device according to 1 or 2.   4. The power semiconductor device according to claim 3, further comprising a reset circuit for initializing data recorded in the nonvolatile memory.   5. The power semiconductor device according to claim 4, wherein the reset circuit initializes data recorded in the nonvolatile memory when a voltage of the control signal reaches a predetermined value.   5. The power semiconductor device according to claim 4, further comprising an external reset terminal for inputting a reset signal for initializing data recorded in the nonvolatile memory to the reset circuit.   The said state holding circuit is equipped with a fuse, The fuse is blown when the output of the said operation state detection circuit becomes a value which shows abnormality of the said power semiconductor element, The fuse of Claim 1 or 2 characterized by the above-mentioned. Semiconductor device.   The semiconductor device according to claim 7, wherein the fuse is embedded in the package of the semiconductor device so as not to be replaced.   The semiconductor device according to claim 7, wherein the fuse is detachably attached.   The semiconductor device according to claim 7, wherein the fuse is exposed and disposed so that the presence or absence of fusing can be visually observed.   The said state holding circuit is provided with the latch type switch stabilized in a conduction | electrical_connection state or interruption | blocking state, The said predetermined | prescribed output state is hold | maintained by conduction | electrical_connection or interruption | blocking of the said latch type switch. Semiconductor device.   The latch-type switch includes reset means for returning to the initial state when the other state indicates the predetermined output state as an initial state of one of the conductive state and the cut-off state. The power semiconductor device according to claim 11.   13. The power semiconductor device according to claim 12, wherein the reset means is an operation member that selects the conducting state or the cutoff state by a mechanical operation.   13. The power semiconductor device according to claim 12, wherein the reset means returns the latch switch to the initial state by an electric signal input from the outside.   The power semiconductor device according to claim 1, wherein the operation state detection circuit is a temperature detection circuit that detects a temperature of the power semiconductor device.   16. The power semiconductor device according to claim 1, further comprising a status terminal for leading the output of the state holding circuit to the outside.   The power semiconductor device according to claim 1, further comprising a status terminal for deriving an output of the control circuit to the outside.

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