CN116707500A - Driver stage - Google Patents

Driver stage Download PDF

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Publication number
CN116707500A
CN116707500A CN202310629535.4A CN202310629535A CN116707500A CN 116707500 A CN116707500 A CN 116707500A CN 202310629535 A CN202310629535 A CN 202310629535A CN 116707500 A CN116707500 A CN 116707500A
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CN
China
Prior art keywords
power transistor
bootstrap
value
time
voltage
Prior art date
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Pending
Application number
CN202310629535.4A
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Chinese (zh)
Inventor
约尔格·克鲁帕
彼得鲁斯·德维利
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Elmers Semiconductor Europe
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Elmers Semiconductor Europe
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Publication date
Priority claimed from DE102018123816.9A external-priority patent/DE102018123816B4/en
Priority claimed from DE102018123769.3A external-priority patent/DE102018123769A1/en
Priority claimed from DE102018123825.8A external-priority patent/DE102018123825B4/en
Priority claimed from DE102018123808.8A external-priority patent/DE102018123808A1/en
Application filed by Elmers Semiconductor Europe filed Critical Elmers Semiconductor Europe
Publication of CN116707500A publication Critical patent/CN116707500A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
    • H03K17/0822—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0027—Measuring means of, e.g. currents through or voltages across the switch
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0081—Power supply means, e.g. to the switch driver

Abstract

The present application relates to a driver stage. The driver stage may comprise: first power transistor (M H ) The method comprises the steps of carrying out a first treatment on the surface of the First, theTwo power transistors (M) L ) The method comprises the steps of carrying out a first treatment on the surface of the And bootstrap capacitance (C) B ) Wherein the driver stage comprises a circuit for detecting a short circuit and/or the bootstrap capacitance (C B ) Is a discharge device (UV, GT) H 、GT L ) Wherein the device is adapted and arranged to distinguish between a short circuit and the bootstrap capacitance (C B ) Wherein the driver stage comprises one or more means for signaling to the computer system a short circuit and the bootstrap capacitance (C B ) And wherein the signaling of the driver stage in case of a short circuit is different from the signaling of the discharge in the bootstrap capacitor (C B ) Is signaled in the case of a discharge of (a).

Description

Driver stage
The application is a divisional application of patent application No. 201910934317.5, of which the application date is 2019, 9 and 26, and the application name is 'driver capable of distinguishing bootstrap capacitor recharging and short-circuit faults'.
Technical Field
The application relates to a device for bootstrap capacitor recharging in a driver circuit.
Background
Preferably, the push-pull stage for driving the electrical load is constituted by a complementary MOS transistor pair or IGBT transistor pair. However, since hole mobility is only half that of electron mobility, the P-channel transistor has both a large chip area and a high on-resistance.
For this reason, P-channel transistors, which are typically high-side switches in push-pull stages, are typically replaced by N-channel transistors.
However, in this case, there arises a problem that: in the case of fault control, such a high-side transistor, which is designed as an N-channel transistor, is turned on by any type of voltage drop at its control terminal, and in the case of a fault, a through current (cross current) may be generated in the push-pull stage, resulting in a fire hazard.
Various circuits are known in the art that ensure that the high-side transistor does not turn on accidentally even if the supply voltage of the gate driver drops.
Prior Art
The prior art is illustrated by means of the accompanying drawings.
Fig. 1 shows a self-powered half-bridge. In comparison with the prior art, fig. 1 also shows a monitoring device UV which is obviously not prior art. However, the problem will be explained with the aid of fig. 1. The left side of fig. 1 shows an integrated circuit IC. The right side of fig. 1 shows typical all external components C related to an integrated circuit IC VG 、D、C B 、M H 、M L . Of course, the integrated circuit IC may also include other components that are not important to the discussion of the present invention and prior art and that are not shown or mentioned herein for simplicity. Half bridge M H 、M L Itself by a first power transistor M H And a second power transistor M L Composition is prepared. Integrated circuit IC and half bridge M H 、M L Mainly by the same positive supply line U with positive supply voltage S And the same negative supply line GND with a negative supply voltage. According to positive supply voltage line U S The integrated circuit IC preferably generates a constant voltage V at its voltage regulator output VG by means of a supply circuit SV (which is typically part of the integrated circuit IC), which is typically a reference potential, at the voltage difference between the potential of the negative supply voltage line GND and the potential of its voltage regulator output VG VG . Preferably, the constant voltage V at the voltage regulator output VG VG By external supporting capacitance C VG Support. External support capacitor C VG Constant voltage V at VG Second gate driver GT as integrated circuit IC L A second gate driver GT L Controlling the second power transistor M by the second gate control output GL of the integrated circuit IC L Is formed on the substrate. Furthermore, when the phase voltage V at the phase output PH PH Always through diode D at constant voltage V at voltage regulator output VG of this integrated circuit IC, at reference potential with respect to negative supply voltage line GND VG To bootstrap capacitor C B And (5) charging. When the second power transistor M L This is especially true when turned on and thus conducting.
And a second gate driver GT L In contrast, the integrated circuit IC drives the first power transistor M by the first gate drive signal GH H Gate driver GT of the gate of (a) H With floating reference potential, i.e. phase output PHPotential V relative to negative supply voltage line GND PH And for example when the first power transistor M is turned off H In the case of (a), the first gate driver GT H At the voltage regulator output V GH Carried at relative to the voltage potential V at the phase output PH PH The gate potential of (a) must always safely switch off the first power transistor M H . In the example of fig. 1, the first gate driver GT H A potential V set such that it passes through the phase output PH PH And the potential of the bootstrap node BST, i.e. through the bootstrap capacitor C B And (5) supplying power.
At the activation of the first power transistor M H In the case of (a), the first gate driver GT H Must be in the first gate driver GT H Provides a potential at the first gate drive signal GH relative to the potential of the negative supply voltage line GND to allow the first power transistor M to H Is not destroyed by the overvoltage by a constant amount exceeding the phase voltage V at the phase output PH PH Is set in the above-described range (a). For this purpose, a bootstrap voltage V is used BST . Preferably, the bootstrap voltage V BST The voltage supply circuit SV in the integrated circuit IC is provided by a diode D at an additional bootstrap node BST of the integrated circuit IC. Because the second power transistor M is only turned on L The bootstrap capacitor C is then supplied by the voltage supply circuit SV via its voltage regulator output VG B Charging, so long as the first power transistor is active, the bootstrap capacitor C B Will not be charged anymore because then the second power transistor M L Is disabled to avoid half bridge M H 、M L Through current in (a) is provided.
Due to the intrinsic current consumption of the integrated circuit IC at the bootstrap node BST of the integrated circuit IC and the external leakage current, provided that the first power transistor M H Effective (i.e. on), bootstrap capacitor C B Will discharge slowly. Thereby, the first power transistor M H Is limited and depends on the bootstrap capacitance C B And thus depends on temperature and other dispersion variables.
At presentIn the technology, there is a capacitor C for bootstrap B Various methods of recharging. These methods are characterized by the need for additional external components and the like within the integrated circuit ICs and thus are associated with corresponding costs in manufacturing the individual integrated circuit ICs. And will not be further described herein.
Monitoring at a drive
U DS Monitoring
Currently, many gate drivers include so-called U DS And (5) monitoring. For this purpose, the term U DS Refers to a first power transistor M H Drain-source voltage at. If the first power transistor M is on H Drain-source voltage U at DS Measured value V of (2) DS Exceeding a preferably configurable threshold, the corresponding first power transistor M is turned off H And stores fault information which is accessible by the control processor normally present in the system and which must normally be provided in the corresponding first power transistor M H Related first gate driver GT of (a) H The fault information is reset before being turned on again. The configurability of the threshold values can be addressed quite differently in various integrated circuits.
Such U DS Monitoring is generally mainly used to detect short circuits at the phase output PH and to avoid dangerous situations in the case of such short circuits. However, such U DS Monitoring may also be at too low a bootstrap voltage V BST Is triggered in the case of (1) because in this case the first power transistor M H Can no longer be fully opened.
Therefore, there arises a problem that the second power transistor M must be periodically turned on L To bootstrap capacitor C B Recharging, thereby avoiding false triggering of short circuit identification. This limits the allowable duty cycle of the PWM signal generated by the driver circuit to a value below 100%, which is undesirable and should be improved here.
Bootstrap monitoring
In the prior art, there is also a bootstrap voltage V BST And (5) monitoring. If the bootstrap voltage V BST Falling below a minimum value, the first power transistor M is also turned on H Shut down and store fault information which can be retrieved by a commonly existing processor and which is preferably provided at the first gate driver GT H The first power transistor M can be turned on again H Previously actively reset.
Bootstrap monitoring has been rarely implemented before because it incurs additional silicon and test costs and, ultimately, the corresponding failure passes through the U utilizing intercept handshake (Intercepted Handshaking) described above DS Monitoring results in bootstrap capacitance C B Is provided.
Use of U for signal exchange DS Monitoring or bootstrap monitoring. On the interface side between the integrated circuit IC and the processor, the most common interrupt line for signaling faults is used and for activating the first power transistor M H And a second power transistor M L Is provided for the standard control lines of (a).
Trimming must be performed only in the digital portion of the integrated circuit IC and the processor.
Disclosure of Invention
Object of the Invention
It is thus an object of the present invention to provide a solution which does not have the above-mentioned drawbacks of the prior art, which is able to distinguish between recharging and shorting of the bootstrap capacitor and which has other advantages.
Technical proposal
The deformation behavior in the gate driver corresponds to the pair U DS The response of the monitoring.
As is commonly implemented in a corresponding integrated circuit IC, a typical immediate response of a gate driver is (fig. 2): when the first power transistor M H Drain-source voltage U at DS Measured value V of (2) DS When the detection threshold value TH is exceeded, the monitoring device UV passes through the first enable line EN H Immediately turn off the first power transistor M H And activates an interrupt line INTN of the integrated circuit IC to the normally present processor in order to signal the problem to the processor.
However, unlike the previous common behavior, the second gate driver GT L The half bridge M must still be activated H 、M L Second power transistor M of (2) L To provide the processor with a recharge bootstrap capacitor C B Is a part of the prior art. This is not the case in the prior art. Here, bootstrap voltage V BST The drop of (1) results in a short-circuit fault detection which turns off the first gate driver GT H And a second gate driver GT L Thereby disabling the first power transistor M H And a second power transistor M L . According to the invention, it has been realized that this behaviour is counterproductive, since at the bootstrap voltage V BST In case of too low, the half bridge does not have to be turned off, but the bootstrap capacitance C has to be adjusted B Recharging is performed. In addition, it is also recognized that half bridge M is not immediately destroyed H 、M L But rather enables and allows a short-circuit again without danger. Thus, according to the inventive concept, the bootstrap capacitance C is first estimated B Undercharge and attempt to bootstrap capacitor C by recharging B Repairing the fault, if unsuccessful, first disabling the first power transistor M H And a second power transistor M L And then signals the short to the processor.
If the first power transistor M is turned on again H Thereafter (after the elapsed jitter time), U DS The monitoring is triggered again immediately, the integrated circuit IC (or rather the monitoring device UV) can at most permanently switch off (disable) the half bridge M H 、M L Until a valid reset of the fault, for example by an appropriate register access of the processor. In this case, bootstrap capacitor C B Is unsuccessful. If the short circuit is the cause of the first shutdown, U DS The monitoring will trigger again immediately after the next start-up after attempting recharging. When the interruption is made twice in rapid succession, the assumption must be a short circuit. In this way the discharge bootstrap capacitance C can be effectively distinguished B Cause of failure and short circuit. This has the advantage that it is then no longer necessary to permanently recharge the bootstrap capacitor C B But rather recharging when needed. Due to absence of bootstrap capacitance C B So that the maximum possible effective duty cycle is approximately 100% of PWM maximum duty cycle.
A modification as shown in fig. 3 is also conceivable.
Here, a first power transistor M H Is divided into different intervals T D 、T A 、T EA . In this case, the time starts at the start time point t 0 And opening the valve. Here, consider U DS The opening time t before monitoring 0 And possibly parametrizable debounce time T D Always remain unchanged. Debounce time T D For allowing the first power transistor M H At the time of activating U DS The monitoring is completely on before.
The subsequent classification should have the following functions:
if at debounce time T D Time of validity T thereafter A Internal trigger U DS Monitoring and turning off the corresponding first power transistor M H Or half bridge M H 、M L The processor is signaled of the fault via interrupt line INTN and, for example, the first power transistor MH cannot be turned on again until the processor actively writes to a corresponding fault register in the integrated circuit.
If at the effective time T A And debounce time T D After which the effective time T is prolonged EA Internal trigger U DS Monitoring, then the corresponding first power transistor M H (as shown in FIG. 2) is off, but may preferably be turned on again by the processor without writing to registers of the integrated circuit IC, because the active time T is prolonged EA Can be estimated from the bootstrap capacitance C B Is U DS The reason for the detection.
Preferably, the duration of the effective time T is constant and preferably parameterizable, for example by programming. Prolonging the effective time T EA Immediately following the effective time T A And always end at the first power transistor M H Is turned off. If the first power transistor M is only briefly activated H For example at duty cycle<With 100% normal PWM control, the extended active time T may not be achievable EA 。
Morphing in a processor
In theory, the response of the integrated circuit IC described herein may also be implemented by software in the processor for controlling the integrated circuit IC. However, due to the distributed delay time of the interrupt routine, the response proposal is implemented in hardware, most preferably in the PWM generator PWMG, which is the first power transistor M, or in the monitoring device UV H Generating a first PWM signal PWMH and being a second power transistor M L The second PWM signal PWML is generated. The monitoring device UV and the PWM generator PWMG can be designed as one unit, for example as a microcomputer.
Fig. 4 shows an interrupt signal INTN for fault information from the integrated circuit IC to the processor. The first PWM signal PWMH is the processor's power supply to the first power transistor M H Is a first gate driver GT of (1) H For activating the first power transistor M H . The second PMW signal PWML is the processor's power supply to the second power transistor M L Is a second gate driver GT of (1) L For activating the second power transistor M L 。
Half bridge M if PWM generator PWMG outputs H 、M L Drive signal pair G of (2) H 、G L With a duty cycle of 100%, or greater than a configurable threshold>90% + x, in the driving signal pair G H 、G L The following responses are achieved:
if a fault is reported at the interrupt input INTN of the processor, the processor immediately turns off the first power transistor M by signaling the integrated circuit IC H Is included in the first PWM driving signal PWMH. This is done, for example, by appropriate programming of the monitoring device and/or PWM generator PWMG. Thereby, the first power transistor M H Enters an off, normally high impedance state (transition 1 of fig. 4). On passing by the first gate driver GT H ) After a set dead time, the activation is then performed for the charging time T L Driving the second power transistor M for the duration of (a) L A second PWM driving signal PWML of (a). Thereby, the second power transistor M is activated for driving L Is connected to the first gate driving signal GL. Thereby, the phase output PH is connected to the potential of the negative power supply voltage line GND, and the capacitor C is bootstrapped B The voltage regulator output VG from the voltage supply circuit SV is recharged through diode D. Preferably, the charging time T L Can be configured by register programming of integrated circuit registers so that the requirements of each application can be flexibly adapted. After activating the second PWM driving signal PWML, the second gate driver GT L The fault signal should be disabled again via interrupt line INTN to signal to the processor that the desaturation fault has now been eliminated. At the time of charging T L After that, the second PWM driving signal PWML is disabled again. This is followed by another dead time to avoid through-current, after which the first PWM drive signal PWMH is activated again. Thereafter, the processor, the integrated circuit IC, the driver of the integrated circuit IC and the half bridge M H 、M L Returning again to the initial state.
When the second gate driver GT L Self-monitoring bootstrap voltage V between bootstrap node BST and phase output PH BST The signaling activity may also be implemented in the same manner. In this case, once the bootstrap voltage V between the bootstrap node BST and the phase output PH BST Again reaching a sufficient value, the fault signal on interrupt line INTN disappears. Then, as a modification of the other embodiment, once the failure signal INTN is deactivated again or a certain time elapses after the deactivation of the failure signal, the constant charging time T is replaced L Ending the charging interval of (c).
Certain measurements, such as current measurements that are typically triggered by PWM generator PWMG and fall within the recharging interval, should be suspended for the duration of the recharging interval or identified as invalid by the application's driving algorithm to avoid imbalance of the recharging control.
Description of the inventive features
The following section repeats the above description in a form similar to the claims.
The invention relates to a circuit comprising a first power transistor M H Second power transistor M L First grid electrode driverMotor GT H A second gate driver GT L Voltage supply circuit SV with voltage regulator output VG, diode D, bootstrap capacitor C B Positive power supply voltage line U S A negative supply voltage line GND and a driver stage of the monitoring device UV. Preferably, the first power transistor M H And a second power transistor M L Is a MOS transistor or an IGBT transistor. Other power semiconductors vary appropriately depending on the actual situation. First power transistor M H And a second power transistor M L Connected to positive supply voltage line U S Half bridge M with phase output PH between negative supply voltage line GND H 、M L . First power transistor M H Is connected to the positive power supply voltage line U S And its source is connected to the phase output PH. Second power transistor M L Is connected to the negative supply voltage line GND and its drain is connected to the phase output PH. First power transistor M H Is connected with the first control terminal of the first gate driver GT H GH drive is output by the first gate driver. Second power transistor M L Is connected with the second control terminal of the second gate driver GT L And outputting GL driving through the second gate driver. The logic state of the first gate driver output GH depends on the first PWM drive signal PWMH. The logic state of the second gate driver output GL depends on the second PWM driving signal PWML. A source voltage line U of Yu Zhengdian which is higher in potential relative to the GND potential of the negative power voltage line at the bootstrap node BST S At a potential relative to the potential of the negative supply voltage line GND, then at least through the bootstrap node BST to the first gate driver GT H Providing power for turning on the first power transistor M H . Diode D is connected between voltage regulator output VG and bootstrap node BST. Bootstrap capacitor C B Connected between the bootstrap node BST and the half-bridge M H 、M L Is provided between the phase outputs PH. Monitoring device UV detects the potential at bootstrap node BST and half-bridge M H 、M L Potential difference between potentials at a phase output PH of (c), and determining a corresponding bootstrap potential difference value av BST . The monitoring device UV numerically compares the determined bootstrap potential difference Δv BST And a first threshold. When the determined bootstrap potential difference value DeltaV BST When the value is smaller than the first threshold value, the monitoring device passes through the first gate driver GT H Turning off the first power transistor M H And through a second gate driver GT L Turning on the second power transistor M L . If only bootstrap capacitor C is present B Then it will be charged.
In the first proposed modification, the difference Δv is due to the determined bootstrap potential difference BST After a first switch-off, which is carried out numerically below the first threshold value, if the determined bootstrap potential difference value DeltaV BST Then, again, the value is greater than a second threshold value, which may be equal to the first threshold value, the monitoring device then passes through the first gate driver GT H The first power transistor M is turned on again H And through a second gate driver GT L Turning off the second power transistor M L . This makes it possible to test whether the bootstrap capacitor is discharged and has now been charged again or whether a short circuit exists.
Therefore, it is particularly preferable that after the first shutdown, only the charging time T elapses L Then turn on again, thereby safely giving the bootstrap capacitor C B And (5) charging.
In a further preferred embodiment the monitoring means UV then again detect the potential at the bootstrap node BST and the half-bridge M H 、M L Potential difference between potentials at the phase output PH of (c) and determining a corresponding further bootstrap potential difference value av BST . The monitoring device UV in this case numerically compares the determined further bootstrap potential difference value Δv BST And another threshold value that may be equal to the first threshold value. When another bootstrap potential difference value DeltaV is determined BST When the value is smaller than the other threshold value, the monitoring device passes through the first gate driver GT after being turned on again H Turning off the first power transistor M again H And likewise through the second gate driver GT L Turning off the second power transistor M L . This occurs because it is necessarily estimated that a short circuit is present.
Second modification example
In addition to monitoring the bootstrap voltage, the first power transistor M may be turned on H Time monitoring U DS A voltage.
Likewise, the driver stage comprises a first power transistor M H Second power transistor M L First gate driver GT H A second gate driver GT L Voltage supply circuit SV with voltage regulator output VG, diode D, bootstrap capacitor C B Positive power supply voltage line U S A negative supply voltage line GND and a monitoring device UV. First power transistor M H And a second power transistor M L Preferably MOS transistors or IGBT transistors. Other power semiconductors change as necessary according to practical situations. First power transistor M H And a second power transistor M L Connected to positive supply voltage line U S Half bridge M with phase output PH between negative supply voltage line GND H 、M L . First power transistor M H Is connected to the positive power supply voltage line U S And its source is connected to the phase output PH. Second power transistor M L Is connected to the negative supply voltage line GND and its drain is connected to the phase output PH. First power transistor M H Is connected with the first control terminal of the first gate driver GT H GH drive is output by the first gate driver. Second power transistor M L Is connected with the second control terminal of the second gate driver GT L And outputting GL driving through the second gate driver. The logic state of the first gate driver output GH depends on the first PWM signal PWMH. The logic state of the second gate driver output (GL) depends on the second PWM signal PWML. A source voltage line U of Yu Zhengdian which is higher in potential relative to the GND potential of the negative power voltage line at the bootstrap node BST S At least to the first gate driver GT via the bootstrap node BST H Providing power for turning on the first power transistor M H . Diode D is connected between voltage regulator output VG and bootstrap node BST. Bootstrap capacitor C B Connected between the bootstrap node BST and the half-bridge M H 、M L Is provided between the phase outputs PH. Monitoring device UV detectionA power transistor M H Drain U of (2) S At a potential and a first power transistor M H Potential difference between potentials at source PH of (c) and determining corresponding U DS Difference in potential. The monitoring device UV compares the determined U in value DS The potential difference value and the detection threshold TH. When the determined U DS When the potential difference is greater than the detection threshold value TH, the monitoring device passes through the first gate driver GT H Turning off the first power transistor M H And through a second gate driver GT L Turning on the second power transistor M L . This again allows the bootstrap capacitance C B Is provided.
In the first sub-variant, in the event of a failure due to a determined U DS After a previous turn-off of the potential difference value, which is numerically higher than the detection threshold TH, the monitoring device UV passes through the first gate driver GT H Turning on the first power transistor M H And through a second gate driver GT L Turning off the second power transistor M L . This again makes it possible to check whether it is the bootstrap capacity C B Discharge and bootstrap capacity C of (2) B Whether it is now charged or shorted. Thereby, the monitoring device UV again detects the first power transistor M H Drain terminal U of (2) S Is connected with the first power transistor M H Potential difference between potentials at source PH of (c) and determining the corresponding other U again DS Difference in potential. The monitoring device UV again compares the determined further U numerically DS The potential difference value and another detection threshold value that may be equal to the detection threshold value TH. When the determined other U DS The monitoring device then passes through the first gate driver GT when the potential difference value is numerically higher than the further detection threshold value H The first power transistor is turned off again and now also through the second gate driver GT L Turning off the second power transistor M L Since then a short circuit must be deduced.
Third modification example
The third modification is also related to the first power transistor M H Second power transistor M L Positive power supply voltage line U S Negative power supplyVoltage line GND and a driver stage of monitoring device UV. First power transistor M H And a second power transistor M L Preferably MOS transistors or IGBT transistors. Other power semiconductors change as necessary according to practical situations. First power transistor M H And a second power transistor M L Connected to positive supply voltage line U S Half bridge M with phase output PH between negative supply voltage line GND H 、M L . Monitoring device UV measures a first power transistor M H Drain-source voltage U at DS And determines the corresponding drain-source voltage value V DS . The monitoring device UV or another control device numerically compares the drain-source voltage value V DS And a detection threshold TH. When the drain-source voltage value V DS When the value exceeds the detection threshold TH, the monitoring device UV turns off the first power transistor M for the first time H And turns on the second power transistor M L . Subsequently, in this case, the monitoring device UV or other control means cause, in particular at the charging time T L After which the second power transistor M is turned off L And the first power transistor M is turned on again H . Then, the monitoring device UV again detects the first power transistor M H Source-drain voltage U at DS To determine another drain-source voltage value V DS2 (U DS Voltage value). The monitoring device UV then numerically compares the other drain-source voltage value V DS2 (U DS Voltage value) and another detection threshold value that may be equal to the detection threshold value TH. When the other drain-source voltage value V DS2 (U DS Voltage value) again exceeds the further detection threshold value, the monitoring device UV switches off the first power transistor M a second time H 。
In the first sub-variant, the other drain-source voltage value V DS2 When the further detection threshold is exceeded again, the monitoring device UV also switches off the second power transistor M L 。
Fourth modification example
The fourth modification shows again a first power transistor M H Second power transistor M L Positive power supply voltage line U S Negative power supplyA driver stage for the line voltage GND and the monitoring device UV. First power transistor M H And a second power transistor M L Preferably MOS transistors or IGBT transistors. Other power semiconductors change as necessary according to practical situations. First power transistor M H And a second power transistor M L Connected to positive supply voltage line U S Half bridge M with phase output PH between negative supply voltage line GND H 、M L . Monitoring device UV measures a first power transistor M H Drain-source voltage U at DS And determining the value of the drain-source voltage V DS . The monitoring device UV compares the drain-source voltage value V in value DS And a detection threshold TH. When the drain-source voltage value V DS When the detection threshold TH is exceeded in value (hereinafter referred to as first time exceeding), the monitoring device UV turns off the first power transistor M for the first time H . In this case, the monitoring means UV or other control means turn on the second power transistor M L . Subsequently, the monitoring device UV or other control device monitors the state of charge (in particular during the charging time T) L After) switching off the second power transistor M L And allows the first power transistor M to be turned on again H 。
In a first sub-variant of this variant, the monitoring device UV again measures the first power transistor M when it is turned off again after the first turn-off H Drain-source voltage U at DS To determine another drain-source voltage value V DS2 . The monitoring device UV numerically compares the other drain-source voltage value V DS2 And another detection threshold value that may be equal to the detection threshold value TH. When the other drain-source voltage value V DS2 When the value exceeds the further detection threshold again, the monitoring device UV switches off the first power transistor M a second time H 。
In a second subsidiary modification of this modification, when the other drain-source voltage value V DS2 When the detection threshold TH is exceeded again in value, the monitoring device UV or another sub-device of the drive signals only a short circuit.
In a third sub-variant of this variant, the first power transistor M is turned off for the first time H After which it is againTurning on the first power transistor M H At this time, the monitoring device UV again measures the first power transistor M H Drain-source voltage U at DS And determining another drain-source voltage value V DS2 . The monitoring device UV numerically compares the other drain-source voltage value V DS2 And another detection threshold value that may be equal to the detection threshold value TH. Subsequently, when the other drain-source voltage value V DS2 When the value is again below and then exceeds the further detection threshold again, the monitoring device UV then behaves as if it were first exceeded.
Fifth modification example
A fifth modification relates to a method for driving a power transistor including a first power transistor M H Second power transistor M L And a bootstrap capacitor C having a first connection terminal and a second connection terminal B Is described (see fig. 7). When the second power transistor M is turned on L At the time, bootstrap capacitor C is given B And (5) charging. The method comprises the following steps:
step S21: at the on time t 0 The first power transistor M is turned on (S21) H And turns off the second power transistor M L ；
Step S22: detecting (S22) bootstrap capacitance C B Potential difference between the first connection terminal and the second connection terminal, and determines a corresponding bootstrap potential difference Δv BST ；
Step S23: numerically comparing (S23) the determined bootstrap potential difference value DeltaV BST And a first threshold;
step S24: if the comparison (S23) shows that the determined bootstrap potential difference value DeltaV BST When the value is lower than the first threshold value SW1, the first power transistor M is turned off (S24) for the first time H And first turning on the second power transistor M L . In this case it is first empirically assumed that it is usually not a short circuit but a discharge of the bootstrap capacitance. In contrast to the prior art, it is not immediately concluded that it is a short circuit.
The first sub-variant of this fifth variant comprises the following additional steps:
step S25: in view of determination ofBootstrap potential difference DeltaV BST After a first turn-off, which is performed numerically below the first threshold value SW1, the first power transistor M is turned on again (S25) H And the charging time T elapses from the start of the recharging operation of step S24 L Thereafter, the second power transistor M is turned off again (S25) L . At this time, the bootstrap capacitance C is also estimated B Should be sufficiently recharged. For this purpose, it is advantageous to wait at the beginning of step S25 until the charging time T has elapsed since the charging process of step S24 L ；
Step S26: detecting (S26) the bootstrap capacitor C again B And determining a corresponding further bootstrap capacitance potential difference value DeltaV BST2 ；
Step S27: the determined further bootstrap potential difference value DeltaV is compared (S27) numerically BST2 And another threshold value that may be equal to the first threshold value;
step S28: if the other bootstrap potential difference value DeltaV is determined BST2 Again numerically below a second threshold value SW2, which may be equal to the first threshold value SW1, the first power transistor M is turned off (S28) H And turns off (S28) the second power transistor M L . In this case too, it is assumed that there is a fault. In which case the type of fault is not distinguished. But the method is particularly simple. Thus, an attempt is made to recharge the bootstrap capacitor again, and if unsuccessful, a fault condition is presumed and a safe state is assumed.
Step S29: when the other bootstrap potential difference value DeltaV is determined BST2 When the second threshold value SW2 is exceeded again in value, the first power transistor M is turned on (S29) (corresponding to the state of the holding step S25) H And turns off (S29) the second power transistor M L 。
Preferably, the re-turn-on (S29) after the first turn-off (S24) is performed only after passing through the bootstrap capacitor C B Charging time T of (2) L And then occurs.
Sixth modification example
A sixth modification relates to a method for driving a power transistor including a first power transistor M H First, theTwo-power transistor M L And a bootstrap capacitor C having a first connection terminal and a second connection terminal B Is described (fig. 8). When the second power transistor M is turned on L Bootstrap capacitor C B ) Is recharged. The method comprises the following steps:
step S31: at the start time t 0 The first power transistor M is turned on H And turns off the second power transistor M L . If at the starting time t 0 The first power transistor M has been turned on H And at the opening time point t 0 The second power transistor M has been turned off L This step is not required;
step S32: detecting a first power transistor M H U at DS Voltage and determine corresponding U DS Voltage value V DS ；
Step S33: numerically comparing the determined U DS Voltage value V DS And a first threshold value SW1;
step S34: when the comparison indicates the determined U DS Voltage value V DS When the value is lower than the threshold value SW1, the first power transistor M is turned off for the first time H And first turning on the second power transistor M L 。
The first sub-modification of the sixth modification comprises the steps of:
step S35: after step S34, the first power transistor M is turned on again H And turn off the second power transistor M again L Wherein this step is especially at a charging time T L Then, the process is carried out;
step S36: when the first power transistor M is turned on H At this time, the first power transistor M is again detected H U at DS Voltage U DS And again determine the corresponding other U DS Voltage value V DS2 ；
Step S37: numerically comparing the determined other U DS Voltage value V DS2 And another threshold value SW2 which may be equal to the first threshold value SW1;
Step S38: if another U is determined DS Voltage value V DS2 Exceeding a second threshold value SW2, which may be equal to the first threshold value SW1, again turns off the first power transistor M H The second power transistor M is turned off again L ；
Step S39: if another U is determined DS Voltage value V DS2 When the value is again lower than the second threshold value SW2, the first power transistor M is turned on (S39) (corresponding to the state of maintaining S35) H And turns off (S39) the second power transistor M L 。
Preferably, the re-opening (S35) after the first closing (S34) is performed only after the charging time T has elapsed L And then performed.
Seventh modification example
The seventh modification is again directed to driving a transistor including a first power transistor M H Second power transistor M L And a bootstrap capacitor C having a first connection terminal and a second connection terminal B Is described (fig. 5). When the second power transistor M is turned on L Bootstrap capacitor C B Is recharged. The method again comprises the steps of:
at the start time t 0 The first power transistor M is turned on (S1) H And turns off the second power transistor M L ；
At the start time t 0 After which the jitter time T is passed D Time of validity T thereafter A In (S2) detecting the first power transistor M H U of (2) DS Voltage and determine corresponding U DS Voltage value V DS ；
At the effective time T A Is determined by comparing (S3) the values of the determined U DS Voltage value V DS And a first threshold value SW1; and
when the comparison shows that at the effective time T A Internally determined U DS Voltage value V DS When the value exceeds the first threshold value SW1, the first power transistor M is turned off (S4) H . Therefore, this step is performed here because, in the case where the violation of the first threshold SW1 occurs so rapidly, it is necessary to estimate that there is a short circuit. Thus, the second power transistor M L Also here shut off, becauseIt should then be excluded that there may be damage to the first power transistor M H Through current of the case of (2). Because the drive itself performs the emergency shutdown, no rapid intervention of an external control computer is typically required. Therefore, it is preferable that the information of the occurrence of the short circuit of the device is not signaled by the interrupt line INTN, but the signal of the interrupt line INTN is used only for signaling that something is happening. The actual information is stored in a data memory of the drive, which can be read by an external control computer. The external control computer then typically first attempts to turn off the first power transistor M H And turn on the second power transistor M L To bootstrap capacitor C B Recharging. Only then can the external control computer read the driver register via the data bus DB and thus recognize the short circuit. Thus, the control computer cannot turn on the second power transistor M in the event of a short circuit H For example, after the occurrence of such a fault situation, the monitoring device UV and/or PWM generator G prevents this switching on until a dedicated, separate release command of the external computer system explicitly allows the second power transistor M to be switched on again L ；
At the start time t 0 After a valid time T A And debounce time T D After which the effective time T is prolonged EA In (S5) detecting the first power transistor M H U at DS Voltage and determine another corresponding U DS Voltage value V DS2 。
At prolonged effective time T EA Intrinsic numerically comparing (S6) the determined other U DS Voltage value V DS2 And a second threshold value SW2.
If the comparison shows that the time of validity T is prolonged EA Said another U as determined therein DS Voltage value V DS2 Exceeding a second threshold value SW2, which may be equal to the first threshold value SW1, turns off (S7) the first power transistor M H And turn on the second power transistor M L . Therefore, in this case, the first power transistor M H Is not sufficiently on, has too high a power consumption and must therefore be turned off. In which case this step is carried outSince it is presumed that a short circuit would cause a violation of the thresholds SW1, SW2 faster, the short circuit violation occurs insufficiently fast, and is therefore the bootstrap capacitance C B Is provided. Therefore, in order to recharge the bootstrap capacitor, the second power transistor M is turned on in this case L . Step S7 is also a recharging step. Typically, the shut down is signaled by an interrupt line INTN. By step S7, the bootstrap capacitor C for the possible discharge is thereby started B And (5) charging.
A first sub-variant of the seventh variant (see also fig. 5) relates to a bootstrap capacitor C B And comprises the following additional steps compared to the basic steps of the seventh variant:
if the charging time T has elapsed L Before an extension time T EA Another U determined in (a) DS Voltage value V DS2 The comparison with the second threshold value SW2 has triggered the first power transistor M H Is turned off and the second power transistor M L Is turned on at the charging time T L Thereafter turning on (S8) the first power transistor M H And turns off the second power transistor M L . The bootstrap capacitance C is estimated in the aforementioned step S7 B Is provided. Now presume bootstrap capacitance C B Is sufficiently charged, the previously estimated discharged bootstrap capacitance C is terminated B Is provided. This is preferably signaled by an interrupt line INTN.
Bootstrap capacitor C of seventh modification B Is subject to U DS The second sub-variant of the controlled recharging comprises the following additional steps compared to the basic steps of the seventh variant and to the first sub-variant:
At charging time T L Internal detection (S9) of the first power transistor M H U at DS Voltage U DS And determining a corresponding third U DS Voltage value V DS3 The charging time starts from the first power transistor M in the previous step S7 H Is turned off and the second power transistor M L Is opened.
Numerically comparing (S10) the determined U DS Voltage value V DS3 And can be used forA third threshold value SW3 equal to the first threshold value SW1 and the second threshold value SW 2;
if at charging time T L Before ending, the determined U DS Voltage value V DS3 A numerical comparison with the third threshold value SW3 indicates a determined U DS Voltage value V DS3 Exceeding the third threshold value SW3 in value, turning on (S8) the first power transistor M H And turns off the second power transistor M L . Therefore, bootstrap capacitor C B Is not time controlled but is performed in accordance with the off state of the first power transistor. Thus, at a high duty cycle close to 100%, the bootstrap capacitor C is recharged only to an absolute extent by B To control the corresponding duty cycle. In pure time control with a charging time longer than the maximum charging time, time constraints must be considered for safety reasons in order to exclude any through current. Thus, in the case of purely time-controlled, the interference is significantly greater than in the case of the pass-through U also proposed here DS A recharging method is controlled in which a difference between a short circuit and recharging occurs at the instant when a threshold violation occurs after turning on. In addition, the effective time T can be prolonged EA Selected such that the debounce time T D Plus the effective time T A Plus an extended effective time T EA And is equal to the PWM period, thereby removing the jitter time T A Except for constant monitoring. Preferably, the effective time T A Throughout each PWM period, i.e. no power transistor M occurs between two PWM periods H 、M L The jitter removal time T can be set when the switch state of (1) is changed D Set to 0 seconds.
The third sub-modification of the seventh modification (see also fig. 6) includes the following additional steps compared to the first and second sub-modifications of the seventh modification:
at charging time T L Internal detection (S9) of the first power transistor M H U at DS Voltage U DS And determines the corresponding third U DS Voltage value, charging time T L Starting from a first power transistor M H Is turned off and the second power transistor M L Is opened;
comparing (S10) the determined third U numerically DS Voltage value V DS3 And a third threshold value SW3 which may be equal to the first threshold value SW1 and the second threshold value SW 2;
if the third U is determined DS Voltage value V DS3 A numerical comparison with the third threshold value SW3 indicates a determined third U DS Voltage value V DS3 When the value is lower than the third threshold value, the first power transistor M is turned off (S11) H And turns off the second power transistor M L . Here, bootstrap capacitor C B May be unsuccessful or have a short circuit. Thus, as in the case of a short circuit in step S4, it is preferable here again to signal via the interrupt line INTN, the register of the integrated circuit IC and the monitoring device UV and/or the PWM generator PWMG. Preferably, as in step S4, the PWM generator PWMG and/or the monitoring device UV avoid turning on the second power transistor M again by the external control computer L Until the special release instruction of the external control computer is allowed to be so turned on again via the special register. Preferably, the integrated circuit IC (in particular the monitoring device UV and/or the PWM generator PWMG) outputs a fault code, which is different from the fault code in the case of the short-circuit detection in step S4, to the external control computer via the register and the data bus DB in the event of such a fault.
Advantages of the invention
The main advantage of the above described invention is that the achievable duty cycle at the phase output PH is closer to 100% than in the prior art solutions and the bootstrap capacitance C can be distinguished B Parasitic discharges and shorts of (a). If the recharging of the bootstrap capacitor occurs too frequently, i.e. the period between two recharging is below the minimum recharging period, this is indicative of the bootstrap capacitor C B A fault occurs that may be safety-related and may be reported and handled separately. Such differentiation is also not possible in the prior art. The advantage is not limited thereto.
Drawings
Fig. 1 shows a schematic simplified block diagram of a driver stage according to the invention.
Fig. 2 shows a first power transistor M H Drain-source voltage V at DS A process profile with respect to time t and a process profile of the interrupt signal INTN.
Fig. 3 shows at the opening time t 0 Turning on the first power transistor M H Thereafter, a first power transistor M H Bootstrap voltage V at BST -V PH And gate-source voltage V GS A process curve with respect to time.
Fig. 4 shows the bootstrap capacitor C B Signal process curves for various signals during the recharging process.
Fig. 5 shows self-lifting capacitor C B Time and demand controlled recharging.
Fig. 6 shows self-lifting capacitor C B Is subject to U DS And a demand controlled recharging flow chart.
FIG. 7 shows that the capacitor C is not being shorted and bootstrapped B Bootstrap capacitance C in case of differentiation between faults of (C) B Is bootstrapped by a bootstrap voltage V BST And recharging time T L A flow chart of recharging of the control.
FIG. 8 shows that the capacitor C is not being shorted and bootstrapped B Bootstrap capacitance C in case of differentiation between faults of (C) B Is subjected to drain-source voltage V DS And recharging time T L A flow chart of recharging of the control.
FIG. 9 shows the bootstrap capacitance C without termination condition B Is bootstrapped by a bootstrap voltage V BST And recharging time T L A flow chart of recharging of the control.
Detailed Description
Fig. 1 shows a schematic simplified block diagram of a driver stage according to the invention. The core of the driver stage is a first power transistor M H And a second power transistor M L Composed half bridge M H 、M L . Half bridge M H 、M L Form a phase output PH. Control of the first power transistor M by the first gate control signal GH H Is provided. The first gate control signal GH passes through the first gate driver GT H Is generated in response to a first PWM drive signal PWMH for driving a control electrode of the first power transistor MH. Here, the first gate driver GT H From bootstrap capacitor C B Or positive power supply voltage line U S Directly or indirectly. If the positive power supply voltage line U S Is too low compared to the reference potential GND, then is formed by the bootstrap capacitor C B To the first gate driver GT H The power supply, namely the bootstrap capacitor C B The reason for having to be fully charged at all times. The monitoring device UV may force the first power transistor M to be turned off (i.e. disabled) by the first gate control signal GH H Wherein the monitoring device UV passes through the first enable signal EN H To the first gate driver GT H Signaling to put the first gate control signal GH off the first power transistor M H Is a state of (2). Control of the second power transistor M by the second gate control signal GL L Is provided. The second gate control signal GL passes through the second gate driver GT L Generating in response to the second PWM driving signal PWML for driving the control electrode G of the second power transistor PWML L . Here, the second gate driver GT L Usually by positive supply voltage line U only S Directly or indirectly. The monitoring device UV can forcibly turn off (i.e. disable) the second power transistor M by the second gate control signal GL L Wherein the monitoring device UV passes through the second enable signal EN L To the second gate driver GT L Send out a signal to put the second gate control signal GL to turn off the second power transistor M L Is a state of (2). Preferably, the voltage supply circuit SV generates at its voltage regulator output VG a constant voltage V compared to the reference potential GND VG . By supporting capacitor C VG To make the constant voltage V VG And (3) stability. When the second power transistor M is turned on L And turns off the first power transistor M H In this case, because of the bootstrap capacitance C B The other terminal of (a) is connected to the reference potential GND, so that the voltage regulator output VG of the voltage supply circuit SV can be supplied to the bootstrap capacitor C via the diode D B And (5) charging. When positive power supply voltage line U S The potential on the electrode is for any reason within a short period of timeIn case of breakdown, the bootstrap capacitance may be given to the first gate driver GT in particular subsequently H Is provided. Thus, in the first power transistor M H When to be turned off, ensure the first power transistor M H Has a sufficiently high potential. The monitoring means UV can monitor both the potential at the bootstrap node BST compared to the reference potential and the first power transistor M in the off-state H As U on DS Voltage U DS Is a voltage drop across the capacitor. In the event of a fault, a deviation can be detected and the power transistor M can be switched off H 、M L . Preferably, the PWM generator PWMG is provided for driving the first power transistor M H First PWM signal PWMH of (a) and for driving second power transistor M L Is included in the second PWM signal PWML. In the event of a fault, in this example, the monitoring device communicates with a processor (not shown) via interrupt line INTN.
Fig. 2 shows the first power transistor M H First power transistor M in on state of (2) H Drain-source voltage V at DS A process curve with respect to time t and a process curve of the interrupt signal INTN. Due to bootstrap capacitance C B Is discharged from the first power transistor M H Drain-source voltage V at DS And rises because the transistor can no longer be turned on sufficiently. Whereby the first power transistor M H Increases on-resistance of (2) and drain-source voltage V DS Raised. When the detection threshold TH is exceeded, the monitoring means UV detect this rise and activate the interrupt signal INTN. Here, the exemplary interrupt signal is drawn as Active Low (Low-Active).
Fig. 3 shows when at the opening time point t 0 Turning on the first power transistor M H Thereafter bootstrap capacitor C B Bootstrap voltage V at BST -V PH And a first power transistor M H Gate-source voltage V at GS A process curve with respect to time. At the debounce time T D The signal itself must first stabilize. Only then can the effective time T be started A . If a fault occurs during this time, the fault is highly likely to be a short circuit. But the fault may also be a bootstrap capacitor C B Is provided. In this case, the monitoring device UV therefore first turns on the second power transistor M L And turn off the first power transistor M H Since the bootstrap capacitance C can then be switched from the voltage supply circuit SV to the diode D B And (5) charging. At charging time T L After or when bootstrapping the capacitor C B When the voltage is enough, the monitoring device turns on the first power transistor M again H And turns off the second power transistor M L . If the fault is still present later, then the fault is most likely a short circuit. For example, two power transistors M H 、M L Possibly broken down. Thus, the two power transistors M are then turned off H 、M L . It is also conceivable that such a fault during the active time is essentially evaluated as a short circuit and then immediately turns off both power transistors M H 、M L . If the effective time T is prolonged EA A fault occurs in the capacitor, then the fault is very likely to be the bootstrap capacitor C B Is provided. In this case, the second power transistor M may be omitted L Is turned off. However, it is preferred to propose a two-step process.
Fig. 4 shows the bootstrap capacitor C B Exemplary waveform signal waveforms of various signals during the recharging process. The monitoring means UV first activate the interrupt signal INTN. In this example, the monitoring device UV influences the PWM generator PWMG via this signal INTN and possibly one or more further control signals ST. Because of action chain 1, in this example PWM generator PWMG deactivates first PWM signal PWMH and turns off first power transistor M H . Alternatively, the first enable signal EN may also be provided H And a first gate driver GT H To realize the method. At a first dead time T normally ensured by a PWM generator or monitoring device T1 After that, the second power transistor M is turned on by the second PWM signal PWML L The second PWM signal PWML resets the interrupt signal through the action chain 2.
Fig. 5 shows self-lifting capacitor C B Time and demand controlled recharging.
The flow chart basicallyCorresponding to a seventh variant for operating a driver stage comprising a first power transistor M H Second power transistor M L And a bootstrap capacitor C having a first terminal and a second terminal B . When the second power transistor M is turned on L Bootstrap capacitor C B Is recharged. The method of the seventh modification example includes the steps of:
at the start time t 0 The first power transistor M is turned on (S1) H And turns off the second power transistor M L ；
At the start time t 0 After which the jitter time T is passed D Time of validity T thereafter A In (S2) detecting the first power transistor M H U at DS Voltage and determine corresponding U DS Voltage value V DS ；
Numerically comparing (S3) the time of validity T A Is determined by U DS Voltage value V DS And a first threshold value SW1; and is also provided with
If the comparison indicates that at the effective time T A Internally determined U DS Voltage value V DS Exceeding the first threshold value SW1 in value, turning off (S4) the first power transistor M H . This step is performed here because in case of a rapid violation of the first threshold value SW1, it has to be assumed that a short circuit is present. The second power transistor M is therefore also switched off here L Since the first power transistor M, which may be damaged, should then be excluded H Through current in the case of (2). Because the drive itself performs the emergency shutdown, no rapid intervention of an external control computer is typically required. Thus, preferably, no short-circuit message is signalled to the device via the interrupt line, but the signal of the interrupt line INTN is used only to signal something to happen. The actual information is stored in a data memory of the drive that is accessible by an external control computer. Typically, the external control computer then first tries to turn off the first power transistor M H And turn on the second power transistor M L To bootstrap capacitor C B Recharging. Only then can the external control computer read the driver registers via the data bus DB andthus identifying a short circuit. Thus, the control computer cannot turn on the second power transistor M in the event of a short circuit L For example, after the occurrence of such a fault, the monitoring device UV and/or the PWM generator G prevents this switching on until a special, separate release command of the external computer system explicitly allows the second power transistor M to be switched on again L ；
At the start time t 0 After a valid time T A And debounce time T D After which the effective time T is prolonged EA In (S5) detecting the first power transistor M H U at DS Voltage and determine the corresponding other U DS Voltage value V DS2 ；
At prolonged effective time T EA In (S6) comparing the determined other U in value DS Voltage value V DS2 And a second threshold value SW2; and is also provided with
If the comparison shows that the time of validity T is prolonged EA Another U determined in (a) DS Voltage value V DS2 Exceeding a second threshold value SW2, which may be equal to the first threshold value SW1, turns off (S7) the first power transistor M H And turn on the second power transistor M L . Therefore, in this case, the first power transistor M H Is not sufficiently on, has too high a power consumption and must therefore be turned off. This step is performed in this case because it is believed that the short circuit would cause the threshold values SW1, SW2 to be violated more quickly, and therefore, since no violation of the short circuit occurs fast enough, the violation is the bootstrap capacitance C B Is provided. Therefore, in this case, the second power transistor M is turned on L To bootstrap capacitor C B Recharging is performed. Step S7 is also a recharging step. Typically, the shut down is signaled by an interrupt line INTN.
If the charging time T has elapsed L Before the effective time T is prolonged EA Another U determined in (a) DS Voltage value V DS2 The comparison with the second threshold value SW2 has triggered the first power transistor M H Is turned off and the second power transistor M L Is turned on atCharging time T L Thereafter turning on (S8) the first power transistor M H And turns off the second power transistor M L . In the previous step S7, the assumed violation is the bootstrap capacitance C B Is provided. The bootstrap capacitance C, which will now begin to discharge the presumption B And (5) charging.
At the end of the PWM period TPWM, one period is preferably started again.
Fig. 6 shows self-lifting capacitor C B Is subject to U DS And a demand controlled recharging flow chart. This essentially corresponds to the procedure of the seventh method variant for operating a driver stage comprising a first power transistor M H Second power transistor M L And a bootstrap capacitor C having a first connection terminal and a second connection terminal B . When the second power transistor M is turned on L Bootstrap capacitor C B Is recharged. The method of the seventh modification example includes the steps of:
at the start time t 0 The first power transistor M is turned on (S1) H And turns off the second power transistor M L ；
At the start time t 0 After which the jitter time T is passed D Time of validity T thereafter A In (S2) detecting the first power transistor M H U at DS Voltage and determine corresponding U DS Voltage value V DS ；
Numerically comparing (S3) the time of validity T A Is determined by U DS Voltage value V DS And a first threshold value SW1, and turning off the first power transistor M H The method comprises the steps of carrying out a first treatment on the surface of the And
when the comparison shows that at the effective time T A Is determined by U DS Voltage value V DS When the value is larger than the first threshold value SW1, the second power transistor M is turned off (S4) L . Therefore, this step is performed here because in the case where the violation of the first threshold SW1 occurs so quickly, it must be estimated that there is a short circuit. Thereby, the second power transistor M L Also here turned off, since then the possibly damaged first power transistor M should be excluded H Through current of the case of (2). Because ofThe drive itself performs the emergency shutdown, so that no rapid intervention of an external control computer is typically required. Thus, preferably, no information is signaled to the device that a short circuit has occurred by the interrupt line, but the signal of the interrupt line INTN is used only to signal that something has occurred. The actual information is stored in a data memory of the drive readable by an external control computer. Typically, the external control computer will then attempt to turn off the first power transistor M H And turn on the second power transistor M L To bootstrap capacitor C B Recharging. Only then can the external control computer read the driver register via the data bus DB and thus recognize the short circuit. Thus, the control computer cannot turn on the second power transistor M in the event of a short circuit L For example, after the occurrence of such a fault situation, the monitoring device UV and/or PWM generator G prevents this switching on until a dedicated, separate release command of the external computer system explicitly allows the second power transistor M to be switched on again L 。
At the start time t 0 After which the jitter time T is passed D And effective time T A After which the effective time T is prolonged EA In (S5) detecting the first power transistor M H U at DS Voltage and determine another corresponding U DS Voltage value V DS2 。
At prolonged effective time T EA In (S6) comparing numerically the determined other U DS Voltage value V DS2 And a second threshold value SW2; and
if the comparison shows that the time of validity T is prolonged EA Is determined by the other U DS Voltage value V DS2 When the value exceeds a second threshold value SW2 which can be equal to the first threshold value SW1, the first power transistor M is turned off (S7) H And turn on the second power transistor M L . Therefore, in this case, the first power transistor M H Is not sufficiently on, has too high a power consumption and must therefore be off. This step is performed in this case because it is believed that the short circuit would cause the thresholds SW1, SW2 to be violated more quickly, and therefore, because the short circuit does not occur fast enoughSo the violation threshold is necessarily the bootstrap capacitance C B Is provided. Therefore, in this case, in order to provide the bootstrap capacitor C B Recharging is performed, and the second power transistor M is turned on L . Thus, step S7 is a recharging step. Typically, the shut down is signaled by an interrupt line INTN.
At charging time T L In (S9) detecting the first power transistor M H U at DS Voltage U DS And determines a corresponding third U DS Voltage value V DS3 The charging time T L The first power transistor M starts in the previous step S7 H Is turned off and the second power transistor M L Is opened;
comparing (S10) the determined third U numerically DS Voltage value V DS3 And a third threshold value SW3 which may be equal to the first threshold value SW1 and the second threshold value SW 2;
if at charging time T L Before ending, the third U is determined DS Voltage value V DS3 A numerical comparison with the third threshold value SW3 indicates a determined third U DS Voltage value V DS3 When reaching the third threshold value SW3 in value, the first power transistor M is turned on (S8) H And turns off the second power transistor M L . Therefore, bootstrap capacitor C B Is not time-controlled but is based on a first power transistor M H Is performed in the off state. Thus, in the case of a high duty cycle close to 100%, the bootstrap capacitance C is reduced by only the absolute extent necessary B Recharging to control the corresponding duty cycle. For a charging time T longer than the maximum charging time L For safety reasons, a time delay must be considered in order to exclude any kind of through-current. Thus, in the case of pure time control, the disturbance is significantly greater than the passage U also proposed here DS A recharging method is controlled in which a short-circuit condition and a recharging condition are distinguished by a point in time at which a threshold violation occurs after turning on. In addition, the effective time T can be prolonged EA Selected such that the debounce time T D Plus the effective time T A Plus an extended effective time T EA And is equal to the PWM period, thereby removing the jitter time T D Except for constant monitoring. Preferably, the effective time T A Throughout each PWM period, i.e. no power transistor M occurs between two PWM periods H 、M L The jitter removal time T can be set when the switch state of (1) is changed D Set to 0 seconds.
If the comparison of the determined third threshold value SW3 and the third threshold value SW3 in value indicates the determined third U DS Voltage value V DS3 When the value is lower than the third threshold value, the first power transistor M is turned off (S11) H And turns off the second power transistor M L . Here, bootstrap capacitor C B May be unsuccessful or have a short circuit. Hereby, as in the case of a short circuit in step S4, it is preferable here again to signal via the interrupt line INTN and the register of the integrated circuit IC and the monitoring device UV and/or the PWM generator PWMG. Preferably, as in step S4, the PWM generator PWMG and/or the monitoring means UV avoid turning on the second power transistor M again by means of an external control computer L Until the special release instruction of the external control computer is allowed to be so turned on again via the special register. Preferably, the integrated circuit IC (in particular the monitoring device UV and/or the PWM generator PWMG in the event of such a fault transmits a fault code to the external control computer via the register and the data bus DB which is different from the fault code in the event of the short-circuit detection in step S4.
FIG. 7 shows the bootstrap capacitance C without distinguishing between short circuits and bootstrap capacitance B By bootstrap voltage V in case of failure of (C) BST And recharging time T L Control bootstrap capacitor C B Is provided.
The method of this example may be implemented by a circuit including a first power transistor M H Second power transistor M L First gate driver GT H A second gate driver GT L Voltage supply circuit SV with voltage regulator output VG, diode D, bootstrap capacitor C B Positive power supply voltage line U S Negative supply voltage line GND and monitoring deviceThe driver stage for UV is implemented. First power transistor M H And a second power transistor M L Should be connected again to the positive power supply voltage line U S Half bridge M with phase output PH between negative supply voltage line GND H 、M L . Reference is made herein to the foregoing embodiments.
In a first step S21, the first power transistor M is turned on H And turns off the second power transistor M L . In S22 the monitoring means UV then detects the potential at the bootstrap node BST and the half-bridge M H 、M L Potential difference between potentials at phase outputs PH, and determining corresponding bootstrap potential difference value av BST . The monitoring device UV in a further subsequent step S23 numerically compares the determined bootstrap potential difference Δv BST And a first threshold value SW1. When the determined bootstrap potential difference value DeltaV BST When the value is lower than the first threshold value SW1 in the comparison step S23, the monitoring device UV passes through the first gate driver GT in a further step S24, which is conditionally executed H Turning off (S24) the first power transistor M H And through a second gate driver GT L Turning on the second power transistor M L 。
In (step S24) the bootstrap potential difference Δv due to the bootstrap potential difference value already determined during the comparison step S23 BST Sometime after a first turn-off, which is performed numerically below the first threshold value SW1, the monitoring device UV passes through the first gate driver GT in a further step S25 H The first power transistor M is turned on again H And through a second gate driver GT L Turning off the second power transistor M L . Preferably, the re-turn-on (in step S25) is performed only after the first turn-off (step S24) for the charging time T L And then performed. Safety precautions should be followed here. In a subsequent step S26, the monitoring means UV again detect the potential at the bootstrap node BST and the half-bridge M H 、M L Potential difference between potentials at the phase output PH of (c) and determining a corresponding further bootstrap potential difference value av BST2 . In a next step S27, the monitoring device UV numerically compares the determined further bootstrap potential difference value Δv BST2 And can be in combination with a first thresholdAnother threshold value SW2 where the values SW1 are equal. If the further bootstrap potential difference value DeltaV is determined in the above-mentioned comparison step S27 BST2 When the value is lower than the other threshold value SW2, in the next step S28, the monitoring device passes through the first gate driver GT after being turned on again (S25) H Turning off the first power transistor M again H And pass through a second gate driver GT L Likewise turn off the second power transistor M L 。
FIG. 8 shows the bootstrap capacitance C without distinguishing between short circuits and bootstrap capacitance B By drain-source voltage V in case of failure DS And recharging time T L Control bootstrap capacitor C B Is provided.
The method of this example may be implemented by a circuit including a first power transistor M H Second power transistor M L First gate driver GT H A second gate driver GT L Voltage supply circuit SV with voltage regulator output VG, diode D, bootstrap capacitor C B Positive power supply voltage line U S The driver stage of the negative supply voltage line GND and the monitoring device UV. First power transistor M H And a second power transistor M L Should be connected with the positive power voltage line U again S Half bridge M with phase output PH between negative supply voltage line GND H 、M L And (5) connection. Reference is made herein to the foregoing embodiments.
In a first step S31, at an on time point t 0 Turning on the first power transistor M H And turns off the second power transistor M L . Time t and the opening time t 0 Related to the following. First wait for debounce time T D In the past, transients were thereby completed. In the next step S32, when the first power transistor M is turned on H When (already occurring in step S31), the monitoring means UV detects the first power transistor M H Potential at drain of (c) and first power transistor M H Potential difference between potentials at source PH of (c) and at least temporarily determining drain-source voltage U DS Corresponding drain-source voltage value V of DS . In a next step S33, the monitoring device UV numerically compares the drain-source voltage U DS Is determined by (3)Constant drain-source voltage value V DS And a detection threshold TH (first threshold SW 1). In a conditional next step S34, when the determined drain-source voltage U DS Drain-source voltage value V of (2) DS When the value exceeds the detection threshold TH (the first threshold SW 1), the monitoring device passes through the first gate driver GT H Turning off the first power transistor M H And through a second gate driver GT L Turning on the second power transistor M L . Thereby starting to try to bootstrap capacitor C B Recharging. In (due to the determined drain-source voltage U in the comparison step S33 DS Drain-source voltage value V of (2) DS After a switch-off in step S34, which is performed numerically exceeding the detection threshold TH (first threshold SW 1), the monitoring device UV passes through the first gate driver GT in a next step S35 after a period of time H Turning on the first power transistor M H And through a second gate driver GT L Turning off the second power transistor M L . The monitoring device UV again detects the first power transistor M in a subsequent next measurement step S36 H Drain terminal U of (2) S And a first power transistor M H Potential difference between potentials at source PH of (C) and determining drain-source voltage U DS Another corresponding drain-source voltage value V DS2 . In a subsequent next comparison step S37, the monitoring device UV numerically compares the determined further drain-source voltage value V DS2 And another detection threshold value (second threshold value SW 2) that may be equal to the detection threshold value TH (first threshold value SW 1). In a further conditional step S38, when the drain-source voltage U determined in the comparing step S37 DS Another drain-source voltage value V of (2) DS2 When the value exceeds the other threshold value (second threshold value SW 2), the monitoring device UV passes through the first gate driver GT in S38 H Turning off the first power transistor M again H And through a second gate driver GT L The second power transistor M is also turned off L . Subsequently there is a short circuit or bootstrap capacitance C B Failure, the short circuit or bootstrap capacitor C B Faults may then be signaled to higher level computer systems by interrupt lines INTN and/or data bus DB in combination with specially set register information within the integrated circuit ICNotification and communication.
In the comparing step S37, when the determined drain-source voltage U DS Another drain-source voltage value V of (2) DS2 When the value is lower than the other detection threshold value (second threshold value SW 2), the bootstrap capacitor C B Is sufficiently charged and then there is no short circuit either. In the next step S29, the first power transistor M H Can be safely kept on and the second power transistor M L Remain off. Preferably, then wait until PWM period T PWM Ending until the next measurement S32. In step S31, in the first power transistor M H And a second power transistor M L Without a change in the switching state, the debounce time T can be reduced due to the absence of transients D Selected to be 0 seconds.
FIG. 9 shows the passage of the bootstrap voltage V without termination conditions BST And recharging time T L Control bootstrap capacitor C B Is provided. The figure shows an exemplary method for operating a driver stage comprising a first power transistor M H Second power transistor M L And a bootstrap capacitor C having a first connection terminal and a second connection terminal B . When the second power transistor M L Bootstrap capacitor C when turned on B Is charged. The method comprises the following steps:
step S42: detection bootstrap capacitor C B And determines a corresponding bootstrap potential difference DeltaV BST (S22、S42)；
Step S43: numerically comparing the determined bootstrap potential difference value DeltaV BST And a first threshold value SW1;
step S44: when the comparison step S43 shows that the determined bootstrap potential difference value DeltaV BST When the value is lower than the first threshold value SW1, the first power transistor M is turned off H And first turning on (S24, S44) the second power transistor M L . Thereby starting to recharge the bootstrap capacitor C B ；
Step S45: due to the determined bootstrap potential difference DeltaV BST Numerically, a method of manufacturing the sameLess than the first threshold value SW1, after the first turn-off in step S44, in particular at the charging time T L After that, the first power transistor M is turned on again H And turns off the second power transistor M again L ；
Step S46: detecting (S46) the bootstrap capacitor C again B And determining (S46) a corresponding further bootstrap potential difference value Δv BST2 ；
Step S47: numerically comparing the determined further bootstrap potential difference value DeltaV BST2 And another threshold value SW2 which may be equal to the first threshold value SW 1. However, contrary to FIG. 7, if another bootstrap potential difference value DeltaV is determined BST2 When the value is again lower than the second threshold value SW2 which can be equal to the first threshold value SW1, as in step S44, the first power transistor M is turned off again (S44) H And turns on again (S44) the second power transistor M L . Where it will be recharged for a long time until the bootstrap voltage V BST Is equal to the second threshold value SW2. This can be used to prevent through-currents in the device in different ways. As previously mentioned, it is particularly advantageous that in step S45 after the first shutdown in step S44, only the charging time T has elapsed L And then turned on again.
List of reference numerals
A BST bootstrap input;
C VG constant voltage V for voltage regulator output VG of regulated voltage supply circuit SV VG External support capacitance of (a);
a D diode;
DB data bus. For example, the external computer may access the integrated circuit IC and/or the monitoring device UV and/or the internal registers of the PWM generator PWMG via a data bus. For example, a data bus interface may be used to signal a short circuit and/or bootstrap capacitance C B Is a discharge or sufficient charge of (a);
ΔV BST bootstrap potential difference value. By detecting bootstrap capacitance C B The potential difference between the first connection terminal and the second connection terminal determines the bootstrap potential difference value. Bootstrap potential difference value general tableShowing the voltage value between these terminals. Determining a bootstrap potential difference value in steps S22 and S42 in the example of the drawing;
ΔV BST2 another bootstrap potential difference value. By detecting bootstrap capacitance C B The potential difference between the first connection terminal and the second connection terminal determines another bootstrap potential difference value. Another bootstrap potential difference value generally represents the voltage value between these terminals. In the example of the drawing, another bootstrap potential difference value is determined in steps S26 and S46;
EN H a first enable signal. The monitoring device UV uses the first enable signal to the first gate driver GT H Signaling that the first gate control signal GH should be set to turn off (i.e., disable) the first power transistor M H Is a state of (2).
EN L A second enable signal. The monitoring device UV uses the second enable signal to the second gate driver GT L Signaling that the second gate control signal GL should be set to turn off (i.e., disable) the second power transistor M L State of (2);
GND negative supply voltage line. The potential of the negative supply voltage line is the reference potential in the embodiments presented herein, unless otherwise specified;
GH first gate control signal. The first gate control signal is generated by the first gate driver GT H Responsive to the first power transistor M being driven H The first PWM driving signal PWMH of the control electrode of (a) is generated. Here, the first gate driver GT H From bootstrap capacitor C B Or positive power supply voltage line U S Directly or indirectly. If the positive power supply voltage line U S Is too low compared to the reference potential GND, then from the bootstrap capacitance C B Proceed with the first gate driver GT H The bootstrap capacitance must always be power-hungry. The control device UV can forcibly turn off the first power transistor M by the first gate control signal GH H Wherein the monitoring device UV passes through the first enable signal EN H To the first gate driver GT H Signaling to set the first gate control signal to turn off (i.e., disable) the first power transistor M H State of (2);
and GL second gate control signal. The second gate control signal is generated by the second gate driver GT L Responsive to being used to drive the second power transistor M L The second PWM driving signal PWML of the control electrode of (a) is generated. Here, the second gate driver GT L Usually by positive supply voltage line U only S Directly or indirectly. The monitoring device UV can forcibly turn off the second power transistor M by the second gate control signal GL L Wherein the monitoring device UV passes through the second enable signal EN L To the second gate driver GT L Signaling to set the second gate control signal to turn off (i.e. disable) the second power transistor M L State of (2);
GND negative supply voltage line whose potential is usually a reference potential;
GT H a first gate driver. The first gate driver generates a first power transistor M H A first gate control signal GH of the control electrode of (a);
GT L and a second gate driver. The second gate driver generates a second power transistor M L A second gate control signal GL of the control electrode of (c). Preferably, the second gate driver is powered by a voltage supply circuit SV;
an IC integrated circuit;
INTN is typically present on the interrupt line of the integrated circuit IC of the processor. For example, an interrupt signal for the interrupt line may be generated by the monitoring device UV. Preferably, the INTN signal on the interrupt line is interpreted as the bootstrap capacitance C B As no countermeasures have to be taken in this case. In case of a short circuit, a corresponding fault, which is not a charging fault of the bootstrap capacitor, is preferably signaled, typically via the data bus DB, in addition to the INTN signal via the interrupt line.
M H A first power transistor;
M H 、M L a half bridge. Half-bridge through first power transistor M H And a second power transistor M L Forming;
M L a second power transistor;
PH phase output;
PWMH first PWM driving signal. Preferably, the first PWM driving signal is generated by a PWM generator PWMG having a PWM period;
PWML second PWM driving signal. Preferably, the second PWM driving signal is generated by a PWM generator PWMG having a PWM period;
S1 first step (fig. 5 and 6). In a first step, at an on time t 0 Turning on the first power transistor M H And at the opening time t 0 Turning off the second power transistor M L . Preferably, the on-time point is equal to the start of the PWM period. Therefore, the on-time point is preferably repeated in a PWM period. To avoid through-current, at M L Is turned off and M H A dead time may be inserted between the opening of (c).
S2 a second step (FIGS. 5 and 6). In the second step, after the debounce time T has elapsed D Then determining the drain-source voltage U DS Drain-source voltage value V of (2) DS 。
S3, a third step. In the third step, the determined drain-source voltage U is compared DS Drain-source voltage value V of (2) DS And a first threshold value SW1.
S4, a fourth step. Only when the comparison in the third step shows that the determined drain-source voltage U DS Drain-source voltage value V of (2) DS And when the threshold value is larger than the first threshold value SW1, executing the fourth step. In this case, the first power transistor M H Is not fully turned on, and the first power transistor M H The voltage drop across it is excessive. In this case, since the failure occurs too fast (equal to the time of validity T A (see also fig. 3)), it is assumed that a short circuit exists. Thus, in a fourth step, the two power transistors M are turned off H 、M L In order to safely interrupt the short-circuit current.
S5 fifth step (FIGS. 5 and 6). In the fifth step, a jitter time T is elapsed D And effective time T A Then, determining the drain-source voltage U DS Is the other or second drain-source voltage value V DS2 . If the value is below the second threshold value SW2 for an extended period of time of validityBootstrap capacitor C B Is fully charged.
S6, a sixth step. In the sixth step, the determined drain-source voltage U is compared DS Is the other or second drain-source voltage value V DS2 And a second threshold value SW2.
S7, a seventh step. Only when the comparison in the sixth step shows that the determined drain-source voltage U DS Is the other or second drain-source voltage value V DS2 And when the threshold value is larger than the second threshold value SW2, executing a seventh step. In this case, the first power transistor M H At prolonged effective time T EA Is not fully turned on, and the first power transistor M H The voltage drop across it is excessive. However, it is assumed in this case that there is no short circuit, since the fault occurs too slowly (equal to not being in the active time T A As well as (see also fig. 3 and/or fig. 4)). Thus, the first power transistor M is turned off in the seventh step H And turn on the second power transistor M L To recharge the bootstrap capacitor C B 。
S8, eighth step (figure 5). In the eighth step, after the charging time T has elapsed L After that, the first power transistor M is turned on H And after the charging time T has elapsed L After which the second power transistor M is turned off L . Thereby completing the bootstrap capacitor C B Is provided.
S9, a ninth step (see FIG. 6). In the ninth step, the drain-source voltage U is determined during recharging (see also S7) DS Third drain-source voltage value V of (2) DS3 。
S1 0 And a tenth step. In the tenth step, the drain-source voltage U is compared DS Third drain-source voltage value V of (2) DS3 And a third threshold value SW3.
S11, eleventh step. In the eleventh step, the bootstrap capacitor C is passed through B Recharging time T of (2) L And drain-source voltage U DS Drain-source voltage value V of (2) DS3 The third threshold value SW3 is not exceeded. This is then interpreted as a fault. For example, this may be a potentially weak short circuit and/or the bootstrap capacitance may still not be rechargeable for some reason. Thus, the fault condition is preferably considered to be a short circuit, butAnd preferably a different signaling to the external computer, the fault situation can be effectively distinguished from the fault situation in step S4. Similar to the short-circuit situation in step S4, the first power transistor M is therefore switched off here H And simultaneously turn off the second power transistor M L Because the third U is determined numerically DS Voltage value V DS3 Comparison with a third threshold value SW3, which may be equal to the first threshold value SW1 and the second threshold value SW2, indicates a determined third U DS Voltage value V DS3 Is numerically smaller than the third threshold. As already mentioned, here as in the case of a short circuit in step S4, it is preferable to signal again via the interrupt line INTN and the integrated circuit IC or the register of the monitoring device UV and/or PWM generator PWMG. As in step S4, the PWM generator PWMG and/or the monitoring device UV blocks the second power transistor M by means of an external control computer L Until such re-start is again allowed via a dedicated register by a dedicated release instruction of the external control computer. Preferably, the integrated circuit IC, in particular the monitoring device UV and/or the PWM generator, signals to the external control computer, in the event of a fault, a fault code that differs from the fault code in the event of the short-circuit detection in step S4 via the register and the data bus DB;
s21 step S21: in step S21, at the on time point t 0 Turning on the first power transistor M H And at the opening time t 0 Turning off the second power transistor M L . Preferably, the on-time point is the start of the PWM period. Therefore, the on-time point is preferably repeated in a PWM period. However, this step may also be performed within the PWM cycle for the charging time T L And then appears.
S22 step S22: the monitoring means UV detect the potential at the bootstrap node BST and the half-bridge M in step S22 after step S21 H 、M L Potential difference between potentials at phase outputs PH, and determining corresponding bootstrap potential difference value av BST ；
S23 step S23: in step S23, the monitoring device UV numerically compares the bootstrap potential difference Δv determined in step S22 BST And a first threshold value SW1;
s24, step S24: in step S24, the monitoring device UV passes through the first gate driver GT H Turning off the first power transistor M H And through a second gate driver GT L Turning on the second power transistor M L . When the bootstrap potential difference value DeltaV determined in step S22 is determined in the comparison step S23 BST When the value is lower than the first threshold value SW1, step S24 is performed;
s25 step S25: in the step S22, since the bootstrap potential difference value DeltaV determined in the step S22 is determined in the comparing step S23 BST The monitoring means UV pass the first gate driver GT in a next step S25, a period of time after the first turn-off in step S24, which is performed numerically below the first threshold value SW1 H The first power transistor M is turned on again H And through a second gate driver GT L Turning off the second power transistor M L . Preferably, after the first turn-off in step S24, only the charging time T elapses L The re-start in step S25 is then performed. Safety precautions should be followed here.
S26 in a next step S26 of step S25, the monitoring means UV detects the potential at the bootstrap node BST and the half bridge M H 、M L Potential difference between potentials at the phase output PH of (c) and determining a corresponding further bootstrap potential difference value av BST 。
S27 in step S27, the monitoring device UV numerically compares the determined further bootstrap potential difference value DeltaV BST2 And another threshold value SW2 which may be equal to the first threshold value SW 1.
S28 in step S28, when another bootstrap potential difference value Δv determined in step S26 is determined in the aforementioned comparison step S27 BST2 If the value falls below the further threshold value SW2, the monitoring device UV passes through the first gate driver GT after being switched on again in step S25 H Turning off the first power transistor M again H And likewise through the second gate driver GT L Turning off the second power transistor M L 。
S31 step S31: in step S31, at the time of openingPoint t of separation 0 Turning on the first power transistor M H And at the opening time t 0 Turning off the second power transistor M L . Preferably, the on-time point is the start of the PWM period. Thus, the on-time point is preferably repeated in PWM cycles.
S32 step S32: when the first power transistor M is turned on H (see step S31), the first power transistor M is detected H U at DS Voltage and determine drain-source voltage U DS Corresponding drain-source voltage value V DS ；
S33 step S33: numerically comparing the determined drain-source voltages U DS Drain-source voltage value V of (2) DS And a first threshold value SW1;
s34 step S34: when the comparison step S33 indicates the drain-source voltage U determined in the step S32 DS Drain-source voltage value V of (2) DS When exceeding the first threshold value SW1 in value, the first power transistor M is turned off for the first time H And first turning on the second power transistor M L 。
S35 step S35: due to the drain-source voltage U determined in step S32 DS Drain-source voltage value V of (2) DS The first threshold value SW1 is exceeded in value, so after the first turn-off in step S34, the first power transistor M is turned on H And turns off the second power transistor M again L Wherein this step is especially at a charging time T L Then, the process is carried out;
s36 step S36: detecting a first power transistor M H U at DS Voltage and again determine drain-source voltage U DS Corresponding another drain-source voltage value V DS2 ；
S37 step S37: numerically comparing the drain-source voltage U determined in step S36 DS Another drain-source voltage value V of (2) DS2 Another threshold value SW2 which may be equal to the first threshold value SW1;
s38 step S38: when the drain-source voltage U determined in step S36 is determined in the corresponding comparing step S37 DS Another drain-source voltage value V of (2) DS2 When the value exceeds a second threshold value SW2 which can be equal to the first threshold value SW1, the first valve is turned offPower transistor M H And turn off the second power transistor M another time L 。
S41 step S41: in the comparison step S41, at the on time point t 0 Turning on the first power transistor M H And at the opening time t 0 Turning off the second power transistor M L . Preferably, the on-time point is the start of the PWM period. Thus, the on-time point is preferably repeated in PWM cycles.
S42 step S42: detection bootstrap capacitor C B And determines a corresponding bootstrap potential difference DeltaV BST ；
S43 step S43: numerically comparing the bootstrap potential difference value Δv determined in step S42 BST And a first threshold value SW1;
s44 step S44: when the comparison step S43 shows the bootstrap potential difference value DeltaV determined in the step S42 BST When the value is lower than the first threshold value SW1, the first power transistor M is turned off H And first turning on the second power transistor M L . Thereby starting bootstrap capacitor C B Is provided.
S45 step S45: in the case of the bootstrap potential difference value DeltaV due to the determination in step S42 BST After the first switch-off in step S44, which is performed numerically below the first threshold value SW1 (in particular at the charging time T L After that, the first power transistor M is turned on again H And turn off the second power transistor M again L . It is particularly advantageous if the charging time T has elapsed after the first switch-off in step S44 L After that, the process first starts again in step S45.
S46 step S46: detection bootstrap capacitor C B And determines a corresponding further bootstrap potential difference value DeltaV BST2 ；
S47 step S47: numerically comparing the other bootstrap potential difference value Δv determined in step S46 BST2 And another threshold value SW2 which may be equal to the first threshold value SW 1. Contrary to step S37, if it is determined in step S45 in comparison step S46Another bootstrap potential difference value DeltaV determined BST When again below the second threshold value SW2, which may be equal to the first threshold value SW1, step S44 is followed by the first power transistor M H Is turned off again and the second power transistor M L Is turned on again. Here too, the charging is continued for a long time until the bootstrap voltage V BST Is equal to the second threshold value SW2. This can be used to prevent through-currents in the device in different ways.
SV voltage power supply circuit. Preferably, the voltage supply circuit SV generates at its voltage regulator output VG a constant voltage V compared to the reference potential GND VG ；
SW1 a first threshold;
SW2 a second threshold;
SW3 a third threshold;
ST is from the monitoring device to other control signals of PWM generator PWMG.
T is in PWM period T PWM Relative to the opening time t 0 Is a time of (a) to be used.
t' with respect to bootstrap capacitance C B Is set to the recharging start time point.
t 0 The time point is turned on. Time point t of opening 0 Typically the start of each PWM period of PWM generator PWMG;
T A an effective time;
T D jitter removal time;
T EA the effective time is prolonged;
a TH detection threshold;
T L charging time;
T PWM a PWM period;
T T1 a first dead time;
T T2 a second dead time;
U DS first power transistor M H Drain-source voltage at.
U S Positive power supply line U having a positive power supply voltage opposite to that of negative power supply voltage line GND S ；
A UV monitoring device;
V DS first power transistor M H Drain-source voltage U at DS Drain-source voltage value of (2);
V DS2 first power transistor M H Drain-source voltage U at DS Or a second drain-source voltage value. Typically, the second drain-source voltage value is detected at the drain-source voltage value V DS After detection of (2);
V DS3 first power transistor M H Drain-source voltage U at DS A third drain-source voltage value of (a). Typically, the third drain-source voltage value is detected at the drain-source voltage value V DS After detection of (2) and at the second drain-source voltage value V DS3 After detection of (2);
the voltage regulator output of VG voltage supply circuit SV;
V BST a bootstrap voltage;
V GH a voltage between the first gate driving signal VG and the negative supply voltage line GND;
V PH phase voltage V at phase output PH relative to reference potential GND PH ；
V VG The constant voltage at the voltage regulator output VG of the voltage supply circuit SV compared to the reference potential GND.

Claims (3)

1. A driver stage, comprising:
first power transistor (M H )；
Second power transistor (M L ) The method comprises the steps of carrying out a first treatment on the surface of the And
bootstrap capacitor (C) B )，
Wherein the driver stage comprises a circuit for detecting a short circuit and/or the bootstrap capacitance (C B ) Is a discharge device (UV, GT) H 、GT L )，
Wherein the device is adapted and arranged to distinguish between a short circuit and the bootstrap capacitance (C B ) Is used for the discharge of the electric power,
wherein the driver stage comprises one or more means for signaling to the computer system a short circuit and the bootstrap capacitance (C B ) A kind of electronic deviceMeans for discharging, an
Wherein the driver stage signals in case of a short circuit differently than in the bootstrap capacitor (C B ) Is signaled in the case of a discharge of (a).
2. A driver stage, comprising:
first power transistor (M H )；
Second power transistor (M L ) The method comprises the steps of carrying out a first treatment on the surface of the And
bootstrap capacitor (C) B )，
Wherein the driver stage comprises a circuit for detecting a short circuit and the bootstrap capacitance (C B ) Defective devices (UV, GT) H 、GT L )，
Wherein the device is adapted and arranged to distinguish between a short circuit and the bootstrap capacitance (C B ) Is not limited to the above-mentioned drawbacks,
wherein the driver stage comprises one or more means for signaling to a computer system that the computer system is capable of distinguishing between:
short circuit; and
the bootstrap capacitor (C B ) Is a drawback of (a).
3. A driver stage, comprising:
first power transistor (M H )；
Second power transistor (M L ) The method comprises the steps of carrying out a first treatment on the surface of the And
bootstrap capacitor (C) B )，
Wherein the driver stage comprises a circuit for detecting a short circuit and a circuit between the bootstrap capacitor (C B ) The bootstrap capacitance (C B ) And/or the bootstrap capacitance (C B ) Defective devices (UV, GT) H 、GT L )，
Wherein, the device is adapted and arranged to distinguish between a short circuit after the bootstrap capacitor (C B ) The bootstrap capacitance (C B ) And/or the bootstrap capacitance (C B ) And (2) defects of
Wherein the driver stage comprises one or more means for signaling to a computer system that the computer system is capable of distinguishing between:
short circuit;
after the bootstrap capacitor (C B ) The bootstrap capacitance (C B ) Is a discharge of (2); and
the bootstrap capacitor (C B ) Is a drawback of (a).
CN202310629535.4A 2018-09-26 2019-09-26 Driver stage Pending CN116707500A (en)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
DE102018123816.9A DE102018123816B4 (en) 2018-09-26 2018-09-26 Drivers with means to distinguish between insufficient bootstrap capacity reloading and a short-circuit fault
DE102018123769.3 2018-09-26
DE102018123825.8 2018-09-26
DE102018123769.3A DE102018123769A1 (en) 2018-09-26 2018-09-26 Driver with the ability to differentiate between bootstrap capacity recharge and short-circuit failure and method for operating the same
DE102018123816.9 2018-09-26
DE102018123825.8A DE102018123825B4 (en) 2018-09-26 2018-09-26 Driver with the option to differentiate between bootstrap capacity recharge and short-circuit error
DE102018123808.8A DE102018123808A1 (en) 2018-09-26 2018-09-26 Driver with voltage-controlled distinction between bootstrap capacity recharging and short-circuit failure
DE102018123808.8 2018-09-26
CN201910934317.5A CN110958004B (en) 2018-09-26 2019-09-26 Driver capable of distinguishing bootstrap capacitor recharging and short circuit fault

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