JP2008147372A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which can reduce or suppress leakage current, when the semiconductor device is used in a high-temperature environment. <P>SOLUTION: In the method of manufacturing a power management semiconductor device, including a CMOS when a source high-concentration diffusion layer and a drain high-concentration diffusion layer are set to have a higher concentration, a leakage current, between the source high-concentration diffusion layer and a substrate or at the source and drain high-concentration diffusion layers, can be reduced or suppressed, even if the semiconductor device is used at a high temperature state. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention reduces the leakage current from the source high-concentration diffusion layer in a CMOS of a power management semiconductor device such as a voltage detector, a constant voltage regulator, or a switching regulator. The present invention relates to a manufacturing method to be suppressed.

  A conventional manufacturing technique of a LOCOS offset drain type MOS transistor having a LOCOS in the drain low concentration diffusion layer in the semiconductor device described above will be described with reference to FIG.

  FIG. 3 is a schematic cross-sectional view in order of steps showing a conventional method for manufacturing a semiconductor device.

3A, in order to form a drain low concentration diffusion layer on a P-type semiconductor substrate 14, for example, a semiconductor substrate having a resistivity of 20 Ωcm to 30 Ωcm to which boron is added, for example, phosphorus is added at 1 × 10 ¹² atoms / Ions are implanted at a dose of cm ² to 1 × 10 ¹³ atoms / cm ² and thermally oxidized at 1000 to 1200 ° C. for several hours to form the drain low concentration diffusion layer 16, and at the same time, the oxide film 15 is formed by the LOCOS method. To do. Here, for example, the oxide film having an oxide film thickness of 500 nm to 1 μm is thermally oxidized and grown. Thereafter, the oxide film 15 in the region where the MOS transistor is to be formed is removed, and a gate insulating film 17, for example, a thermal oxide film having a film thickness of several hundreds to several thousands of cm is formed. Next, a polycrystalline silicon gate film 18 is preferably deposited on the gate insulating film 17 so as to have a thickness of 100 nm to 500 nm, and impurities are introduced by predeposition or ion implantation. Thereafter, as shown in FIG. 3B, patterning of the gate insulating film 17 and the polycrystalline silicon gate film 18 for forming a gate electrode with the resist film 19 is performed. Next, as shown in FIG. 3C, an impurity is added to form the source high-concentration diffusion layer and the drain diffusion layer by self-alignment using the shape of the gate electrode. For example, arsenic is ion-implanted at a dose of 1 × 10 ¹⁵ atoms / cm ² to 1 × 10 ¹⁶ atoms / cm ² . Subsequently, as shown in FIG. 3D, the drain high concentration diffusion layer 20 and the source high concentration diffusion layer 21 are formed by heat treatment at 800 ° C. to 1000 ° C. for several hours.

In the above, an example of a method for manufacturing a CMOS of a LOCOS offset drain type MOS transistor among power management semiconductor devices has been described with reference to Patent Document 1. On the other hand, a source high in a use state at a high driving current and a high temperature is shown. Low current consumption by suppressing leakage current between the concentration diffusion layer and the substrate or between the source high concentration diffusion layer and the drain high concentration diffusion layer has been regarded as a problem.
JP-A-7-226505

  In the semiconductor device according to the above-described conventional manufacturing method, due to the use in a high temperature state, that is, due to the strong influence from the outside, on the performance of the MOS transistor, between the source high concentration diffusion layer and the substrate or between the source high concentration diffusion layer and the drain high concentration. Leakage current between the diffusion layers may occur, and it is difficult to reduce current consumption in a high temperature environment.

  The present invention has been made paying attention to the above points, and an object of the present invention is to provide a method for manufacturing a semiconductor device with little leakage current even in a high temperature environment.

In order to solve the above problems, the present invention uses the following means.
(1) A step of forming a drain low concentration diffusion layer of a first conductivity type in a region in a semiconductor substrate, and a thick oxide film on the drain low concentration diffusion layer simultaneously with the formation of the drain low concentration diffusion layer A step of forming a gate insulating film, a step of forming a polycrystalline silicon gate on the gate insulating film, and a source high-concentration diffusion layer and a drain high-concentration diffusion through the polycrystalline silicon gate. In the method of manufacturing a MOS transistor comprising a step of forming a layer, the step of forming the high-concentration source diffusion layer and the high-concentration drain diffusion layer includes an impurity concentration of 1 × 10 ¹⁶ atoms / cm ² to 1 × 10 ¹⁷ atoms / A method of manufacturing a semiconductor device including a step of performing ion implantation at cm ² was adopted.
(2) The semiconductor device manufacturing method is such that the MOS transistor is an NMOS transistor.
(3) The manufacturing method of a semiconductor device in which the MOS transistor is a PMOS transistor.
(4) The method according to claim 1, wherein the region is a region having a conductivity type opposite to that of the semiconductor substrate.
(5) The semiconductor device manufacturing method according to claim 2, wherein an impurity of ion implantation in the source high concentration diffusion layer and the drain high concentration diffusion layer in the NMOS transistor region is arsenic.
(6) The semiconductor device manufacturing method according to claim 3, wherein the impurity of ion implantation of the source high concentration diffusion layer and the drain high concentration diffusion layer in the PMOS transistor region is boron difluoride.

  As described above, according to the present invention, in a method for manufacturing a power management semiconductor device including a CMOS, a source high concentration diffusion layer and a drain high concentration diffusion layer are highly concentrated, so that the source high concentration diffusion can be used even in a high temperature environment. Leakage current between the layer and the substrate or between the source high concentration diffusion layer and the drain high concentration diffusion layer can be reduced or suppressed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a schematic cross-sectional view showing a first embodiment of a method of manufacturing a semiconductor device according to the present invention.

In FIG. 1, a CMOS NMOS transistor will be described below as an example. In FIG. 1A, after forming an oxide film 2, for example, a thermal oxide film having a thickness of several hundreds of micrometers on a P-type semiconductor substrate 1, for example, a semiconductor substrate having a resistivity of 20 Ωcm to 30 Ωcm to which boron is added, The nitride film 3 is deposited, for example, to a thickness of several thousand Å. Here, for example, in the case of PMOS, Nwell is formed before the oxide film 2 is formed. For example, phosphorus is ion-implanted at a dose of 1 × 10 ¹² atoms / cm ² to 1 × 10 ¹³ atoms / cm ² and then thermally diffused at 900 ° C. to 1000 ° C. for several hours to form a well diffusion layer.

  Next, as shown in FIG. 1B, patterning is performed on the resist film 4 to remove the nitride film for forming the drain low concentration diffusion layer. This nitride film is used for forming an oxide film by the LOCOS method in the subsequent process. The conductivity type of the substrate is not related to the essence of the present invention.

Subsequently, as shown in FIG. 1C, the resist film 5 is patterned while holding the resist film 4, and an impurity is added to form a drain low concentration diffusion layer. For example, phosphorus is ion-implanted at a dose of 1 × 10 ¹² atoms / cm ² to 1 × 10 ¹³ atoms / cm ² . Here, in the case of PMOS, ion implantation is performed using, for example, boron.

  Thereafter, as shown in FIG. 1D, after the resist film 4 and the resist film 5 are removed, an oxide film is subsequently formed by the LOCOS method. Here, by performing thermal oxidation at 1000 to 1200 ° C. for several hours, for example, thermal oxidation growth is performed on an oxide film having an oxide film thickness of 500 nm to 1 μm, and at the same time, the drain low concentration diffusion layer 6 is formed.

  Subsequently, as shown in FIG. 1E, after the nitride film 3 and the oxide film 2 are removed, a gate insulating film 7, for example, a thermal oxide film having a film thickness of several hundreds to several thousands is formed. Subsequently, a polycrystalline silicon gate film 8 is preferably deposited to a thickness of 100 nm to 500 nm on the gate insulating film 7, and impurities are introduced by predeposition or ion implantation. Thereafter, as shown in FIG. 1F, patterning of the gate insulating film 7 and the polycrystalline silicon gate film 8 for forming a gate electrode with the resist film 9 is performed.

Next, as shown in FIG. 1G, patterning is performed to form a source high-concentration diffusion layer with the resist film 10. Impurities are added to this to form a source high-concentration diffusion layer. For example, arsenic is ion-implanted at a relatively high dose of 1 × 10 ¹⁶ atoms / cm ² to 1 × 10 ¹⁷ atoms / cm ² . Here, in the case of PMOS, it is preferable to perform ion implantation with boron difluoride.

Subsequently, after removing the resist film 10, patterning for forming a drain high-concentration diffusion layer with the resist film 11 is performed as shown in FIG. An impurity is added to this to form a drain high concentration diffusion layer. For example, arsenic is ion-implanted at a dose of 1 × 10 ¹⁶ atoms / cm ² to 1 × 10 ¹⁷ atoms / cm ² . Here, in the case of PMOS, it is preferable to perform ion implantation with boron difluoride.

  Here, when the resist film 11 is peeled off, as shown in FIG. 1I, an insulated gate field effect transistor having a polycrystalline silicon gate film 8 is formed. Thereafter, as shown in FIG. 1J, the drain high concentration diffusion layer 12 and the source high concentration diffusion layer 13 are formed by heat treatment at 800 ° C. to 1000 ° C. for several hours. By changing the thermal oxidation method and the deposition method for forming the oxide film 2, the gate insulating film 7 or the polycrystalline silicon gate film 8 so far, the structure other than the structure shown in the embodiment of FIGS. In addition, the present invention can be applied to a high voltage insulated gate field effect transistor.

  Next, an Example is described based on FIG.

  FIG. 2 is a schematic cross-sectional view of the first embodiment of the method of manufacturing the semiconductor device according to the present invention shown in FIGS. 1A to 1J, and shows the source height of the completed form shown in FIG. The semiconductor energy band figure from a concentration diffusion layer to a drain high concentration diffusion layer is shown.

  In FIG. 2A, for example, a semiconductor energy band diagram of the source high-concentration diffusion layer 22, the P-type semiconductor substrate 23, the drain low-concentration diffusion layer 24, and the drain high-concentration diffusion layer 25 shows the thermal equilibrium state at the junction. Yes. Here, energy 26 at the bottom of the conduction band, Fermi level 27, intrinsic Fermi level 28, and energy 29 at the top of the valence band were used for interpretation of the figure. These are not related to the essence of the present invention.

  Subsequently, when normal operation is performed, in FIG. 1J of the embodiment, when a positive voltage is applied to the polycrystalline silicon gate film and the drain high concentration diffusion layer and the source high concentration diffusion layer is set to the ground voltage, A semiconductor energy band diagram as shown in FIG. 2B is obtained, and current flows as carriers move from the source high concentration diffusion layer 22 to the drain high concentration diffusion layer 25. This is a so-called operating state of the semiconductor device.

  Next, FIG. 2C shows the state of the problem to be solved by the present invention. In the conventional semiconductor device manufacturing method, when the semiconductor device is used in a high temperature state, the source device high-concentration diffusion layer and the substrate or between the source high-concentration diffusion layer and the drain high concentration even though the semiconductor device is not operating. In some cases, leakage current occurs between the diffusion layers. For example, as shown in FIG. 2C, the P-type semiconductor substrate 23 exhibits an increase in minority carriers, which is a general physical characteristic of a semiconductor, due to a strong external influence such as a rise in usage environment. This is because the conductivity type is close to that of an intrinsic semiconductor. Therefore, the height of the barrier as energy is relaxed, and between the source high concentration diffusion layer 22 and the P-type semiconductor 23 or between the source high concentration diffusion layer 22 and the drain high concentration diffusion layer 25. Leakage current is generated despite the non-operating state.

  Therefore, in the means for increasing the impurity concentration of the source high concentration diffusion layer 22 or the drain high concentration diffusion layer 25 used for solving the present invention, as shown in FIG. 2D, the source high concentration diffusion layer 22 is used. Alternatively, by increasing the concentration of the drain high-concentration diffusion layer 25, the barrier as energy of the P-type semiconductor substrate 23 is increased, and the source high-concentration diffusion layer 22 and the P-type semiconductor due to the temperature rise in the use environment even in the non-operating state. It is intended to suppress the occurrence of leakage current between the substrate 23 or between the source high concentration diffusion layer 22 and the drain high concentration diffusion layer 25.

  The above is the case of NMOS, but in the case of PMOS, the occurrence of leakage current can be suppressed for the same reason.

Schematic sectional view showing a first embodiment of a method of manufacturing a semiconductor device of the present invention Detailed explanatory view of the first embodiment in the method of manufacturing a semiconductor device of the present invention Schematic cross-sectional view in order of steps showing the manufacturing method of the semiconductor device of the prior art

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 P type semiconductor substrate 2 Oxide film 3 Nitride film 4 Resist film 5 Resist film 6 Drain low concentration diffusion layer 7 Gate insulating film 8 Polycrystalline silicon gate 9 Resist film 10 Resist film 11 Resist film 12 Drain high concentration diffusion layer 13 Source height Concentration diffusion layer 14 P type semiconductor substrate 15 Oxide film 16 Drain low concentration diffusion layer 17 Gate insulating film 18 Polycrystalline silicon gate 19 Resist film 20 Drain high concentration diffusion layer 21 Source high concentration diffusion layer 22 Source high concentration diffusion layer 23 P type Semiconductor substrate 24 Drain low concentration diffusion layer 25 Drain high concentration diffusion layer 26 Energy at the bottom of the conduction band 27 Fermi level 28 Intrinsic Fermi level 29 Energy at the top of the valence band

Claims (6)

Forming a first conductivity type drain low concentration diffusion layer in a region within a semiconductor substrate; and forming a thick oxide film on the drain low concentration diffusion layer simultaneously with the formation of the drain low concentration diffusion layer; Next, a step of forming a gate insulating film, a step of forming a polycrystalline silicon gate on the gate insulating film, and forming a source high concentration diffusion layer and a drain high concentration diffusion layer through the polycrystalline silicon gate In the method of manufacturing a MOS transistor, the step of forming the source high concentration diffusion layer and the drain high concentration diffusion layer is performed at an impurity concentration of 1 × 10 ¹⁶ atoms / cm ² to 1 × 10 ¹⁷ atoms / cm ² . A method for manufacturing a semiconductor device, including a step of performing ion implantation.   The method of manufacturing a semiconductor device according to claim 1, wherein the MOS transistor is an NMOS transistor.   The method of manufacturing a semiconductor device according to claim 1, wherein the MOS transistor is a PMOS transistor.   The method of manufacturing a semiconductor device according to claim 1, wherein the region is a region having a conductivity type opposite to that of the semiconductor substrate.   3. The method of manufacturing a semiconductor device according to claim 2, wherein an impurity for ion implantation in the high-concentration source diffusion layer and the high-concentration drain diffusion layer in the NMOS transistor region is arsenic.   4. The method of manufacturing a semiconductor device according to claim 3, wherein the impurity for ion implantation of the source high concentration diffusion layer and the drain high concentration diffusion layer in the PMOS transistor region is boron difluoride.

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