JP2008143062A - Pixel clock forming apparatus and image forming apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To highly precisely correct an error in scanning speed and a non-linear error caused by various factors, and make a highly precise control for the reduction in size and cost of an apparatus. <P>SOLUTION: The pixel clock generation apparatus is provided with: a first and second edge detectors 2 and 3 detecting for synchronous information showing rising/trailing edge time of the synchronous signal provided by mixing some of a plurality of first or second synchronous signals to be inputted to a pixel clock generator 111 and sampling them by the high frequency of the nixed synchronous signals; and a synchronous information separation means for separating and extracting corresponding synchronous information from the synchronous information so as to calculate a time interval between the first and second synchronous signals from the output. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a laser printer, a digital copying machine, and other image forming apparatuses, and more particularly to a pixel clock generating apparatus and an image forming apparatus that generate a pixel clock used in these image forming apparatuses.

  FIG. 37 shows a general schematic configuration of an image forming apparatus such as a laser printer or a digital copying machine. In FIG. 37, the laser light emitted from the semiconductor laser unit 1009 is scanned by a rotating polygon mirror 1003 to form a light spot on a photoconductor 1001 that is a medium to be scanned through a scanning lens 1002, and the photoconductor 1001 is exposed to form an electrostatic latent image. At this time, the photodetector 1004 detects the scanning beam for each line. The phase synchronization circuit 1006 receives the clock from the clock generation circuit 1005, generates an image clock (pixel clock) synchronized in phase for each line based on the output signal of the photodetector 1004, and generates an image processing unit 1007. And supplied to the laser driving circuit 1008. The semiconductor laser unit 1009 controls the emission time of the semiconductor laser according to the image data generated by the image processing unit 1007 and the image clock whose phase is set for each line by the phase synchronization circuit 1006. Controls formation of an electrostatic latent image on the body 1001.

  In such a scanning optical system, unevenness in scanning speed causes image fluctuation and causes deterioration in image quality. In particular, in a color image, the main scanning dot position shift of each color occurs, resulting in a color shift, leading to deterioration in color reproducibility and resolution. Therefore, in order to obtain high quality image quality, it is essential to correct the scanning speed unevenness. The scanning speed unevenness (error) is roughly classified into the following (1) to (5), and main factors will be described respectively.

(1) Error for each surface (each scanning line) of the polygon mirror (hereinafter referred to as an error for each surface as appropriate)
Factors that cause such scanning speed unevenness include variations in the distance from the rotation axis of the deflecting and reflecting surface of a deflector such as a polygon mirror (that is, eccentricity of the polygon mirror) and surface accuracy of each surface of the polygon mirror. is there. This type of error is an error having a periodicity of several lines (for example, the number of lines corresponding to the number of polygon mirror surfaces).

(2) Error due to scanning average speed fluctuation The scanning average speed indicates the average scanning speed of each surface of the polygon mirror, and causes of such scanning speed unevenness include fluctuations in the rotational speed of the polygon mirror, temperature, Some are caused by fluctuations in the scanning optical system due to various environmental fluctuations such as humidity and vibration. In addition, the oscillation speed of the semiconductor laser, which is a light source, changes due to temperature fluctuations, etc., so that the scanning speed varies due to chromatic aberration of the scanning optical system. This type of error is a relatively gradual variation. Further, in the case of a multi-beam optical system that includes a plurality of light sources such as a semiconductor laser array and simultaneously scans a plurality of light beams with a common scanning optical system, the following scanning speed unevenness also occurs.

(3) Error for each light source The main factor is that there is a difference in the oscillation wavelength of each light source, and the scanning speed fluctuates due to the chromatic aberration of the scanning optical system. In addition, since the fluctuation | variation of an oscillation wavelength changes for every light source, the error of said (2) may differ for every light source. In addition, the scanning speed of a plurality of beams varies depending on the assembly accuracy of a plurality of light sources. Furthermore, in the case of an image forming apparatus that includes a plurality of photoconductors / scanning optical systems and is compatible with multiple colors, the following difference in scanning speed between the scanning optical systems greatly affects the image quality.

(4) Errors for each scanning optical system The main factors for this are manufacturing accuracy and assembly accuracy of each component of the scanning optical system, deformation due to changes over time, etc. An error also occurs. This error is different from the scanning average speed itself, and the above errors (1) and (2) occur individually. Some of these image forming apparatuses use a part of the scanning optical system in common, but the optical paths from the respective light sources to the scanned medium (photosensitive member) are different. )

  As a method of correcting these scanning speed errors, for example, as disclosed in Patent Document 1, there is a method of changing the frequency of the pixel clock in accordance with the scanning speed. This is to control the frequency of the oscillator that generates the pixel clock (so-called PLL (Phase Locked Loop) control) so that the number of counts of the pixel clock from the start to the end of the scan becomes a predetermined value.

  However, the conventional pixel clock frequency control method has the following problems. That is, since the frequency of the reference clock for phase comparison is one line frequency, it is very low (several thousand to several tens of thousands) with respect to the oscillating pixel clock, and sufficient PLL open loop gain cannot be secured. Therefore, sufficient control accuracy cannot be obtained. In addition, the clock frequency fluctuates weakly to disturbances, and a highly accurate clock cannot be generated. Furthermore, when the error for each surface is corrected as in Patent Document 1, the control voltage of the VCO that is the oscillator is changed for each scan, so that it takes time until the clock frequency oscillates stably. End up.

  As another method for correcting the scanning speed error, for example, as disclosed in Patent Document 2, there is a method of controlling the phase of the pixel clock based on the generated high-frequency clock. This controls the phase of the pixel clock so that the count number of the high-frequency clock from the start to the end of the scan becomes a predetermined value.

  Since this high-frequency clock can be generated with a high-accuracy clock such as a crystal oscillator as a reference clock, a high-accuracy clock can be obtained, and the phase control of the pixel clock is performed based on this clock, so the pixel clock control accuracy is also good. Things can be generated. However, since the error of the scanning speed is corrected by appropriately performing the phase control of the pixel clock, it is necessary to generate the phase control data for this one scanning line, and further, local by the phase change of the pixel clock. In order to reduce the deviation, that is, to generate a highly accurate pixel clock, it is necessary to perform phase control with high resolution, and phase control data increases. Therefore, it is not easy to generate this phase control data at high speed and with high accuracy. In addition, when applied to a device that corrects errors for each surface, it is necessary to generate phase control data for each surface, and in order to perform highly accurate correction, it is necessary to generate and store a large amount of phase control data. It was not easy to realize. Further, the scanning speed fluctuates during scanning of one line due to the accuracy error and assembly error of each unit of the scanning optical system.

(5) Nonlinearity Error FIG. 38A shows an example of the nonlinear error of the scanning speed in one line. The horizontal axis x is the position of the scanning line, and the vertical axis is the scanning speed V (x) with respect to the position x. An alternate long and short dash line Vavg is an average value of the scanning speed in one line. When such a change in scanning speed occurs, the deviation Δ from the ideal value scanned at a constant speed is as shown in FIG. This means a dot position shift and causes image degradation. In FIG. 38, when scanning from the position X2 to the direction X1, the deviation Δ from the ideal value is as indicated by a dotted line. Therefore, especially when scanning is performed bidirectionally in such a scanning optical system that causes asymmetric positional deviation with respect to the scanning center, color misregistration increases and image degradation becomes serious.

  Further, depending on the surface accuracy of each surface of the polygon mirror, the amount and distribution of this non-linearity error may vary from surface to surface. Further, this error is different for each scanning optical system.

  As a method of correcting such a nonlinear error in scanning speed, for example, as disclosed in Patent Document 3, there is a method of correcting by correcting the frequency of the pixel clock corresponding to the position in the scanning line. However, since the generation of the center frequency of the pixel clock is the same as in the prior art, the accurate clock cannot be generated as described above, and sufficient correction cannot be performed.

JP 2001-183600 A JP 2004-262101 A JP 2000-152001 A

  However, in the image forming apparatus that includes the multi-beam optical system described above and a plurality of photoconductors / scanning optical systems and is compatible with multiple colors, a part of the scanning optical system is shared, thereby reducing the size and cost. The device has been put into practical use. In addition, in response to the demand for further downsizing and cost reduction, there is a demand to share the above-mentioned synchronization signal detection means corresponding to each beam. In such a case, the above-described errors can be corrected with high accuracy. In order to control the clock frequency, it is necessary to detect the synchronization signal corresponding to each beam with high accuracy.

  The present invention has been made in view of the above, and can accurately correct a scanning speed error and a non-linearity error caused by various factors, and is also highly accurate in response to a demand for downsizing and cost reduction of the apparatus. It is an object of the present invention to provide a pixel clock generation apparatus and an image forming apparatus that can perform such control.

  In order to solve the above-described problems and achieve the object, the invention according to claim 1 detects the time interval between the high-frequency clock generating means for generating the high-frequency clock and the input first and second synchronization signals. The detected time interval is compared with the target value, a comparison means for outputting the error, and a set value of the pixel clock frequency is calculated according to the error output from the comparison means, and according to the calculated set value Frequency calculating means for outputting a frequency specifying signal for specifying a pixel clock frequency, and frequency dividing means for dividing the high frequency clock by a frequency dividing ratio based on the frequency specifying signal output by the frequency calculating means to generate a pixel clock; , A plurality of pixel clock generation means including a plurality of first or second pixel clock generation means to be input to the pixel clock generation means. Edge detection in which some of the synchronization signals are mixed, and the mixed synchronization signal is sampled by the high frequency clock to detect synchronization information indicating rising or falling edge time of the synchronization signal And synchronization information separation means for separating and extracting corresponding synchronization information from the synchronization information output from the edge detection means, and the time interval between the first and second synchronization signals from the output of the synchronization information separation means Is calculated.

  According to a second aspect of the present invention, there is provided a multi-phase clock generating means for generating a multi-phase clock having a phase number P, the phase of which is shifted by a phase difference T / P with a period T, and first and second input The time interval of the synchronization signal is detected, the detected time interval is compared with the target value, and the setting value of the pixel clock frequency is calculated according to the comparison means for outputting the error and the error output by the comparison means. A frequency calculating means for outputting a frequency specifying signal for specifying a pixel clock frequency in accordance with the calculated set value, and a phase difference T / P of the multiphase clock as a unit time, and counting according to the frequency specifying signal. Count means for calculating the rise time and fall time of the pixel clock, and the rise time and fall time of the pixel clock based on the multiphase clock And a plurality of pixel clock generation means having a pixel clock output means for generating a pixel clock according to the time, a plurality of first or second synchronization signals to be input to the pixel clock generation means Are some of the mixed sync signals, the mixed sync signals are sampled by the multiphase clock, and the rise of the sync signal with the phase difference T / P of the multiphase clock as a unit time Or an edge detection means for detecting synchronization information indicating a falling edge time; and a synchronization information separation means for separating and extracting corresponding synchronization information from the synchronization information output by the edge detection means. The time interval between the first and second synchronization signals is calculated from the output.

  According to a third aspect of the present invention, there is provided the synchronization detection signal generation means, wherein the plurality of pixel clock generation means generate first and second synchronization detection signals instructing detection of the first and second synchronization signals. Each of the synchronization information separating means is configured to separate and extract corresponding synchronization information from the synchronization information output from the edge detection means in accordance with the corresponding first or second synchronization detection signal. .

  According to a fourth aspect of the present invention, the synchronization information separation means outputs one of the synchronization information output from the edge detection means as line reference information, and the synchronization detection signal generation means Each of them generates the first or second synchronization detection signal according to a predetermined time difference between the line reference information obtained in advance and the corresponding synchronization information.

  According to a fifth aspect of the present invention, a pixel clock generated by at least one pixel clock generation unit is defined as a leading reference, and the synchronization detection signal generation unit provided in the pixel clock generation unit includes the first and second synchronization clocks. In the other pixel clock generation means, the synchronization information separation means converts the synchronization information output from the edge detection means to the first and second synchronization detection signals of the preceding reference. The synchronization information obtained correspondingly is generated, and the pixel clock is generated with a constant initial phase offset.

  According to a sixth aspect of the present invention, in the other pixel clock generation means, the comparison means adds the initial phase offset to the detected time interval, or adds the initial phase offset to the target value. The comparison is performed using the subtracted value.

  The invention according to claim 7 is provided with a plurality of the edge detection means, and the synchronization information separation means detects one of the plurality of synchronization information output from the edge detection means and including the corresponding synchronization information. Selecting means for separating and extracting the corresponding synchronization information from the output of the detecting and selecting means;

  According to an eighth aspect of the present invention, there is provided a synchronization detection signal selection unit, wherein the synchronization information separation unit selects one of the first or second synchronization detection signals output from a plurality of pixel clock generation units, There is provided logical product means for separating and extracting corresponding synchronous information from the logical product of the synchronous detection signal selecting means and the synchronous information output by the edge detecting means.

  The invention according to claim 9 detects the time interval between the input first and second synchronization signals, and compares the detected time interval with a target value. Then, a comparison means for outputting the error, a set value of the pixel clock frequency is calculated according to the error output from the comparison means, and a frequency specifying signal for specifying the pixel clock frequency is output according to the calculated set value. A pixel comprising a plurality of pixel clock generating means having frequency calculating means and frequency dividing means for dividing the high frequency clock by a frequency dividing ratio based on a frequency designation signal output from the frequency calculating means to generate a pixel clock A plurality of light sources by means of a clock generation device and respective pulse modulation signals pulse-modulated according to image data based on the plurality of pixel clocks; An image forming apparatus that drives and scans a light beam output from the plurality of light sources onto a scanned medium to form an image. The image forming apparatus includes two light detection means on a scanning line of the light beam, and the two light detection devices Means for scanning several of the luminous fluxes of the plurality of light sources, and sampling the synchronizing signals, which are the outputs of the two light detecting means, with the high-frequency clock, respectively, and the rising or falling edge of the synchronizing signal Edge detection means for detecting synchronization information indicating an edge time; and synchronization information separation means for separating and extracting corresponding synchronization information from the synchronization information output by the edge detection means, from the output of the synchronization information separation means The time interval between the first and second synchronization signals is calculated.

  According to a tenth aspect of the present invention, there is provided a multi-phase clock generating means for generating a multi-phase clock having a phase number P, the phase of which is shifted by a phase difference T / P with a period T, and first and second input The time interval of the synchronization signal is detected, the detected time interval is compared with the target value, and the setting value of the pixel clock frequency is calculated according to the comparison means for outputting the error and the error output by the comparison means. A frequency calculating means for outputting a frequency specifying signal for specifying a pixel clock frequency in accordance with the calculated set value, and a phase difference T / P of the multiphase clock as a unit time, and counting according to the frequency specifying signal. Counting means for calculating the rise time and fall time of the pixel clock, and the rise time and fall time of the pixel clock on the basis of the multiphase clock. A pixel clock generating device comprising a plurality of pixel clock generating means having a pixel clock output means for generating a pixel clock according to the time, and each pulse modulation signal that is pulse-modulated according to image data based on the plurality of pixel clocks In the image forming apparatus that drives a plurality of light sources and scans a light beam output from the plurality of light sources onto a scanned medium to form an image, the image forming apparatus includes two light detection units on a scanning line of the light beam, Some of the light beams of the plurality of light sources scan the two light detection means, and a synchronization signal that is an output of the two light detection means is sampled by the multiphase clock, and the multiple light detection means Detecting synchronization information indicating the rising or falling edge time of the synchronization signal with the phase difference T / P of the phase clock as the unit time. Detection means and synchronization information separation means for separating and extracting corresponding synchronization information from the synchronization information output from the edge detection means, and the time of the first and second synchronization signals from the output of the synchronization information separation means An interval is calculated.

  According to an eleventh aspect of the present invention, the first and second synchronization detection signals instructing the plurality of pixel clock generation means to light up when the luminous flux of the corresponding light source passes through the two light detection means. Respectively, and the synchronization information separating means separates and extracts the corresponding synchronization information from the synchronization information output from the edge detection means according to the corresponding first or second synchronization detection signal. It is a thing to do.

  According to a twelfth aspect of the present invention, at least one of the light beams passing through the two light detection means is defined as a master beam, and the synchronization information separation means is a master of the synchronization information output from the edge detection means. The synchronization information by the beam is output as line reference information, and each of the synchronization detection signal generating means is configured to output the first or second signal according to the interval between the master beam obtained in advance and the light beam of the corresponding light source. The synchronization detection signal is generated.

  According to a thirteenth aspect of the present invention, the plurality of light sources are each element of the semiconductor laser array, and a light beam output from one of them is instructed to turn on when passing through the two light detection means. In the pixel clock generating means corresponding to the other semiconductor laser array elements, the synchronization information separating means outputs the synchronization output from the edge detecting means. Synchronizing information obtained corresponding to the first and second preceding synchronization detection signals is generated from information, and a pixel clock is generated with a constant initial phase offset. And

  According to a fourteenth aspect of the present invention, in the pixel clock generation unit corresponding to the other semiconductor laser array element, the comparison unit adds the initial phase offset to the detected time interval, or the The comparison is performed using a value obtained by subtracting the initial phase offset from the target value.

  The pixel clock generation apparatus and the image forming apparatus according to the present invention generate a pixel clock based on a high-frequency clock or a multiphase clock generated with accuracy, and control the pixel clock frequency in accordance with a change in scanning time. A pixel clock that can correct this error with high accuracy can be generated even if the scanning average speed fluctuates. Further, the pixel clock frequency is controlled in correspondence with each surface of the polygon mirror. Even if there is a scanning speed error, a pixel clock that can be corrected with high accuracy can be generated. Furthermore, since the pixel clock frequency is modulated so as to correct the nonlinear error of the scanning speed, a more accurate pixel clock can be generated. In addition, since the pixel clock generation unit is applied to the image forming apparatus, an image can be formed on the basis of the pixel clock in which the scanning speed error is corrected with high accuracy, and a high quality image can be obtained. Therefore, there is an effect that high-precision control is realized even in response to a request for downsizing and cost reduction of the apparatus.

  Exemplary embodiments of a pixel clock generating apparatus and an image forming apparatus according to the present invention are explained in detail below with reference to the accompanying drawings.

(First embodiment)
Hereinafter, embodiments of the present invention will be described with reference to the drawings. First, a basic embodiment for correcting the aforementioned errors (1) to (4), which is the basis of the present invention, will be described.

  FIG. 1 shows the overall configuration of a first embodiment of an image forming apparatus according to the present invention. In this image forming apparatus, laser light from a semiconductor laser 101 as a light source is shaped through a collimator lens 102 and a cylinder lens 103 and then incident on a polygon mirror 104 as a polarizer, thereby having periodicity. And reflected so as to scan the photosensitive member 105. The reflected laser light is irradiated to the photosensitive member 105 through the fθ lens 106, the mirror 110, and the toroidal lens 107, thereby forming a light spot. Thereby, an image (electrostatic latent image) corresponding to the output of the semiconductor laser 101 is formed on the photoconductor 105.

  Further, a photodetector PD1 (reference numeral 108) and a photodetector PD2 (reference numeral 109) are arranged at both ends of the mirror 110, and the start and end of scanning are detected. That is, the laser beam reflected by the polygon mirror 104 is incident on the PD1 before scanning the photosensitive member 105 for one line, and is incident on the PD2 after scanning. Each photodetector converts the incident laser light into a first synchronization signal SPSYNC and a second synchronization signal EPSYNC, respectively, and supplies them to the pixel clock generation unit 111. The pixel clock generator 111 measures the time interval during which the laser beam is scanned between PD1 and PD2 from the two synchronization signals SPSYNC and EPSYNC, and obtains a predetermined number of clocks within the time interval. A pixel clock PCLK having the specified frequency is generated and supplied to the image processing unit 112 and the modulation data generation unit 113. The configuration of the pixel clock generation unit 111 will be described later. The first synchronization signal SPSYNC which is an output signal of the photodetector PD1 is also given to the image processing unit 112 as a line synchronization signal. The image processing unit 112 generates image data based on the pixel clock PCLK. The modulation data generation unit 113 generates modulation data from the input image data with the pixel clock PCLK as a reference, and drives the semiconductor laser 101 via the laser driving unit 114.

  Next, a detailed embodiment of the pixel clock generation unit 111 in the above-described image forming apparatus will be described with reference to the drawings. FIG. 2 is a block diagram showing a first embodiment of the pixel clock generator 111 according to the present invention. In the pixel clock generation unit 111 of FIG. 2, the high frequency clock generation unit 1 generates a multiplied high frequency clock VCLK based on the reference clock RefCLK, and is configured by a general PLL (Phase Locked Loop) circuit. An accurate high frequency clock VCLK can be obtained by using, for example, an accurate crystal oscillator output as the input reference clock RefCLK. A pixel clock PCLK is generated based on the high-frequency clock VCLK. The frequency divider 4 generates a pixel clock PCLK obtained by dividing the high frequency clock VCLK by M. This is constituted by an M-ary counter, for example, and outputs a count value countM. If counting is started at the rising edge of the synchronization signal SPSYNC, a pixel clock that is phase-synchronized with the scanning start time can be generated. Further, the frequency division ratio M is changed according to the pixel clock frequency instruction signal Mnow from the frequency calculation unit 7. As described above, the pixel clock PCLK is generated by dividing the high-frequency clock VCLK oscillated stably and with high accuracy. Therefore, the pixel clock frequency can be changed instantaneously and stably by changing the division ratio. It becomes possible to do. Therefore, even if the frequency for each line is changed, the transition can be made instantaneously.

  The first edge detector 2 detects the rising edge of the first synchronization signal SPSYNC with reference to the high frequency clock VCLK, and when the rising edge of the first synchronization signal SPSYNC is detected, the detection pulse SPpls synchronized with the pixel clock PCLK. Is output. The second edge detector 3 detects the rising edge of the second synchronization signal EPSYNC with reference to the high frequency clock VCLK, and outputs a detection pulse EPpls and a count value EPm. The comparison unit 5 detects the time Tline between the two synchronization signals SPSYNC and EPSYNC, and calculates the difference between the reference time predetermined according to the writing frequency and the distance between the two photodetectors PD1 and PD2 and the measured time Tline. Calculated as the error LErr of the line. That is, the difference between the appropriate scanning time (reference time) and the scanning time Tline of the line is the scanning speed error. The error LErr may be counted and calculated based on the high-frequency clock VCLK. However, the high-frequency clock VCLK has a very high frequency and the number of bits to be counted becomes very large. It is disadvantageous. Therefore, in the present embodiment, the time Tline is counted using the pixel clock PCLK as a reference, compared with the reference value RefN, and finally converted as an error LErr of the line based on the high frequency clock. The filter 6 is a digital filter that filters the line error LErr and outputs error data Err. For example, the filter 6 simply calculates the error LErr by averaging the errors LErr for the latest plural lines.

The frequency calculation unit 7 calculates an appropriate pixel clock frequency according to the error data Err, converts it to a pixel clock frequency instruction signal Mnow, and outputs it. When the high frequency clock cycle is Tv, the pixel clock cycle is Tp, and scanning is performed with the pixel clock frequency set to Tp = KTv, an error Err from the target value Tp ′ (Tp ′ = K′Tv) is input. . Therefore, since RefN · Tp ′ = RefN · Tp + Err · Tv,
K ′ = K + Err / RefN (1) If K ′ is set as equation (1), the pixel clock frequency can be controlled to the target value.

  That is, the digital PLL control is performed by the frequency divider 4, the comparison unit 5, the filter 6, and the frequency calculation unit 7. The characteristics of the filter 6 determine the PLL control characteristics, and the filter characteristics are determined so that the control system becomes stable. Further, the loop gain may be changed as K ′ = K + α · Err / RefN. Further, since the frequency division ratio M of the frequency divider 4 is a natural number, the rounding error can be reduced by converting the set value K of the pixel clock frequency into the pixel clock frequency instruction signal Mnow as follows. An accurate pixel clock can be obtained. For example, normally, a value obtained by rounding the set value K to a whole number and rounding it to an integer is M, Mnow = M, and Mnow = M + 1 or M−1 once every C clock cycle, so that K = (M ± 1 / C) and rounding error can be reduced. Further, since the rounding error can be equally distributed, the local deviation of the pixel clock can be suppressed. In this case, the M value and the C value may be controlled. Detailed description will be given later.

  FIG. 4 is a detailed configuration example of the comparison unit 5. FIG. 3 is an example of a timing chart of some signals in FIG. 2, and the detailed operation of the comparison unit 5 will be described based on these. In FIG. 3, (a) SPSYNC is a first synchronization signal indicating the start of scanning, and is input to the first edge detector 2. (b) EPSYNC is a second synchronization signal indicating the end of scanning, and is input to the second edge detector 3. (c) VCLK indicates the rising edge of the high-frequency clock generated by the high-frequency clock generator 1. (d) countM is a count value counted by the frequency divider 4 with reference to the high frequency clock VCLK, and (e) PCLK is a pixel clock that rises when (d) countM is 0. (f-1) SPpls and (f-2) EPpls are pulses synchronized with PCLK indicating the rise of (a) SPSYNC and (b) EPSYNC, respectively. (g-2) EPm is (b) the rise of EPSYNC. It is the value of (d) countM at the time. (h) is the value of the counter in the comparison unit 5 that counts on the basis of the pixel clock PCLK, and is reset to 0 at (f-1) SPpls and stopped at (f-2) EPpls.

In the comparison unit 5 of FIG. 4, the counter 11 is a counter that counts based on the pixel clock PCLK, is reset to 0 by SPpls, and stops counting at EPpls. The subtracting unit 12 subtracts the reference count value RefN from the value countN (n in FIG. 3) of the counter 11 after the count is stopped, and outputs a subtraction result diffN. The error calculator 13 performs the following calculation and outputs an error LErr with the high-frequency clock VCLK cycle Tv as a unit.
LErr = diffN · K + EPm
Here, diffN = n−RefN, EPm = m2, Tp = K · Tv, Tp: the period of PCLK.

  If the distance between the two photodetectors PD1 and PD2 is not an integral multiple of the dot width, that is, if the reference time is not an integral multiple of the target pixel clock period, the fraction is converted into the number of cycles of the high-frequency clock VCLK. Is input to the error calculation unit 13 as RefM and calculated as LErr = diffN · K + EPm−RefM, the pixel clock frequency can be controlled more accurately.

FIG. 5 is a detailed configuration example of the frequency calculation unit 7. In this embodiment, it is assumed that the polygon mirror has a six-surface configuration, and the pixel clock frequency is controlled for each surface in order to correct an error for each surface. The calculation unit 16 calculates the next set values NextM, NextC, NextR from the current set values M, C, R and the error data Err. This calculation is performed for each surface according to the calculation surface instruction signal CalcNo. Do. As described above, the relationship between M, C, and R is Tp = (M ± 1 / C) Tv, and C = RefN / R. From these equations and equation (1), (NextM = M ′, NextR = R ′, RefN = Nr)
M ′ + R ′ / Nr = M + R / Nr + Err / Nr, C ′ = Nr / R ′
Therefore, the calculation is performed according to the following procedure.

<1> R + Err (= TmpR) is calculated.
<2> If TmpR> Nr / 2, M ′ = M + 1 and R ′ = TmpR−Nr. If TmpR <−Nr / 2, M ′ = M−1 and R ′ = TmpR + Nr. In other cases, M ′ = M and R ′ = TmpR.
<3> Let C ′ be the quotient of Nr ÷ R. If R ′ = 0, C ′ = 0.

  The register 17 is a data holding unit for holding the M value obtained by the above calculation, and the value to be held is a value of F0M to F5M for each surface of the polygon mirror. Further, the corresponding register value is updated to NextM in accordance with the update signal Renew. Here, F * (* is the polygon mirror surface number 0 to 5) indicates a value corresponding to the polygon mirror surface number (the same applies hereinafter). Note that the surface number indicates a relative relationship, and the corresponding value is automatically controlled, so it is not necessary to match the actual surface. Similarly, the register 18 is a data holding unit that holds the currently set C value, and the register 19 is a data holding unit that holds the currently set R value. The corresponding register values are updated to NextC and NextR according to the update signal Renew.

  The selection unit 20 selects and outputs a corresponding M value among F0M to F5M according to the surface selection signal FNo. Similarly, the selection unit 21 selectively outputs a corresponding C value among F0C to F5C according to the surface selection signal FNo. Csign represents the sign of the C value.

  The counter 23 counts the C value (from 0 to C-1) with reference to PCLK. When the count value becomes C-1, the counter 23 indicates +1 if Csign is positive and indicates negative. If this is the case, -1 is output, otherwise 0 is output. When C = 0, 0 is always output. The adder 22 adds M output from the selector 20 and the value output from the counter 23, and outputs the result as a pixel clock frequency instruction signal Mnow. Therefore, the M value is converted to +1 or −1 once every C cycle of PCLK, and the average period of the pixel clock is (M ± 1 / C) Tv.

  The calculation control unit 15 controls the above-described calculation, and generates and outputs a calculation surface instruction signal CalcNo, an update signal Renew, and a surface selection signal FNo according to the flowchart shown in FIG. In FIG. 6, first, initialization is performed with FNo = 0 and CalcNo = 0 (step S1), and the process waits until scanning of one line is completed (step S2). That is, it waits until the end of scanning is detected by EPpls. Note that the waiting time includes a grace period until the calculation of the error data Err is finalized. Subsequently, the above-described calculation corresponding to the current CalcNo is performed (step S3), the update signal Renew corresponding to the current CalcNo is activated, and the value of each register is updated to the Next value (step S4). Subsequently, CalcNo is incremented. When CalcNo = 5, the process returns to 0 (step S5). Subsequently, the process branches according to a lock flag Lock indicating whether or not the pixel clock frequency control is locked (step S6). Here, the lock flag Lock may be determined based on, for example, a predetermined line (for example, 6 lines) error LErr (or error data Err) within a predetermined range (a variation range of the inter-surface error, desired control accuracy, or the like). (For example, within ± 2M), the signal is regarded as being locked, and the signal generator may be provided in the filter 6, for example. Alternatively, a predetermined time (designated by the number of lines or the like) may be determined in advance from the start of control based on control responsiveness, and the Lock signal may be activated when this time has elapsed. In step S7, if the determination result in step S6 is No (that is, if it is not yet locked), it is determined whether or not the setting value has been updated by performing calculations on all surfaces. If all six planes have been calculated, FNo = CalcNo, and the process proceeds to step S8. If the result is NO, the process returns to step S2 to perform another surface calculation. In step S8, FNo is incremented (in the case of 5, it returns to 0), and FNo is substituted for CalcNo (value after increment). As a result, the M and C values to be converted into the pixel clock frequency instruction signal Mnow are changed to the set values for the next line. The operations up to this point are performed until the next line starts scanning (SPSYNC is detected). Thereafter, the process returns to step S2 and the above routine is repeated. By controlling in this way, the error Err is controlled to be reduced on all surfaces until the clock frequency of each surface is within the predetermined error, so that high-speed pull-in can be performed and the clock frequency is within the predetermined error. Thereafter, since each surface is individually controlled, errors between the surfaces are reduced, and highly accurate clock frequency control can be performed.

  FIG. 7 is a diagram showing an example of the pull-in process according to this control method, where the horizontal axis represents time and the vertical axis represents line error LErr. Black circles are errors corresponding to the 0th surface, and errors on the other surfaces are indicated by crosses. A dotted line indicates an average value of errors for six surfaces.

FIG. 8 is another detailed configuration example of the frequency calculation unit 7. The calculation control unit 15 controls this calculation in the same manner as that of FIG. The calculation unit 25 calculates the next set values NextM and NextF from the current set values M and F and the error data Err, and performs this calculation for each surface in accordance with the calculation surface instruction signal CalcNo. In this embodiment, the set value K of the pixel clock frequency is converted into the pixel clock frequency instruction signal Mnow as follows. That is, the integer part of the set value K is set to M, and the decimal part is rounded to a value F of a digit (binary notation). Then, K = (M + F / Na) is set by setting Mnow = M + 1 F times in 2 ^ a (= Na) cycles. Here, since the rounding error due to the set value is the maximum NRefNa, it is only necessary to determine the number of digits a in the decimal part so that it falls within the desired error tolerance. In order to suppress local frequency deviation, F cycles of +1 are distributed evenly. This function is performed by the conversion unit 31 (details of the operation will be described later). Therefore, from the equation (1) and the relational expression of K, (NextF = F ′)
K ′ + F ′ / Na = M + F / Na + Err / Nr
Therefore, the calculation is performed according to the following procedure.

<1> F + Err / Nr * Na (= TmF) is calculated. Since Na is 2 ^ a, * Na only needs to take the upper a bits of the multiplicand (Err / Nr), and Nr is fixed during this frequency control, so the reciprocal of Nr is calculated in advance. If this is multiplied by Err, the calculation can be performed easily.
<2> If TmpF> Na, M ′ = M + 1 and F ′ = TmpF−Na. If TmpF <0, M ′ = M−1 and F ′ = TmpF + Na.

  Similarly to FIG. 5, the register 26 is a data holding unit that holds the M value obtained by the above calculation, and the register 27 is a data holding unit that similarly holds the F value. These held values are held in F0 to F5 for each surface of the polygon mirror. Then, the corresponding register values are updated to NextC and NextR in accordance with the update signal Renew.

  The selection unit 28 selects and outputs a corresponding M value from F0M to F5M in accordance with the surface selection signal FNo. Similarly, the selection unit 29 selects and outputs the corresponding C value among F0F to F5F in accordance with the surface selection signal FNo.

  The counter 30 is an a-bit counter that counts based on PCLK, and outputs the count value countA. In accordance with the count value countA, the conversion unit 31 outputs a signal UP with “1” for the F cycle and “0” for the remaining Na-F cycles during the Na (= 2 ^ a) cycle. The generation of the UP signal is set to 1 when Arev is smaller than F when countA [0: a-1] obtained by reversing the bit arrangement of the count value countA [a-1: 0] is Arev. (UP = (Arev <F)), “1” is generated F times evenly during the Na cycle.

  The adder 32 adds M output from the selector 28 and UP output from the converter 31, and outputs the result as a pixel clock frequency instruction signal Mnow. Therefore, the conversion is made so that the M value is incremented by +1 F times in the Na cycle of PCLK, and the average period of the pixel clock becomes (M + F / Na) Tv.

  As described above, the pixel clock frequency is controlled by detecting the phase error LErr for each line and performing digital PLL control so that the phase error LErr becomes zero. The filter 6 is a digital filter placed in the control loop, and the control band can be set by changing the filter characteristics. An example of filter setting is shown below.

First, the loop gain of the DPLL control system excluding the loop filter is as shown in FIG. Here, fs is the sampling frequency, that is, here the line frequency. The control system can be stabilized by inserting a lag reed filter having the characteristics as shown in (b) into the control system to obtain the loop gain shown in (c).
Assuming that τ1 = / 2πf1 and τ2 = 1 / 2πf2, the transfer function H (s) of the loop filter is as follows.
H (s) · (1τ2s) / (1τ1s)
If the above equation is converted into a z-transform form by bilinear transformation (s = 2 / T · (1-z ^ -1) / (1 + z ^ -1)) and further normalized as T = 1, the loop filter The transfer function H (z) is
H (z) = (b0 + b1z ^ -1) / (1 + a1z ^ -1)
a1 = (1-2τ1) / (1 + 2τ1), bo = (1 + 2τ2) / (1 + 2τ1), b1 = (1-2τ2) / (1 + 2τ1)

  FIG. 10 is a detailed configuration example of the filter 6 that realizes the above transfer function H (z). This is a first-order IIR type filter. The adders 40 and 45 add the respective inputs, and the multipliers 42, 43 and 44 output values obtained by multiplying the inputs by the coefficients -a1, b1 and b0, respectively. The delay element 41 delays the intermediate variable w every sample (that is, every line). If the line error LErr is input to this filter, error data Err is obtained.

  Further, if means for changing each coefficient of the multiplier is provided, the filter characteristics can be dynamically changed. For example, the filter characteristics may be changed according to the above-described Lock signal. Note that the filter characteristics and configuration of this example are merely examples, and the present invention can be applied to filters having other configurations. Since the digital filter is a known technique, the illustration of other configurations is omitted.

  Next, a suitable modulation method of the modulation data generation unit 113 that modulates the image data based on the pixel clock PCLK generated by the pixel clock generation unit 111 of FIG. 2 will be described. FIG. 11 is a timing chart for explaining the operation of the modulation data generation unit 113. Here, it is assumed that modulation data Mdata subjected to 8-value pulse width modulation is generated in accordance with the image data Pdata. In FIG. 11, (a) VCLK indicates the rising edge of the high-frequency clock (cycle Tv), and (b) countM is the count value counted by the frequency divider 4, and now Mnow = 16 is set. . (c) PCLK is a pixel clock, and here the period is 16 Tv. (d) Pdata is image data input in synchronization with PCLK, and modulates the pulse width Tw of modulation data (e) Mdata to be output according to this value Dm. The modulation data Mdata is generated based on the high-frequency clock VCLK. If Dm ≠ 0, it is set to “H” when countM = 0. In addition, when countM = Dm / Nm · Mnow (Nm is the number of gradations and 8 here), it is set to “L”. Or, if “M” is set to “H” when countM = (Nm−Dm) / Nm · Mnow, and “L” is set when countM = 0 if Dm ≠ 8, modulation data such as (e ′) is generated. it can. Further, these two generation modes may be switched so that each dot can be changed.

  In the above description, the mode in which the pixel clock frequency is controlled in accordance with the variation of the scanning time between the two points of scanning start and end has been described. However, if the scanning speed in one line is substantially constant, one line The control may be performed in accordance with the fluctuation of the scanning time between any two of the points, and this embodiment can be applied.

  As described above, according to the first embodiment of the pixel clock generation unit, the pixel clock is generated based on the high-frequency clock VCLK generated with high accuracy, and the pixel clock frequency is set in accordance with the variation in the scanning time. Since it is controlled, a pixel clock that can correct this error with high accuracy can be generated even if the scanning average speed fluctuates, and the pixel clock frequency is controlled corresponding to each surface of the polygon mirror. Therefore, it is possible to generate a pixel clock that can be corrected with high accuracy even if there is a scanning speed error for each surface. Further, when this pixel clock generation unit is applied to an image forming apparatus, an image is formed on the basis of a pixel clock in which a scanning speed error is corrected with high accuracy, so that a high quality image can be obtained.

  Next, FIG. 12 is a block diagram showing another embodiment of the pixel clock generation unit according to the present invention, and the operation configuration will be described based on the drawing. In the pixel clock generation unit 118 of FIG. 12, the high frequency clock generation unit 51 multiplies based on the reference clock RefCLK to generate a multiphase clock with equal phase differences (in this embodiment, 16 phase). (It is assumed that multiphase clocks VCLK0 to VCLK15 are generated), and an internal operation clock GCLK is generated by dividing one of the multiphase clocks by Q (here, Q = 4), not shown. Is supplied to each part of the pixel clock generator 118.

  FIG. 14 is a timing chart showing the timing of each clock generated by the high-frequency clock generation unit 51. (a-0) to (a-15) are clocks of the multiphase clocks VCLK0 to VCLK15 and have a phase difference of equal intervals, and this time interval is assumed to be Tv. (B) GCLK is a clock obtained by dividing (a-0) VCLK0 by four. The pixel clock generation unit 118 in FIG. 12 basically operates using this clock GCLK as an operation clock, and the periods obtained by dividing GCLK into four are called QT0, QT1, QT2, and QT3 in order. The corresponding times are referred to as PH0 to PH15, and the time information QP in GCLK is represented by the period QT and the phase PH. Here, the time information QP is 64 values of 0 to 63, and in the present embodiment, the pixel clock PCLK is generated with reference to the phase difference Tv of the multiphase clock at equal intervals. That is, the control operation of the pixel clock frequency is performed by calculating the time information QP (QTPH) based on the operation clock GCLK.

  Returning to FIG. 12, the first edge detection unit 52 detects the rising edge of the first synchronization signal SPSYNC with reference to the multiphase clocks VCLK0 to VCLK15. When the rising edge of the synchronization signal SPSYNC is detected, the first edge detection unit 52 synchronizes with the clock GCLK. Time information SPQP indicating the detected pulse SPpls, the rising period QT, and the phase PH is output. Similarly, the second edge detection unit 53 detects the rising edge of the second synchronization signal EPSYNC with reference to the multiphase clocks VCLK0 to VCLK15. When the rising edge of the synchronization signal EPSYNC is detected, the detection is performed in synchronization with the clock GCLK. Time information EPQP indicating the pulse EPpls, the rising period QT, and the phase PH is output.

  The counting unit 54 counts time according to the pixel clock frequency instruction signal Mnow from the frequency calculation unit 57, and generates a Set signal (consisting of a SETpls signal synchronized with GCLK and time information SETQP) every time it reaches Mnow. In addition, the time corresponding to Mnow / 2 is counted from the Set signal, and an Rst signal (consisting of an RSTpls signal synchronized with GCLK and time information RSTQP) is generated. The time unit for counting is the phase difference Tv between the multiphase clocks VCLK0 to VCLK15. The pixel clock output unit 58 generates and outputs a pixel clock PCLK by switching “H” <−> “L” in accordance with the Set signal and the Rst signal supplied from the counting unit 54. Details of the configuration and operation will be described later.

  The comparison unit 55 detects the time Tline between the two synchronization signals SPSYNC and EPSYNC, and calculates the difference between the reference time predetermined according to the writing frequency and the distance between the two photodetectors PD1 and PD2 and the measured time Tline. Calculated as the error LErr of the line. That is, the difference between the appropriate scanning time (reference time) and the scanning time Tline of the line is the scanning speed error. Here, the number of SETpls input during the period from the input of SPpls to the input of EPpls is counted, this value is compared with the reference value RefN, and the error of the line is calculated from the time information of each pulse. It is converted as LErr. The unit of this error is the phase difference Tv.

  The filter 56 is a digital filter that filters the line error LErr and outputs error data Err. The frequency calculation unit 57 calculates an appropriate pixel clock frequency according to the error data Err, converts it into a pixel clock frequency instruction signal Mnow, and outputs it. When the pixel clock cycle is Tp and scanning is performed with the pixel clock frequency set as Tp = KTv, an error Err from the target value Tp ′ (Tp ′ = K′Tv) is input. Therefore, the pixel clock frequency can be controlled to the target value by setting K ′ obtained by the equation (1) as described above.

  The filter 56 and the frequency calculation unit 57 perform the same functions as the filter 6 and the frequency calculation unit 7 in FIG.

(Second Embodiment)
Next, details of each part of the second embodiment of the pixel clock generation part will be described. FIG. 13 is a block diagram illustrating a configuration example of the high-frequency clock generation unit 51. The high-frequency clock generation unit generates multiphase clocks VCLK0 to VCLK15 and an internal operation clock GCLK from the reference clock RefCLK. The voltage controlled oscillator VCO 63 is configured by a ring oscillator to which eight stages of differential buffers 64a to 64h are connected, and generates 16-phase clocks VCLK0 to VCLK15. The frequency divider 60 divides one of the multiphase clocks (here, VCLK8) by Nv. The phase frequency comparator PFD 61 performs phase comparison between the reference clock RefCLK and the output of the frequency divider 60, and drives an internal charge pump based on this phase difference information. The low pass filter LPF 62 smoothes the charge pump output and supplies the control voltage Vc to the VCO 63. The differential buffers 64a to 64h in the VCO 63 change in delay amount according to the control voltage Vc, and phase synchronization control is performed. For example, when a 100 MHz clock is supplied as the reference clock RefCLK and the frequency division ratio Nv is 20, the multiphase clocks VCLK0 to VCLK15 can generate clocks having a phase difference of equal intervals at 2 GHz. Further, the frequency divider 65 divides one of the multiphase clocks VCLK0 to VCLK0 to 15 (here, VCLK0) by Q (Q = 4 here) to generate the clock GCLK. Note that the number of phases of the multiphase clock that can be applied is not limited to 16 in this example, but a power of 2 is most desirable from the viewpoint of simplicity of calculation. Similarly, the division ratio Q for generating GCLK is most preferably a power of 2.

  FIG. 15 is a block diagram illustrating a configuration example of the counting unit 54. FIG. 16 is a block diagram illustrating a configuration example of the pixel clock output unit 58. Further, FIG. 17 is a timing chart showing an example of the output timing of each signal of the counting unit 54 and the pixel clock output unit 58. A detailed configuration and operation for generating the pixel clock PCLK in accordance with the pixel clock frequency instruction signal Mnow will be described with reference to these drawings.

  In FIG. 15, each unit operates in synchronization with the clock GCLK. The SET time calculation unit 70 adds the pixel clock frequency instruction signal Mnow to the current PCLK rise time information, and calculates set time information NextS representing the next PCLK rise time. The update of this calculation is performed by the pSet signal. To do. Note that a quotient obtained by dividing the set time information NextS by 64 is NextSc, and the remainder is NextSQP. That is, NextSc = NextS [MSB: 6], NextSQP = NextS [5: 0]. Since the generation of PCLK is started in phase with the rising edge of SPSYNC (more precisely, after a predetermined signal processing time, here, 2GCLK), the first PCLK rising time information is SPQP. Similarly, the RST time calculation unit 71 adds 1/2 of the pixel clock frequency instruction signal Mnow to the current PCLK rise time information, and calculates reset time information NextR representing the next PCLK fall time. Yes, this calculation is updated by the pSet signal. Further, NextRc = NextR [MSB: 6] and NextRQP = NextR [5: 0]. The reason why Mnow / 2 is added is to make the duty of PCLK almost 50%, and when the duty of 50% is not required, a value that can simplify this calculation may be added. The counter 72 counts NextSc cycles with the clock GCLK as a reference, and generates a pSet signal. When this pSet signal is “H”, the counter is cleared to “1”, and when the count value matches NextSc, the pSet signal is set to “H”.

  The F / F 73 is a flip-flop that generates a SETpls signal by delaying the pSet signal and the SPpls signal by 1 GCLK. The F / F 74 is a flip-flop that enables NextSQP by enabling the pSet signal, latches SPQP by enabling SPpls, and generates a SETQP signal. This SETpls signal designates the rise of PCLK in units of GCLK, and designates rise time information in the GCLK cycle by the SETQP signal synchronized therewith. These are called Set signals and are supplied to the pixel clock output unit 58. The counter 75 counts the NextRc cycle with reference to the clock GCLK, and generates an RSTpls signal. When SETpls is “H”, the counter is cleared to “1”, and when the count value matches NextRc, the RSTpls signal is set to “H”. The F / F 76 is a flip-flop that enables SETpls to latch NextRQP and generate an RSTQP signal. This RSTQP signal designates the fall of PCLK in units of GCLK, and the RSTQP signal designates fall time information within the GCLK cycle. These are called Rst signals and supplied to the pixel clock output unit 58.

  Since the SETQP signal and the RSTQP signal only need to be valid when the SETpls and RSTpls signals are “H”, respectively, the control timing of each unit is not limited to this embodiment.

  In FIG. 16, a delay unit 77 outputs a pulse S obtained by delaying SETpls supplied from the counting unit 54 according to time information SETQP with reference to the multiphase clocks VCLK0 to VCLK, and during the GCLK cycle. The clock GCLK is also input to specify the period QT. Alternatively, a period signal QT indicating a period may be input (in this case, the high-frequency clock generation unit 51 generates this QT signal). That is, the pulse S is a pulse obtained by delaying SETpls by SETQPTv.

  Similarly, the delay unit 78 outputs a pulse R obtained by delaying the RSTpls supplied from the counting unit 54 according to the time information RSTQP with reference to the multiphase clocks VCLK0 to VCLK15. Only a delayed pulse is obtained. The SR-F / F 79 is a Set-ReSet flip-flop that outputs a pixel clock PCLK that is set to “H” at the rising edge of the pulse S and reset to “L” at the rising edge of the pulse R.

  In FIG. 17, (a) is GCLK. When the first edge detection unit 52 detects the rising edge of the first synchronization signal (b) SPSYNC, the next GCLK1 cycle becomes “H”. (C−1) The SPpls signal is output, and the GCLK cycle (C-2) An SPQP signal (in this example, 10) is also output indicating at what time it started. (d) Mnow is a pixel clock frequency instruction signal supplied from the frequency calculation unit 57, and is input as shown. (e-1) NextS represents the rise time of the next PCLK calculated by the SET time calculation unit 70. First, since PCLK rises in synchronization with the rise of SPSYNC, the next rise of PCLK is after SPQP + Mnow = 250 Tv. Here, the numerical value before the comma on the right side represents NextSc, and the numerical value after the comma represents NextSQP. The next NextS is NextSPQP + Mnow = 298. (e-2) NextR represents the fall time of the next PCLK calculated by the RST time calculation unit 71. First, the value obtained by adding Mnow / 2 to the rising edge of SPSYNC (= 130) is the falling time of PCLK. Like (e-1) NextS, the numerical value before the comma on the right side is NextRc, and the numerical value after the comma is Represents NextRQP.

  (f) pSet is a pulse output 1 GCLK before SETpls in order to update the SETQP signal, and becomes “H” when the count value of the counter 72 coincides with NextSc. In addition, the [] number shown in the figure represents the count value of NextSc. (g-1) SETpls is a pulse obtained by delaying the SPpls and pSet signals by 1 GCLK, and specifies the rising edge of PCLK in GCLK units. (g-2) SETQP is PCLK rise time information indicating the delay value of SETpls, and (f) is updated to the value of (e-1) NextSQP when pSet is “H”. (h-1) RSTpls is a pulse in which the falling edge of PCLK is designated in units of GCLK, and becomes “H” when the count value of the counter 75 coincides with NextRc. (h-2) RSTQP is PCLK fall time information indicating a delay value of RSTpls.

  (i-1) S is a pulse obtained by delaying (g-1) SETpls by the corresponding (g-2) SETQP value, and the unit of the delay value is the phase difference Tv of the multiphase clocks VCLK0 to VCLK15. . Similarly, (i-2) R is a pulse obtained by delaying (h-1) RSTpls by the corresponding (h-2) RSTQP value. (j) PCLK is a pixel clock generated as (i-1) “H” at the rising edge of S and (i-2) “L” at the rising edge of R.

  FIG. 18 is a block diagram illustrating a detailed configuration example of the comparison unit 55. FIG. 19 is a timing chart showing an example of the output timing of each signal, and the detailed operation of the comparison unit 55 will be described based on these timing charts.

  In FIG. 19, (a) is GCLK. (b-1) is SPSYNC, and (b-2) is EPSYNC. The time interval between the rises of these two signals is the scanning time Tline of the line. (c-1) is SPpls, and (c-2) is EPpls. (D-2) EPQP is time information of the synchronization signal EPSYNC. Further, (e-1) SETpls and (e-2) SETQP are time information indicating the rising edge of PCLK. Since these have been described above, description thereof will be omitted. (e-3) SETcnt is the count value of the counter 72. In this example, Mnow = 192 is constant. At this time, (f) PCLK is generated. Since PCLK is generated in synchronization with exactly 2GCLK after SPSYNC, the scan end point EP is also detected when it is delayed by 2GCLK from EPSYNC. Therefore, (c-2) EPpls is delayed by 1 GCLK, (d-1) Error LErr is detected from each signal value when EPdet is "H". (g) is pSet, and (h) countN is a count value of the counter 81 that is cleared to “0” by (c−1) SPpls and incremented by (g) pSet. From these, the number of PCLK cycles n and the phase error m2 from the start of scanning to the end of scanning EP are detected.

In FIG. 18, a counter 81 is a counter that is cleared to 0 by SPpls and incremented by pSet, and outputs the count value countN. The subtracting unit 82 subtracts the reference count value RefN from the value countN (n in FIG. 19) of the counter 81 when EPdet is “H”, and outputs a subtraction result diff (= n−RefN). The error detection unit 84 calculates the phase difference diffM by performing the following equation when SETQP and SETcnt when EPdet is “H” are respectively EndQP and Endcnt.
diffM = Endcnt · Mp + (EPQP−EndQP)
Here, Mp is the number of time information divisions of GCLK, and is 64 in this example. In the example of FIG. 19, diffM = 144.

The error calculation unit 83 performs the following calculation and outputs an error LErr in units of the phase difference Tv between the multiphase clocks VCLK0 to VCLK15.
LErr = diffN · K + diffM
Here, Tp = K · Tv, Tp: PCLK.
Similar to FIG. 4, LErr = diffN · K + diffM−RefM may be calculated to set the reference time setting value more finely, so that the pixel clock frequency can be controlled more accurately.

  Next, a preferred configuration and operation of the modulation data generation unit 119 that modulates image data based on the pixel clock PCLK generated by the pixel clock generation unit 118 of FIG. 12 will be described. FIG. 20 is a diagram illustrating a detailed configuration example of the modulation data generation unit 119. FIG. 21 shows an example of a timing chart of each signal of the modulation data generation unit 119, and a detailed operation will be described based on these drawings. In this example, it is assumed that modulation data Mdata obtained by performing 8-value pulse width modulation is generated in accordance with the image data Pdata.

  In FIG. 20, the modulation data generation unit 119 is supplied with GCLK to each unit and operates as a reference clock. The clock pattern generation unit 90 corresponds to a clock having a predetermined phase difference of the pixel clock PCLK from the Set signal that is supplied from the pixel clock generation unit 118 and configured from the SETpls and SETQP signals and the pixel clock frequency instruction signal Mnow. A clock pattern signal CKP (here, CKP0 to 3 and a clock pattern delayed by 0, π / 8, π / 4, and 3π / 8 phases from PCLK, respectively) is generated. This clock pattern signal CKP is a signal that changes based on GCLK, and is 64-bit data corresponding to 64 periods TQP obtained by dividing the GCLK cycle by time information QP. If the period TQP is “H”, this clock pattern signal CKP corresponds to this clock pattern signal CKP. When the bit to be “1” is “L”, it is “0”.

  The clock pattern generation procedure is performed as follows. First, offset data sofs0 to 3 and falling offset data rofs0 to 3 indicating the rising edge of each clock pattern are obtained. Sofs0 = SETQP, sofs1 = SETofs + Mnow / 8, sofs2 = SETofs + Mnow / 4, sofs3 = SETofs + 3Mnow / 8, and rofs0-3 adds Mnow / 2 to rofs0-3, respectively. Next, the MSB of the clock pattern CKP for each cycle of GCLK is converted into “0” from sofs to “0”, from sofs to rofs, to “1”, and from rofs to “0”. If each offset data is 64 or more, this conversion is performed by delaying 1 GCLK for every 64. For example, when Mnow = 192 and SETQP = 16, CKP1 is sofs = 40 and rofs = 136 (= 2GCLK + 8). 0 ”, 23 to 0 bits are“ 1 ”, the second GCLK cycle pattern is all“ 1 ”, the third GCLK cycle pattern is 63 to 56 bits“ 1 ”, and 55 to 0 bits are“ 1 ”. 0 ".

  The image data decoding unit 91 converts the image data Pdata into 8-value pulse width modulation data DecData (8 bits). In the pulse width modulation data DecData, each bit corresponds to MSB to LSB in order of time in a period in which one cycle of the pixel clock PCLK is time-divided into eight. For example, if Pdata = 3, it is converted to DecData = 'b11100000 (' b indicates binary notation). Alternatively, it may be converted as DecData = 'b00000111, or both modes may be switched by adding a mode switching signal. Note that this conversion method can be freely selected within a range that does not contradict the gist of the present invention.

  The modulation pattern generation unit 92 generates a modulation pattern signal MDP from the pulse width modulation data DecData and the clock pattern signals CKP0 to CKP3. Similar to the clock pattern signal CKP, the modulation pattern signal MDP is a signal that changes with reference to GCLK, and is 64-bit data corresponding to 64 periods TQP obtained by dividing the GCLK cycle by the time information QP.

  The serializer 93 generates modulation data Mdata that is serially output from the MSB in order of the Tv time with respect to the multi-phase clocks VCLK0 to 15 with the modulation pattern signal MDP as a reference.

  In FIG. 21, description will be made with specific numerical examples. (a) is GCLK which becomes a reference clock. Now, when (b-1) SETpls and (b-2) SETQP constituting the Set signal are supplied as shown in the figure, the pixel clock is generated as (c-1) PCLK. Further, it is assumed that the pixel clock frequency instruction signal Mnow = 192. Also, although not actually generated, the clocks whose phases are delayed by π / 8, π / 4, and 3π / 8, respectively, are (c-2) PCLK1, (c-3) PCLK2, and (c-4) PCLK3. Shown for explanation. (d-1) to (d-4) are clock patterns CKP0 to CK3 representing PCLK and PCLK1 to PCLK3, respectively. Each is 64-bit data in MSB to LSB in chronological order and is expressed in HE. Therefore, from these clock patterns CKP <b> 0 to 3, patterns (referred to as PT <b> 0 to PT <b> 7 in order of time) indicating periods (tp <b> 0 to tp <b> 7) obtained by time-dividing the pixel clock PCLK into eight can be generated. That is, PT0 = CKP0 & ˜CKP1, PT1 = CKP1 & ˜CKP2,..., PT7 = ˜CKP3 & ˜CKP0. Here, & indicates a logical product, and ~ indicates a negative logic.

  (e) DecData is pulse width modulation data, and is converted as shown in the figure. (f) MDP is a modulation pattern signal. First, ([64 [DecData [7-i]]] & PTi) when i is changed from 0 to 7 is calculated, and then the logical sum of these is calculated. Can be obtained. Here, [64 [DecData [i]]] is data obtained by connecting DecData [i] for 64 bits. By serializing the modulation pattern signal thus generated, (g) Mdata modulation data can be generated. In this example, a pulse whose width is modulated so that the first 3/8 period of the PCLK period Tp is “H” and the remaining period is “L” is generated.

  In addition, instead of generating clock patterns CKP0 to CKP3 whose phases are shifted by π / 8 each, patterns PT0 to PT7 indicating respective periods obtained by time-dividing one cycle of the pixel clock PCLK into eight are generated. The modulation pattern signal MDP may be generated from these and the pulse width modulation data DecData.

  Furthermore, in this example, the case of performing 8-value pulse width modulation has been described, but other modulation schemes can also be applied. For example, when 16-value pulse width modulation is performed, the image data decoding unit 91 converts the image data Pdata into 16-bit pulse width modulation data DecData, and the clock pattern generation unit 90 is π / 16 each of the pixel clock PCLK. Eight clock patterns CKP0 to CKP7 whose phases are shifted may be generated, and the modulation pattern signal generation unit 92 may generate the modulation pattern signal MDP in the same manner.

  Further, this configuration example may be applied to the pixel clock output unit 58 of FIG. That is, the clock pattern PCKP of the pixel clock PCLK is generated (the above-described clock pattern signal CKP0 may be used), and this is serially output in order of Tv time from the MSB (that is, in time order) on the basis of the multiphase clocks VCLK0 to VCLK15. Then, the pixel clock PCLK can be generated.

  As described above, according to the second embodiment of the pixel clock generation unit, the pixel clock is generated based on the multiphase clocks VCLK0 to VCLK15 generated with high accuracy, and is adjusted according to the variation of the scanning time. Since the pixel clock frequency is controlled, it is possible to generate a pixel clock that can correct this error with high accuracy even if the scanning average speed fluctuates. Further, the pixel clock frequency is controlled corresponding to each surface of the polygon mirror. Since the control is performed, it is possible to generate a pixel clock that can be accurately corrected even if there is a scanning speed error for each surface. Further, since the generation of the pixel clock can be accurately controlled in units of the phase difference Tv between the multiphase clocks VCLK0 to VCLK15, it is not necessary to increase the oscillation frequency of the multiphase clock, so that the circuit design is facilitated and the current consumption can be reduced. . For example, when the pixel clock is generated with the same resolution as that of the first embodiment, the oscillation frequency of the multiphase clock may be 1/16. In other words, the pixel clock generation resolution can be improved 16 times when the oscillation frequencies are the same. That is, a highly accurate pixel clock can be generated. Furthermore, most of the pixel clock generator 118 operates with a clock GCLK obtained by further dividing one of the multiphase clocks, so that the operating frequency can be further reduced and the current consumption can be reduced.

  Further, when the pixel clock generation unit 118 is applied to an image forming apparatus, an image is formed on the basis of a pixel clock in which a scanning speed error is corrected with high accuracy, so that a high quality image can be obtained.

  Next, another embodiment of the image forming apparatus according to the present invention will be described. FIG. 22 shows a second embodiment of the image forming apparatus. This image forming apparatus uses a multi-beam scanning optical system that forms an image (electrostatic latent image) by irradiating light emitted from a plurality of light sources onto a photoconductor using a common scanning optical system.

  In FIG. 22, the semiconductor lasers 124 and 125 are laid out so that the optical axes of the collimator lenses 122 and 123 coincide with each other and have an emission angle symmetrical in the main scanning direction, and the emission axes intersect at the reflection point of the polygon mirror 104. ing. A plurality of beams emitted from the respective semiconductor lasers 124 and 125 are collectively scanned by the polygon mirror 104 via the cylinder lens 120 and imaged on the photoconductor 105 by the fθ lens 106, the mirror 110, and the toroidal lens 107. The Image data for one line is stored in the image processing unit 133 for each light source, read out for each surface of the polygon mirror, and written in two lines simultaneously.

  Further, a photodetector PD1 (reference numeral 108) and a photodetector PD2 (reference numeral 109) are arranged at both ends of the mirror 110, and the start and end of scanning are detected. That is, the laser beams emitted from the two light sources reflected by the polygon mirror 104 are sequentially incident on the PD1 before scanning the photosensitive member 105 for one line, and are incident on the PD2 after scanning. In each photodetector, the incident laser beam is converted into a first synchronization signal SPSYNC and a second synchronization signal EPSYNC, respectively, and input to the synchronization signal separation unit 126. Since the two light sources are arranged to scan the photosensitive member 105 with a time difference, the synchronization signal separation unit 126 similarly synchronizes the synchronization signal SPSYNC with the synchronization signals SPSYNCa and SPSYNCb corresponding to the respective light sources. The signal EPSYNC is separated into synchronization signals EPSYNCa and EPSYNCb corresponding to the respective light sources.

  FIG. 23 is an example of a timing chart of this synchronization signal. (a) is the first synchronization signal SPSYNC, and (b) is the second synchronization signal EPSYNC. Here, assuming that the laser beam of the semiconductor laser 125 is scanned first, the synchronization signal SPSYNC is separated into (c-1) SPSYNCa and (c-2) SPSYNCb. Similarly, the synchronization signal EPSYNC is separated as (d-1) EPSYNCa and (d-2) EPSYNCb.

  Returning to FIG. 22, one set of separated synchronization signals SPSYNCa and EPSYNCa is supplied to the pixel clock generation unit 127, and the other set of SPSYNCb and EPSYNCb is supplied to the pixel clock generation unit 130. The pixel clock generation unit 127 measures the scanning time Tlinea from the two synchronization signals SPSYNCa and EPSYNCa, and generates a pixel clock PCLKa having a frequency that is determined so that a predetermined number of clocks fall within the time interval. The image processing unit 133 generates image data a based on the pixel clock PCLKa. The modulation data generation unit 128 generates modulation data a from the input image data a on the basis of the pixel clock PCLKa, and drives the semiconductor laser 125 via the laser driving unit 129. Similarly, the pixel clock generation unit 130 generates a pixel clock PCLKb from the two synchronization signals SPSYNCb and EPSYNCb, and the image processing unit 133 generates the modulation data generation unit 131 from the image data b generated based on the pixel clock PCLKb. Modulation data b is generated, and the semiconductor laser 124 is driven via the laser driving unit 132.

  Here, the pixel clock generation units 127 and 130 perform the same function as the pixel clock generation unit 111 in FIG. 1, and the first and second embodiments of the pixel clock generation unit described above can be applied. Detailed configuration and operation description will be omitted. The description of the modulation data generation units 128 and 131 is also omitted.

  If the high-frequency clock generators 1 and 51 are configured to be used in common by the pixel clock generators 127 and 130, the circuit scale can be reduced and the current consumption can be reduced. Alternatively, the two edge detection units 2 and 3 (or 52 and 53) for detecting the synchronization signal may be detected by the pixel clock generation units 127 and 130 in common, and the detection signals may be separated.

  Furthermore, since some of the calculation processes of the filters 6 and 56 and the frequency calculation units 7 and 57 operate only once per line, they are shared and processed in time series for a plurality of pixel clock frequency calculations. You may make it do.

  According to this embodiment, (3) even if there is a scanning speed error for each light source, that is, the wavelengths of the two light sources are different, and the scanning speed fluctuates due to chromatic aberration of the scanning optical system. Even if the scanning speeds of the two beams are different (even if the scanning times Tlinea and Tlineb of the two beams in FIG. 23 vary independently), the frequencies of the pixel clocks PCLKa and PCLKb are made independent according to the respective scanning speed fluctuations. Therefore, the speed fluctuation can be corrected with high accuracy, and a high quality image can be formed.

  Further, the multi-beam scanning optical system is not provided with a plurality of semiconductor lasers, but there is also a multi-beam scanning optical system that scans a plurality of laser beams emitted from one semiconductor laser array using a common scanning optical system. The same applies to such an optical system. Although the multi-beam scanning optical system has various embodiments, the effects of the present invention can be applied regardless of the form of the scanning optical system, and thus detailed illustration and description thereof will be omitted.

(Third embodiment)
Furthermore, a third embodiment of the image forming apparatus according to the present invention will be described. The third embodiment of the image forming apparatus is a multicolor image forming apparatus having a plurality of photoconductors, and includes separate photoconductors corresponding to cyan, magenta, yellow, and black colors, and scanning optics. A system is also provided corresponding to each photoconductor, and an image (electrostatic latent image) corresponding to each color is formed on each photoconductor. A color image is formed by transferring an image of each color onto one image forming medium (for example, paper). This embodiment can be realized simply by providing four image forming apparatuses shown in FIG. Further, for the sake of miniaturization, a form in which a part of the scanning optical system is shared may be adopted. However, since each optical path is different, it may be considered that a plurality of different image forming apparatuses are provided. FIG. 24-1 is an example of the configuration (sub-scanning sectional view, only a part of the units are shown). Hereinafter, the third embodiment will be described with reference to FIGS. 24-1 and 24-2. I do.

  In FIGS. 24-1 and 24-2, the polygon mirror 151 has a two-stage configuration, rotates about a dotted line as an axis, and is commonly used in each scanning optical system. Laser light emitted from the semiconductor laser 161a is reflected at a point a of the polygon mirror 151 through a collimator lens and a cylinder lens (both not shown). Similarly, the laser beams emitted from the semiconductor lasers 161 b to d are reflected at points b to d of the polygon mirror 151. The laser beam reflected by the polygon mirror scans the photosensitive member 157 via the scanning lenses 152 and 154 and the folding mirrors 153, 155 and 156 (the beam scanning direction, ie, the main scanning direction is perpendicular to the drawing). Image (electrostatic latent image). Here, “a” to “d” at the end of the figure correspond to the semiconductor lasers “a” to “d”, and images corresponding to the respective colors of yellow, magenta, cyan, and black are formed. The color image formed on each of the photoconductors 157a to 157d is transferred to an image forming medium that is placed on the intermediate transfer belt 158 and moves in the direction of the arrow to form a color image.

  At this time, the beam is guided to the detector (photodetector) 171 by the mirrors 170 arranged on both sides outside the effective scanning range, and the start and end of scanning are detected and converted into synchronization signals SPSYNC and EPSYNC. These synchronization signals SPSYNC and EPSYNC are supplied to the pixel clock generator 164 in the same manner as described above, and generate a pixel clock PCLK whose frequency is controlled so as to correct the scanning speed error. The image processing unit 165 generates image data Pdata based on the pixel clock PCLK. The modulation data generation unit 163 generates modulation data from the input image data Pdata based on the pixel clock PCLK, and drives the semiconductor laser 161 via the laser driving unit 162. These are performed in the same manner for each color corresponding beam. The pixel clock generation unit 164 can apply the first embodiment and the second embodiment of the pixel clock generation unit described above. Here, the scanning time in each scanning optical system differs depending on the manufacturing accuracy and assembly accuracy of each component of the scanning optical system, deformation due to changes over time, etc., and two photodetectors that detect the start and end of scanning Since the distance between them varies depending on the assembling accuracy and the like, a reference value RefN as a reference for image clock frequency control is obtained in advance for each scanning optical system at the time of manufacture of the image forming apparatus or the like (image degradation is caused by a change over time, etc.). When they occur, they may be obtained again), and these are given to the pixel clock generator 164 as reference values RefN, respectively. In addition, since the scanning start detection position by the synchronization signal SPSYNC may be different for each scanning optical system, image writing is started after a predetermined time (after a predetermined cycle of the pixel clock PCLK) after the rising of the synchronization signal SPSYNC. This write start offset is obtained in advance for each scanning optical system (referred to as a write start offset).

  FIG. 25 is a diagram showing the relationship between the scanning width and the scanning time by each scanning optical system. (a-1) indicates the scanning width of one line of the scanning optical system a. SPa and EPa are positions where the positions of the detectors that detect the start and end of scanning are associated on the photosensitive member. Let this distance be La. Further, when the one-dot width of the image is Lp, La / Lp = RefNa is the number of dots in one line, and this is set as the reference value RefN. In addition, a range where an image is actually formed is an area between PSP and PEP. (A-2) indicates the scanning time of one line of the scanning optical system a. Synchronization signals SPSYNC and EPSYNC are detected corresponding to the scanning start position SP and end position EP, respectively, and this time interval is set as a scanning time Tla. Although the scanning time Tla varies depending on various factors as described above, the pixel clock cycle Tpa is controlled so that the relationship of Tpa = Tla / RefNa is established. Therefore, after a predetermined PCLK cycle from SPSYNC (N1 N2), the output write pulse always forms dots at the same position on the scanning line (D1 and D2). The actual image writing is started after the Mofsa cycle.

  Similarly, (b-1) indicates the scanning width of one line of the scanning optical system b, and when the distance between the scanning start position SPb and the end position EPb is Lb, Lb / Lp = RefNb is set as the reference value RefN. To do. (B-2) indicates the scanning time of one line of the scanning optical system b, and the time interval between the synchronization signals SPSYNC and EPSYNC is defined as a scanning time Tlb. Similarly, the pixel clock cycle Tpb is controlled so that the relationship of Tpb = Tlb / RefNb is established. Further, by setting the image writing start offset Nofsb in accordance with the distance difference between the two scanning start positions SPa and Spb, the range PSP to PEP in which the image is actually formed matches regardless of the scanning optical system.

  That is, according to this embodiment, even if a scanning speed error occurs due to various factors including a speed error for each scanning optical system, the frequency of the pixel clock PCLK is independently adjusted according to each scanning speed difference / variation. Therefore, the color image formed in this way does not cause color misregistration, does not cause deterioration in color reproducibility and resolution, and can obtain high quality image quality.

  As described above, according to the basic embodiment of the present invention, the scanning speed errors (1) to (4) shown in the above-described problem can be corrected with high accuracy. By making the following modifications to this basic embodiment, it is possible to correct the non-linearity error of the scanning speed with high accuracy. This embodiment will be described below with reference to the drawings.

  FIG. 26 is a block diagram showing a third embodiment of the pixel clock generator. This pixel clock generation unit 111 can be applied as each pixel clock generation unit of the image forming apparatus of FIGS.

  In FIG. 26, blocks denoted by the same reference numerals as those in FIG. The frequency calculation unit 201 calculates an appropriate pixel clock frequency according to the error data Err in the same manner as the frequency calculation unit 7 of FIG. 2, converts this into a pixel clock average frequency signal Mavg, and outputs it. The frequency modulation unit 202 generates a pixel clock frequency instruction signal Mnow for performing desired frequency modulation by converting the pixel clock average frequency signal Mavg according to the frequency modulation data FMdata supplied from the frequency modulation data generation unit 203. To the frequency divider 4. The frequency divider 4 divides the high-frequency clock VCLK according to the pixel clock frequency instruction signal Mnow to generate the pixel clock PCLK. Therefore, the frequency of the pixel clock PCLK can be modulated by modulating the pixel clock average frequency signal Mavg. The frequency modulation data generation unit 203 generates frequency modulation data FMdata corresponding to a scanning position (here, represented by the number of pixel clocks PCLK n) with the first synchronization signal SPSYNC as the origin. This frequency modulation data FMdata is the difference between the pixel clock frequency corresponding to the scanning speed V (n) at the scanning position n, here, M (n) represented by the divided value of the high frequency clock VCLK and the pixel clock average frequency signal Mavg. It is.

  FIG. 27 shows the scanning speed V (n) for the scanning position n (FIG. 27A), the deviation Δ (n) from the ideal position (FIG. 27B), and the frequency modulation data FMdata (n) (FIG. 27C). )) An example is shown. The deviation Δ from the ideal position is an integrated value of V (n) −Vavg. Since the non-linearity error of the scanning speed is mainly determined by the accuracy of the scanning optical system and the assembly error, the frequency modulation data FMdata may be acquired in advance, for example, when the apparatus is manufactured and stored. An example of the acquisition method of frequency modulation data is shown. First, scanning is performed at a constant pixel clock frequency, and a deviation Δ from the ideal position at each scanning position is measured. Since the differential value of the deviation Δ is the scanning speed V, it is converted into the pixel clock frequency from this, and the difference from the pixel clock average frequency signal Mavg is obtained. Briefly, the inclination between predetermined scanning positions (Δn in FIG. 27) is approximated to the scanning speed V ′, and a converted value from this value is used as frequency modulation data in this region (broken lines in FIG. 27). In this way, frequency modulation data can be easily obtained, and the same data can be used between the areas, so that the amount of memory for storing data can also be reduced. If the scanning speed correction is to be performed with higher accuracy, the region Δn may be shortened.

  For the frequency modulation data FMdata, the difference data ΔM of the frequency division ratio M can be obtained simply. Conversion to the pixel clock frequency instruction signal Mnow can be performed by adding the difference data ΔM to the pixel clock average frequency signal Mavg.

  Further, in order to perform the frequency modulation of the pixel clock with higher accuracy, the frequency modulation data may include not only the frequency division ratio M but also its decimal part. The processing of the decimal part may be performed in the same manner as described above. That is, the M value and C value in FIG. 5, or the M value and F value in FIG. When frequency modulation is divided into regions as described above, the processing is simple if the region length Δn is an integral multiple (1 or more) of Na (Na = 2 ^ a, a: number of decimals in binary notation). It is more suitable. In the following detailed description, the case where the frequency modulation data FMdata is handled by the integer part ΔM and the a-digit decimal part ΔF will be described.

  Next, details of each part of the pixel clock generation unit 111 according to the third embodiment will be described. The frequency calculation unit 201 applies the same configuration as in FIG. 8 (not shown). However, the counter 30, the conversion unit 31, and the addition unit 32 have the same function as the frequency modulation unit 202 described later, and thus are shared and deleted from the frequency calculation unit 201. Therefore, the selection unit 28 output M and the selection unit 29 output F are output as the pixel clock average frequency signal Mavg.

  FIG. 28 is a detailed configuration example of the frequency modulation unit 202. The frequency modulation unit 202 in FIG. 28 adds frequency data (M ′, F ′) obtained by adding the pixel clock average frequency signal Mavg (M, F) and the frequency modulation data FMdata (ΔM, ΔF) to the pixel clock frequency instruction signal Mnow. Convert. Here, ΔM is a positive / negative number, and ΔF is a positive number. The adder 211 adds F and ΔF to obtain F ′. At this time, if there is a carry, CO is output. Adder 210 adds M, ΔM, and carry signal CO to obtain M ′. The counter 212, the conversion unit 213, and the addition unit 214 perform the same functions as the counter 30, the conversion unit 31, and the addition unit 32 of FIG. 8, respectively, and convert M ′ and F ′ to the pixel clock frequency instruction signal Mnow. Since it is the same operation as described above, a detailed description is omitted.

  FIG. 29 is a detailed configuration example of the frequency modulation data generation unit 203. The frequency modulation data storage unit 220 is a memory that stores frequency modulation data FMdata corresponding to each area in the scanning line with each area number as an address, and outputs data corresponding to the supplied address signal. The data to be stored is obtained in advance as described above. This data may be stored in another storage unit in the apparatus and loaded when the apparatus is started up.

  The frequency modulation control unit 221 calculates an area number in the scanning line and generates an address signal. The address is cleared to 0 by the input of the synchronization signal SPSYNC, the pixel clock PCLK is counted, and the address signal is incremented every time the area length Δn is reached. A detection pulse SPpls may be input instead of the synchronization signal SPSYNC. Also, if the area length of each area is set in advance and the address is incremented each time the area length is reached, the area length can be changed according to the amount of frequency change, and the amount of storage memory can be reduced. Both reduction and improved frequency correction accuracy can be achieved.

  By the way, if the scanning speed or the pixel clock frequency is changed, the frequency modulation data needs to be changed in proportion. For example, when the pixel clock frequency is changed by changing the pixel clock frequency without changing the scanning speed (polygon rotation speed), the frequency modulation data obtained in advance may be changed in proportion to the magnification for changing. That is, for example, when the pixel clock frequency for calculating the frequency modulation data is halved and the pixel density is halved, the data obtained by halving the frequency modulation data at the time of calculation is the frequency modulation data storage unit. 220 may be stored.

  According to the third embodiment of the pixel clock generation unit 111, in addition to the effects of the first embodiment, it is possible to generate a high-accuracy pixel clock in which nonlinear errors are also corrected.

  Further, when this pixel clock generation unit 111 is applied to an image forming apparatus, an image is formed on the basis of a pixel clock in which a scanning speed error is corrected with high accuracy, so that a high quality image can be obtained.

  Also, if the nonlinearity error has periodicity for each scanning line, such as the scanning speed nonlinearity error is different for each surface of the polygon mirror, frequency modulation data corresponding to each surface is acquired in advance, and that surface is scanned during scanning. The frequency modulation data corresponding to the above may be used.

  FIG. 30 shows another embodiment of a frequency modulation data generation unit suitable for such a case. In FIG. 30, the frequency modulation control unit 221 calculates an area number in the scan line and generates an address signal, as in FIG. The frequency modulation data storage memories 223 (1) to 223 (Nf) store frequency modulation data FMdata corresponding to each area and each area in the scan line corresponding to each area when the number of polygon mirror faces is Nf. This is a memory for storing numbers as addresses, and outputs data corresponding to supplied address signals. Here, the memory corresponding to which surface is effectively selected is selected by a memory selection signal. The memory selection signal generation unit 222 converts the surface selection signal FNo output from the frequency calculation unit 201 into a memory selection signal and outputs it. Here, the surface selection signal FNo indicates a relative surface number, and the memory selection signal corresponds to an absolute surface number.

  An example of this association method is shown. When acquiring frequency modulation data, scanning is first performed at a fixed pixel clock frequency (without frequency control), and a deviation Δ from the ideal position at each scanning position is measured for each surface. Since the scanning speed is different, the output LErr of the comparison unit 5 is unique for each surface and takes different values. Usually, the absolute surface number of each surface can be specified from at least the permutation of the error LErr. Therefore, the error LErr for each surface is also stored in correspondence with the memory number storing the frequency modulation data calculated from the deviation Δ from the ideal position. Next, during normal operation, after the rotation of the polygon mirror is stabilized, scanning is performed at a constant pixel clock frequency (without frequency control), and the surface selection signal FNo and the error LErr are obtained in association with each other and measured. By matching the error LErr sequence with the stored error LErr sequence, the surface selection signal FNo and the memory number are associated with each other. Thereafter, a pixel clock frequency control operation may be performed. The accuracy can be improved by using the average of the error LErr for a plurality of lines.

  In this way, even when the non-linearity error of the scanning speed differs for each surface of the polygon mirror, the pixel clock frequency no correction corresponding to each non-linearity error can be performed, so that a more accurate pixel clock can be generated. .

(Fourth embodiment)
Next, another embodiment of the pixel clock generation unit will be described. FIG. 31 is a configuration diagram showing a fourth embodiment of the pixel clock generation unit. The pixel clock generation unit 118 can be applied as each pixel clock generation unit of the image forming apparatus shown in FIGS.

  In FIG. 31, blocks with the same reference numbers as those in FIG. The frequency calculation unit 231 calculates an appropriate pixel clock frequency according to the error data Err in the same manner as the frequency calculation unit 57 in FIG. 12, converts this into a pixel clock average frequency signal Mav, and outputs it. The frequency modulation unit 232 and the frequency modulation data generation unit 233 perform the same functions as those of the frequency modulation unit 202 and the frequency modulation data generation unit 203 of FIG. However, in this example, the scanning position (n) is counted by operating based on the clock GCLK instead of the pixel clock PCLK and counting the set pulse Set. Of course, the operation may be performed based on the pixel clock PCLK.

  According to the fourth embodiment of the pixel clock generation unit 118, in addition to the effects of the second embodiment, it is possible to generate a high-accuracy pixel clock in which nonlinear errors are also corrected.

  Further, when this pixel clock generation unit is applied to an image forming apparatus, an image is formed on the basis of a pixel clock in which a scanning speed error is corrected with high accuracy, so that a high quality image can be obtained.

  As described above, according to the basic embodiment of the present invention, the scanning speed errors (1) to (5) shown in the above-described problem can be corrected with high accuracy. By making the following modifications to this basic embodiment, it becomes possible to generate synchronization information corresponding to each synchronization signal detected by sharing a detection unit in a device that generates a plurality of pixel clocks. Thus, each pixel clock can be controlled with high accuracy.

(Fifth embodiment)
FIG. 32-1 is a configuration diagram illustrating a fifth embodiment of the pixel clock generation unit. In addition, an embodiment in which the image forming apparatus is configured in conjunction with FIG. This embodiment is a modification of the second embodiment (FIG. 12) of the pixel clock generation unit described above, and the blocks with the same reference numerals perform the same configuration, function, and operation, and thus are described in detail. The detailed explanation is omitted.

  In FIG. 32A, this pixel clock generation unit generates a plurality of n pixel clocks, and is configured by blocks described below.

  The high frequency clock generator 51 generates 16-phase multiphase clocks VCLK0 to 15 based on the reference clock RefCLK. Also, one of the multiphase clocks is divided by Q (here, Q = 4) to generate an internal operation clock GCLK. The first edge detection unit 402 detects, for example, the rising edge of the first synchronization signal SPSYNC indicating the scanning start position on the basis of the multiphase clocks VCLK0 to VCLK15. When the rising edge of the synchronization signal SPSYNC is detected, the first edge detection unit 402 detects the rising edge of the synchronization signal SPSYNC. Synchronized detection pulse SPpls, rising time period QT, and time information SPQP indicating phase PH are output. Similarly, the second edge detection unit 403 detects, for example, the rising edge of the second synchronization signal EPSYNC indicating the scanning end position with reference to the multiphase clocks VCLK0 to VCLK15, and detects the rising edge of the synchronization signal EPSYNC. The detection pulse EPpls synchronized with the clock GCLK, the period QT at the time of rising, and the time information EPQP indicating the phase PH are output. Note that these two synchronization signals are generated by a synchronization detection unit composed of, for example, a photodetector (PD), and a signal that becomes “H” is generated when a light beam passes through the synchronization detection unit. When the synchronization detection unit is shared by a plurality of beams, the synchronization signal becomes “H” a plurality of times during one scan, and the first edge detection unit 402 detects each rising edge and detects the detection pulse SPpls. And rise time information SPQP is output. The same applies to the second edge detector. When a plurality of synchronization detection units are provided and a plurality of synchronization signals are supplied corresponding to the synchronization detection units, rising edges are detected for the respective synchronization signals.

  The pixel clock generation unit 405 includes n (1) to (n), and generates pixel clocks PCLK [1] to [n], respectively. Detailed configuration will be described later. The modulation data generation unit 409 includes n pixels corresponding to the n pixel clock generation units 405, and each image is input with reference to the corresponding pixel clock PCLK (or the set pulse Set indicating the rising edge of PCLK). Modulated data WrPLS [1] to [n] that has been subjected to pulse width modulation according to the data is generated.

  FIG. 32-2 is a configuration example of an image forming apparatus suitable for the fifth embodiment of the pixel clock generation unit. This is one form of a multicolor image forming apparatus having a plurality of photoconductors, and separate photoconductors (417, 418, 419, and 420, respectively) corresponding to black, magenta, cyan, and yellow colors. And irradiating each photoconductor with two beams to form an image (electrostatic latent image). Then, each color image formed on each photoconductor is transferred to an image forming medium placed on the intermediate transfer belt 421 and moving in the direction of the arrow to form a color image. A total of eight light beams Beam1 to 8 that irradiate each photoconductor are supplied with modulated data WrPLS [1] to [8] output from the pixel clock generation device of FIG. The semiconductor lasers LD1 to 8 (reference numerals 411 (1) to (8)) are driven and emitted through (1) to (8)). The emitted beams Beam 1 to 8 are scanned through a scanning optical system 412 (the beam scanning direction is a direction perpendicular to the paper surface) and imaged on each photoconductor. In Beams 1 to 4, the mirrors are arranged at the scanning start point and the ending point so as to be incident on the photodetectors 413 and 414 that are the synchronization detection units arranged at the point a in the beam scanning direction. Detected. These photodetectors are used in common with the four beams Beam1 to Beam4, and output sync signals SPSYNCkm and EPSYNCkm that output a pulse each time each beam passes, and the first edge detector 402 and the second edge respectively. It supplies to the detection part 403. Similarly, in Beams 5 to 8, the light enters the photodetectors 415 and 416 which are synchronization detection units arranged at the point b in the beam scanning direction, the start and end of scanning are detected, and the synchronization signals SPSYNCcy and EPSYNCcy are output, respectively. It supplies to the 1st edge detection part 402 and the 2nd edge detection part 403. It is assumed that the scanning optical system 412 is arranged so that the four beam spots and the photodetector PD have a positional relationship as shown in FIG. 33, and sequentially passes through the PD from Beam 1 and outputs a detection pulse. At this time, the detection pulse time interval is determined by the scanning speed and the beam spot interval. Note that the arrangement in FIG. 32-2 is described for convenience of illustration and does not necessarily match the arrangement of the actual apparatus. Further, since the arrangement and details of the scanning optical system are not directly related to the gist of the present invention and the effects can be applied regardless of the form, illustration and description of the detailed configuration are omitted.

  Next, returning to FIG. 32A, the operation will be described based on FIG. 34 illustrating the detailed configuration of the pixel clock generation unit 405 and the waveform diagram of main signals.

  In FIG. 34, each signal waveform is a waveform of the same signal name in FIG. (b-1) SPSYNCkm indicates the scanning start point of Beams 1 to 4 output from the PD 413 (shows pulses corresponding to Beams 1, 2, 3, and 4 from the left). (b-2) EPSYNCkm indicates the scanning end point of Beams 1 to 4 output from PD 414 (here, only pulses corresponding to Beams 1 and 2 are shown). (c-1) SPpls_km is a detection pulse generated by the first edge detection unit 402 detecting the rising edge of (b-1) SPSYNCkm and synchronizing with the clock GCLK. SPQP_km indicating rise time information is not shown. Similarly, (c-2) EPpls_km is a detection pulse output by detecting the rising edge of (b-2) EPSYNCkm by the second edge detection unit 403.

  In order for a pulse to be output to the synchronization signal (SPSYNC, EPSYNC), it is necessary to light when each beam passes through the photodetector PD (reference numerals 413 to 416), and the synchronization detection lighting signal generation unit 408 A synchronization detection lighting signal for instructing lighting (hereinafter referred to as synchronization detection lighting) is generated. For each of the scan start synchronization and the scan end synchronization, and for each corresponding beam Beam [n], they are generated as bdgate [n] and bdegate [n], respectively. (d-1) bdgate [1] to (d-4) bdgate [4] are scanning detection synchronization detection signals (hereinafter referred to as tip synchronization detection lighting signals) corresponding to Beams 1 to 4, respectively. (g-1) bdegate [1] to (g-4) bdegate [4] ([3] and [4] are not shown), the synchronization detection lighting signals for detecting the scanning end synchronization corresponding to Beams 1 to 4, respectively. (Hereinafter, rear end synchronization detection lighting signal). These are supplied to the modulation data generation unit 409, and the modulation data WrPLS [1] to [n] are modulated so that the LD corresponding to the period of “H” is turned on. Since the synchronization detection lighting period is performed outside the normal effective image area, no effective image data is supplied at this time, and therefore modulation data is generated regardless of the image data. In addition, the synchronization detection lighting signals of the respective beams that share the same PD are generated so as not to be “H” at the same time for the reason described later.

  (e-1) SPpls [1] to (e-4) SPpls [4] separate and extract detection pulses corresponding to each beam from (c-1) SPpls_km, which are detection pulses of the first synchronization signal. (C-1) can be generated by taking the logical product of SPpls_km and the corresponding tip synchronization detection lighting signal bdgate [n]. Similarly, the corresponding time information SPQP [n] can be extracted from SPQP_km indicating the rise time information. These detection pulses SPpls [n] and time information SPQP [n] are used as first synchronization information and are generated by the first synchronization information generation unit 406. Further, since the time information SPQP [n] can be used as valid data only during the period when the detection pulse SPpls [n] is “H”, the corresponding time information is not extracted and the rise time information of each beam is used. May output SPQP_km obtained by polymerization. Also, all the tip synchronization detection signals corresponding to each beam are input (here [1] to [8]), and the tip synchronization detection lighting signal corresponding to the SPchSel signal is selected and used for extraction. . Details will be described later. Since the tip synchronization detection lighting signal bdgate is used for the separation and extraction of the detection pulse in this way, accurate separation cannot be performed if there is a signal that simultaneously becomes “H”, and therefore, it is generated so that it does not simultaneously become “H”.

  Similarly, in the second synchronization information generation unit 407, the detection pulse (c-2) EPpls_km generated by the second edge detection unit 403 is separated and extracted by the rear end synchronization detection lighting signal bdgate [n]. Detection pulse EPpls [n] and time information EPQP [n], which are two synchronization information, are generated. (h-1) EPpls [1] and (h-2) EPpls [2] are detection pulses of the second synchronization signal corresponding to Beams 1 and 2, respectively. As described above, the rear-end synchronization detection lighting signal bdgate [n] is generated so as not to simultaneously become “H” in each beam that shares and uses the same PD.

  Using the first and second synchronization information generated in this manner, the counting unit 54, the comparison unit 55, the filter 56, and the frequency calculation are performed in the same manner as in the second embodiment of the pixel clock frequency generation unit described above. The pixel clock PCLK [n] is generated by the unit 57 and the pixel clock output unit 58.

  Next, the operation of the synchronization detection lighting signal generation unit 408 will be described. The synchronization detection lighting signals bdgate [n] and bdegate [n] generated here are generated so as to be “H” before and after the predicted point so as to be surely lit when passing through the photodetector PD even if there is a variation in scanning speed. Even if the rise and fall times are not controlled with high accuracy, the detection time accuracy is not affected. Therefore, the generation may be performed based on the pixel clock instead of the multiphase clock VCLK. More specifically, when a PD is shared by a plurality of beams as in the present embodiment, one of them is determined as a master beam (the beam that is scanned most first is the master beam). (Beam1 is assumed here), and the rest is assumed to be a slave beam. Then, when the leading edge synchronization detection lighting signal rise by the master beam is used as a reference for the scanning line of the master / slave beam, the synchronization detection lighting signal is set to “H” after a predetermined time (bdfs [n] or bdeofs [n]). Good. As described above, since the measurement of the predetermined time is sufficient for each pixel clock, the first edge detection unit 402 also synchronizes the leading edge synchronization detection signal rising edge by the master beam with each pixel clock (may be synchronized with GCLK). A master reference pulse Mpls is generated. Further, the synchronization detection lighting signal bdgate [n] is only required to be separated by the detection pulse SPpls [n] separated for each beam, as long as the detection pulse SPpls from which the rise of the synchronization signal is detected can be separated. Similarly, bdegate [n] may be lowered by a detection pulse EPpls [n] separated for each beam.

  Further, the lighting signal bofs [n] of the tip synchronization detection lighting signal is set in advance as follows. The master beam lighting signal (bofs [1] here) is determined by one scanning line cycle. Here, it is preferable to set a value that is sufficiently shorter than the minimum value in consideration of fluctuations in one scanning line period due to fluctuations in scanning speed. Further, the slave beam lighting signal (bdfs [2] to [4] in FIG. 34) converts the beam spot interval between the master beam (Beam1) and the slave beam (any of Beams 2 to 4) into a scanning time difference. It is better to set it to be sufficiently shorter than this. The rear end synchronization detection lighting signal bdeofs [n] is determined according to the distance between the two synchronization signal detection PDs (reference numerals 413 and 414 or reference numerals 415 and 416). The master beam lighting signal (bdeofs [1] in this case) is set so that the distance between the PDs is converted into time according to the scanning speed and is sufficiently shorter than this.

  The slave beam lighting signals (bdeofs [2] to [4]) may be values obtained by adding the value of bdeofs [1] to the corresponding bdofs [n]. If there is a difference in scanning speed due to a difference in the wavelength of the beam, etc., the time may be converted according to the beam scanning speed of each of the above-mentioned distances between PDs, and set according to this.

  Further, the beam spot interval and the distance between the PDs are different due to an assembly error of the optical system at the time of manufacture or a change with time. The measurement of the beam spot interval is obtained, for example, every time two beams per scan line pass through the PD while scanning with the synchronous detection lighting signal of the two beams concerned set to “H” (lighted). It is obtained by acquiring two pieces of synchronization information and measuring the time interval (since the two pieces of synchronization information are obtained as information in units of GCLK and Tv, this time interval is easily obtained). The distance between the PDs is scanned, for example, with the leading and trailing end synchronization detection lighting signals “H” of the passing beam (lit) and the first and second synchronization information is acquired and the interval is measured. do it.

  By the way, in the multi-beam optical system, one using one semiconductor laser array LDA instead of a plurality of semiconductor lasers is also applied. For example, in FIG. 32-2, instead of LD1 and LD2, an LDA1 in which two LD elements are arranged in an array is used, and two beams emitted from the LDA1 are incident on the scanning optical system 412 as Beam1 and Beam2. In such a case, the distance between the LD elements of the LDA may be short, and it may be difficult to increase the distance between the beam spots that pass on the PD (the distance between Beam1 and Beam2 in FIG. 33). In such a case, it may be difficult to set the slave beam lighting signal bdofs [2] as described above so that the synchronization detection lighting signal does not simultaneously become “H”. In the case of such an optical system, the following is preferable.

  Usually, there is almost no wavelength difference between the LD elements of the semiconductor laser array LDA, and the optical path when passing through the scanning optical system is almost the same, so that the scanning speed and its fluctuation are almost the same. By utilizing this property, the synchronization information of the trailing beam of the LDA is not acquired, and the frequency control of the pixel clock is performed using the synchronization information of the preceding beam. FIG. 35 illustrates a signal waveform diagram in such a case. It is assumed that the LDs 3 and 4 are also composed of LDA. In other words, the following beam does not perform the sync detection lighting when passing through the PD (bdgate [2] and bdgate [4] remain “L”), so the synchronization signal SPSYNCkm has two pulses when passing through Beam1 and Beam3. Only detected. The preceding beam synchronization information SPpls [1], [3] is generated in the same manner as described above, but the following beam synchronization information SPpls [2], [4] outputs the preceding beam synchronization information. Then, the beam spot interval is converted into a dot unit (pixel clock unit) (for example, 2.75 dots), its integer part is SPdly [n] (= 2PCLK), and its decimal part is the pixel clock frequency instruction signal Mnow. Based on the value, the phase difference Tv of the multi-phase clock is converted into a value, and this is set as SPofs [n] (= 0.75 * Mnow). When generating the pixel clocks PCLK [2] and [4], the initial phase is delayed by SPofs [n], and the image data is delayed by SPdly [n] PCLK (the output start of the image data is delayed. It can be easily realized by adding to the image writing offset Nofs). Alternatively, the synchronization information SPpls [2] and SPQP [2] obtained by delaying the synchronization information SPpls [1] and SPQP [1] by SPofs [n] may be generated and used.

  At this time, the calculation of the pixel clock frequency instruction signal Mnow of the subsequent beam may be performed as follows. First, since it substantially matches the scanning speed of the preceding beam, the pixel clock frequency instruction signal Mnow generated by the pixel clock generating unit for the preceding beam is used. Second, since the second synchronization information indicating the end of scanning is similarly used for the preceding beam, an error of SPofs [n] occurs in the detected line scanning time Tline [n]. You may make it calculate in consideration of this error in a frequency calculating part. Simply, a value obtained by correcting the reference value RefN by SPofs [n] may be used.

  In this way, by applying an initial phase offset to the pixel clock of the subsequent beam according to the beam spot interval and controlling the frequency of the pixel clock as described above, high accuracy can be achieved even if synchronous control is performed based on other beams. Control is possible.

  FIG. 36 is a block diagram illustrating a detailed configuration of the first synchronization information generation unit 406. The detection selection unit 430 receives a plurality of sets of detection pulses SPpls and time information SPQP of the synchronization signal detected by the first edge detection unit (here, two systems of km and cy), and sets one set according to the detection signal selection signal DechSel. Select output. In this embodiment, the km sequence is selected when n = 1 to 4, and the cy sequence is selected when n = 5 to 8. By providing such a detection selection unit, even when the number and combination of the synchronization detection units PD are different from those of the present embodiment, it is possible to cope with this by simply changing the detection signal selection signal, so that versatility is expanded. For example, the number of synchronization detectors PD that detect a synchronization signal may be different between the first and second synchronization signals. That is, the first synchronization signal is four synchronization signals obtained by four PDs (Beam 1 and 2, 3 and 4, 5, and 6, and 7 and 8, respectively), and the second synchronization signal is two PDs. The two synchronization signals obtained may be used.

  The SPch selection unit 431 receives a plurality of tip synchronization detection lighting signals bdgate (eight here) and selectively outputs the tip synchronization detection lighting signal bdgate corresponding to the beam used as the first synchronization information according to the tip synchronization information selection signal SPchSel. Is done. In the former example, the own beam is selected, and in the latter LDA example, the preceding beam is selected as the own beam, and the subsequent beam is selected as the preceding beam. The AND circuit 433 calculates the logical product of the detection pulse output from the detection selection unit 430 and the tip synchronization detection lighting signal bdgate [sel] output from the SPch selection unit 431, and separates and extracts the necessary synchronization information pulse SPpls [n]. Is. The time information SPQP [n] is output corresponding to the synchronization information pulse SPpls [n]. The Mch selection unit 432 receives a plurality of tip synchronization detection lighting signals bdgate, and selectively outputs the tip synchronization detection lighting signal bdgate corresponding to the master beam in the beam sharing the synchronization detection unit PD according to the master beam selection signal MchSel. The AND circuit 434 calculates the logical product of the detection pulse output from the detection selection unit 430 and the output of the Mch selection unit 432, and generates a line reference position signal Mpls. By providing such a selection unit, it is possible to cope with various configurations of the image forming apparatus. Similarly, the second synchronization information generation unit may be configured.

  According to the fifth embodiment of the pixel clock generation unit that generates the plurality of pixel clocks, the detection unit that detects the first and second synchronization signals serving as the reference for the synchronization control of each pixel clock frequency is shared. Even when applied to a system that achieves downsizing and cost reduction, for example, an image forming apparatus, the necessary synchronization information is separated and extracted from a plurality of synchronization detection signals superimposed on the basis of this. Since the pixel clock frequency is controlled, it is possible to generate a pixel clock in which this error is corrected with high accuracy even if the above-described various scan average speed fluctuations occur.

  In addition, after converting the time information based on the high-frequency clocks VCLK0 to 15 generated with high accuracy in the edge detection units 402 and 403 in the first stage, processing such as separation and selection of synchronization information is performed based on the internal operation clock GCLK. Since this is performed, control can be performed while maintaining an accurate synchronization position without performing processing such as matching the propagation delays of the synchronization signals, so that the pixel clock frequency can be controlled with high accuracy.

  Further, as described above, since various selection units are provided, the system to be applied can correspond to not only the image forming apparatus of FIG.

  Further, although this embodiment has described the change of the pixel clock generation unit from the second embodiment, the above-described effects can be obtained by applying the same change to the embodiment of another pixel clock generation unit. Be able to.

  As described above, according to the present invention, the pixel clock is generated based on the high-frequency clock VCLK or the multiphase clocks VCLK0 to 15 generated with high precision, and the pixel clock frequency is controlled in accordance with the variation of the scanning time. Therefore, even if there is a change in the scanning average speed, it is possible to generate a pixel clock that can correct this error with high accuracy, and the pixel clock frequency is controlled corresponding to each surface of the polygon mirror. Even if there is a scanning speed error for each surface, a pixel clock that can be corrected with high accuracy can be generated. Furthermore, since the pixel clock frequency is modulated so as to correct the nonlinear error of the scanning speed, a more accurate pixel clock can be generated. In addition, since the pixel clock generation unit is applied to the image forming apparatus, an image can be formed on the basis of the pixel clock in which the scanning speed error is corrected with high accuracy, and a high quality image can be obtained.

  In addition to these effects, in the image forming apparatus that is equipped with a multi-beam optical system and multiple photoconductor / scanning optical systems and is compatible with multiple colors, it is possible to detect the synchronization signal of each beam in order to reduce the size and cost. Even when a common photodetection means is used, the necessary synchronization information is separated and extracted, and the pixel clock frequency is controlled based on this. A pixel clock in which errors are corrected with high accuracy can be generated.

  Further, after synchronizing the synchronization signal output from the light detection means into time information based on the high-frequency clock VCLK or multiphase clocks VCLK0 to 15 generated with high accuracy, the synchronization information is separated based on the internal operation clock GCLK. And processing such as selection, so even if processing such as matching the propagation delay of each synchronization signal is not performed, control can be performed while maintaining an accurate synchronization position, so high-precision pixel clock frequency control is possible. Yes.

  Furthermore, since the detection signal and separation / extraction signal can be selected, it can be easily handled by simply changing the selection signal in various forms of image forming apparatuses that differ in the number of light detection means and the combination of shared light sources. High versatility that can be obtained.

  As described above, the pixel clock generation apparatus and the image forming apparatus according to the present invention are useful for an apparatus that forms an image by scanning a laser beam, and are particularly suitable for a digital color copying machine, a color laser printer, and the like. .

It is explanatory drawing which shows the structural example (1) of the scanning optical system concerning embodiment of this invention. It is a block diagram which shows the internal structure (1) of the pixel clock generation part of FIG. It is a timing chart which shows the signal output operation | movement of a pixel clock generation part. It is a block diagram which shows the internal structure of a comparison part. It is a block diagram which shows the internal structure (1) of a frequency calculating part. It is a flowchart which shows operation | movement of a calculation control part. It is a graph which shows the mode of the drawing-in process by a clock frequency control method. It is a block diagram which shows the internal structure (2) of a frequency calculating part. It is a graph which shows the loop gain of a DPLL control system. It is a block diagram which shows the internal structure of a filter. It is a timing chart which shows operation | movement of a modulation data generation part. It is a block diagram which shows the internal structure (2) of a pixel clock generation part. It is a block diagram which shows the internal structure of a high frequency clock generation part. It is a timing chart which shows the output timing of each clock which a high frequency clock generation part produces | generates. It is a block diagram which shows the internal structure of a counting part. It is a block diagram which shows the internal structure of a pixel clock output part. It is a timing chart which shows the output timing of a pixel clock output part. It is a block diagram which shows the internal structure of a comparison part. It is a timing chart which shows the output timing of each signal of a comparison part. It is a block diagram which shows the internal structure of a modulation data generation part. It is a timing chart which shows the output timing of each signal of a modulation data generation part. It is explanatory drawing which shows the structural example (2) of the laser writing system concerning embodiment of this invention. It is a timing chart which shows the output timing of the synchronizing signal in FIG. It is explanatory drawing which shows the structure of the image forming apparatus which has a scanning optical system by the polygon mirror of 2 steps | paragraphs structure. It is a block diagram which shows the structure of the image forming apparatus of FIGS. 24-1. It is explanatory drawing which shows the relationship between the scanning width by each scanning optical system, and scanning time. It is a block diagram which shows the internal structure (3) of a pixel clock generation part. It is a graph which shows an example of scanning speed V (n) with respect to scanning position n, deviation (n) from ideal position, and frequency modulation data FMdata (n). It is a block diagram which shows the internal structure of a frequency modulation part. It is a block diagram which shows the internal structure (1) of a frequency modulation data generation part. It is a block diagram which shows the internal structure (2) of a frequency modulation data generation part. It is a block diagram which shows the internal structure (4) of a pixel clock generation part. It is a block diagram which shows the internal structure (5) of a pixel clock generation part. It is explanatory drawing which shows the structure of the image forming apparatus which has an internal clock generation part of FIG. It is explanatory drawing which shows the positional relationship of four beam spots and the photodetector PD in a scanning optical system. It is a timing chart which shows the output timing of the main signal of a pixel clock generation part. It is a flowchart which shows the output timing of the signal which performs the frequency control of a pixel clock using the synchronization information of a preceding beam, without acquiring the synchronization information of the following beam of LDA. It is a block diagram which shows the internal structure of a 1st synchronous information generation part. It is a block diagram which shows the structure of the conventional scanning optical system. It is a graph which shows an example of the nonlinear error of the scanning speed in 1 line in the conventional scanning optical system.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 High frequency clock generation part 2 1st edge detection part 3 2nd edge detection part 4 Frequency divider 5 Comparison part 6 Filter 7 Frequency calculation part 51 High frequency clock generation part 54 Counting part 55 Comparison part 58 Pixel clock output part 111 Pixel clock generation Unit 112 image processing unit 113 modulation data generation unit 114 laser drive unit 118 pixel clock generation unit 119 modulation data generation unit 202 frequency modulation unit 203 frequency modulation data generation unit 406 first synchronization information generation unit

Claims (14)

High-frequency clock generation means for generating a high-frequency clock, and comparison means for detecting the time interval between the input first and second synchronization signals, comparing the detected time interval with a target value, and outputting the error. The frequency calculation means for calculating a set value of the pixel clock frequency according to the error output from the comparison means, and outputting a frequency specifying signal for specifying the pixel clock frequency according to the calculated set value, and the frequency calculation means, In a pixel clock generation device comprising a plurality of pixel clock generation means, the frequency division means for dividing the high-frequency clock by a division ratio based on a frequency designation signal to be output to generate a pixel clock,
Some of the plurality of first or second synchronization signals to be input to the pixel clock generation means are mixed signals,
Edge detection means for sampling the mixed synchronization signal with the high-frequency clock and detecting synchronization information indicating a rising or falling edge time of the synchronization signal;
Synchronization information separation means for separating and extracting corresponding synchronization information from the synchronization information output by the edge detection means;
With
2. A pixel clock generation device, wherein a time interval between the first and second synchronization signals is calculated from an output of the synchronization information separation means. Detects and detects the time interval between the multiphase clock generation means for generating the multiphase clock having the number of phases P, the phases of which are shifted from each other by the phase difference T / P in the period T, and the input first and second synchronization signals. A comparison unit that compares the time interval and the target value, and outputs an error thereof; a set value of the pixel clock frequency is calculated according to the error output from the comparison unit; and the pixel clock is calculated according to the calculated set value Frequency calculation means for outputting a frequency designation signal for designating a frequency, and a phase difference T / P of the multiphase clock as a unit time, and counting according to the frequency designation signal makes it possible to determine the rise time and fall time of the pixel clock. Based on the counting means for calculating and the multi-phase clock, the pixel clock is determined according to the rise time and fall time of the pixel clock. In the pixel clock generating device having a plurality of pixel clock generating unit having a pixel clock output unit that formed,
Some of the plurality of first or second synchronization signals to be input to the pixel clock generation means are mixed signals,
Edge detection means for sampling the mixed synchronization signal with the multiphase clock and detecting synchronization information indicating a rising or falling edge time of the synchronization signal with a phase difference T / P of the multiphase clock as a unit time When,
Synchronization information separation means for separating and extracting corresponding synchronization information from the synchronization information output by the edge detection means;
With
2. A pixel clock generation device, wherein a time interval between the first and second synchronization signals is calculated from an output of the synchronization information separation means. The plurality of pixel clock generation means each include synchronization detection signal generation means for generating first and second synchronization detection signals for instructing detection of the first and second synchronization signals, respectively.
2. The synchronization information separating unit is configured to separate and extract corresponding synchronization information from the synchronization information output from the edge detection unit in accordance with the corresponding first or second synchronization detection signal. Or the pixel clock generation device according to 2; The synchronization information separation means outputs one of the synchronization information output by the edge detection means as line reference information;
Each of the synchronization detection signal generation means generates the first or second synchronization detection signal according to a predetermined time difference between the line reference information obtained in advance and the corresponding synchronization information. The pixel clock generation device according to claim 3. A pixel clock generated by at least one pixel clock generation unit is defined as a leading reference, and the synchronization detection signal generation unit included in the pixel clock generation unit generates the first and second synchronization detection signals. ,
In the other pixel clock generation means, the synchronization information separation means generates synchronization information obtained corresponding to the first and second synchronization detection signals of the preceding reference from the synchronization information output from the edge detection means. 4. The pixel clock generation apparatus according to claim 3, wherein the pixel clock is generated with a constant initial phase offset.   In the other pixel clock generation means, the comparison means performs comparison using a value obtained by adding the initial phase offset to the detected time interval or a value obtained by subtracting the initial phase offset from the target value. 6. The pixel clock generation apparatus according to claim 5, wherein A plurality of the edge detection means;
The synchronization information separation means includes detection selection means for selecting one of the plurality of synchronization information output from the edge detection means and including corresponding synchronization information, and separates the corresponding synchronization information from the output of the detection selection means The pixel clock generation device according to claim 1, wherein the pixel clock generation device is extracted.   The synchronization information separating unit selects one of the first or second synchronization detection signals output from the plurality of pixel clock generation units, the synchronization detection signal selection unit, and the edge detection 8. The pixel clock generation apparatus according to claim 3, further comprising: logical product means for separating and extracting corresponding synchronous information from logical product with the synchronous information output by the means. High-frequency clock generation means for generating a high-frequency clock, and comparison means for detecting the time interval between the input first and second synchronization signals, comparing the detected time interval with a target value, and outputting the error. The frequency calculation means for calculating a set value of the pixel clock frequency according to the error output from the comparison means, and outputting a frequency specifying signal for specifying the pixel clock frequency according to the calculated set value, and the frequency calculation means, A plurality of pixel clock generators, and a plurality of pixel clock generators, each of which generates a pixel clock by dividing the high-frequency clock by a division ratio based on a frequency designation signal to be output; And driving a plurality of light sources with respective pulse modulation signals modulated in accordance with image data based on the An image forming apparatus for forming an image by scanning on a scanned medium the light flux,
Two light detection means are provided on the scanning line of the light beam, and some of the light beams of the plurality of light sources scan the two light detection means,
Edge detection means for detecting the synchronization information indicating the rising or falling edge time of the synchronization signal by sampling the synchronization signal that is the output of the two light detection means by the high frequency clock, respectively;
Synchronization information separation means for separating and extracting corresponding synchronization information from the synchronization information output by the edge detection means;
With
An image forming apparatus, wherein a time interval between the first and second synchronization signals is calculated from an output of the synchronization information separating means. Detects and detects the time interval between the multiphase clock generation means for generating the multiphase clock having the number of phases P, the phases of which are shifted from each other by the phase difference T / P in the period T, and the input first and second synchronization signals. A comparison unit that compares the time interval and the target value, and outputs an error thereof; a set value of the pixel clock frequency is calculated according to the error output from the comparison unit; and the pixel clock is calculated according to the calculated set value Frequency calculation means for outputting a frequency designation signal for designating a frequency, and a phase difference T / P of the multiphase clock as a unit time, and counting according to the frequency designation signal makes it possible to determine the rise time and fall time of the pixel clock. Based on the counting means for calculating and the multi-phase clock, the pixel clock is determined according to the rise time and fall time of the pixel clock. And a plurality of pixel clock generation means having a plurality of pixel clock generation means, and a plurality of light sources driven by respective pulse modulation signals modulated in accordance with image data based on the plurality of pixel clocks. In the image forming apparatus for forming an image by scanning light beams output from the plurality of light sources onto a scanned medium,
Two light detection means are provided on the scanning line of the light beam, and some of the light beams of the plurality of light sources scan the two light detection means,
Synchronization information indicating the rising or falling edge time of the synchronization signal obtained by sampling the synchronization signal, which is the output of the two photodetecting means, with the multiphase clock and using the phase difference T / P of the multiphase clock as a unit time Edge detecting means for detecting
Synchronization information separation means for separating and extracting corresponding synchronization information from the synchronization information output by the edge detection means;
With
An image forming apparatus, wherein a time interval between the first and second synchronization signals is calculated from an output of the synchronization information separating means. The plurality of pixel clock generation means respectively generate synchronization detection signal generation means for generating first and second synchronization detection signals for instructing to light up when the light flux of the corresponding light source passes through the two light detection means. Prepared,
10. The synchronization information separating unit separates and extracts corresponding synchronization information from the synchronization information output from the edge detection unit according to the corresponding first or second synchronization detection signal. Or the image forming apparatus according to 10. At least one of the light beams passing through the two light detection means is defined as a master beam, and the synchronization information separation means outputs the synchronization information by the master beam among the synchronization information output from the edge detection means as line reference information. To do,
Each of the synchronization detection signal generation means generates the first or second synchronization detection signal according to an interval between a master beam obtained in advance and a light beam of a corresponding light source. Item 12. The image forming apparatus according to Item 11. The plurality of light sources are each element of the semiconductor laser array,
Generating a first and a second preceding synchronization detection signal for instructing to turn on a light beam output from one of the two light detection means,
In the other pixel clock generation means corresponding to the semiconductor laser array element, the synchronization information separation means is obtained corresponding to the first and second preceding synchronization detection signals from the synchronization information output from the edge detection means. 12. The image forming apparatus according to claim 11, wherein the synchronization information is generated, and the pixel clock is generated with a constant initial phase offset.   In the pixel clock generation means corresponding to the other semiconductor laser array elements, the comparison means subtracts the initial phase offset from the value obtained by adding the initial phase offset to the detected time interval or the target value. The image forming apparatus according to claim 13, wherein the comparison is performed using a value.

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