JP2008141642A - Image processor, imaging apparatus, image recording/reproducing device, and activation control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make an image processor and an imaging apparatus adaptable to a plurality of image formats and reduced in power consumption. <P>SOLUTION: To a signal processing circuit configured as an FPGA circuit, a flash memory is connected which stores a plurality of configuration data items for constructing, in the signal processing circuit, circuits respectively individually corresponding to processes of a plurality of image formats. When a camcoder is powered on (step S5), a system CPU is first activated (step S6), blocks in the image processor are then initiated (step S7), configuration data corresponding to an image format that was set in the last end are selected (step S8), and loaded from the flash memory to a corresponding signal processing circuit, and a logic circuit specialized for processing of that image format is constructed (step S9). <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an image processing apparatus, an imaging apparatus, an image recording / reproducing apparatus, and an activation control method suitable for a camcorder that processes video signals in a plurality of operation formats.

  In recent years, digital signal processing has been increasingly used in video signal processing, and signal processing circuits used in image processing apparatuses such as video cameras have been digitized. In a video camera, if the signal processing circuit used in it is digitized, for example, it is possible to change the number of pixels and aspect ratio of the frame image at the camera head, and when there is one camera, it is a movie shooting format. At other times, it can be used in the ENG (Electronic News Gathering) format for news coverage.

  In the conventional video camera, in order to cope with switching of the operation format, a plurality of digital video signal processing circuits must be provided, and there is a problem that the circuit scale and the apparatus scale become enormous.

  On the other hand, in recent video cameras, an FPGA (Field Programmable Gate Array) circuit in which a logic circuit configuration can be arbitrarily changed is incorporated so that various specifications can be easily changed. It was. The FPGA circuit is composed of a large number of logic circuit cells, a switching transistor for arbitrarily switching and wiring each cell, and a memory for storing the wiring state. The FPGA circuit is stored in an external ROM (Read Only Memory) or the like. By loading the configured data (hereinafter referred to as configuration data), various signal processing circuits can be constructed.

  As described above, in a video camera, various digital video signals can be processed by a single unit if the internal video signal processing circuit is switched to process different image formats according to the purpose of use. . When an FPGA circuit is used, a circuit function corresponding to processing in all image formats is built in advance for the FPGA circuit constituting each signal processing circuit in the video camera, and which image format is selected. However, the necessary circuit area in the FPGA circuit is configured to operate by switching the switch circuit in the camera accordingly.

As a conventional device using an FPGA circuit, there is a computer device that loads circuit data to be written to an FPGA board together with an application program so that the FPGA board can be used as a dedicated logic circuit in the application program ( For example, see Patent Document 1).
Japanese Patent Laid-Open No. 5-150943 (paragraph numbers [0015] to [0016], FIG. 3)

  By the way, the memory that configures the FPGA circuit is SRAM (Static Random Access Memory), etc. When the device power is turned off, all written data is erased, so it is always necessary to construct a circuit with configuration data at startup and restart. It is. However, when an FPGA circuit is provided in a video camera, if the FPGA circuit is constructed to accommodate any image format, current flows in the circuit part that is not actually used in the video camera, and program switching is performed. The switch consumes current, and the power consumption increases and the power consumption increases. For this reason, battery-powered video cameras have had problems such as shortening the continuous shooting time.

  Also, as the image formats that can be processed by video cameras become diversified, it takes longer time to download all the configuration data to the FPGA circuit at startup such as when the power is turned on, or the amount of configuration data increases and the program capacity is insufficient. There was also a risk of doing so.

  The present invention has been made in view of the above points, and is an image processing apparatus, an imaging apparatus, an image recording / reproducing apparatus, and an image processing apparatus that are compatible with a plurality of image formats and have reduced power consumption. An object is to provide a control method.

  In the present invention, in order to solve the above problem, in an image processing apparatus for processing an image signal, a programmable logic circuit serving as a circuit for processing a digital image signal, and processing of a plurality of image formats in the programmable logic circuit A data storage unit storing configuration data for constructing a circuit individually corresponding to each of the configuration data, and the program can be selected by selecting any one of the configuration data at the start timing of the image processing apparatus There is provided an image processing apparatus characterized by including an activation control unit for instructing a logic circuit to construct a circuit corresponding to any one of the image formats.

  In such an image processing apparatus, configuration data individually corresponding to processing of a plurality of image formats is stored in a data storage unit, and one of these configuration data is loaded into a programmable logic circuit. Thus, the logic circuit is constructed as a circuit specialized for processing a digital image signal having a corresponding image format. Then, the activation control unit selects one of the configuration data in the data storage unit at the timing of activation of the image processing device, loads the configuration data into a programmable logic circuit, and performs signal processing corresponding to a specific image format. Control to build a circuit.

  According to the present invention, a programmable logic circuit can be used to handle a plurality of image format processes, and when the image processing apparatus is started, a circuit specialized for a certain image format process is provided. Since the logic circuit is constructed, a circuit that is not necessary for the processing of the image format is not constructed and operated, and the power consumption of the logic circuit can be suppressed.

  Hereinafter, as an image processing apparatus of the present invention, a camcorder in which an imaging unit and a recording unit are integrated will be described with reference to the drawings. Here, as an example, a recording means using a magnetic tape is provided.

FIG. 1 is a block diagram showing the main configuration of the camcorder.
In a camcorder in which a camera and a VTR (Video Tape Recorder) are integrated, a camera signal processing unit A1 is configured by a camera head block (CHB) 1, an A / D conversion circuit (AD) 2, and a digital camera processor (DCP) 3. The video processor (VPR) 4, the equalizer / ECC (Error Correcting Code) circuit (EQ / ECC) 5, and the drum head 6 constitute a recording / reproducing unit A 2 for the recording tape 7.

  The camera head block (CHB) 1 of the camera signal processing unit A1 includes a CCD (Charge Coupled Devices) and optical system parts, and converts an image formed into an electric video signal to generate an A / D conversion circuit. (AD) 2 is output. In the camera head block (CHB) 1, the frame frequency of the video signal to be output may be variable.

  The A / D conversion circuit (AD) 2 converts the analog video signal from the camera head block (CHB) 1 into a digital signal, and the states of the three primary color signals of R (red), G (green), and B (blue) To the digital camera processor (DCP) 3. In this A / D conversion circuit (AD) 2, the number of quantization bits at the time of conversion may be variable.

  The digital camera processor (DCP) 3 performs correction and compensation on the video signal so as to process the digital video signal in a format that conforms to a predetermined standard. Here, a 10-bit or 12-bit digital video signal (LVDS: Low Voltage Differential Signaling) from the A / D conversion circuit (AD) 2 is input, and this signal is converted into a serial frame-converted image signal (S-LVDS). ) Is output to the video processor (VPR) 4 of the recording / reproducing unit A2.

  The video processor (VPR) 4 of the recording / reproducing unit A2 uses the memories PR and MY to perform encoding (compression) processing and decoding according to the MPEG (Moving Picture Experts Group) system including image motion compensation processing ( Expansion) processing. The equalizer / ECC circuit (EQ / ECC) 5 is a filter circuit that performs characteristic compensation by performing adaptive equalization processing on the recording / reproducing signal, an error correction processing circuit, a control circuit for controlling the rotation of the drum head 6, and the like. Consists of

  The camera control unit A3 that controls the camera signal processing unit A1 includes a camera controller (AT) 8 and a video D / A conversion circuit (VDA) 9. The camera controller (AT) 8 performs lens focus and zoom control in the camera head block (CHB) 1, image quality control, exposure control, white balance control and the like in the digital camera processor (DCP) 3. The video D / A conversion circuit (VDA) 9 receives an image signal processed by the digital camera processor (DCP) 3 and outputs a video signal for displaying a monitor video on a viewfinder or the like.

  Camera adapters (CA1, CA2) 9a and 9b for audio input and the like are connected to the video D / A conversion circuit (VDA) 9 via connectors CN1 and CN2 for connecting external devices, respectively. Various terminal devices and the like are connected to the camera controller (AT) 8 via an internal panel 8a.

  The system controller A4 on the VTR side is remotely connected via a system controller (SA) 10, a servo controller (SV) 11, a sensor circuit 12, a mechanical deck 13, a connector panel 14, and a Bluetooth (registered trademark) terminal (BT) 15a. It comprises a control panel 15 to be operated, a main power supply (PS) 16, and the like. The main power supply (PS) 16 is provided with a power switch (not shown), and supplies power to each block via regulators 17a and 17b composed of a plurality of DC / DC converters. Further, the power supply of each block can be performed by operating the power switch of the control panel 15.

  Here, a main power supply (PS) 16 is connected to the system controller (SA) 10 via a regulator 17a and is supplied with power. The system controller (SA) 10 receives signals from various switches via the connector panel 14 and controls the video processor (VPR) 4. Furthermore, the camera side is controlled via a camera controller (AT) 8. The servo controller (SV) 11 includes a plurality of motor drivers, and controls the running of the recording tape 7 by the mechanical deck 13.

Next, a detailed configuration of each block constituting the camcorder will be described.
FIG. 2 is a block diagram showing a detailed configuration of the digital camera processor 3.
The digital camera processor 3 includes a preprocessor (PRE) 31, a camera processor 32, signal processing circuits 33 to 35, and the like. The preprocessor 31 is a signal processing circuit for receiving a digital video signal. The camera processor 32 performs various camera process processing such as nonlinear processing such as γ correction, contour enhancement, and color correction on the video signal input from the A / D conversion circuit 2 based on the data stored in the RAM 32a. This image signal is converted into a signal of a predetermined color space format. Here, as an example, it is assumed that a so-called 4: 2: 2 mode YC (luminance / color difference) signal and an RGB signal called 4: 4: 4 mode can be output. The signal processing circuit 33 converts the recording video signal into serial data and outputs it, and converts the playback video signal into parallel data. In addition, the signal processing circuit 34 is a circuit that selects either reproduction video or camera video and generates additional information such as characters, and the signal processing circuit 35 outputs a video signal for reproduction to the camera control unit A3. It is a circuit for converting into a signal.

  Among these, the preprocessor 31 and the signal processing circuits 33 and 35 use an FPGA circuit having a configuration described later, and a flash memory (CF: Config) is used as a storage circuit for storing configuration data corresponding to each FPGA circuit. Flash) 31a, 33a and 35a are connected to each other. The camera processor 32 is connected to a RAM 32a as an external memory.

FIG. 3 is a block diagram showing a detailed configuration of the video processor 4.
The video processor 4 includes a signal processing circuit 41 for exchanging signals in the circuit, a compression circuit 42 for compressing and encoding a digital video signal sent from the camera side, and a reproduced video signal reproduced from the recording tape 7 Decoding circuit 43 for decoding, RAMs 42a and 43a connected to compression circuit 42 and expansion circuit 43, and parallel serial (P / S) for serially converting the compressed signal output to equalizer / ECC circuit (EQ / ECC) 5 ) Circuit 44, and a serial / parallel (S / P) circuit 45 for converting the reproduced video signal sent as a serial signal from the equalizer / ECC circuit (EQ / ECC) 5 into a parallel signal. The compression circuit 42 is connected to a prediction circuit 4 a that stores adjacent frames at the time of compression, and the signal processing circuit 41 is connected to a memory circuit 4 b for a transmission buffer. Among these, the signal processing circuit 41 uses an FPGA circuit having a configuration which will be described later, and a flash memory 41a is connected as a storage circuit for storing corresponding configuration data.

FIG. 4 is a block diagram showing detailed configurations of the camera controller 8 and the video D / A conversion circuit 9.
The camera controller 8 includes a camera CPU (Central Processing Unit) 81, and the video D / A conversion circuit 9 includes a signal processing circuit 91 for converting and outputting video and audio signals.

  The camera controller 8 includes a cooling fan 82, a lens signal input terminal 83, a remote signal terminal 84, a meta input terminal 85, a memory slot 86, a menu enter terminal 81a, a menu switch 81b, a liquid crystal display via an internal panel 8a. A monitor (LCD: Liquid Crystal Display) terminal 81c, an assignable button 81d, a VTR start / stop button 81e, and the like are connected, and control signals and the like exchanged between these terminals and devices are controlled by the camera CPU 81.

  The video D / A conversion circuit 9 receives two signal output terminals VF1 and VF2 to the viewfinder, an output terminal 92 for a video synchronization (Y / SYNC / VBS) signal, and an HD-SDI (High Definition-Serial Digital Interface) signal. The terminal 93 for taking out and outputting to a monitor, RS232C terminal 94, etc. are provided. The D / A conversion signal processing circuit 91 uses an FPGA circuit having a configuration described later, and a flash memory 91a is connected as a storage circuit for storing corresponding configuration data.

FIG. 5 is a block diagram showing a detailed configuration of the system controller 10.
The system controller 10 includes a system CPU 100 for controlling the entire VTR system, an audio converter 101 that converts digital audio and analog audio, and a signal processing circuit 102 that generates a time code and timing signal for video editing. It is configured. The system controller 10 includes a cooling fan 103, a display LED (Light Emitting Diode) 104, a cassette eject button 105, a USB (Universal Serial Bus) terminal 14a, an audio input terminal 14b, an audio via a connector panel 14. A volume 14c, an audio output terminal 14d, and time code (TC) input / output terminals 14e and 14f are connected.

  Here, the system CPU 100 exchanges a control signal such as a Cam-VTR protocol with the camera controller 8 and sends an audio output control signal to the signal processing circuit 91 of the video D / A conversion circuit (VDA) 9. Communicating. The signal processing circuit 102 uses an FPGA circuit having a configuration described later, and a flash memory 102a is connected as a storage circuit for storing corresponding configuration data.

Next, a configuration data loading procedure for each FPGA circuit provided in the camcorder will be described.
FIG. 6 is a flowchart showing a camcorder termination and activation procedure.

  In step S1, the system CPU 100 determines whether or not an instruction to turn off the camcorder is given. This step S1 is repeatedly executed until the power-off is instructed. When power off is instructed, the process proceeds to step S2.

  In step S2, the system CPU 100 determines whether or not an instruction to change the next image format has been issued. If there is an instruction to change the format, the process proceeds to step S3, and if there is no instruction, the process proceeds to step S4.

  In step S <b> 3, the system CPU 100 stores identification information indicating a new image format in a non-illustrated non-volatile memory connected to the system CPU 100. If no change of the image format is instructed in step S2, identification information indicating the image format being processed at that time is stored in the nonvolatile memory.

In step S4, the system CPU 100 executes termination processing for each part of the camcorder, and the camcorder is turned off.
In step S5, the camcorder is powered on by the camcorder power switch. As a result, in step S6, the system CPU 100, which is the startup main CPU, starts up.

  When the activation process of the system CPU 100 is completed, in the subsequent step S7, a process of starting up each block of the camcorder is executed in accordance with a command from the system CPU 100. At the same time, in step S8, configuration data to be read from the flash memory connected to each FPGA circuit is selected. Specifically, the system CPU 100 outputs a selection signal to each flash memory in accordance with the image format identification information stored in the nonvolatile memory, and the control circuit of each flash memory selects from the system CPU 100. The configuration data corresponding to the designated image format is read from the read address corresponding to the signal. Next, in step S9, the configuration data read from the flash memory is supplied to the corresponding FPGA circuit, and circuit construction corresponding to a predetermined image format is started.

  In this example, the procedure for ending and starting the camcorder when the camcorder ends and the power is turned on has been described. However, even when the camcorder is restarted, the selection is made based on the image format identification information stored in the nonvolatile memory. Only the set configuration data can be supplied to the FPGA circuit. For example, when an image format change is instructed from the control panel 15 or the like during processing in a certain image format, the system is reset, and the power-off and power-on processing as shown in FIG. 6 is automatically performed. It may be executed.

  In the above description, an example in which image signals of two types of image formats (4: 2: 2 mode, 4: 4: 4 mode) having different color space formats can be processed has been shown. In addition to color space format differences, image formats with different bit assignments between color components or between color components and luminance components (pixel format), frame frequency, quantization bit number, or a combination of these It is also possible to support many image formats. In such a case, basically, configuration data is separately prepared for each image format and stored in the flash memory, and any one configuration data is selected according to the control from the system CPU 100, and the corresponding data is handled. Supplied to the FPGA circuit. Also, when considering a plurality of FPGA circuits provided in the entire camcorder, even when different image formats are specified and started or restarted, the same configuration data is loaded if, for example, the above frame frequency is the same. There may be an FPGA circuit to be used.

  According to the above processing, at the time of starting up the camcorder, only necessary configuration data can be downloaded to each FPGA circuit in a short time. In addition, since the signal processing circuits in the camera signal processing unit A1, the recording / reproducing unit A2, the camera control unit A3, and the system control unit A4 are each configured by an FPGA circuit corresponding to a predetermined image format, the camcorder It becomes easy to cope with the mode change.

  In addition, since only the circuit functions necessary for the FPGA circuit are constructed, unnecessary circuit current in the signal processing circuit can be reduced. When the camcorder needs only a function corresponding to the 4: 2: 2 format, for example, an FPGA circuit not having a functional part corresponding to the 4: 4: 4 format is configured. Current consumption in the switching portion for selecting a circuit portion necessary for image format processing is eliminated. Therefore, current consumption in the FPGA circuit can be suppressed, and power saving of a camcorder or the like can be achieved.

  Furthermore, in the case where the image data of a plurality of image formats having different color space formats, pixel formats, frame frequencies, quantization bit numbers, etc. can be processed, in a portion not constituted by the FPGA circuit in the camcorder. The necessary circuits are provided to support all of these image formats, but by constructing only the circuit functions necessary for the specific image format in the FPGA circuit, It becomes possible to completely stop the operation of the circuit area that is not required in the image format. For example, when an image format with a relatively small processing band for image signals is selected, an unnecessary signal line is set to a high impedance state, for example, so that no image signal or control signal flows through the signal line. It becomes possible to stop the clock supply and power supply to the circuit block not to be performed. Therefore, unnecessary circuit current in the camcorder can be further reduced and power consumption can be suppressed. In particular, such a power saving effect is increased in a camcorder that can support a large number of image formats corresponding to combinations of a color space format, a pixel format, a frame frequency, the number of quantization bits, and the like.

Next, another example of the starting procedure in the above camcorder will be given. Here, the signal processing circuit 102 of the system controller 10 described above will be described as an example.
FIG. 7 is a diagram illustrating an example of a program control device of the FPGA circuit.

  The control panel 15 of the camcorder is provided with a power switch and the like, and when the power is turned on to the camcorder, the system CPU 100 is first activated as described above. The mode switching circuit 110 includes a non-volatile (NV) memory 111 and a switch circuit 112, and the flash memory 102a and the system CPU 100 are connected by the switch circuit 112. The flash memory 102a is connected to a signal processing circuit 102 which is an FPGA circuit, and stores a plurality of configuration data for constructing a circuit corresponding to each of a plurality of image formats in the signal processing circuit 102.

  The non-volatile (NV) memory 111 receives a mode command signal corresponding to the processing mode of the digital image signal from the system CPU 100 and then supplies predetermined configuration data to the signal processing circuit 102 from the flash memory 102a. Commands to the memory 102a. That is, without receiving a direct command from the system CPU 100, two types of mode data, that is, any one configuration data of 4: 2: 2 mode and 4: 4: 4 mode are generated by the command output from the mode switching circuit 110. Is selected and read into the signal processing circuit 102.

FIG. 8 is a flowchart showing a termination and activation procedure when the program control apparatus is used.
In step S11, the system CPU 100 determines whether or not the camcorder is instructed to be turned off. This step S11 is repeatedly executed until the power-off is instructed. When power off is instructed, the process proceeds to step S12.

  In step S12, the system CPU 100 determines whether or not an instruction to change the next image format has been issued. If there is an instruction to change the format, the process proceeds to step S13, and if there is no instruction, the process proceeds to step S14.

  In step S <b> 13, the system CPU 100 generates a mode command signal corresponding to the new image format and outputs the mode command signal to the switch circuit 112. In the switch circuit 112, the mode command signal is stored in the nonvolatile memory 111. If no change of the image format is instructed in step S12, the mode command signal corresponding to the image format being processed at that time is stored in the nonvolatile memory 111.

In step S14, the system CPU 100 executes an end process for each part of the camcorder, and the camcorder is turned off.
In step S15, the camcorder is powered on by the camcorder power switch. As a result, in step S16, the system CPU 100, which is the startup main CPU, starts up. When the activation processing of the system CPU 100 is completed, in the subsequent step S17, processing for starting up each block of the camcorder is executed in accordance with a command from the system CPU 100.

  On the other hand, the process in step S18 is executed after or before the start-up process of the system CPU 100 in step S16. In step S18, a mode command signal is read from the nonvolatile (NV) memory 111, and configuration data to be read is selected from the flash memory 102a in accordance with this signal. In step S19, only the selected configuration data is supplied to the signal processing circuit 102, which is an FPGA circuit, and circuit construction corresponding to a predetermined image format is started.

  As described above, according to the configuration of FIG. 7, it is possible to load necessary configuration data from the flash memory to the FPGA circuit without waiting for the completion of the startup process of the system CPU 100, thereby reducing the time required for the startup process of the camcorder. It can be further shortened. In particular, when the system is always reset when an image format change operation is performed, processing in the changed image format can be started in a short time, which is effective.

  In the above embodiment, the case where the present invention is applied to a camcorder has been described. However, the present invention is not limited to this, and the same effect can be obtained when applied to an apparatus having only an image recording / playback function such as a VTR. Conversely, the present invention can be applied to a camera that does not have an image recording / playback function and has an imaging function, an image processing function of a captured image, and the like.

It is a block diagram which shows the main structures of a camcorder. It is a block diagram which shows the detailed structure of a digital camera processor. It is a block diagram which shows the detailed structure of a video processor. It is a block diagram which shows the detailed structure of a camera controller and a video D / A conversion circuit. It is a block diagram which shows the detailed structure of a system controller. It is a flowchart which shows the completion | finish and starting procedure of a camcorder. It is a figure which shows an example of the program control apparatus of an FPGA circuit. It is a flowchart which shows the procedure of completion | finish and starting at the time of using the program control apparatus of FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Camera head block, 2 ... A / D conversion circuit, 3 ... Digital camera processor, 4 ... Video processor, 5 ... Equalizer / ECC circuit, 6 ... Drum head, 7 ... Recording tape, 8 ...... Camera controller, 8a ... Internal panel, 9 ... Video D / A conversion circuit, 9a, 9b ... Camera adapter, 10 ... System controller, 11 ... Servo controller, 12 ... Sensor circuit, 13 ... Mechanical deck, 14... Connector panel, 15. ... Camera control unit, A4 ... System control unit, CN1, CN2 ... Connector, PR, MY ... Memory

Claims (11)

In an image processing apparatus that processes an image signal,
A programmable logic circuit to be a circuit for processing a digital image signal;
A data storage unit storing configuration data for constructing circuits individually corresponding to processing of a plurality of image formats in the programmable logic circuit;
An activation control unit that selects any one of the configuration data at the activation timing of the image processing apparatus and instructs the programmable logic circuit to construct a circuit corresponding to any one of the image formats. When,
An image processing apparatus comprising: A format storage unit for storing information indicating the image format to be applied at startup;
The activation control unit controls the configuration circuit to read out the configuration data corresponding to the image format based on information stored in the format storage unit at a timing of activation of the image processing apparatus. The image processing apparatus according to claim 1. A selection operation unit that receives a selection input of the image format;
When the selection operation unit receives a selection input, the format storage unit stores information indicating the latest selected image format,
When the selection operation unit receives a selection input, the activation control unit executes a restart process of the image processing apparatus after updating the storage information in the format storage unit, and based on the storage information in the format storage unit To control the reading of the configuration data,
The image processing apparatus according to claim 2. The activation control unit
An initial activation control unit for performing an initial activation process of the image processing apparatus;
A read control unit that controls a process of reading the configuration data corresponding to the storage information of the format storage unit from the data storage unit to the logic circuit;
With
When starting up the image processing apparatus, before the initial start-up process by the initial start-up control unit is completed, an application process of the configuration data to the programmable logic circuit by the read-out control unit is started. The image processing apparatus according to claim 2, wherein:   In the logic circuit, an unnecessary signal is not sent to a signal line that is not required in the processing of the image signal of the image format corresponding to the loaded configuration data among the signal lines connected to the logic circuit. The image processing apparatus according to claim 1, wherein a circuit is constructed.   The data storage unit is different in at least one of a plurality of color space formats in the digital image signal, bit allocation between color components or between a color component and a luminance component, the number of quantization bits, and a frame frequency. The image processing apparatus according to claim 1, wherein the configuration data is stored for each image format.   The image processing apparatus according to claim 1, wherein the programmable logic circuit is an FPGA (Field Programmable Gate Array) circuit. In an imaging device that captures an image using a solid-state imaging device,
A programmable logic circuit serving as a circuit for processing a digital image signal obtained by imaging;
A data storage unit storing configuration data for constructing circuits individually corresponding to processing of a plurality of image formats in the programmable logic circuit;
An activation control unit that selects any one of the configuration data at the activation timing of the image processing apparatus and instructs the programmable logic circuit to construct a circuit corresponding to any one of the image formats. When,
An imaging device comprising: In an image recording / reproducing apparatus for recording an image signal on a recording medium and reproducing the image signal,
A programmable logic circuit serving as a circuit for processing at least one of a digital image signal recorded on the recording medium or a digital image signal reproduced from the recording medium;
A data storage unit storing configuration data for constructing circuits individually corresponding to processing of a plurality of image formats in the programmable logic circuit;
An activation control unit that selects any one of the configuration data at the activation timing of the image processing apparatus and instructs the programmable logic circuit to construct a circuit corresponding to any one of the image formats. When,
An image recording / reproducing apparatus comprising: In an activation control method for activating an image processing apparatus provided with a programmable logic circuit serving as a circuit for processing a digital image signal,
Configuration data for constructing circuits individually corresponding to processing of a plurality of image formats in the programmable logic circuit is stored in advance in a data storage unit,
The activation control unit selects any one of the configuration data at the activation timing of the image processing apparatus, and configures a circuit construction corresponding to any one of the image formats in the programmable logic circuit. Instruct,
An activation control method characterized by the above. Information indicating the image format to be applied at startup is stored in the format storage unit at any time,
When the image processing apparatus is activated, the activation control unit controls the configuration circuit to read out the configuration data corresponding to the image format based on information stored in the format storage unit. The activation control method according to claim 10.

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