JP4540422B2 - Semiconductor integrated circuit and imaging device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit and an imaging apparatus, and more particularly, to a semiconductor integrated circuit having a plurality of internal buses and a plurality of functional blocks each realizing a predetermined function, and imaging using the semiconductor integrated circuit. Relates to the device.

  In recent years, the demand for digital cameras has been rapidly increasing with the increase in resolution of imaging devices such as CCD (Charge Coupled Device) area sensors and CMOS (Complementary Metal Oxide Semiconductor) image sensors.

  By the way, in this type of digital camera, for example, when displaying a real-time moving image by a display means such as a liquid crystal display, image data transferred from the CCD area sensor via the bus is processed by DMA (Direct Memory Access) ( The image data is referred to as “DMA processing data”), and is output to the display means via the bus. On the other hand, when recording still image data on a recording medium in response to an operation of a release switch (so-called shutter), still image data at the time when the release switch is pressed is processed by a CPU (central processing unit) ( The still image data is referred to as “CPU processing data”) and is output to the recording medium via the bus. At this time, both the DMA processing data and the CPU processing data are transferred via a common bus.

  However, if a common bus is used to transfer high-speed DMA processing data and low-speed CPU processing data, one of them has an adverse effect on the other, and there is a problem that efficiency is lowered. That is, there are cases where the processing rate of the CPU is delayed due to the high bus occupancy rate of the DMA processing data, or the transfer of the DMA processing data is hindered because the processing speed of the CPU is slow.

  In order to solve this problem, conventionally, an image based on the image data output from the photographing unit is displayed on the display unit, and the compressed image data generated by the compression unit when a recording instruction is given is displayed on the CPU. In a digital camera for recording on a recording medium, a first bus connecting the photographing means, the display means and the compression means to each other, and a DMA system connected to the first bus for writing / reading image data and compressed image data in the main memory Access means for accessing the second bus, a second bus connected to the CPU, and a bus that connects the first bus and the second bus when a recording instruction is given, and provides compressed image data from the first bus side to the second bus side There has been a technique including a bridge (see, for example, Patent Document 1).

According to this technique, DMA processing data is transferred through the first bus, and CPU processing data is transferred through the second bus, so that the data can be processed efficiently.
Japanese Patent No. 3296780

  By the way, in information processing apparatuses such as the above digital cameras, PDAs (Personal Digital Assistants, personal digital assistants), personal computers, mobile phones, etc., downsizing, cost reduction, high-speed processing, and high reliability are possible. In many cases, for the purpose of characterization or the like, part or all of the processing executed by the apparatus is configured by a semiconductor integrated circuit such as an LSI (Large Scale Integrated Circuit) or an ASIC (Application Specific Integrated Circuit).

  Therefore, it is conceivable to realize the conventional technology having the first bus, the second bus, and the bus bridge as a semiconductor integrated circuit. By applying this semiconductor integrated circuit, it is possible to reduce the size, cost, processing speed, and reliability of the digital camera in the conventional technology.

  However, when the above conventional technique is realized as a semiconductor integrated circuit, it does not function as a digital camera unless both the first bus and the second bus are used, which causes a problem of high power consumption.

  Further, in this case, the versatility of the semiconductor integrated circuit is low, and it is necessary to manufacture each device. As a result, the semiconductor integrated circuit becomes expensive. In other words, since the development cost of a semiconductor integrated circuit is high, it is desired to use one semiconductor integrated circuit in common for as many models as possible, from low-end models to high-end models. However, since the above semiconductor integrated circuit does not operate unless both the first bus and the second bus are used, it must be a semiconductor integrated circuit specialized for only a single model, and a mass production effect cannot be expected so much. It will be expensive.

  Therefore, when such a semiconductor integrated circuit is mounted on an imaging apparatus having a photographing function such as a digital camera, a PDA, or a mobile phone, the imaging apparatus also consumes a large amount of power and is expensive.

  The present invention has been made to solve the above problems, and an object thereof is to provide a semiconductor integrated circuit and an imaging apparatus capable of suppressing power consumption and reducing the cost.

In order to achieve the above object, a semiconductor integrated circuit according to claim 1 is a semiconductor integrated circuit comprising a plurality of internal buses and a plurality of functional blocks each realizing a predetermined function. Each of the functional blocks is electrically connected to the plurality of internal buses, and the bit width of a part of the plurality of internal buses is smaller than that of the other internal buses . Including the DMA-compatible functional block having an interface circuit for supporting DMA transfer by the DMA controller, and the same number of the interface circuits in the DMA-compatible functional block as the internal bus that electrically connects the DMA-compatible functional block. in, and characterized in that as the bit width the same data transfer bit width and the internal bus, each connected Is intended to.

  According to a first aspect of the present invention, there is provided a semiconductor integrated circuit comprising a plurality of internal buses and a plurality of functional blocks each realizing a predetermined function. The internal bus includes all buses such as a PCI (Peripheral Component Interconnect Bus), a PCI-X bus, an ISA bus (Industry Standard Architecture Bus), and an EISA bus (Extended Industry Standard Architecture Bus).

  Here, in the semiconductor integrated circuit according to the present invention, the plurality of functional blocks are electrically connected to the plurality of internal buses, respectively, and the bit widths of some of the plurality of internal buses are different from those of other internal buses. It is supposed to be small.

  That is, in the present invention, a plurality of functional blocks are electrically connected to the plurality of internal buses, respectively, and the number of internal buses used is adjusted according to the price and specifications of the device to be applied. Thus, the number of processes that can be executed can be increased or decreased, thereby supporting a plurality of models. As a result, the cost of the semiconductor integrated circuit can be reduced. .

  Further, in the present invention, by making the bit width of a part of the plurality of internal buses smaller than that of other internal buses, the power consumption when only a part of the plurality of internal buses is used can be reduced. The bit width of a part of the internal bus can be reduced as compared with the case where the bit width of another internal bus is set to be equal to or larger.

As described above, according to the semiconductor integrated circuit of the first aspect, the semiconductor integrated circuit includes a plurality of internal buses and a plurality of functional blocks each realizing a predetermined function, and the plurality of functional blocks are respectively connected to the plurality of functional blocks. Since it is electrically connected to the internal bus and the bit width of a part of the plurality of internal buses is smaller than that of the other internal buses, the power consumption when only a part of the plurality of internal buses is used is reduced. It can be suppressed and the cost can be reduced. In addition, since the plurality of functional blocks include a DMA controller and a DMA-compatible functional block having an interface circuit for supporting DMA transfer by the DMA controller, it is possible to support DMA transfer. High-speed processing is possible. Further, the interface circuit in the DMA-compatible functional block has the same number as the internal bus that electrically connects the DMA-compatible functional block, and has the same data transfer bit width as the bit width of each internal bus to be connected. Therefore, since data can be transferred independently to a plurality of internal buses, processing can be speeded up.

According to a second aspect of the present invention, there is provided a semiconductor integrated circuit comprising a plurality of internal buses and a plurality of functional blocks each realizing a predetermined function, each of the plurality of functional blocks being a plurality of the plurality of functional blocks. The internal bus is electrically connected, and the bit width of a part of the plurality of internal buses is made smaller than that of the other internal buses. Including at least two external buses for electrically connecting an external memory to at least two of the plurality of internal buses, and a DMA-compatible functional block having an interface circuit for corresponding to the at least two external buses. When an external memory is connected to each of the buses, the addresses in the storage area of each external memory are assumed to be one continuous A memory controller for controlling the external memories, and the number of the interface circuits in the DMA-compatible functional blocks is the same as the number of internal buses that electrically connect the DMA-compatible functional blocks. The data transfer bit width is the same as the bit width. As a result, power consumption when only a part of the plurality of internal buses is used can be suppressed, and the cost can be reduced. In addition, DMA transfer can be supported, and high-speed processing is possible. In addition, an external memory connected to a plurality of internal buses via an external bus can be used as one memory, and convenience can be improved. Furthermore, since data can be transferred independently to a plurality of internal buses, processing can be speeded up.

Further, according to the present invention, as in the invention described in claim 3 , the plurality of functional blocks include a data input functional block that performs only data input and a data output functional block that performs only data output. The functional block and the data output functional block may be electrically connected to only one of the plurality of internal buses. As a result, the number of connections from the data input function block and the data output function block to the internal bus can be reduced, and the circuit scale can be reduced.

Further, according to the present invention, as in the invention described in claim 4 , the data transfer function block includes a data transfer function block having a plurality of data transfer units having different data transfer bit widths in the plurality of function blocks. The plurality of data transfer units may be electrically connected only to an internal bus having a minimum data transfer bit width and a minimum bit width. As a result, the number of connections from the data transfer function block to the internal bus can be reduced, and the circuit scale can be reduced.

On the other hand, in order to achieve the above object, an imaging device according to claim 5 is an imaging device for acquiring image data indicating a subject image by imaging with the semiconductor integrated circuit according to any one of claims 1 to 4. The semiconductor integrated circuit performs a predetermined process on the image data acquired by the imaging means.

Therefore, according to the imaging device described in claim 5 , the semiconductor integrated circuit of the present invention is used to perform predetermined processing on the image data acquired by the imaging means. Similarly to the invention, power consumption when only a part of a plurality of internal buses provided in the semiconductor integrated circuit is used can be suppressed and the cost can be reduced. The imaging means includes a solid-state imaging device such as a CCD area sensor or a CMOS image sensor.

  According to a semiconductor integrated circuit of the present invention, a plurality of internal buses and a plurality of functional blocks each realizing a predetermined function are provided, and each of the plurality of functional blocks is electrically connected to the plurality of internal buses. In addition to being connected, since the bit width of a part of the plurality of internal buses is made smaller than that of other internal buses, power consumption when only a part of the plurality of internal buses is used can be suppressed. The effect that the cost can be reduced is obtained.

  Further, according to the imaging apparatus according to the present invention, the semiconductor integrated circuit according to the present invention is used to perform predetermined processing on the image data acquired by the imaging means, and thus is provided in the semiconductor integrated circuit. The power consumption when only a part of the plurality of internal buses is used can be suppressed, and the cost can be reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Here, a case where the semiconductor integrated circuit and the imaging device according to the present invention are applied to a digital camera having a function of taking a still image will be described.

  FIG. 1 shows a main configuration of an electric system of a digital camera 10 on which an LSI 30 as a semiconductor integrated circuit of the present invention is mounted.

  As shown in the figure, the digital camera 10 according to the present embodiment includes a lens 21 for forming a subject image and a charge coupled device (hereinafter referred to as “the rear side of the optical axis of the lens 21”). CCD ”) 24, an analog signal processing circuit 26 that performs various analog signal processing on the input analog signal, and an analog / digital converter (hereinafter referred to as“ digital signal ”) that converts the input analog signal into digital data. ADC ”) 28).

  The output terminal of the CCD 24 is connected to the input terminal of the analog signal processing circuit 26, and the output terminal of the analog signal processing circuit 26 is connected to the input terminal of the ADC 28. Therefore, the analog signal indicating the subject image output from the CCD 24 is subjected to predetermined analog signal processing by the analog signal processing circuit 26 and converted into digital image data by the ADC 28.

  Specifically, the CCD 24 performs imaging through the lens 21 and sequentially outputs analog signals for R (red), G (green), and B (blue) indicating the subject image to the analog signal processing circuit 26. The analog signal processing circuit 26 performs analog signal processing such as correlated double sampling processing on the analog signal input from the CCD 24 and sequentially outputs the analog signal to the ADC 28. The ADC 28 converts the R, G, and B analog signals input from the analog signal processing circuit 26 into 12-bit R, G, and B signals (digital image data).

  On the other hand, the LSI 30 according to the present embodiment includes a digital signal processing circuit 30A that performs various types of digital signal processing on input digital data, a CPU 30B that controls the operation of the entire digital camera 10, and input digital image data. A compression / decompression processing circuit 30C that performs compression processing in a predetermined compression format (in this embodiment, JPEG (Joint Photographic Experts Group) format) and decompression processing according to the compression format, and a program executed by the CPU 30B A functional block includes a built-in RAM (Random Access Memory) 30D that functions as a work area and the like, and a DMA controller 30E that controls DMA transfer of digital data.

  The digital signal processing circuit 30A according to the present embodiment performs a function of performing white balance adjustment by applying a digital gain corresponding to a predetermined physical quantity to input digital image data, gamma processing, and sharpness processing. A function to generate 8-bit digital image data, a function to perform YC signal processing on the generated 8-bit digital image data, and generate a luminance signal Y and chroma signals Cr and Cb (so-called YC signals). is doing.

  In addition, the LSI 30 according to the present embodiment includes an ADC 30F that converts a video signal input from the outside as an analog signal into digital data, and a portable memory card (for example, smart media (registered trademark), xD picture card, etc.) Connection of external device for controlling communication according to a predetermined communication standard (for example, USB (Universal Serial Bus), IEEE 1394, etc.) between the external memory interface 30G and the external device such as a personal computer or a printer. And an interface 30H as functional blocks.

  In addition, the LSI 30 according to the present embodiment includes a video encoder 30I that generates a video signal (NTSC signal in the present embodiment) indicating an image to be displayed on an externally connected television monitor (TV monitor); Various characters are superimposed on the video signal generated by the video encoder 30I to display an OSD controller 30J that realizes an OSD (On Screen Display) function and a liquid crystal display (LCD) provided in the digital camera 10. An LCD controller 30K that generates a signal indicating an image is provided as a functional block.

  Furthermore, the LSI 30 according to the present embodiment includes two memory controllers 30L and 30M that control access to various externally connected memories as functional blocks, and two internal buses 32A and 32B. Note that the internal bus 32B according to the present embodiment has a bit width smaller than that of the internal 32A. In this embodiment, the internal bus 32A has a bit width of 32 bits, and the internal bus 32B has a bit width of 16 bits.

  All the functional blocks except the above memory controllers 30L and 30M are electrically connected to the internal bus 32A and the internal bus 32B, respectively.

  The memory controller 30L is electrically connected to the internal bus 32A, and the memory controller 30M is electrically connected to the internal bus 32B. An external bus 34A for connecting an external memory is electrically connected to the memory controller 30L, and an external bus 34B for connecting an external memory is electrically connected to the memory controller 30M. Yes.

  In the digital camera 10 according to the present embodiment, two external memories such as an SDRAM (Synchronous Dynamic RAM) 40 and a ROM (Read Only Memory) 42 are electrically connected to the external bus 34A, and the external bus 34B. The SDRAM 44 is electrically connected.

  The SDRAM 40 and the SDRAM 44 used in the digital camera 10 according to the present embodiment have the same storage capacity. As an example, as shown in FIG. 2, the memory controllers 30L and 30M include the SDRAMs 40 and 44, respectively. The SDRAMs 40 and 44 can be controlled by setting the addresses of the storage area as one continuous address.

  On the other hand, as described above, the LSI 30 according to the present embodiment includes the DMA controller 30E as a functional block, and some of the functional blocks support DMA transfer by the DMA controller 30E. For this reason, these DMA-compatible functional blocks are provided with interface circuits (hereinafter referred to as “DMACI / F”) for supporting DMA transfer, and the DMA-compatible functional blocks are internally connected via the DMACI / F. The buses 32A and 32B are electrically connected. In the LSI 30 according to the present embodiment, the digital signal processing circuit 30A, CPU 30B, compression / decompression processing circuit 30C, built-in RAM 30D, external memory interface 30G, external device connection interface 30H, video encoder 30I, OSD controller 30J, LCD controller 30K is a DMA-compatible functional block.

  FIG. 3 shows a schematic configuration of a digital signal processing circuit 30A as an example of a DMA-compatible functional block.

  As shown in the figure, the DMA-compatible functional blocks according to the present embodiment are connected in the same number (two in the present embodiment) as the internal buses to which the DMA-compatible functional blocks are electrically connected. There are provided DMACI / F 36A and DMACI / F 36B having the same data transfer bit width as the internal bus (32 bits and 16 bits in the present embodiment). Each DMA-compatible functional block is electrically connected to the internal bus 32A via the DMACI / F 36A and electrically connected to the internal bus 32B via the DMACI / F 36B.

  Next, as an explanation of the operation of the digital camera 10 according to the present embodiment, only the SDRAM 40 and the ROM 42 are connected to the external bus 34A as external memories, and the operation when performing processing related to shooting using only the internal bus 32A. Will be described with reference to FIG. FIG. 4 is a flowchart showing a flow of processing of the photographing processing program executed by the CPU 30B at this time, and the program is stored in a predetermined area of the ROM 42 in advance.

  In step 100 in the figure, each related unit is set to start DMA transfer of digital image data input from the ADC 28 to the SDRAM 40. As a result, the DMA transfer of the digital image data input from the lens 21, CCD 24, analog signal processing circuit 26 and ADC 28 in real time to the SDRAM 40 is started.

  In the next step 102, the related units are set to start the DMA transfer of the digital image data transferred to the SDRAM 40 to the video encoder 30I and the LCD controller 30K. As a result, display of the captured image by the TV monitor when the TV monitor is connected to the digital camera 10 is started, and the captured image of the LCD when the setting is made to display the captured image on the LCD. Display starts.

  In the next step 104, the user waits for a release switch (not shown) to be pressed. When the release switch is pressed by the user, the process proceeds to step 106.

  In step 106, a predetermined amount of digital image data is read from the SDRAM 40, and in the next step 108, the read digital image data is compressed by the compression / expansion processing circuit 30C, and further in the next step 110, the compressed digital image data is compressed. Image data is stored in the SDRAM 40.

  In the next step 112, it is determined whether or not the processing of step 106 to step 110 has been completed for one image. If a negative determination is made, the process returns to step 106, and when an affirmative determination is made, the process returns to step 114. Transition. When repeatedly executing the processing of step 106 to step 112, in step 106, the digital image data of the same image that has not been read is read.

  In step 114, the compressed digital image data stored in the SDRAM 40 by the above processing is transferred to the external memory interface 30G, and the related units are set to record the digital image data on the memory card. Terminate the processing program. By the process of step 114, the captured image at the time when the release switch is pressed is recorded in the memory card in a compressed state.

  The above is the operation when only the SDRAM 40 and the ROM 42 are connected to the external bus 34A as the external memory, and the processing relating to photographing is performed using only the internal bus 32A. On the other hand, the SDRAM 40 and the ROM 42 are the external memories. The SDRAM 44 is connected to the external bus 34A and the external bus 34B, respectively, and when performing processing related to shooting using both the internal bus 32A and the internal bus 32B, step 110 of the shooting processing program shown in FIG. The processing is such that the compressed digital image data is stored in the SDRAM 44 instead of the SDRAM 40, and the processing in step 114 is performed in parallel with the processing in steps 106 to 112. Therefore, in this case, the processing speed can be increased compared to the case where one internal bus is used.

  As described above in detail, the LSI 30 according to the present embodiment includes a plurality (here, two) of internal buses and a plurality of functional blocks that each realize a predetermined function, Each of the functional blocks is electrically connected to the plurality of internal buses, and the bit width of a part of the plurality of internal buses (in this case, the internal bus 32B) is set to be larger than that of the other internal buses (here, the internal bus 32A). Since it is small, power consumption when only a part of the plurality of internal buses is used can be suppressed, and the cost can be reduced.

  In the LSI 30 according to the present embodiment, the plurality of functional blocks include a DMA controller and a DMA-compatible functional block having an interface circuit (DMACI / F) for supporting DMA transfer by the DMA controller. Therefore, it is possible to cope with DMA transfer and to perform high-speed processing.

  In the LSI 30 according to the present embodiment, at least two external buses (here, external buses) for electrically connecting external memories to at least two (here, two) of the plurality of internal buses. 34A, 34B), and when an external memory (in this case, SDRAM 40, SDRAM 44) is connected to each of the at least two external buses, the memory controller 30L, 30M sets the address in the storage area of the external memory to 1 Since each external memory is controlled as one continuous memory, an external memory connected to a plurality of internal buses via the external bus can be used as one memory, and convenience can be improved. .

  Furthermore, in the LSI 30 according to the present embodiment, the number of the interface circuits in the DMA-compatible functional block is the same as the internal bus that electrically connects the DMA-compatible functional block and has the same bit width as the internal bus that is connected to each. Since the data transfer bit width is adopted, data can be independently transferred to a plurality of internal buses, and the processing speed can be increased.

  On the other hand, in the digital camera 10 according to the present embodiment, the LSI 30 as described above is used, and the LSI 30 is used to perform predetermined processing on the image data acquired by the CCD 24. The power consumption when only a part of the provided plurality of internal buses is used can be suppressed, and the cost can be reduced.

  In the present embodiment, the case where the functional block provided in the LSI 30 has a plurality of data transfer units having different data transfer bit widths is not mentioned, but the plurality of data transfer units are each connected to their own data. It is also possible to adopt a configuration in which only the internal bus having the transfer bit width or more and the minimum bit width is electrically connected.

  For example, the compression / decompression processing circuit 30C is included in the DMA-compatible functional block, and this functional block has a role of inputting digital image data to be compressed and compressed as shown in FIG. A data transfer unit (here, DMACI / F36A) having a role of outputting digital image data obtained by decompressing digital image data has a data transfer bit width of 32 bits, and a role of outputting compressed digital image data; The data transfer bit width of the data transfer unit (here, DMACI / F 36B) having a role of inputting compressed digital image data is 16 bits. As described above, the compression / decompression processing circuit 30C includes two data transfer units having different data transfer bit widths.

  Therefore, as a method of connecting the compression / decompression processing circuit 30C to the internal bus, the above two data transfer units are each set to an internal bus having a minimum bit width that is not less than its own data transfer bit width (the DMACI / F 36A is an internal bus 32A). The DMACI / F 36B may be electrically connected only to the internal bus 32B). As a result, the number of connections from the compression / decompression processing circuit 30C (corresponding to the data transfer functional block of the present invention) to the internal bus can be reduced, and the circuit scale can be reduced.

  In the present embodiment, the case where only the internal bus 32A is used and the case where both the internal bus 32A and the internal bus 32B are used as the processing at the time of photographing have been described. However, only the internal bus 32B is used. You can also As an example of the form in this case, an example in which the process for accessing the SDRAM 40 in the photographing process program shown in FIG. 4 is made to access the SDRAM 44 connected to the internal bus 32B can be exemplified. In this case, although the processing speed may be lower than when only the internal bus 32A is used, power consumption can be reduced.

  In this embodiment, the case where the internal bus of the LSI 30 is selectively used by a program executed by the CPU 30B has been described. However, the present invention is not limited to this, and for example, the internal bus used for the LSI 30 It is also possible to provide an external terminal for setting and selectively use the internal bus of the LSI 30 by setting the external terminal. Also in this case, the same effects as in the present embodiment can be obtained.

  In this embodiment, the DMACI / F in the DMA-compatible functional block is equal in number to the internal bus that electrically connects the DMA-compatible functional block, and has the same data transfer bit as the bit width of each internal bus that is connected. Although the present invention has been described with respect to the width, the present invention is not limited to this. For example, a plurality of internal buses that are electrically connected to the DMA-compatible functional block are connected to the DMA-compatible functional block. A bit width conversion circuit that converts the bit width to a common bit width may be provided.

  FIG. 6 shows a schematic configuration example of the DMA-compatible functional block in this case. As shown at the same time, the DMA function block 30A 'is provided with a bit width conversion circuit 38 for converting the bit widths of a plurality of electrically connected internal buses to a common bit width. The bit width conversion circuit 38 converts the bit width of the internal bus 32A having a bit width of 32 bits into 16 bits common to the other internal buses 32B. In the present embodiment, 32-bit data is sent and received in 16-bit portions by time division. As a result, only one interface circuit (DMACI / F 36) for supporting DMA transfer needs to be provided, and the circuit scale can be reduced.

  In this embodiment, the case where all the functional blocks are connected to each internal bus has been described. However, the present invention is not limited to this, and only the data input functional block for performing data input and the data output only are described. The data output function block that performs the above-described processing may be electrically connected to only one of a plurality of internal buses provided in the LSI 30.

  FIG. 7 shows the main configuration of the electrical system of the digital camera 10 ′ on which the LSI 30 ′ is mounted in this case. In addition, the same code | symbol as FIG. 1 is attached | subjected to the component same as FIG. 1 of the same figure. In the example shown in the figure, the ADC 30F is a data output functional block, the video encoder 30I, the OSD controller 30J, and the LCD controller 30K are data input functional blocks, and these functional blocks are connected only to the internal bus 32A. . In this case, the number of connections from the data input function block and the data output function block to the internal bus can be reduced, and the circuit scale can be reduced.

  In addition, the configuration of the LSI 30 described in this embodiment (see FIG. 1) is merely an example, and it is needless to say that the configuration can be appropriately changed without departing from the gist of the present invention.

  For example, in the present embodiment, the LSI 30 having two internal buses is illustrated as the semiconductor integrated circuit of the present invention. However, the present invention is not limited to this, and has three or more internal buses. You can also. Also in this case, the same effects as in the present embodiment can be obtained.

  Further, the processing flow (see FIG. 4) of the photographing processing program described in the present embodiment is also an example, and it goes without saying that it can be changed as appropriate without departing from the gist of the present invention.

  For example, in the shooting processing program, when the release switch is pressed by the user, the digital image data for one image is compressed by a predetermined amount, and the compressed digital image data is collectively recorded on the memory card for one image. However, when the digital image data is compressed by a predetermined amount, recording of the compressed digital image data on the memory card is repeated for one image, so that one image can be recorded. . Also in this case, the same effects as in the present embodiment can be obtained.

  Further, in the present embodiment, the case where the present invention is applied to a digital camera has been described. However, the present invention can reduce the size, cost, and processing speed of devices such as PDAs, personal computers, and mobile phones. Needless to say, a part or all of the processing executed by the apparatus can be applied to any information processing apparatus configured by a semiconductor integrated circuit such as an LSI or an ASIC for the purpose of achieving high reliability.

It is a block diagram which shows the main structures of the electric system of the digital camera 10 which concerns on embodiment. 3 is a schematic diagram showing an example of an addressing state in a plurality of external memories connected to an external bus of an LSI 30 in the digital camera 10 according to the embodiment. FIG. It is a block diagram which shows the structural example of the DMA corresponding | compatible functional block which concerns on embodiment. It is a flowchart which shows the flow of a process of the imaging | photography processing program which concerns on embodiment. In the case where the functional block of the LSI 30 according to the embodiment includes a plurality of data transfer units having different data transfer bit widths, the plurality of data transfer units are each set to have a minimum bit width that is equal to or larger than each data transfer bit width. It is a block diagram which shows the structural example of the said functional block in the case of electrically connecting only to this internal bus. A bit width conversion circuit that converts the bit width of a plurality of internal buses to which the DMA compatible functional block is electrically connected to a common bit width is provided for the DMA compatible functional block according to the embodiment. It is a block diagram which shows the structural example of the said DMA corresponding | compatible functional block in a case. A block showing the main configuration of the electrical system of the digital camera 10 'when the data input function block and the data output function block included in the LSI 30 according to the embodiment are electrically connected to only one of the plurality of internal buses. FIG.

Explanation of symbols

10 Digital camera 24 CCD (Imaging means)
30 LSI
30A Digital signal processing circuit 30B CPU
30C Compression / decompression processing circuit 30D Built-in RAM
30E DMA controller 30F ADC
30G External memory interface 30H External device connection interface 30I Video encoder 30J OSD controller 30K LCD controller 30L, 30M Memory controller 32A, 32B Internal bus 34A, 34B External bus 36A, 36B DMAC I / F (interface circuit)
40 SDRAM (external memory)
42 ROM (external memory)
44 SDRAM (external memory)

Claims (5)

A semiconductor integrated circuit comprising a plurality of internal buses and a plurality of functional blocks each realizing a predetermined function,
The plurality of functional blocks are electrically connected to the plurality of internal buses, respectively, and a bit width of a part of the plurality of internal buses is made smaller than that of other internal buses ,
The plurality of functional blocks include a DMA controller and a DMA-compatible functional block having an interface circuit for supporting DMA transfer by the DMA controller,
The interface circuit in the DMA-compatible functional block has the same number of internal buses that electrically connect the DMA-compatible functional block and the data transfer bit width that is the same as the bit width of the internal bus that is connected to each of the interface circuits. A semiconductor integrated circuit.   A semiconductor integrated circuit comprising a plurality of internal buses and a plurality of functional blocks each realizing a predetermined function,
  The plurality of functional blocks are electrically connected to the plurality of internal buses, respectively, and a bit width of a part of the plurality of internal buses is made smaller than that of other internal buses,
  The plurality of functional blocks include a DMA controller and a DMA-compatible functional block having an interface circuit for supporting DMA transfer by the DMA controller,
  At least two external buses for electrically connecting an external memory to at least two of each of the plurality of internal buses;
  A memory controller that controls each external memory as one continuous address in the storage area of each external memory when an external memory is connected to each of the at least two external buses;
  The interface circuit in the DMA-compatible functional block has the same number of data transfer bit widths as the internal buses to which the DMA-compatible functional blocks are electrically connected and the internal buses to which the DMA-compatible functional blocks are connected.
  A semiconductor integrated circuit. In the plurality of functional blocks, including a data input functional block for performing only data input and a data output functional block for performing only data output,
The data input function block and said data output function block, the semiconductor integrated circuit according to claim 1 or claim 2, wherein in that the electrically connects to only one of said plurality of internal buses . The plurality of functional blocks include a data transfer functional block having a plurality of data transfer units having different data transfer bit widths,
The plurality of data transfer units in the data transfer function block are electrically connected only to an internal bus having a minimum bit width that is equal to or greater than the data transfer bit width of each of the data transfer function blocks. The semiconductor integrated circuit according to claim 3 . A semiconductor integrated circuit according to any one of claims 1 to 4 , and
Imaging means for acquiring image data indicating a subject image by imaging;
An imaging device comprising:
An imaging apparatus characterized in that the semiconductor integrated circuit performs a predetermined process on the image data acquired by the imaging means.

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