JP2008134382A - Method and program for designing mask layout for integrated circuit and optimization method of mask layout of integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for correcting an optical proximity effect on a mask layout of an integrated circuit. <P>SOLUTION: The method ensures an appropriate functional interaction among circuit features by including functional interlayer and intra-layer constraints on a wafer. The functional constraints used by the present invention are applied to simulated wafer images, which reduces or eliminates EPE (edge placement error) constraints with respect to positions of wafer images while ensuring an appropriate functional interaction. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates generally to the field of optical lithography, and more particularly to photomasks used in optical lithography systems to accurately correct device shapes that meet the performance criteria required for the resulting very large scale integrated (VLSI) circuits. In particular, it relates to a method of incorporating inter-layer constraints into a model-based optical proximity correction (MBOPC) software tool.

  An optical microlithographic process of semiconductor manufacturing, also known as a photolithography process, consists of replicating a desired circuit pattern on a semiconductor for the desired overall circuit performance. The desired circuit pattern is typically represented as opaque, fully and translucent areas on a template commonly referred to as a photomask. In optical microlithography, a pattern on a photomask template is projected onto a photoresist-coated wafer by optical imaging through an exposure system.

  In order to meet Moore's law that device dimensions shrink in a geometric sequence, the VLSI chip manufacturing technology is constantly evolving, so resolution enhancement techniques (OPT) and optical proximity effects The development of the Optical Proximity Correction (OPC) method has been spurred. The latter is a way for chip manufacturers to choose for the foreseeable future because of the high volume yield in manufacturing and the history of past success. However, the ever-decreasing device dimensions are combined with the desire to improve circuit performance in the deep sub-wavelength domain so that complex OPC methods achieve high fidelity of mask patterns. However, it has become increasingly difficult to ensure proper circuit performance on printed wafers.

  Very large scale integrated (VLSI) circuits are made up of several patterned physical layers of material on top of each other on a wafer and are manufactured as patterned shapes on the wafer. In a typical VLSI circuit, the lowest layer of the circuit is comprised of diffusion layers (RX) that generate the source and drain regions of complementary metal oxide silicon field effect transistors (CMOS-FETs, or CMOS). . The layer above RX is composed of a polycrystalline silicon (PC) layer. The region of the PC layer that overlaps the RX region is called a gate region, and the rest of the PC layer is connected to several CMOS transistors. The source, drain and gate regions are connected to several layers of metal interconnects (Mx, x = 1, 2, 3,...) By contact pads (CA). Each metal layer is connected to the upper metal layer by a via layer (Vx, x = 1, 2, 3,...). With current technology, the final VLSI circuit has a number of metal layers and via layers.

  A lithographic process used to form an optional physical layer on a wafer involves designing a layout of one or more mask shapes used to transfer the circuit design shape to the wafer. Optical proximity effect correction (OPC) is a process used to optimize the shape on the mask so that the transfer of the mask pattern to the physical layer reproduces the desired circuit design shape with optimal fidelity. Typically, the lithography process of each physical layer is considered independently of the other physical layers.

  Current OPC algorithms pre-correct the mask shape by dividing the edge of the shape into segments and shifting the position of the segments by a small amount. In the current state of the art, model-based OPC (MBOPC) software provides the physical and optical effects that are most responsible for the infidelity of the mask shape printed on the wafer, as described below with respect to FIG. To imitate. In the MBOPC correction phase, the mask shape is iteratively modified so that the shape printed on the wafer matches as closely as possible to the desired shape. This method automatically deforms the existing mask shape to achieve the target dimensions on the wafer. However, current technology cannot objectively incorporate and satisfy the proper functions of the circuit.

  The aforementioned method of single layer MBOPC is shown in FIG. In the state of the art, an input mask layout 101 and a target image 106 are prepared. The mask shape is divided into segments to form a segmented mask shape 103, and each segment is typically provided with a self-supporting evaluation point at which the mask image value is calculated. Next, the optical and resist images are evaluated at the evaluation points (block 104). Next, the image at each evaluation point is checked against the target image 106 (block 105) to ensure that the simulated image is within predetermined tolerances. In other words, the deviation of the edge of the simulated mask image with respect to the edge of the target image is called an edge placement error (EPE) and must be within a predetermined tolerance. Here, the edge of the image shape can be defined by an image intensity contour equal to or exceeding the dose-to-clear value of the lithography process, and the resist used Depends on the type of Typically, EPE tolerance is expressed as a geometric rule or constraint of the image shape for shapes on the same physical layer. If the image does not stay within tolerance or acceptable EPE, the segment will move forward or backward until all of the simulated image edges are within acceptable tolerances for the target image edge position. Move iteratively (block 107). Finally, the corrected final mask layout is output (block 108).

  In order for the circuit to function properly, it is important that each layer overlaps subsequent layers in the proper area and that the overlapping areas meet certain tolerance criteria. For example, in order for a circuit to function properly, it may be important that the contact layer and metal layer overlap properly at the circuit level and have a sufficient overlap area. The position may not be as important.

  The current technology of MBOPC corrects the mask in such a way that only one layer can be manufactured according to the specification. While it is important to manufacture each layer to individual specifications, it is equally important to ensure that the specifications between layers are met.

  In view of the above, there is a need for an OPC method that takes into account the proper functioning of the interacting circuit layers, for example by taking into account the overlapping shapes of the circuit layers.

  Accordingly, it is an object of the present invention to provide a method of designing an integrated circuit mask layout that ensures proper functional interaction between layers.

  It is another object of the present invention to incorporate functional intra-layer and inter-layer constraint specifications into model-based optical proximity correction (MBOPC).

  It is a further object of the present invention to provide an MBOPC method in which functional constraints are given higher priority than edge placement error constraints.

  It is yet another object of the present invention to guarantee a mask layout that prevents failure of very large scale integration (VLSI) circuits and improves yield.

  These and other objects, aspects and advantages of the present invention are provided by a method for calculating a model-based optical proximity correction for a shape present in a mask layout used in an optical lithography process. The calculation depends on the specification of inter-layer and intra-layer constraints, in particular functional inter-layer constraints and functional intra-layer constraints. According to the present invention, it is possible to relax or eliminate the restriction on the edge arrangement error by giving priority to the functional restriction.

  According to one aspect of the present invention, a method for designing a mask layout of an integrated circuit is provided, the method comprising: preparing a plurality of mask shapes corresponding to a plurality of layers; and from the mask shape to a wafer Preparing a lithography model in the plurality of layers, describing a process of transferring an image, determining a simulated wafer image resulting from transferring the plurality of masks according to the model, and the simulation Providing constraints including functional constraints that ensure proper functional interaction between typical wafer images; evaluating the simulated wafer image relative to other simulated wafer images; Modifying the mask layout to correct the violation if the constraint is violated.

  Functional constraints may consist of inter-layer constraints and further intra-layer constraints. Unlike conventional MBOPC, which applies edge placement error (EPE) constraints on the design target image location in any layer, the functional constraints used by the present invention alleviate the EPE constraints on wafer image location. However, it can be seen that it is applied between simulated wafer images.

According to another aspect of the present invention, a target image representing the desired image is prepared on the wafer and may include appropriate edge placement error (EPE) constraints in addition to the functional constraints. Is given higher priority than EPE constraints.
Mask layout modifications in accordance with the present invention may include circuit design features or resolution enhancement technology (RET) design features such as phase shift shapes, trim mask shapes, block mask shapes, sub-resolution assist features (SRAF). This can be done by correcting features, fill shapes, and negative fill shapes, and may also include arrangements of such RET shapes.

  The method according to the invention can be realized by a computer system or a computer program. The method can be provided as a service to customers who desire a mask layout that ensures proper functional interaction between the layers of the integrated circuit and improves yield.

  Other objects, advantages and embodiments of the present invention will be more readily understood and will become apparent when reference is made to the following detailed description.

  The invention will be better understood from the following detailed description with reference to the drawings.

  In describing the preferred embodiments of the invention, reference will now be made to the drawings in which like numerals refer to like features of the invention. The features in the drawings are not necessarily scaled in the same ratio.

  The present invention is finally used in optical lithography and distortion of a photomask having a pattern of circuit design features to achieve projection onto a photoresist coated wafer so that proper functioning of the circuit is ensured. Correct all. In accordance with the present invention, model-based OPC is performed, where conventional edge placement error (EPE) constraints are relaxed or ensure proper inter-layer and inter-layer constraints and multiple layers of interaction. To be exchanged for specifications.

  Referring to FIG. 2, the relationship between several layers is illustrated. Here, three layers are shown: layer 1, layer 2 and layer 3. The mask layout corresponding to these layers includes mask shapes representing various circuit design features. In this example, layer 1 represents a diffusion layer or active region (RX). Layer 1 has three shapes. That is, S_11, S_12, and S_13. This example is for illustrative purposes only. In an actual mask, there can be millions of shapes. Layer 2 has two shapes, S_21 and S_22, which in this example represent polycrystalline silicon lines (PC). Layer 3 has several shapes, namely S_31, S_32, S_33, etc., which in this example represent contacts (CA). One of the layer constraints among the shapes of the layer 1 and the layer 2 is denoted as C_12_1. Similarly, one of the layer constraints among the shapes of the layer 2 and the layer 3 is denoted as C_23_1. Similarly, one of the layer constraints among the shapes of the layer 1 and the layer 3 is denoted as C_13_1. Interlayer constraints are described in further detail below.

  In addition to this, the present invention considers intra-layer constraints that exist in each layer. This is illustrated in FIG. In this figure, the same three layers 1, 2 and 3 as shown in FIG. 2 are shown, and the same shape is considered in each layer as shown. Some examples of layer 1 intra-layer constraints are shown as C_11 and C_12, respectively. C_11 is an example of a width constraint, and C_12 is an example of an interval constraint. A width constraint typically describes the maximum width or length that an image must satisfy. Spacing constraints typically describe the maximum spacing between two shapes that must be met. Similarly, C_21 and C_22 are examples of width constraints for shape S_21 on layer 2. Similarly, C_31 and C_32 are examples of width constraints for shape S_31 on layer 3.

  Conventional MBOPC uses constraints that consider EPE constraints for a single layer without considering the interaction between shapes from different layers. In contrast, according to the present invention, the EPE constraints may be relaxed or eliminated, and the functional functionality of the shape from all the interacting layer shapes required to produce a particular VLSI chip. Both intra-layer and inter-layer functional constraints that ensure interaction are selected. Such functional constraints can be determined by simulation or prepared by a circuit designer or lithographer, for example.

  MBOPC intra-layer constraints can be placed between the simulated wafer image shape and the target shape, or between features of the simulated wafer image shape itself. The wafer shape can be simulated by calculating an image at multiple points of the target shape and then interpolating the contour.

  FIG. 4 shows an example of an intra-layer constraint that uses the shape of layer 2 as an example for a polycrystalline silicon line (or a line formed from other suitable conductive materials as known in the art). The geometry of this embodiment from layer 2 can be used to form the gate of a transistor device on a CMOS VLSI chip, where the polycrystalline silicon line is, for example, an active or diffusion region (RX) from layer 1 Intersect. Other parts of such lines may serve other functions, such as bit lines or word lines. In this description, such a line shape is hereinafter referred to as a “polyline” shape, but this is not limited to a line made of polycrystalline silicon or a portion intersecting the diffusion region. Including the entire shape of such a linear body. Referring to FIG. 4, the target polyline image shape S1 and the simulated line image shape W1 are projected onto the same plane and are superimposed. The three regions where the target image S1 and the simulated image W1 overlap are indicated by circled regions R1, R2 and R3, and are shown enlarged to further illustrate an example of intra-layer constraints. In region R1, constraint C1 indicates the maximum allowable line-end pull back and indicates how far the simulated image W1 can be pulled back from the target image S1. In region R2, constraints C2 and C4 indicate the maximum allowable edge placement (EPE) deviation of the simulated image W1 from the target image S1 at the evaluation point. The constraint C3 indicates the allowable limit dimension (CD) (that is, the maximum allowable width) of the simulated wafer image W1. In region R3, constraint C5 indicates the maximum allowable corner distance between simulated image W1 and target image S1, ie, allowable corner rounding.

  Another embodiment of the intra-layer constraint is further illustrated in FIG. 5 for the shape of layer 3 having a contact shape, the shape of the target contact is S2, and is superimposed on the same projection plane as the corresponding simulated wafer image W2. It is illustrated in the state. EPE constraints C_6 and C_7 indicate the maximum allowable edge placement error from the target image S2 of the simulated image W2. The CD constraint C_8 is a constraint that defines the maximum width that the contact shape S2 must achieve.

  In conventional MBOPC, OPC is performed at each layer by considering the EPE constraints shown only within that layer. According to the present invention, the constraints that guarantee functionality between multiple layers are obeyed.

  An example is illustrated in FIG. 6, which shows that the shapes from the two interacting layers overlap the same projection plane, in particular the polyline shape S1 from layer 2 and the contact shape S2 from layer 3. On the same projection plane, corresponding simulated wafer images are superimposed for the polyline shape W1 of layer 2 and the contact image shape W2 of layer 3, respectively. In order for the circuit to function properly, it is desirable to ensure that the polyline image W1 completely surrounds the contact image W2 and that the contact image W2 has a minimum CD. This is not guaranteed just by using EPE intra-layer constraints, as shown in FIGS. According to the present invention, an inter-layer enclosure constraint that requires the contact image contour W2 to be completely surrounded by the polyline image W1 to ensure that the contact image W2 is surrounded by the polyline image W1. C_12 is added. The position of the outer edge of the contact image W2 must be equal to or greater than the minimum distance C_12 inside the edge of the polyline image W1. Therefore, the symbol of the distance from the edge of the image is positive when the position of the contact image edge W2 is in the direction toward the inside of the polyline image W1, and when the distance is in the direction toward the outside of the polyline image W1. Defined as negative. Therefore, in this embodiment, the contact enclosure by the polyline is guaranteed by the positive value enclosure constraint C_12. The intra-layer CD constraint C_8 must also be satisfied. However, as long as the interlayer enclosure constraint C_12 is satisfied, the EPE constraint C_6 or C_7 given to the position of the contact image W2 with respect to the position of the target image S2, or the line end of the line target S1 and the line end of the simulated image W1 It is not so important to satisfy the EPE constraint C_1 between. Therefore, according to the present invention, the OPC of the present invention focuses on and guarantees the proper functioning of the shape between the interacting layers while relaxing or eliminating the constraints focused on a specific location in the image. In-layer and inter-layer constraints are used in the method. Note that the constraints between interacting layers need not be limited to sequential interactions, but may include interactions between relatively distant layers, which may include electrical interactions. For example, on a physical embodiment of an integrated circuit, a via or contact may be electrically connected to a polyline, diffusion region or interconnect, so that the contact shape or via shape is polyline shape, diffusion region shape, interconnect. Interlayer enclosure constraints can be added so that they must be enclosed by shapes, or combinations thereof.

  Another embodiment of an interlayer constraint according to the present invention is illustrated in FIGS. An interconnect line 61 embedded in the first layer 609 and a second interconnect line 62 embedded in the second layer 611 are illustrated in the cross-sectional view of the wafer 600 of FIG. 7, where the third dielectric layer 610 is shown. Is inserted between the first layer 609 and the second layer 611. FIG. 7 shows a projection of the interconnect shapes 61, 62 on the same plane, where both shapes 61, 62 have the same direction and in this embodiment are substantially parallel to each other. Such similarly oriented interconnect lines on two different layers must be separated by a minimum distance so that the parasitic capacitance between the lines is not too high. High parasitic capacitance tends to reduce the speed of data flow along the line, and thus negatively affects circuit performance. In this embodiment, the required minimum distance can be expressed as an interlayer constraint D12. Alternatively, given the thickness T12 of the intervening layer 610, the interlayer constraint can be represented as an interlayer constraint P12 on a common projection plane.

  The above shows only two examples of functional inter-layer constraints according to the present invention, and is not limited to these examples. Circuit simulations, design rules, circuit designers, lithography considerations, manufacturability Those skilled in the art will recognize that many other types of functional interlayer constraints may be determined, including but not limited to the following considerations.

  A preferred embodiment of the process according to the invention is illustrated in FIG. All mask shapes associated with the design input, in particular the physical layer, are prepared for all relevant layers, i.e. l = 1,... L (block 801). Each layer is associated with a corresponding simulation model, ie, M1, M2, M3,... ML (block 820). A target image shape S (l, i) is prepared (block 822), where l = 1 for L layers,... L, i = 1 for N fragments,. Note that the number may vary from layer to layer. In addition to these target shapes, resolution enhancement techniques (RET) such as sub-resolution assist features (SRAF), and yield and manufacturability such as filled and negative filled shapes (not shown) There may be additional shapes. In addition to modifying the shape of the circuit features on the mask, other aspects of the mask layout may be modified, such as the shape or placement of the RET shape. Some of these additional shapes should not be modified during MBOPC due to the impact on simulated image shapes, but are used for simulation, for example as part of a lithography process model be able to. For some layers, multiple mask shapes can be associated with a single target shape. For example, in the case of alternating phase shift masks (altPSM), each target shape can be associated with three types of mask shapes, including 0 and 180 ° phase shift shapes, blocks, or trim mask shapes, All three may need to be modified during MBOPC so that the simulated wafer image meets the constraints defined between the simulated wafer image and the target shape. Also, SRAF shape and layout modifications can be considered with the MBOPC algorithm. In addition to shape, all inter-layer and intra-layer constraints are prepared (block 823).

  Each mask shape on each layer is fragmented (block 803). Fragmentation, or segmentation, can be performed by any means currently known or developed in the future, eg, rule-based, adaptive, and model-based. For example, if multiple mask shapes are associated with the target shape, as in the case of alternating phase shift masks, all mask shapes are fragmented accordingly. A segmentation example is illustrated in FIG. 10 for two superimposed target shapes from two different mask layers. That is, S1 representing a part of the polycrystalline silicon line shape in the layer 2 and S2 representing the contact shape in the layer 3. The line shape S1 is segmented into three pieces F_11, F_12 and F_13. The contact shape S2 is segmented into four pieces, namely F_21, F_22, F_23 and F_24.

  Next, an initial set of simulated images W (l, i) for each segment (block 809) is determined for each layer when the OPC iteration k = 0 (block 807). Each segment is associated with the proper inter-layer and intra-layer constraints (block 823). The segment F (l, i) inherits the corresponding constraints related to the mask shape from which it is derived. Like conventional OPC, each mask-shaped segment may be associated with a simulated wafer image. This is illustrated in FIG. 11 where the same shape from FIG. 10 from layer 2 and layer 3 is considered, but the shape is fragmented and the fragments are illustrated as line fragments between nodes. Here, C_12_1 represents an enclosure restriction between the fragment F_11 of the polycrystalline silicon linear shape S1 from the layer 2 and the F_21 of the contact shape S2 from the layer 3, and C_12_2 is a contact with the fragment F_12 of the linear shape S1. C_12_3 represents an inter-layer enclosure constraint between the F_13 of the linear shape S1 and F_23 of the contact shape S2. The intra-layer CD constraint C_2_1 defines the minimum distance between the contact shape fragments F_22 and F_24, and the interlayer CD constraint C_2_2 represents the minimum distance constraint between the fragments F_21 and F_23 of the contact shape S2. In this embodiment, the interlayer enclosure constraints C_12_1, C_12_2, and C_12_3 are typically any number greater than zero, such as 10 nm. These must be positive to ensure that the contacts CA are surrounded by the polycrystalline silicon PC shape. The intra-layer CD constraints C_2_1 and C_2_2 represent the minimum length and width of the simulated shape of the contact shape S2, which may be on the order of 50 nm.

  All simulated images W (l, i) are calculated for the initial OPC iteration k = 0 (block 805). The OPC iteration starts, for example, by comparing the image W (l, i) (k) of that fragment for OPC iteration k for each layer l (block 807) and for each fragment i (block 809). (Block 806). Next, a simulated image W (i, i) (k) is combined with an appropriate set of target images S (l, i), and other fragments and other layers, with both interlayer and intralayer constraints. Compare with the resulting image (block 811).

  If any of the constraints are violated (block 813), modify fragment F (l, i) to obtain a new fragment F (l, i) (k + 1) with OPC iteration k + 1 and new according to the layer model. An image W (l, i) (k + 1) is determined (block 820). Next (block 814), another image and fragment are evaluated for the proper set of target image S, simulated image W, and constraint C until the OPC converges (block 818). Note that within any OPC iteration, the evaluation may include new images based on recently modified fragments.

  After the OPC algorithm has converged (block 819), a final set of modified mask shapes is generated.

  FIGS. 11 and 13 provide a schematic representation of the shape expected from the application of the OPC method of the present invention to the shape of FIG. 10 and the intra-layer and inter-layer constraints of FIG. Finally, the inventive OPC algorithm as shown in FIG. 9 converges after several iterations K. The resulting moving direction of all fragments is illustrated in FIG. Arrows 1001, 1002, and 1003 represent the direction in which the fragment associated with line S1 moves as expected to offset the behavior of the image that shortens the line. However, arrows 1004 and 1006 indicate that fragments F_21 and F_23 of contact S2 are further spaced apart, and operations 1005 and 1007 of fragments F_22 and F_24 are from the line end of S1 and from the original position of contact S2. The distances are adjusted to reach the final positions F_22 (K) and F_24 (K) as shown in FIG. The operation of such contact shape violates the conventional EPE constraints C_6 and C_8 (see FIG. 5), but satisfies the enclosure constraints C_12_1, C_12_2 and C_12_3 according to the present invention (see FIG. 11), and the mutual relationship between the line and the contact Guarantee proper functioning of action.

  An example of the advantages of the OPC method of the present invention over conventional OPC is shown by a comparison of FIG. 14 and FIG. In FIG. 14, two interacting layers are superimposed on the same projection plane, layer A includes a shape representing a gate or polyline, and layer B includes a shape representing a first interconnect layer. In order for the circuit to function properly, it is important that layer A and layer B intersect each other only at the proper location. Crossing elsewhere can cause a short circuit and failure of the proper functioning of the chip. In FIG. 14, the target images from layer A (500) and layer B (400) are represented by hashed regions 500 and 400, respectively, and also represent the initial mask shape. After performing conventional OPC, the modified gate shape 501 represents the OPC execution shape corresponding to the gate target image 500 of layer A, and the post OPC execution shape 401 corresponds to the interconnect shape 400 of layer B. . The resulting simulated gate wafer image 505 corresponding to the modified post-OPC gate shape 501 of layer A and the simulated interconnect wafer image corresponding to the modified post-OPC interconnect shape 401 of layer B 405 is also illustrated. The minimum overlay distance 701 between the simulated gate image 505 and the interconnect image 405 is too small and may cause a loss of yield in chip manufacturing by the possibility of creating a short circuit.

  Referring to FIG. 15, in contrast, after the OPC method of the present invention has been applied to layer A gate shape 500 and layer B interconnect shape 400, the resulting simulated gate wafer image 506 and simulation are shown. Separate interconnect images 406 by an overlay distance that is sufficiently large to avoid improper shorting between interconnect wafer image 406 and gate wafer image 506. According to the present invention, an interlayer overlay distance constraint C_AB_701 is added to ensure that the interconnect image 406 remains sufficiently away from the gate image 506. Using this inter-layer constraint, as a result of the present invention, post-OPC gate shape 502 corresponding to layer A gate target image 500 and post-OPC interconnect shape 402 corresponding to layer B interconnect target image 400 are obtained. The OPC post-execution shapes 501 and 401 (see FIG. 14) generated as a result of the conventional OPC method are modified. In particular, the post-OPC interconnect shape 402 resulting from the OPC method of the present invention is narrower than the post-OPC interconnect shape 401 from conventional OPC. More importantly, the minimum distance between the simulated gate image 506 and the simulated interconnect image 406 does not violate the interlayer constraint C_AB_701, and manufacturing due to a potential short circuit between the gate and the first interconnect layer. Reduce or eliminate yield loss.

  The present invention can be realized by a digital computer or system as shown in FIG. 16, and its main components are a central processing unit (CPU) 2101 and at least one input / output (I / O) device 2102 (keyboard, mouse). A control device 2103, a display device 2108, a storage device 2109 capable of reading and writing computer readable code, and a memory 2106, all connected by, for example, a bus or communication network 2105 Is done. The present invention can be realized as a computer program stored on a computer readable medium 2107 such as a tape or a CD or a storage device 2109. The computer program contains instructions for implementing the method according to the invention on a digital computer. The present invention may be implemented on a plurality of such digital computers, and the items of the present invention may reside in close physical proximity or may be distributed over a large geographical area and connected by a communications network. The method according to the invention may be provided as a service to customers who want to optimize the mask layout that guarantees the functionality of the circuit and improve yield.

  Although the invention has been particularly described with respect to specific preferred embodiments, it is evident that many changes, modifications, and variations will be apparent to those skilled in the art in view of the description herein. Accordingly, the claims are intended to cover all such changes, modifications and variations that fall within the true scope and spirit of the present invention.

The flowchart of the conventional optical proximity effect correction method is shown. FIG. 4 is a schematic diagram of three design layers including circuit design geometry, interlayer interactions and interlayer constraints. 3 is a schematic diagram of three design layers including design geometry and intra-layer constraints. 4 is a schematic illustration of the design shape of a layer 2 of polycrystalline silicon lines and the shape of a corresponding image projected on the same plane. 4 is a schematic illustration of the design shape of the contact layer 3 and the shape of the corresponding image projected on the same plane. It is the top view of what projected the design shape of the layer 2 and the layer 3 on the same surface, and a corresponding wafer image. FIG. 3 is a cross-sectional view of a substrate including two interconnect features on different layers. FIG. 8 is a plan view of the two interconnect features of FIG. 7 projected onto the same plane. 2 is a schematic flow diagram of one embodiment of a method according to the present invention. Fig. 4 is a schematic illustration of two fragmented design shapes from two different layers superimposed on the same projection plane. 11 is a schematic illustration of the fragmented design shape of FIG. 12 is a schematic illustration of possible modifications to the design shape of FIG. 10 according to the present invention using the constraints illustrated in FIG. 12 is a schematic diagram of possible results with the modified mask layout of FIG. 11 in accordance with the present invention. FIG. 6 is a plan view of two interconnect features from different layers projected on the same projection plane, including a modified shape as a result of conventional MBOPC. FIG. 15 is a plan view of two interconnect features from different layers illustrated in FIG. 14 that include shapes that have been projected onto the same projection plane and modified as a result of MBOPC performed in accordance with the present invention. 1 is a schematic diagram of a computer system and computer program configured to carry out the method of the present invention.

Explanation of symbols

61 Interconnect Shape 62 Interconnect Shape 101 Input Mask Layout 103 Mask Shape 106 Target Image 400 Interconnect Shape 401 Post-OPC Shape 402 Post-OPC Interconnect Shape 405 Interconnect Image 406 Simulated Interconnect Image 500 Gate Target Shape 501 Gate shape after OPC execution 502 Gate shape after OPC execution 505 Simulated gate wafer image 506 Gate wafer image 600 Wafer 609 First layer 610 Third dielectric layer 611 Second layer 1001 Arrow 1002 Arrow 1003 Arrow 1004 Arrow 1005 operation 1006 arrow 1007 operation 2101 central processing unit 2102 input / output device 2103 control device 2105 communication network 2106 memory 2107 computer readable medium 2108 display Location 2109 storage device

Claims (14)

A method for designing a mask layout for an integrated circuit comprising:
Preparing a plurality of mask shapes corresponding to a plurality of layers;
Providing a lithography model for the plurality of layers describing a process of transferring a wafer image from the mask shape to a wafer;
Determining a simulated wafer image resulting from the transfer of the plurality of mask shapes according to the lithography model;
Providing constraints including functional constraints that ensure proper functional interaction between the simulated wafer images;
Evaluating the simulated wafer image relative to the other simulated wafer images;
Modifying the mask layout to correct the violation if the constraint is violated. The method of claim 1, wherein the functional constraints include interlayer constraints. The method of claim 1, wherein the functional constraints include intra-layer constraints and inter-layer constraints. Providing a target image representing a desired wafer image on the wafer;
Providing an edge placement error constraint of the simulated wafer image with respect to the target image;
Evaluating the simulated wafer image relative to the other simulated wafer image further comprises evaluating the simulated wafer image relative to the target image, wherein the functional constraint is the The method of claim 1, wherein the method has a higher priority than an edge placement error constraint. The method of claim 1, wherein the mask shape has circuit design features. The method of claim 1, wherein the mask shape has a resolution enhancement technique (RET) shape. The method of claim 6, wherein the RET shape is selected from the group consisting of sub-resolution assist features, fill shapes, negative fill shapes, phase shift shapes, trim mask shapes, and block mask shapes. 3. The interlayer constraint includes a requirement that the projection of the first layer shape onto the plane of the simulated image surrounds the projection of the second layer shape onto the plane of the simulated image. The method described in 1. The method of claim 8, wherein the shape of the first layer is selected from the group consisting of a polyline shape, an interconnect shape, and a diffusion layer shape. The method of claim 8, wherein the shape of the second layer is selected from the group consisting of a contact shape and a via shape. The interlayer constraint is that the simulated image of the shape of the first layer interacts with the shape of the first layer and the shape of the second layer from the simulated image of the shape of the second layer. The method of claim 2, comprising the requirement of being separated by a distance that guarantees that there is no. The distance is predetermined between the projection of the shape of the first layer onto the plane of the simulated image and the projection of the shape of the second layer onto the plane of the simulated image. The method of claim 11, wherein the distance is a measured distance. A computer program for designing a mask layout of an integrated circuit, comprising:
Preparing a plurality of mask shapes corresponding to a plurality of layers;
Providing a lithography model of the plurality of layers describing a process of transferring a wafer image from the mask shape to a wafer;
Determining a simulated wafer image resulting from the transfer of the plurality of mask shapes according to the lithography model;
Providing constraints including functional constraints that ensure proper functional interaction between the simulated wafer images;
Evaluating the simulated wafer image relative to the other simulated wafer images;
And a step of modifying the mask layout to correct the violation when the constraint is violated. A method for optimizing the mask layout of an integrated circuit, where the mask layout includes multiple mask shapes corresponding to multiple layers, and the process of transferring the multiple mask shapes to the wafer is described by a set of lithography models And
Determining a simulated wafer image resulting from the transfer of the plurality of mask shapes according to the lithography model;
Providing constraints including functional constraints that ensure proper functional interaction between the simulated wafer images;
Evaluating the simulated wafer image relative to the other simulated wafer images;
Modifying the mask layout to correct the violation if the constraint is violated.

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