JP2008130845A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which a static electricity tolerance lowered by elevating an upper limit value of a voltage applicable to a drain region can be maintained without upsizing the device. <P>SOLUTION: In this semiconductor device 1, a P well layer 12a is formed so that a product of the average acceptor concentration of the P well layer 12a and the thickness of the P well layer 12a becomes smaller than a value obtained by dividing a product of a predetermined value and an electrical charge per one electron by a dielectric constant of silicone which is a forming material of a SOI substrate 10. As the predetermined value, a value obtained by adding an allowance value to an upper limit value of electric field intensity capable of avoiding the generation of a current concentration caused by a punch-through current passed through the P well layer 12a is adopted. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device in which a lateral MOS transistor element is formed on a surface layer portion of a semiconductor substrate.

  As this type of semiconductor device, for example, a semiconductor device having a structure shown in FIG. 11A is generally known. As shown in FIG. 11A, in the semiconductor device 100a, the lateral MOS transistor element 120 is formed in the SOI layer 112 of the SOI substrate 101 having the buried oxide film 111 therein. Specifically, the SOI layer 112 has a P well layer 112a on the front surface side of the SOI substrate 101 and a buried N layer 112b on the back surface side of the SOI substrate 101, and the lateral MOS transistor element 120 includes the P well layer 112a. It is formed in the surface layer part. By adopting such a structure, the semiconductor device 100a in which the lateral MOS transistor element 2 can be mixedly mounted on the same substrate as the bipolar transistor element (not shown) is obtained.

  However, in the SOI substrate 101 on which such a buried N layer 112b is formed, a parasitic NPN such as “N-type drain region 114a and 114b / P well layer 112a / buried N layer 112b constituting a lateral MOS transistor element” is used. The transistor element 115 is configured. For example, when a positive surge (electrostatic discharge) or the like is applied to the semiconductor device 100a, the parasitic NPN transistor element 115 operates, and a very narrow portion (for example, “1 square”) of the P well layer 112a is operated. In a "millimeter" lateral MOS transistor element, current may flow in a concentrated manner (region of "several square micrometers" or less) (current concentration). In this case, the semiconductor device 100a is often destroyed. That is, such a semiconductor device 100a has a small electrostatic resistance. Here, the electrostatic tolerance is actually a value measured through an electrostatic breakdown test, and is a voltage value for evaluating the tolerance of the semiconductor device against an applied electrostatic discharge.

  Therefore, conventionally, for example, Patent Document 1 describes a technique in which the embedded N layer 112b is not fixed in potential and is in a floating state. In this case, even if a positive (negative) surge is applied to the semiconductor device 100a, the parasitic NPN transistor element 115 does not operate because its emitter is open. In other words, it is possible to suppress the occurrence of current concentration, which is a factor for reducing the static electricity resistance of the semiconductor device 100a.

In addition, Patent Document 1 describes a technique for electrically connecting the buried N layer 112b and the first and second drain regions 114a and 114b, respectively. In this way, even if a positive (negative) surge is applied to the semiconductor device 100a, the parasitic NPN transistor element 115 does not operate because its collector and emitter are short-circuited. This also makes it possible to suppress the occurrence of current concentration, which is a factor that reduces the static electricity resistance of the semiconductor device 100a.
Japanese Patent No. 3298455

  By the way, in recent years, such a semiconductor device is required to be able to be driven without being broken even when a higher voltage of about 70 V to 130 V, for example, is applied to the drain region. That is, by controlling the voltage applied to the gate electrode, the amount of current flowing through the channel region between the source region and the drain region can be controlled, and the upper limit value of the voltage applied to the drain region can be further increased. There is a need to increase it.

  However, in the above conventional technique, it has been newly found that the following problems occur when such a high voltage is applied to the drain region.

  That is, when a high voltage is applied to the drain regions 114a and 114b after the buried N layer 112b is brought into a floating state in which the potential is not fixed, a depletion layer extends from the drain regions 114a and 114b into the P well layer 112a. The layer 112b is reached. Then, electrons flow from the buried N layer 112b toward the drain region 114a, and a punch-through current flows (punch-through state). Due to such punch-through current, the parasitic NPN transistor element 115 operates, and eventually the semiconductor device 100a may be destroyed. That is, when a very high voltage is applied to the drain region, the above-described floating state reduces the electrostatic resistance of the semiconductor device 100a.

  On the other hand, when a high voltage is applied to the drain regions 114a and 114b after the buried N layer 112b and the drain regions 114a and 114b are electrically connected, a high voltage is also applied to the buried N layer 112b. Become. At this time, for example, when a potential difference exceeding the breakdown voltage of the PN junction occurs in the PN junction between the buried N layer 112b and the P well layer 112a, the voltage applied to the drain regions 114a and 114b causes the semiconductor device 100a to punch. Even when the voltage is lower than the punch-through voltage to enter the through state, the PN junction may break down and the parasitic NPN transistor element 115 may be turned on. That is, when the voltage applied to the gate electrode is controlled, the current flowing from the buried N layer 112b toward the drain regions 114a and 114b cannot be controlled. Thus, the breakdown voltage of the semiconductor device 100a as a whole is limited by, for example, the breakdown voltage of the PN junction between the P well layer 112a and the buried N layer 112b.

  For example, the P well layer 112a is formed thick so that the depletion layer extending from the drain regions 114a and 114b toward the P well layer 112a does not reach the buried N layer 112b. It is conceivable to increase the breakdown voltage of the PN junction between 112a and the buried N layer 112b.

  However, forming the P well layer 112a thick is not desirable in terms of processing or manufacturing of a semiconductor device. That is, in order to form a thick P layer corresponding to the P well layer 112a, it is generally considered that the P layer is formed on the SOI substrate 101 through epitaxial growth. Thus, it takes a long time to form a thick P layer through epitaxial growth, and there is a concern that the manufacturing cost of the semiconductor device is increased. Further, when the P layer is formed thick, the size of the semiconductor device 100a is increased.

  Further, as described above, since the lateral MOS transistor element is intended to be mixedly mounted on the same SOI substrate 101 as the bipolar transistor element (not shown), a groove is formed in the P layer in the subsequent process, and the inside of the groove is formed. It is necessary to insulate and separate the lateral MOS transistor element and the bipolar transistor element by embedding an insulating film, polycrystalline silicon, or the like in the electrode. Therefore, if the P layer is formed thick, processing accuracy and processing time are required in subsequent processes such as formation of such a groove and embedding an insulating film or the like in the inside of the groove, which in turn increases the manufacturing cost of the semiconductor device. Is concerned.

  Although the case where the lateral MOS transistor element is mixedly mounted on the same SOI substrate as the bipolar transistor element has been described, the lateral MOS transistor element is not limited to the semiconductor as in the semiconductor device 100b shown in FIG. The same situation as described above can occur in the case where the substrate is fabricated by being separated from the substrate in terms of potential.

  The present invention has been made in view of such circumstances, the purpose of which is to increase the upper limit value of the voltage that can be applied to the drain region without causing an increase in the size of the physique, and to reduce the static electricity resistance, It is an object to provide a semiconductor device that can be kept high.

  In order to achieve these objects, according to the first aspect of the present invention, as a semiconductor device in which a lateral MOS transistor element is formed on a semiconductor substrate, first, two layers having different conductivity types on the front surface side and the back surface side of the semiconductor substrate are used. A first conductivity type source region formed in a surface layer portion of the semiconductor substrate surface side of the two layers constituting the semiconductor layer, and the two layers constituting the semiconductor layer A first drain region of a first conductivity type formed in a position separated from the source region within the surface of the semiconductor substrate, and a surface layer of the first drain region, in a surface layer portion of a layer on the surface side of the semiconductor substrate A second drain region of the first conductivity type formed at a higher concentration than the first drain region, and a surface layer portion of the layer on the semiconductor substrate surface side of the two layers constituting the semiconductor layer ,in front A portion located between a source region and the first drain region as a channel region, and a gate electrode formed through a gate insulating film from the channel region to the first drain region, the semiconductor Of the two layers constituting the layer, the layer on the back side of the semiconductor substrate is in a floating state that is not fixed in potential.

  In such a configuration as a semiconductor device, when a high voltage is applied to the second drain region, the depletion layer extends from the first drain region toward the layer on the back side of the semiconductor substrate of the two layers constituting the semiconductor layer. . Such a depletion layer exceeds the layer on the semiconductor substrate surface side of the two layers constituting the semiconductor layer, and reaches the layer on the back side of the semiconductor substrate in the two layers constituting the semiconductor layer. That is, through this depletion layer, the first drain region and the layer on the back side of the semiconductor substrate of the two layers constituting the semiconductor layer are connected to each other. At this time, a parasitic capacitor is formed between the two layers constituting the semiconductor layer. “A layer on the back side of the semiconductor substrate (first conductivity type) of the two layers constituting the semiconductor layer → the semiconductor layer is constituted. Electrons move along a path of the two layers on the semiconductor substrate surface side (second conductivity type) → first drain region (first conductivity type) → second drain region (first conductivity type) ”. As a result, a minute current (punch-through current) flows, and the parasitic capacitor is charged.

  When the electric field strength is higher than a predetermined value in the portion immediately below the second drain region, which is the main current path of the punch-through current thus generated, so-called impact ionization (impact ionization) may occur. That is, electrons flowing as a punch-through current are excessively accelerated by an electric field strength higher than a predetermined value, and collide with atoms constituting the semiconductor substrate. As a result of this collision, a large number of electron-hole pairs are generated, and the holes generated at this time are attracted to the source region. That is, a current flows from the source region to the semiconductor layer, and the voltage of the semiconductor layer near the first drain region is boosted by this current.

  As described in the Background Art section, in the above configuration as a semiconductor device, “the layer on the back side of the semiconductor substrate (first conductivity type) of the two layers configuring the semiconductor layer, the semiconductor layer is configured. Parasitic bipolar transistors such as a layer on the semiconductor substrate surface side of the two layers (second conductivity type) and first and second drain regions (first conductivity type) ”are configured. Therefore, when the voltage of the semiconductor layer in the vicinity of the first drain region is boosted, the parasitic bipolar transistor is operated. In addition, such a parasitic bipolar transistor has a negative resistance characteristic in a high current region, and positive feedback is applied, so that current concentration may locally occur in the part that has been operated earliest.

  In that respect, according to the first aspect of the present invention, the amount of current flowing between the first drain region and the source region via the channel region even if the voltage applied to the gate electrode is controlled. When the electric field intensity cannot be controlled, the electric field intensity in the portion immediately below the first drain region is set to a predetermined value or less.

  As a result, even if the voltage applied to the gate electrode is controlled, a voltage that cannot control the amount of current flowing between the first drain region and the source region via the channel region is increased to the second drain region. Even when applied to the region, the electrons flowing as a punch-through current are not excessively accelerated by an electric field larger than a predetermined value, and as a result, the parasitic current does not cause local current concentration. Capacitor can be charged. Therefore, it is possible to maintain a high static electricity resistance that is reduced by allowing a high voltage to be applied to the drain region. Note that, as described in the background art section, since it is not necessary to form a thick semiconductor layer, the size of the semiconductor device is hardly increased.

  Further, for example, as in the invention described in claim 2, current concentration occurs as the predetermined value due to a punch-through current flowing through a layer on the semiconductor substrate surface side of the two layers constituting the semiconductor layer. It is desirable to adopt a value including a margin in the upper limit value of the electric field strength that can avoid this.

  In the configuration according to claim 1 or 2, as in the invention according to claim 3, for example, an average impurity concentration of a layer on the semiconductor substrate surface side of two layers constituting the semiconductor layer, and the semiconductor The product of the thickness of the portion immediately below the first drain region in the layer on the semiconductor substrate surface side of the two layers constituting the layer is the product of the predetermined value and the amount of charge per electron. If the structure on the semiconductor substrate surface side of the two layers constituting the semiconductor layer is formed so as to be smaller than the value obtained by dividing by the dielectric constant of the substrate forming material, The above-described structure that can further increase the upper limit value of the voltage that can be applied to the drain region without increasing the size of the drain region can be realized with a simple configuration.

  On the other hand, in the configuration according to claim 1 or 2, in the invention according to claim 4, for example, the first drain region is partially overlapped with a depth deeper than a lower end of the first drain region reaches. In addition, the third drain region of the first conductivity type is formed at the same concentration as the first drain region so as to surround the second drain region.

  In such a configuration as a semiconductor device, the punch-through often occurs in a portion immediately below the third drain region in the semiconductor layer. That is, the place where the punch-through occurs can be determined in advance. In addition, in the portion of the semiconductor layer other than the portion immediately below where the third drain region is formed, the electric field strength need not be lower than the predetermined value, and the thickness, concentration, etc. can be designed independently. Since it becomes possible, the freedom degree of design improves.

  As described above, the main current path of the punch-through current is a portion immediately below the second drain region. In that respect, in particular, as in the invention described in claim 5, it is desirable that the third drain region is formed below the second drain region.

  On the other hand, in the configuration according to claim 1 or 2, in the invention according to claim 6, for example, the second drain region of the layer on the semiconductor substrate surface side of the two layers constituting the semiconductor layer is formed. The lower portion is configured to have a concentration different from that of the other portions. As a result, the electric field strength can be easily reduced to the predetermined value or less in the portions formed at different concentrations of the two layers constituting the semiconductor layer on the semiconductor substrate surface side. Since the thickness, concentration, etc. can be designed independently in portions other than the portion formed at different concentrations in the two layers constituting the semiconductor layer on the surface side of the semiconductor substrate, the design freedom The degree is improved.

  Specifically, in the configuration according to claim 6, for example, as in the invention according to claim 7, the second of the layers on the semiconductor substrate surface side of the two layers constituting the semiconductor layer. It is desirable that the portion located below the drain region has a lower concentration than other portions.

  In the structure according to any one of claims 1 to 7, for example, as in the invention according to claim 8, the semiconductor substrate is an SOI substrate having a buried oxide film, and the semiconductor layer is the buried oxide film. The upper SOI layer may be used.

(First embodiment)
A semiconductor device according to a first embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a side cross-sectional view of the semiconductor device of the present embodiment. With reference to this FIG. 1, the structure of the semiconductor device of this Embodiment is demonstrated first.

  As shown in FIG. 1, the semiconductor device 1 includes an N-channel lateral MOS transistor element 2 on the surface layer portion of an SOI substrate (semiconductor substrate) 10 having a buried oxide film 11 made of, for example, silicon oxide (SiO 2). have.

  Specifically, the SOI substrate 10 has an SOI layer (semiconductor layer) 12 immediately above the buried oxide film 11, and this SOI layer 12 basically has conductivity types on the front side and the back side of the SOI substrate 10. It consists of two different layers. That is, the SOI layer 12 has an N-type buried N layer 12b immediately above the buried oxide film 11, and has a P-type P well layer 12a directly above the buried N layer 12b. The SOI substrate 10 is manufactured through an appropriate method such as “SIMOX” or “bonding”, for example. In any method, the embedded N layer 12b is a base material used when the SOI substrate 10 is manufactured. And is in a floating state that is not fixed in potential.

  Further, as shown in FIG. 1, an N-type high-concentration impurity region is formed in the surface layer portion of the P well layer 12a through an appropriate method such as ion implantation, for example. It functions as the source region 13 of the lateral MOS transistor element 2. Incidentally, the source region 13 is formed at a concentration of, for example, “10 ^ 20 [cm ^ (− 2)]”. Similarly, an N-type impurity region is formed at a position away from the source region 13 in the surface layer portion of the P well layer 12a by an appropriate method such as ion implantation, for example. In the surface layer portion, an N-type high concentration impurity region is formed. Both these regions function as the drain region of the lateral MOS transistor element 2. Of these two regions constituting the drain region, the N-type impurity region is formed at a concentration of, for example, “10 ^ 16 to 10 ^ 17 [cm ^ (− 2)]”, and this is the drain low concentration region. The (first drain region) 14a is an N-type high-concentration impurity region formed with a concentration of, for example, “10 ^ 20 [cm ^ (− 2)]”. Drain region) 14b. Further, a region surrounded by a broken line in FIG. 1 located between the source region 13 and the low drain concentration region 14a in the P well layer 12a functions as the channel region 15 of the lateral MOS transistor element 2. Incidentally, the channel region 15 is formed at a concentration of, for example, “10 ^ 17 to 10 ^ 18 [cm ^ (− 2)]”.

  Further, as shown in FIG. 1, in the surface layer portion of the P well layer 12a, a P-type high-concentration impurity region is adjacent to the source region 13 through an appropriate method such as ion implantation, for example. It is formed at a concentration of “10 ^ 20 [cm ^ (− 2)]”. This impurity region functions as a channel potential fixing diffusion layer 18 for fixing the potential of the channel region 15.

  Further, as shown in FIG. 1, a gate insulating film 17 and a field oxide film 19 are formed from the channel region 15 to the low drain concentration region 14a using an insulating material such as silicon oxide, for example. 17 and field oxide film 19 are used to form gate electrode 16 using an appropriate conductive material such as polycrystalline silicon.

  Incidentally, in the semiconductor device 1 configured as described above, as shown in FIG. 1, “the drain region (drain low concentration region 14a) of the lateral MOS transistor element 2 / the P well layer 12a (precisely, P Parasitic NPN transistor elements such as a portion of the well layer 12a sandwiched between the low drain concentration region 14a and the buried N layer 12b) / the buried N layer 12b are configured. The drain low concentration region 14a corresponds to the collector of the parasitic NPN transistor element, the P well layer 12a corresponds to the base of the parasitic NPN transistor element, and the buried N layer 12b corresponds to the emitter of the parasitic NPN transistor element.

  When a high voltage of, for example, “70 V to 130 V” is applied to the drain high concentration region 14b of the semiconductor device 1 through an appropriate terminal or the like, the drain low concentration region 14a is directed toward the buried N layer 12b. The depletion layer grows. Such a depletion layer reaches the upper surface of the buried N layer beyond the P well layer 12a. As described above, since the buried N layer 12b is in a floating state that is not fixed in potential, the depletion layer hardly extends from the buried N layer 12b toward the drain low concentration region 14a. Thus, the drain low concentration region 14a and the buried N layer 12b are connected through the depletion layer extending from the drain low concentration region 14a. At this time, as shown in FIG. 2, a parasitic capacitor C is formed between the P well layer 12a and the buried N layer 12b, and “the buried N layer 12b → the P well layer 12a → the drain low concentration region 14a. → Electrons move along a path such as “drain high concentration region 14b”, a minute current (punch through current) flows uniformly to some extent, and the parasitic capacitor C is charged.

  When the electric field strength is higher than a predetermined value in the portion immediately below the drain low-concentration region 14a serving as a current path of the punch-through current generated in this way, so-called impact ionization (impact ionization) occurs, and as a result, current concentration occurs. The inventors have discovered. Note that how to determine the predetermined value will be described later. That is, some of the electrons flowing as the punch-through current are excessively accelerated by the electric field strength higher than a predetermined value, and collide with silicon atoms constituting the SOI substrate 10 (particularly, the P well layer 12a). As a result of these collisions, electron-hole pairs are generated, and the generated electron-hole pairs further collide with silicon atoms, again forming electron-hole pairs in this manner. Hole pairs are generated, producing a large number of electron-hole pairs. The holes generated at this time are attracted to the source region 13 having a low potential. That is, as shown in FIG. 2, a hole current flows from the buried N layer 12 b to the source region 13. The hole current boosts the portion of the P well layer 12a in the vicinity of the drain low concentration region 14a. As a result, a current flows through the base of the parasitic NPN transistor element, and the parasitic NPN transistor element is operated. Moreover, since such a parasitic NPN transistor element has a negative resistance characteristic, positive feedback is applied, and current concentration locally occurs in the part that has been operated earliest. If such current concentration occurs, the semiconductor device 1 may be destroyed. Conversely, even if a punch-through current occurs, the impact ionization (impact ionization) occurs when the electric field strength is equal to or lower than a predetermined value in the portion immediately below the drain low-concentration region 14a serving as the current path of the punch-through current. It does not occur or is small enough. Since impact ionization does not occur or is sufficiently small, the parasitic NPN transistor device hardly operates. Therefore, the semiconductor device 1 is not destroyed.

  Of course, if the semiconductor device 1 itself is destroyed due to the occurrence of the punch-through current in this way, when the voltage applied to the gate electrode 16 is controlled, the low-drain region 14a and the source region 13 are controlled. The amount of current flowing through the channel region 15 cannot be controlled. However, even if the semiconductor device 1 itself is not destroyed, the amount of current may not be controlled. That is, this is a case where the lateral MOS transistor element 2 formed in the surface layer portion of the SOI substrate 10 breaks down. Here, when the lateral MOS transistor element 2 breaks down, a current that flows between the drain low concentration region 14a and the source region 13 through the channel region 15 even if the voltage applied to the gate electrode 16 is controlled. This means that the amount of control can no longer be controlled. The breakdown of the lateral MOS transistor element 2 mainly includes the PN junction between the low drain concentration region 14a and the P well layer 12a and the PN junction between the P well layer 12a and the buried N layer 12b. Caused by yielding between elements. If any of these PN junctions breaks down, the lateral MOS transistor element 2 breaks down. The breakdown voltage Vbr, which is the voltage applied to the drain high concentration region 14b when the lateral MOS transistor element 2 breaks down, is generally applied to the drain high concentration region 14b when the punch-through current starts to flow. Is different from the punch-through voltage Vpt, which is the applied voltage.

  For example, it is assumed that the semiconductor device 1 is configured such that the breakdown voltage Vbr is higher than the punch-through voltage Vpt. In this case, when a voltage of about the breakdown voltage Vbr is applied to the drain high concentration region 14b, a punch-through current is naturally generated. Here, the electric field strength in the portion immediately below the drain low concentration region 14a increases as the applied voltage to the drain high concentration region 14b increases. Therefore, if the electric field strength in the portion immediately below the drain low concentration region 14a at the time of breakdown of the lateral MOS transistor element 2 exceeds a predetermined value, the punch through current starts to flow immediately below the drain low concentration region 14a. It is not known whether the electric field strength in the portion exceeds a predetermined value. However, if the electric field strength in the portion immediately below the drain low concentration region 14a at the time of breakdown of the horizontal MOS transistor element 2 does not exceed the predetermined value, the punch through current starts flowing immediately after the drain low concentration region 14a starts flowing. The electric field strength at the portion does not exceed the predetermined value. That is, if the electric field strength in the portion immediately below the drain low concentration region 14a at the time of breakdown of the lateral MOS transistor element 2 exceeds the predetermined value, the semiconductor device 1 is destroyed due to the punch-through current. there is a possibility. However, if the electric field strength in the portion immediately below the drain low concentration region 14a at the time of breakdown of the lateral MOS transistor element 2 is equal to or less than the predetermined value, the semiconductor device 1 is not destroyed due to the punch-through current.

  Further, for example, it is assumed that the semiconductor device 1 is configured such that the breakdown voltage Vbr and the punch-through voltage Vpt are approximately the same voltage. In this case, basically, when a voltage of about the breakdown voltage Vbr is applied to the drain high concentration region 14b, a punch-through current may be generated. Therefore, if the electric field strength in the portion immediately below the drain low concentration region 14a at the time of breakdown of the lateral MOS transistor element 2 exceeds the predetermined value, the semiconductor device 1 may be destroyed due to the punch-through current. There is. On the contrary, if the electric field strength in the portion immediately below the low drain concentration region 14a at the time of breakdown of the lateral MOS transistor element 2 is equal to or less than the predetermined value, the semiconductor device 1 is not destroyed due to the punch-through current.

  For example, the semiconductor device 1 is configured so that the breakdown voltage Vbr is lower than the punch-through voltage Vpt. In this case, even if a voltage of about the breakdown voltage Vbr is applied to the drain high concentration region 14b, no punch through current is generated in the first place. Therefore, the breakdown of the semiconductor device 1 due to the punch-through current does not occur regardless of the electric field strength in the portion immediately below the drain low concentration region 14a at the time of breakdown of the lateral MOS transistor element 2.

  Therefore, in the semiconductor device 1 of the present embodiment, even if the voltage applied to the gate electrode 16 is controlled, the amount of current flowing between the low drain concentration region 14a and the source region 13 via the channel region 15 is controlled. When it becomes impossible to do so, that is, when the lateral MOS transistor element 2 breaks down, the electric field strength in the portion immediately below the drain low concentration region 14a is set to a predetermined value or less. Then, as such a predetermined value, a value including a margin in the upper limit value of the electric field intensity that can avoid the occurrence of current concentration due to the punch-through current flowing through the P well layer 12a is obtained through a simulation described later. Yes. Further, the product of the average acceptor concentration “NA” of the P well layer 12a and the thickness “Wp” of the P well layer 12a is the product of the predetermined value and the charge amount q per electron. Such a predetermined value is realized by making it smaller than the value obtained by dividing by the dielectric constant of silicon as a material.

  Details will be described below. First, the following assumptions are made to obtain a good solution. That is, since the drain low concentration region 14a is formed at a higher concentration than the P well layer 12a, the drain low concentration region 14a is a one-sided step junction in which a depletion layer extends only to the P well layer 12a side. Further, it is assumed that the concentration of the P well layer 12a is constant and uniform. Further, since the buried N layer 12b is in a floating state where the potential is not fixed and the potential difference between the P well layer 12a and the buried N layer 12b is small, the depletion layer from the buried N layer 12b side is ignored as being small. The concentration of the P well layer 12a is constant.

Under these preconditions, the maximum electric field intensity Emax when the width of the depletion layer (the length in the direction perpendicular to the surface of the SOI substrate 10) “W” is expressed by the following equation (1).
(Equation 1)
Emax = q × W × NA / εs (1)
Here, “q” represents the amount of charge per electron (1.602 × 10 ^ (− 19) [c]), “W” represents the width of the depletion layer, and “εs” is The dielectric constant of the material (silicon) for forming the SOI substrate 10 is represented.

The width W of the depletion layer when the punch-through current flows is equal to the width of the P well layer 12a (more precisely, the width immediately below the drain low concentration region 14a) “Wpt”. Therefore, the maximum electric field strength Emax (pt) when the punch-through current flows is expressed by the following equation (2).
(Equation 2)
Emax (pt) = q × Wpt × NA / εs (2)
This electric field Emax (pt) only needs to be smaller than a predetermined value Ep obtained through a simulation described later. That is, the following equation (3) may be established.
(Equation 3)
q × Wp × NA / εs <Ep (3)
Therefore, as described above and as expressed in the following equation (4), the product of the average acceptor concentration “NA” of the P well layer 12a and the thickness “Wp” of the P well layer 12a is a predetermined value. The semiconductor device 1 may be configured to be smaller than a value obtained by dividing the product of Ep and the amount of electronic charge q by the dielectric constant of silicon.
(Equation 4)
Wp × NA <(εs / q) × Ep (4)
Hereinafter, the simulation executed for obtaining the predetermined value Ep will be described with reference to FIGS. 3 and 4 simulate the state when the lateral MOS transistor element 2 breaks down, and whether or not current concentration occurs in the semiconductor device 1 is different from this simulation. We are investigating through simulation. Specifically, after creating a simulation model in which three semiconductor devices having an area “one third” of the semiconductor device 1 are connected in parallel, the capacitance value is “330 [pF]” as an electrostatic test. A capacitor is charged in advance with a voltage value of “1 [kV]” or “3 [kV]”, and a resistor having a resistance value of “2 [kΩ]” and a drain high concentration region 14b of the semiconductor device 1 are obtained. It was examined whether or not current concentration occurred in any one of the three when connected in series to this charged capacitor.

  FIG. 3A shows a cross section taken along the line III-III of the SOI substrate 10 when the ion implantation amount into the P well layer 12a is “1.0 × 10 ^ 13 [cm ^ (− 3)]” (FIG. 1). 4 shows the relationship between the distance from the upper surface of the SOI substrate 10 along the line and the electric field strength according to the amount of ion implantation into the drain low concentration region 14a. As shown in FIG. 3A, a case where the ion implantation amount into the drain low concentration region 14a is “6.0 × 10 ^ 12 [cm (−3)]” is represented by a curve a1 with a solid line, and the drain low The case where the ion implantation amount into the concentration region 14a is “7.0 × 10 ^ 12 [cm (−3)]” is indicated by a solid line curve a2, and the ion implantation amount into the drain low concentration region 14a is “8. The case of 0 × 10 ^ 12 [cm (−3)] ”is indicated by a broken line as a curve a3, and the ion implantation amount into the drain low concentration region 14a is“ 9.0 × 10 ^ 12 [cm (−3)] ”. "Is indicated by a broken line as a curve a4. At this time, as shown in the list of FIG. 4, in the curves a1 and a2, current concentration occurred when the voltage value was “1 [kV]” and “3 [kV]”. . On the other hand, in the curves a3 and a4, no current concentration occurred when the voltage value was “1 [kV]” or “3 [kV]”.

  3B shows a cross section taken along the line III-III of the SOI substrate 10 when the ion implantation amount into the P well layer 12a is “1.2 × 10 ^ 13 [cm ^ (− 3)]”. 4 shows the relationship between the distance from the upper surface of the SOI substrate 10 along the line and the electric field strength according to the amount of ion implantation into the drain low concentration region 14a. As shown in FIG. 3B, a case where the ion implantation amount into the drain low concentration region 14a is “8.0 × 10 ^ 12 [cm (−3)]” is represented by a dashed line as a curve b1. The case where the ion implantation amount into the low concentration region 14a is “9.0 × 10 ^ 12 [cm (−3)]” is represented by a solid line curve b2, and the ion implantation amount into the drain low concentration region 14a is “1”. .0 × 10 ^ 13 [cm (−3)] ”as a curve b3 with a broken line, the ion implantation amount into the drain low concentration region 14a is“ 1.1 × 10 ^ 13 [cm (−3)] ] "Is indicated by a broken line as a curve b4. At this time, as shown in the list of FIG. 4, in the curve b1, electric field concentration did not occur when the voltage value was “1 [kV]”, and current concentration occurred when the voltage value was “3 [kV]”. On the other hand, in the curves b2 and b3, current concentration occurred when the voltage value was “1 [kV]” and “3 [kV]”. On the other hand, in the curve b4, no current concentration occurred when the voltage value was “1 [kV]” and “3 [kV]”.

  FIG. 3C shows a cross section taken along the line III-III of the SOI substrate 10 when the ion implantation amount into the P well layer 12a is “1.4 × 10 13 [cm ^ (− 3)]”. 4 shows the relationship between the distance from the upper surface of the SOI substrate 10 along the line and the electric field strength according to the amount of ion implantation into the drain low concentration region 14a. As shown in FIG. 3C, a case where the ion implantation amount into the drain low concentration region 14a is “1.0 × 10 ^ 13 [cm (−3)]” is represented as a curve c1 by a one-dot chain line. The case where the ion implantation amount into the low concentration region 14a is “1.1 × 10 ^ 13 [cm (−3)]” is represented by a curve c2 with a solid line, and the ion implantation amount into the drain low concentration region 14a is “1”. .2 × 10 ^ 13 [cm (−3)] ”as a curve c3 with a broken line, the ion implantation amount into the drain low concentration region 14a is“ 1.3 × 10 ^ 13 [cm (−3)] ] "Is indicated by a broken line as a curve b4. At this time, as shown in the list of FIG. 4, in the curve c1, electric field concentration did not occur when the voltage value was “1 [kV]”, and current concentration occurred when the voltage value was “3 [kV]”. On the other hand, in the curves c2 and c3, current concentration occurred when the voltage value was “1 [kV]” and “3 [kV]”. On the other hand, in the curve c4, no current concentration occurred when the voltage value was “1 [kV]” and “3 [kV]”. However, in the lateral MOS transistor of FIGS. 3 and 4, the thickness of the P well layer 12a is about “7 [μm]” and the thickness of the drain low concentration region 14a is about “3 [μm]”. , Each heat treatment is added.

  From such a simulation result, as the predetermined value, “0.25 [MV / cm]” is a value including a margin in the upper limit value of the electric field strength capable of avoiding current concentration due to the punch-through current. The semiconductor device 1 was configured with the amount of ion implantation into the P well layer 12a and the amount of ion implantation into the drain low concentration region 14a satisfying this predetermined value. As shown by the curve b1 in FIG. 3B and the curve c1 in FIG. 3C, in the electrostatic test, when the voltage value is “1 [kV]”, no electric field concentration occurs, and “3 [ kV] ”, the cause of current concentration is considered as follows. That is, such a phenomenon occurs when the punch-through voltage Vpt which is a voltage applied to the drain high concentration region 14b when a punch-through current flows through the P well layer 12a and when the lateral MOS transistor element 2 breaks down. This is a case where the potential difference from the breakdown voltage Vbr, which is a voltage applied to the drain high concentration region 14b, is small. In such a case, since the potential from the punch-through current to the breakdown is small, the amount of current for charging the parasitic capacitance C (FIG. 2) is small. Therefore, it is considered that electric field concentration does not occur when the voltage value is “1 [kV]”, and current concentration occurs when the voltage value is “3 [kV]”.

  As described above, according to the semiconductor device 1 described in detail, even when a voltage sufficient to cause the breakdown of the lateral MOS transistor element 2 is applied to the drain high concentration region 14b, electrons flowing as a punch-through current are An electric field larger than the value will not cause excessive acceleration, and as a result, the parasitic capacitor can be charged without causing local current concentration. Therefore, it is possible to maintain a high static electricity resistance that is reduced by allowing a high voltage to be applied to the drain high concentration region 14b. As a result, the upper limit value of the voltage that can be applied to the drain high concentration region 14b can be further increased. Note that as described in the background art section, it is not necessary to form the SOI layer 12 (particularly, the P well layer 12a) thick, so that the size of the semiconductor device 1 is hardly increased.

(Second Embodiment)
Next, a second embodiment of the semiconductor device according to the present invention will be described with reference to FIGS. In FIG. 5, the same elements as those shown in FIGS. 1 to 4 are denoted by the same reference numerals, and overlapping descriptions of these elements are omitted.

  FIG. 5 is a side sectional view of the present embodiment. As shown in FIG. 5, this embodiment also has a structure according to the first embodiment. However, in the semiconductor device 1a of the present embodiment, the drain high concentration region 14b is formed so as to be deeper than the lower end of the low concentration drain region 14a and partially overlap with the low concentration drain region 14a. A deep N layer (third drain region) 20 is formed below the drain high concentration region 14b at a concentration similar to that of the low drain concentration region 14a.

  The P well layer 12a is formed by performing ion implantation with an ion implantation amount into the P well layer 12a of, for example, “1.2 × 10 ^ 13 [cm ^ (− 3)]”. The average acceptor concentration is, for example, “2.5 × 10 ^ 15 [cm (−2)], and the diffusion depth of the P well layer 12a is, for example,“ 7.0 [μm] ”. ing. Further, the drain low concentration region 14a is formed by performing ion implantation with an ion implantation amount to the drain low concentration region 14a of, for example, “9.0 × 10 ^ 12 [cm ^ (− 3)]”. Yes. The impurity concentration is, for example, “10 ^ 16 to 10 ^ 17 [cm (−2)]. By forming such a deep N layer 20, the breakdown time of the lateral MOS transistor element 2 can be reduced. The electric field strength in the portion immediately below the drain low concentration region 14a is set to be equal to or less than the predetermined value.

  In the semiconductor device 1a, when a high voltage of, for example, “70V to 130V” is applied to the drain high concentration region 14b via an appropriate terminal or the like, the lower end of the drain low concentration region 14a and the lower end of the deep N layer 20 are applied. To the buried N layer 12b. Each of these depletion layers reaches the upper surface of the buried N layer 12b beyond the P well layer 12a. However, as shown in FIG. 5, the distance of the depletion layer extending from the lower end of the deep N layer 20 toward the buried N layer 12b is shorter than that from the lower end of the low drain concentration region 14a. Therefore, the upper end of the buried N layer 12b is reached early. Therefore, the drain low concentration region 14a (deep N layer 20) and the buried N layer are formed through a depletion layer in a portion below the drain high concentration region 14b that extends from the low drain concentration region 14a and reaches the upper surface of the buried N layer 12b. The layer 12b is connected first. At this time, as in the first embodiment, a parasitic capacitor is formed between the P well layer 12a and the buried N layer 12b, and “the buried N layer 12b → the P well layer 12a → the deep Electrons move along a path of “N layer 20 → drain low concentration region 14a → drain high concentration region 14b”, a punch-through current flows, and the parasitic capacitor is charged. Therefore, current concentration due to punch-through often occurs in a portion immediately below where the deep N layer 20 is formed. That is, it is possible to determine in advance a place where punch through and, in turn, current concentration occurs. Further, in the portions other than the portion immediately below where the deep N layer 20 is formed in the P well layer 12a, the electric field strength does not need to be equal to or less than the predetermined value, and the thickness, concentration, etc. are designed independently. Therefore, the degree of freedom in design is improved.

  FIG. 6 shows a list of the relationship between the formation width of such a deep N layer 20 and the presence / absence of current concentration, concentration distribution, potential distribution, electric field distribution, and occurrence of impact ionization. Note that FIG. 6 is a simulation of the state when the lateral MOS transistor element 2 breaks down, and whether or not current concentration occurs in the semiconductor device 1 is different from this simulation. I'm researching. Specifically, after creating a simulation model in which three semiconductor devices having an area “one third” of the semiconductor device 1 are connected in parallel, the capacitance value is “330 [pF]” as an electrostatic test. A capacitor is charged in advance with a voltage value of “1 [kV]” or “3 [kV]”, and a resistor having a resistance value of “2 [kΩ]” and a drain high concentration region 14b of the semiconductor device 1 are obtained. It was examined whether or not current concentration occurred in any one of the three when connected in series to this charged capacitor. As shown in FIG. 3, in the semiconductor device 1a configured with such an ion implantation amount into the P well layer 12a and an ion implantation amount into the drain low concentration region 14a, the voltage value is “1 [kV]”. Current concentration occurs at both time and “3 [kV]”. Further, the formation width is a width for performing ion implantation for forming the deep N layer 20 with reference to the right end of the SOI substrate 10 of the semiconductor device as shown in FIG.

  First, as shown in FIG. 6 as “no formation width”, the potential distribution of the drain high concentration region 14b is the highest when the deep N layer 20 is not formed. As the distance from here increases, the potential gradually decreases. Regarding the electric field strength distribution at this time, the electric field strength in the portion immediately below the low concentration region of the drain is the highest, and impact ionization has occurred at the portion where the electric field strength is the highest. That is, when the deep N layer 20 is not formed, current concentration may occur and the semiconductor device 1a may be destroyed.

  On the other hand, as shown in FIG. 6 as “formation width 0.4 [μm]”, the potential distribution when the deep N layer 20 is formed with “0.4 [μm]” is the drain high concentration region 14b. The potential is gradually the lower from the drain high concentration region 14b as the base point. However, the change in potential is slightly gentle compared to the case where the deep N layer 20 is not formed. Therefore, regarding the electric field strength distribution, although the electric field strength in the portion immediately below the low drain concentration region 14a is the highest, the range in which the electric field strength is the highest is slightly compared with the case where the deep N layer 20 is not formed. It is narrower and its size is slightly smaller. However, impact ionization has occurred, and the semiconductor device 1a may be destroyed.

  On the other hand, as shown in FIG. 6 as “formation width 0.8 [μm]”, regarding the potential distribution when the deep N layer 20 is formed at “0.8 [μm], the drain concentration region 14b The potential is the highest, and the potential gradually decreases with increasing distance from the drain high concentration region 14b as a base point.However, when the deep N layer 20 is not formed, the “formation width is 0.4 [μm]”. As compared with the case of “”, the change in the potential is drastically reduced. Therefore, regarding the electric field strength distribution, the electric field strength in the portion immediately below the drain low concentration region 14a does not become so large, and when the deep N layer 20 is not formed or “the formed layer is 0.4 [μm ] ”, The range in which the electric field strength is greatest is greatly expanded, and the size thereof is also greatly reduced. Therefore, impact ionization does not occur, and the possibility that the semiconductor device 1a is destroyed is wiped out.

  FIG. 7 shows the relationship between the distance in the depth direction from the upper surface of the SOI substrate 10 and the electric field strength as a diagram corresponding to FIG. As shown by the curve e1 in FIG. 7, when the deep N layer 20 is not formed, the electric field strength in the portion immediately below the drain low concentration region 14a exceeds the predetermined value “2.5 [MV / cm]”. Therefore, current concentration occurs. On the other hand, as shown by the curve e2 in FIG. 7, when the deep N layer 20 is formed with the formation width “0.4 [μm]”, the electric field strength in the portion immediately below the drain low concentration region 14a is Since the value is slightly exceeded, current concentration occurs. On the other hand, as shown by the curve e3 in FIG. 7, when the deep N layer 20 is formed with the formation width “0.8 [μm]”, the electric field strength at the portion immediately below the drain low concentration region 14a is Since it is slightly below the value, no electric field concentration occurs.

  From the above, in the semiconductor device 1a of the present embodiment, the deep N layer 20 is formed with the formation width “1.0 [μm]” including the margin in “0.8 [μm]”.

(Third embodiment)
Next, a third embodiment of the semiconductor device according to the present invention will be described with reference to FIGS. In FIG. 8, the same elements as those shown in FIGS. 1 to 7 are denoted by the same reference numerals, and overlapping descriptions of these elements are omitted.

  FIG. 8 is a side sectional view of the present embodiment. As shown in FIG. 8, this embodiment also has a structure according to the first and second embodiments. However, in the semiconductor device 1b of the present embodiment, the concentration of the portion of the P well layer 12a immediately below the drain low concentration region and below the drain high concentration region is configured to be lower than the other portions. . That is, as shown in FIG. 8, in the P well layer 12a, a portion of the P well layer 12a immediately below the drain low concentration region 14a and below the drain high concentration region 14b has a lower concentration (about half) than other portions. 30 is formed. Such a low concentration region 30 is usually formed through ion implantation. Precisely, in the ion implantation process for forming the P well layer 12a, such a low concentration region is formed by providing a width in which ions are not intentionally implanted. Further, due to such a low concentration region 30, a raised region 31 is formed in a portion below the low concentration region 30 of the buried N layer 12b. In this way, by forming the low concentration region 30 (the raised region 31), the electric field strength in the portion immediately below the drain low concentration region 14a at the time of breakdown of the lateral MOS transistor element 2 is less than the predetermined value. I have to.

  In the semiconductor device 1b, when a high voltage of, for example, “70 V to 130 V” is applied to the drain high concentration region 14b via an appropriate terminal or the like, the depletion layer is buried from the lower end of the drain low concentration region 14a to the buried N layer. Extends towards 12b. Such a depletion layer reaches the upper surface of the buried N layer 12b beyond the P well layer 12a. However, of course, as shown in FIG. 8, among the depletion layers extending from the lower end of the drain low concentration region 14a, the depletion layer that has passed through the low concentration region 30 does not pass through the low concentration region 30. Since the distance is shorter by the raised region 31 than the depletion layer, the upper end of the buried N layer 12b is reached earlier. Therefore, the drain low concentration region 14a and the buried N layer 12b (the raised region are formed through the depletion layer in a portion below the drain high concentration region 14b that extends from the drain low concentration region 14a and reaches the upper surface of the buried N layer 12b. 31). At this time, as in the first and second embodiments, a parasitic capacitor is formed between the P well layer 12a and the buried N layer 12b. 31) → P well layer 12a → drain low concentration region 14a → drain high concentration region 14b ”, a punch-through current flows, and this parasitic capacitor is charged. Therefore, current concentration due to punch-through often occurs in the portion where the low concentration region 30 is formed. In other words, it is possible to predetermine a place where punch-through and consequently current concentration occurs. In the portion of the P well layer 12a other than the portion where the low concentration region 30 is formed, the electric field strength does not need to be less than the predetermined value, and the thickness, concentration, etc. can be designed independently. As a result, the degree of freedom in design is improved.

  FIG. 9 shows a list of the relationship between the formation width of such a low concentration region 30 and the presence / absence of current concentration, concentration distribution, potential distribution, electric field distribution, and impact ionization occurrence. FIG. 9 is a diagram corresponding to FIG. 6 and simulates the state when the lateral MOS transistor element 2 is broken down. Does current concentration occur in the semiconductor device 1? Whether or not is checked through a simulation different from this simulation. Specifically, after creating a simulation model in which three semiconductor devices having an area “one third” of the semiconductor device 1 are connected in parallel, the capacitance value is “330 [pF]” as an electrostatic test. A capacitor is charged in advance with a voltage value of “1 [kV]” or “3 [kV]”, and a resistor having a resistance value of “2 [kΩ]” and a drain high concentration region 14b of the semiconductor device 1 are obtained. It was examined whether or not current concentration occurred in any one of the three when connected in series to this charged capacitor. As shown in FIG. 3, in the semiconductor device 1b configured with such an ion implantation amount into the P well layer 12a and an ion implantation amount into the drain low concentration region 14a, the voltage value is “1 [kV]”. Current concentration occurs at both time and “3 [kV]”. In addition, as shown in FIG. 6, the formation width is a width in which ions are not intentionally implanted in the ion implantation step for forming the P well layer 12a with reference to the right end of the SOI substrate 10 of the semiconductor device. It is.

  First, as shown in FIG. 9 as “no formation width”, the potential of the drain high concentration region 14b is the highest in the potential distribution when the low concentration region 30 (the raised region 31) is not formed. Starting from the high concentration region 14b, the potential gradually decreases as the distance from the high concentration region 14b increases. Regarding the electric field strength distribution at this time, the electric field strength is highest in the portion immediately below the drain low concentration region 14a, and impact ionization occurs at the portion where the electric field strength is the highest. That is, when the low concentration region 30 is not formed, current concentration may occur and the semiconductor device 1b may be destroyed.

  On the other hand, as shown in FIG. 9 as “formation width 0.4 [μm]”, the potential distribution when the low concentration region 30 is formed with the formation width “0.4 [μm]” The potential of the region 14b is the highest, and with the drain high concentration region 14b as a base point, the potential gradually decreases as the distance from the region 14b increases. However, the change in potential is much gentler than in the case where the low concentration region 30 is not formed. Therefore, regarding the electric field strength distribution, the electric field strength is highest in the portion immediately below the drain low concentration region 14a, that is, in the vicinity of the low concentration region 30, but compared with the case where the low concentration region 30 is not formed. The range where the strength is maximized is greatly narrowed, and the size itself is also greatly reduced. Therefore, impact ionization does not occur, and the possibility that the semiconductor device 1b is destroyed is wiped out.

  Similarly, as shown in FIG. 9 as “formation width 0.8 [μm]” or “formation width 1.2 [μm]”, the low concentration region 30 has a formation width “0.8 [μm]” or formation width. Also regarding the potential distribution when formed at “1.2 [μm]”, the potential of the drain high concentration region 14b is the highest, and the potential gradually decreases with increasing distance from this drain high concentration region 14b. Become. In addition, the change in potential is much gentler than when the low-concentration region 30 is formed with the formation width “0.4 [μm]”. Therefore, regarding the electric field strength distribution, although the electric field strength is highest in the portion immediately below the drain low concentration region 14a, that is, in the vicinity of the low concentration region 30, the low concentration region 30 has a formation width of “0.4 [μm]”. Compared to the case where the electric field strength is formed, the range in which the electric field intensity is the largest is very small, and the size itself is small. Therefore, impact ionization does not occur and the semiconductor device 1b is hardly destroyed.

  FIG. 10 is a diagram corresponding to FIG. 3 described above, and shows the relationship between the distance in the depth direction from the upper surface of the SOI substrate 10 and the electric field strength according to the formation width. As shown by the curve f1 in FIG. 10, when the low concentration region 30 is not formed, the electric field strength in the portion immediately below the drain low concentration region 14a exceeds the predetermined value “2.5 [MV / cm]”. Therefore, current concentration occurs. On the other hand, as shown by the curve f2 in FIG. 10, when the low concentration region 30 is formed with the formation width “0.4 [μm]”, the electric field strength in the portion immediately below the drain low concentration region 14a is the predetermined value. The value is substantially the same as the value, and no current concentration occurs. Further, as shown by curves f3 to f5 in FIG. 10, the low concentration region 30 is formed with formation widths “0.8 [μm]”, “1.2 [μm]”, and “1.6 [μm]”. In this case, the electric field strength in the portion immediately below the drain low concentration region 14a is significantly lower than the predetermined value, so that electric field concentration does not occur.

  From the above, in the semiconductor device 1b of the present embodiment, the low concentration region 30 is formed with a formation width “0.8 [μm]” including a margin in “0.4 [μm]”.

  The semiconductor device according to the present invention is not limited to the configuration exemplified in each of the above-described embodiments, and can be implemented as, for example, the following embodiment in which the embodiment is appropriately changed.

  In the semiconductor device 1a of the second embodiment, the drain lightly doped region 14b is deeper than the lower end of the lightly doped drain region 14a and partially overlaps the lightly doped drain region 14a. The deep N layer (third drain region) 20 is formed below the drain high concentration region 14b at the same concentration as that of the low drain concentration region 14a. In addition, a deep N layer having a concentration similar to that of the drain low concentration region 14a is formed so as to be deeper than the depth reached by the lower end of the drain low concentration region 14a and partially overlap the drain low concentration region 14a. It is good also as forming. In short, as long as the electric field strength at the portion immediately below the drain low concentration region 14a at the time of breakdown of the lateral MOS transistor element 2 is set to be equal to or lower than the predetermined value, the deep N layer can be formed at any location. . This also eliminates the need for the electric field strength to be equal to or lower than the predetermined value in the portion of the P well layer 12a other than the portion where the deep N layer is formed, and the thickness, concentration, etc. can be designed independently. It becomes like this.

  In the semiconductor device 1b of the third embodiment, the concentration of the portion of the P well layer 12a immediately below the drain low concentration region 14a and below the drain high concentration region 14b is lower than the other portions. However, it is not limited to this. Conversely, the drain of the P well layer 12a is configured such that the concentration of the portion immediately below the drain low concentration region 14a and below the drain high concentration region 14b is higher than the other portions. You may form the density | concentration of the part right under the low concentration area | region 14a and the lower part of the drain high concentration area | region 14b in the density | concentration different from another part. In short, the concentration distribution of the P-well layer 12a is arbitrary as long as the electric field strength in the portion immediately below the drain low-concentration region 14a at the time of breakdown of the lateral MOS transistor element 2 is not more than the predetermined value. . This eliminates the need for the electric field strength to be equal to or lower than the predetermined value in the portion of the P well layer 12a other than the portion where the concentration is different, so that the thickness, concentration, etc. can be designed independently. Become.

  In each of the above embodiments, the semiconductor devices 1, 1 a and 1 b have a structure in which the lateral MOS transistor element 2 is formed in the surface layer portion of the SOI substrate 10 having the buried oxide film 11 inside. Not limited. The present invention is similarly effective as long as the lateral MOS transistor element 2 is formed not only in the SOI substrate 10 but in the surface layer portion of the semiconductor substrate.

  In each of the above embodiments, the semiconductor device is configured as the N-channel lateral MOS transistor element 2. However, the present invention is not limited thereto, and the semiconductor device may be configured as a P-channel lateral MOS transistor element. . In such a case, the conductivity type (n-type or p-type) of each semiconductor region shown so far may be changed to the opposite conductivity type (p-type or n-type).

1 is a side sectional view of a first embodiment of a semiconductor device according to the present invention. The schematic diagram which shows the principle in which electric current concentration arises in the said 1st Embodiment. In the first embodiment, (a) to (c) show the relationship between the distance from the upper surface of the SOI substrate and the electric field strength, depending on the amount of ion implantation into the P well layer constituting the SOI layer. Figure. FIG. 7 is a table showing a list of relationships between the amount of ion implantation into a P well layer, the amount of ion implantation into a low-concentration drain region, and whether or not current concentration occurs in the first embodiment. Side surface sectional drawing of 2nd Embodiment of the semiconductor device concerning this invention. The figure which showed the relationship between the formation width of a deep N layer, the presence or absence of current concentration, concentration distribution, electric potential distribution, electric field distribution, and the occurrence state of impact ionization as a list in the second embodiment. In the 2nd Embodiment, the figure which shows the relationship between the distance from the upper surface of an SOI substrate, and electric field strength separately with the formation width of a deep N layer. Side surface sectional drawing of 3rd Embodiment of the semiconductor device concerning this invention. The figure which showed the relationship between the formation width of a low concentration area | region, the presence or absence of current concentration, density | concentration distribution, electric potential distribution, electric field distribution, and the occurrence state of impact ionization in the 3rd Embodiment as a list. In the 3rd Embodiment, the figure which shows the relationship between the distance from the upper surface of an SOI substrate, and electric field strength separately according to the formation width of a low concentration area | region. (A) And (b) is side surface sectional drawing of the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 1a, 1b ... Semiconductor device, 2 ... Horizontal MOS transistor element, 10 ... SOI substrate (semiconductor substrate), 11 ... Embedded oxide film, 12 ... SOI layer (semiconductor layer), 12a ... P well layer, 12b ... Embedded N Layer 13... Source region 14 a. Low drain concentration region (first drain region) 14 b High drain concentration region (second drain region) 15. Channel region 16. Gate electrode 17. Gate insulating film 18 ... Diffusion layer for fixing channel potential, 19 ... Field oxide film, 20 ... Deep N layer, 30 ... Low-concentration region, 31 ... Raised region, 100a, 100b ... Semiconductor device, 101, 101a ... Semiconductor substrate, 111 ... Built-in oxidation Film 112... SOI layer 112 a. P well layer 112 b buried N layer 114 a drain low concentration region 114 b drain high concentration Frequency, 115 ... parasitic NPN transistor element, 120 ... lateral MOS transistor elements.

Claims (8)

A semiconductor device in which a lateral MOS transistor element is formed on a semiconductor substrate,
A semiconductor layer composed of two layers having different conductivity types on the front side and the back side of the semiconductor substrate;
A source region of a first conductivity type formed in a surface layer portion of a layer on the semiconductor substrate surface side of the two layers constituting the semiconductor layer;
A first drain region of the first conductivity type formed in a position separated from the source region in the surface of the semiconductor substrate in a surface layer portion of the layer on the semiconductor substrate surface side of the two layers constituting the semiconductor layer When,
A second drain region of a first conductivity type formed in a surface layer portion of the first drain region at a higher concentration than the first drain region;
Of the two layers constituting the semiconductor layer, of the surface layer portion of the layer on the semiconductor substrate surface side, a portion located between the source region and the first drain region is a channel region, and the channel region A gate electrode formed through a gate insulating film over the first drain region,
Of the two layers constituting the semiconductor layer, the layer on the back side of the semiconductor substrate is in a floating state that is not electrically fixed,
When the voltage applied to the gate electrode is controlled, the amount of current flowing between the first drain region and the source region through the channel region cannot be controlled. A semiconductor device characterized in that an electric field strength in a portion immediately below a drain region is a predetermined value or less.   The predetermined value includes a margin in the upper limit value of the electric field intensity that can prevent current concentration from occurring due to a punch-through current flowing through the layer on the semiconductor substrate surface side of the two layers constituting the semiconductor layer. The semiconductor device according to claim 1, wherein   Of the two layers constituting the semiconductor layer, the average impurity concentration of the layer on the semiconductor substrate surface side, and immediately below the first drain region in the layer on the semiconductor substrate surface side of the two layers constituting the semiconductor layer The semiconductor layer has a thickness obtained by dividing the product of the predetermined value and the amount of charge per electron by the dielectric constant of the material for forming the semiconductor substrate. 3. The semiconductor device according to claim 1, wherein a layer on a surface side of the semiconductor substrate among the two layers constituting the semiconductor device is formed.   The depth of the first drain region is substantially the same as the first drain region so as to be deeper than the depth reached by the lower end of the first drain region, partially overlapping the first drain region, and surrounding the second drain region. The semiconductor device according to claim 1, wherein a third drain region of the first conductivity type is formed at a concentration of 1.   The semiconductor device according to claim 4, wherein the third drain region is formed below the second drain region.   The part of the layer on the semiconductor substrate surface side of the two layers constituting the semiconductor layer, which is located below the second drain region, is formed at a different concentration from the other parts. The semiconductor device described.   The portion of the two layers constituting the semiconductor layer on the surface side of the semiconductor substrate that is located below the second drain region is formed at a lower concentration than the other portions. Semiconductor device. The semiconductor substrate is an SOI substrate having a buried oxide film therein,
The semiconductor device according to claim 1, wherein the semiconductor layer is an SOI layer on the buried oxide film.

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