JP2001168320A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device as a smart power IC which is enhanced in withstand voltage without increasing a transistor in ON-state resistance and area occupied by itself. SOLUTION: A second conductivity-type drain diffusion layer 2 and a second conductivity-type source diffusion layer 3 are formed separated from each other on the main surface of a first conductivity-type semiconductor substrate 1, a gate electrode 7 is formed on the main surface of the semiconductor substrate 1 between the drain diffusion layer 2 and the source diffusion layer 3 through the intermediary of a gate insulating film 6 for the formation of a field effect transistor, where a depletion layer is expanded in the lower region of the drain diffusion layer 2, an electrical field is set uniform in intensity near the surface of the first conductivity semiconductor substrate 1, and a semiconductor device is enhanced in breakdown voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, in particular, a smart power IC, which realizes a high breakdown voltage without increasing the on-resistance and occupied area of a transistor.

[0002]

2. Description of the Related Art Liquid crystal display (LCD), CD-ROM
A semiconductor device (IC) for driving and controlling a motor and the like is called a smart power IC, and includes a CMOS logic circuit for processing a normal digital signal and a high-power circuit for controlling a load based on a signal processed by the CMOS logic circuit. The structure is such that the withstand voltage output transistor is mounted on the same chip.

[0003] The manufacturing process of a smart power IC is based on a standard CMOS process, and a few manufacturing steps for manufacturing a high breakdown voltage transistor are added to this process.

FIG. 4 shows a high breakdown voltage transistor used in a conventional smart power IC, wherein 1 is a P-type semiconductor substrate, 2 is an N-type high-concentration drain diffusion layer, and 3 is an N-type high-concentration source diffusion. Layer, 4 is a P-type high concentration substrate contact diffusion layer, 6 is a gate oxide film, 7 is a gate electrode, 8 is a drain electrode, 9 is a source electrode, 10 is a field oxide film, 1
Reference numeral 1 denotes an interlayer insulating film, and reference numeral 18 denotes an N-type medium-concentration extended drain diffusion layer.

The high breakdown voltage transistor used in the conventional smart power IC shown in FIG. 4 is, for example, an N-channel type, in which the N-type medium-concentration extended drain diffusion layer 18 which functions as an electric field drift region when turned off has an N-type high voltage. The structure was added to the side of the concentration drain diffusion layer 2.

In the high breakdown voltage transistor used in the conventional smart power IC shown in FIG. 4, a depletion layer in a critical state at the time of off is shown in FIG. 5 due to the presence of the N-type medium-concentration extended drain diffusion layer 18. State. In FIG. 5, 1
Reference numeral 2 denotes a boundary of a drain potential side depletion layer in a critical state, and reference numeral 14 denotes a boundary of a source potential side depletion layer in a critical state.

[0007] The N-type medium-concentration extended drain diffusion layer 18 is set to a concentration such that it is completely depleted in the process of reaching the critical state. As shown in FIG. 5, the breakdown voltage is increased by sharing most of the drain-source voltage in the portion of the N-type medium-concentration extended drain diffusion layer 18 as shown in FIG.

[0008]

However, the high breakdown voltage transistor used in the conventional smart power IC shown in FIG. 4 completely depletes the N-type medium-concentration extended drain diffusion layer 18 in the process of reaching the critical state. Need to
The concentration of the N-type medium-concentration extended drain diffusion layer 18 cannot be set to a high concentration, and the concentration of the N-type medium-concentration extended drain diffusion layer 18 is about 10 ¹⁷ / cm ^2. The diffusion layer 2 and the N-type high-concentration source diffusion layer 3 must be set to be as low as about one-hundredth. Therefore, a high-resistance portion is included in the path of the drain current at the time of ON, and the ON resistance is increased. Problem.

Further, since the N-type medium-concentration extended drain diffusion layer 18 occupies a part of the surface of the semiconductor substrate 1, there is a problem that the area occupied by the transistor increases.

At present, the problem of increasing the on-resistance and the occupied area has been accepted as a trade-off with the increase in the withstand voltage.

An object of the present invention is to provide a semiconductor device which realizes a high breakdown voltage without increasing the on-resistance and occupied area of a transistor in a smart power IC.

[0012]

In order to achieve the above object, a semiconductor device according to the present invention has a second conductivity type drain diffusion layer formed on a main surface of a first conductivity type semiconductor substrate, A second conductivity type source diffusion layer is formed on a main surface of the first conductivity type semiconductor substrate remote from the drain diffusion layer, and is sandwiched between the second conductivity type drain diffusion layer and the second conductivity type source diffusion layer. Further, in a field effect transistor in which a gate insulating film is formed on a main surface of the first conductivity type semiconductor substrate and a gate electrode is formed on the gate insulating film, particularly in a region below the second conductivity type drain diffusion layer. The breakdown voltage can be increased by expanding the depletion layer and making the electric field intensity near the substrate surface uniform.

Further, a buried drain diffusion layer of the second conductivity type is formed immediately below the drain diffusion layer of the second conductivity type without contacting the drain diffusion layer of the second conductivity type.

The gate electrode is turned off, and a depletion layer that grows from the second conductivity type drain diffusion layer according to a voltage value applied between the drain and the source is supplied to the second conductivity type drain diffusion layer. When reaching a value determined by a diffusion layer structure extending from the conductivity type drain diffusion layer downward to the second conductivity type buried drain diffusion layer formed in the region below the second conductivity type drain diffusion layer, the second By contacting the buried drain diffusion layer with two conductivity type, the depletion layer is further expanded until the buried drain diffusion layer with second conductivity type is completely contained.

Further, the expanded depletion layer contacts the buried floating drain diffusion layer of the second conductivity type, and a barrier of a built-in potential between the second conduction type drain diffusion layer and the second conductivity type buried drain diffusion layer. And the free carriers trapped in the buried floating drain diffusion layer of the second conductivity type are drawn into the side of the second conductivity type drain diffusion layer by the electric field of the depletion layer, so that the buried floating drain of the second conductivity type is buried. The depletion layer is depleted until the total amount of space charges formed in the buried floating drain diffusion layer of the second conductivity type is neutralized by depleting the diffusion layer and depleting the buried floating drain diffusion layer of the second conductivity type. Is grown outward from the buried floating drain diffusion layer of the second conductivity type.

When the donor concentration of the second conductivity type drain diffusion layer is about 10 ¹⁹ / cm ² , the donor concentration of the second conductivity type buried floating drain diffusion layer is 10 ¹⁶ / c.
m ² .

When the depth of the junction of the second conductivity type drain diffusion layer is about 0.5 μm, the depth of the junction of the second conductivity type buried floating drain diffusion layer is 1.
The thickness is about 0 μm and the lower part is about 2.0 μm.

The electric field intensity near the surface of the semiconductor substrate is made uniform due to the influence of the growth of the depletion layer extending laterally in the direction of the gate region at the depth of the buried floating drain diffusion layer of the second conductivity type. In this case, the breakdown voltage is improved.

The second-conductivity-type drain diffusion layer includes at least two layers, a high-concentration layer having a relatively high impurity concentration of the second conductivity type and a low-concentration layer having a relatively low impurity concentration of the second conductivity type.
It is composed of layers or more.

A second conductivity type buried drain diffusion layer is formed directly below the second conductivity type drain diffusion layer without being in contact with the second conductivity type drain diffusion layer, and the second conductivity type drain diffusion layer is mainly formed. A depletion layer is expanded in a region below the diffusion layer, and the second-concentration-type medium-concentration extended drain layer is formed in the second conductivity type.
It is formed so as to protrude from the conductivity type drain diffusion layer to the gate region side and has an electric field relaxation effect.

Further, the donor concentration of the second conductivity type drain diffusion layer is about 10 ¹⁹ / cm ² , and the depth of the junction is 0.1 mm / cm ² .
When the thickness is about 5 μm, the second-conductivity-type medium-concentration extended drain layer has a donor concentration of about 10 ¹⁷ / cm ² and a junction depth of about 0.4 μm.

Further, the breakdown voltage is improved by making the electric field in the depletion layer near the surface of the semiconductor substrate more uniform than the expansion growth of the depletion layer.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a cross-sectional view showing a semiconductor device according to the present invention. FIG. 2 is a cross-sectional view showing a depletion layer formation state immediately before avalanche breakdown (critical state) in an off state according to the present invention. FIG. 4 is a cross-sectional view showing an electric field intensity distribution state in an off state according to the present invention.

Referring to FIG. 1, a semiconductor device according to the present invention comprises:
On the main surface of the first conductivity type semiconductor substrate 1, a second conductivity type drain diffusion layer 2 and a second conductivity type source diffusion layer 3 are formed separately, and the second conductivity type drain diffusion layer 2 and the second conductivity type source diffusion layer are formed. In a field-effect transistor in which a gate electrode 7 is formed on a main surface of a first conductivity type semiconductor substrate 1 sandwiched between layers 3 and insulated by a gate insulating film 6, a region below a second conductivity type drain diffusion layer 2 In addition, the breakdown voltage can be expanded by expanding the depletion layer and making the electric field intensity near the surface of the first conductivity type semiconductor substrate 1 uniform.

Next, a description will be given of realizing a high breakdown voltage without increasing the on-resistance and occupied area of the transistor in the smart power IC according to the present invention.

In the semiconductor device according to the present invention shown in FIG. 1, when the gate electrode 7 is turned off and the value of the voltage applied between the drain electrode 8 and the source electrode 9 is increased,
As shown in FIG. 2, focusing on the junction of the drain diffusion layer 2,
A depletion layer grows according to the applied voltage value.

In FIG. 2, reference numeral 12 denotes a junction of the drain diffusion layer 2 when the gate electrode 7 is turned off and the value of the voltage applied between the drain electrode 8 and the source electrode 9 is increased as described above. It shows the boundary of the drain potential side depletion layer in the critical state among the depletion layers that grow in accordance with the applied voltage value with the portion as the center.

In FIG. 2, a depletion layer is expanded below the second conductivity type drain diffusion layer 2 and the electric field intensity near the surface of the first conductivity type semiconductor substrate 1 is made uniform as in the present invention. For reference, the boundary 13 of the depletion layer on the source potential side in the critical state in the related art without taking the technical means of increasing the breakdown voltage is shown for reference.

In the present invention, the breakdown voltage is increased by expanding the depletion layer below the second conductivity type drain diffusion layer 2 and making the electric field intensity near the surface of the first conductivity type semiconductor substrate 1 uniform. In FIG. 1, the depletion layer is expanded below the second conductivity type drain diffusion layer 2 and the electric field strength near the surface of the first conductivity type semiconductor substrate 1 is reduced in FIG. In order to make the breakdown voltage uniform and to increase the breakdown voltage, the second conductivity type buried drain diffusion layer 5 is formed in a region below the second conductivity type drain diffusion layer 2 without being in contact with the second conductivity type drain diffusion layer 2. Is formed.

Therefore, in the present invention, when the gate electrode 7 is turned off and the value of the voltage applied between the drain electrode 8 and the source electrode 9 is increased, the drain diffusion layer 2
A depletion layer that grows in accordance with the applied voltage value is formed around the junction, but the voltage value of the applied voltage is formed in a downward direction from the drain diffusion layer 2 and in a region below the drain diffusion layer 2. When the value reaches the value determined by the diffusion layer structure up to the buried drain diffusion layer 5 of the second conductivity type, the depletion layer grown according to the applied voltage value becomes the buried floating drain diffusion layer 5.
Contact

When the depletion layer comes into contact with the buried floating drain diffusion layer 5, there is no built-in potential barrier between the drain diffusion layer 2 and the buried drain diffusion layer 5 of the second conductivity type. The free carriers confined in 5 are drawn toward the drain diffusion layer 2 by the electric field of the depletion layer, and the buried floating drain diffusion layer 5 is completely depleted.

Further, space charge is formed in the buried floating drain diffusion layer 5 by depletion of the buried floating drain diffusion layer 5, but the depletion layer is filled until the total amount of the space charge is neutralized. From the floating drain diffusion layer 5 to the outside.

After the depletion layer comes into contact with the buried floating drain diffusion layer 5, at the stage where the depletion layer grows outward from the buried floating drain diffusion layer 5 as a depletion layer, the drain electrode 8 and the source electrode 9 are formed. The above-mentioned phenomenon occurs without increasing the applied voltage applied between the first and second states.

Therefore, in the present invention, as shown in FIG.
The boundary 14 of the source potential side depletion layer in the critical state expands beyond the boundary 13 of the source potential side depletion layer in the critical state in the related art. That is, in FIG. 2, the depletion layer immediately before avalanche breakdown (critical state) in the present invention is a depletion layer between the boundary 12 and the boundary 14, while the depletion layer immediately before avalanche breakdown (critical state) of the conventional technology is used. The depletion layer is a depletion layer in a region between the boundary 12 and the boundary 13, and the depletion layer of the present invention immediately before avalanche breakdown (critical state) is larger than that of the prior art.

In FIG. 2, the portion where the electric field becomes strong and avalanche breakdown occurs is in the vicinity of the surface of the semiconductor substrate 1 in the depletion layer region.

FIG. 3 shows the electric field intensity distribution near the surface of the semiconductor substrate 1. In FIG. 3, the horizontal axis is the arrow 1 in FIG.
The vertical axis indicates the electric field strength in the direction indicated by the arrow 15 of the electric field.

The critical electric field shown in FIG. 3 is an electric field that causes avalanche breakdown, and when the semiconductor substrate 1 is made of silicon,
Its critical electric field is 300-500 KV / cm. FIG.
In the figure, 17 is a curve showing the electric field intensity distribution in the present invention in which the buried floating drain diffusion layer 5 is formed, and 16 is a curve showing the electric field intensity distribution in the prior art in which the buried floating drain diffusion layer 5 is not formed.

The depletion layer region in the region indicated by the arrow 15 in FIG. 2 is between 0 and C in the present invention in which the buried floating drain diffusion layer 5 is formed as shown in FIG. In the prior art in which 5 is not formed, the width is as narrow as 0-B.

In FIG. 3, the area surrounded by the electric field intensity distribution curve 16 or 17 and the horizontal axis is the breakdown voltage.
As is apparent from the above description, in the present invention, by forming the buried floating drain diffusion layer 5, it is possible to greatly improve the breakdown voltage.

In the present invention, the reason why the breakdown voltage can be greatly improved is that the growth of the depletion layer is promoted. In FIG. 3, the depletion layer region 0-B is expanded to 0-C and the depletion layer is increased. Is grown laterally in the direction of the region of the gate electrode 7 at the depth of the buried floating drain diffusion layer 5,
This is because the electric field intensity near the surface of the semiconductor substrate 1 is brought about by a synergistic effect of more uniformity.

In the prior art, in order to improve the breakdown voltage, the drain high-concentration diffusion layer 2 has a relatively low concentration and protrudes from the drain high-concentration diffusion layer 2 toward the region of the gate electrode 7 as shown in FIG. Although the middle-concentration extended drain diffusion layer 18 for reducing the electric field of the same conductivity type is additionally formed, in the present invention, it is not necessary to additionally form the middle-concentration extended drain diffusion layer 18 for relaxing the electric field. .

Further, if a medium-concentration extended drain diffusion layer 18 for relaxing the electric field is additionally formed as in the prior art, the breakdown voltage is improved, but the on-resistance and the area occupied by the transistor are increased. However, in the present invention, it is not necessary to additionally form the middle-concentration extended drain diffusion layer 18 for alleviating the electric field, so that it is possible to prevent an increase in the on-resistance and the occupied area of the transistor.

In the present invention, in order to form the buried floating drain diffusion layer 5, it is necessary to add a mask step and a high energy ion implantation step once each in the manufacturing process. Considering that the mask step and the ion implantation step are each required once to improve the breakdown voltage by forming the middle-concentration extension drain diffusion layer 18 for alleviating the electric field, the manufacturing steps required to improve the breakdown voltage in the present invention are considered. Is not added as compared with the conventional example, and the manufacturing process is not increased.

Accordingly, the present invention expands the depletion layer below the second conductivity type drain diffusion layer 2 and makes the electric field intensity near the surface of the first conductivity type semiconductor substrate 1 uniform, thereby reducing the breakdown voltage. By making it expandable, without increasing the number of manufacturing processes, on-resistance, and the area occupied by transistors,
This has the effect of greatly improving the breakdown voltage.

Embodiment 1 Next, a semiconductor device according to Embodiment 1 of the present invention will be described with reference to FIG.

In FIG. 1, a P-type semiconductor substrate is used as the semiconductor substrate 1. In the P-type semiconductor substrate 1, single crystal silicon is doped with boron to about 10 ¹⁵ / cm ² . The N-type high-concentration drain diffusion layer 2 and the N-type high-concentration source diffusion layer 3 formed on the P-type semiconductor substrate 1 have a density of 10 ¹⁹ / c.
having a donor concentration of about m ² and the junction depth
It is about 0.5 μm.

The gate oxide film 6 formed on the substrate surface between the N-type high-concentration drain diffusion layer 2 and the N-type high-concentration source diffusion layer 3 is formed to a thickness of several tens of nm. The gate electrode 7 formed thereon is made of polycrystalline silicon heavily doped with phosphorus. The P-type high-concentration substrate contact diffusion layer 4 formed adjacent to the N-type high-concentration source diffusion layer 3 has an acceptor concentration of about 10 ¹⁹ / cm ² and a junction depth of about 0.5 μm. .

The N-type high-concentration drain diffusion layer 2 is supplied with power from the drain electrode 8, and the N-type high-concentration source diffusion layer 3 and the P-type high-concentration substrate contact diffusion layer 4 have a wiring structure supplied with power from the source electrode 9. I have. Therefore, the potential of the P-type semiconductor substrate 1 is the same as the potential of the source diffusion layer 3.

The N-type buried floating drain diffusion layer 5 is formed immediately below the N-type high-concentration drain diffusion layer 2 in a non-contact state with the N-type high-concentration drain diffusion layer 2. , The upper part is about 1.0 μm, the lower part is about 2.0 μm,
It has a donor concentration of about 10 ¹⁶ / cm ² .

As shown in FIG. 2, the depletion layer immediately before the avalanche breakdown (critical state) in the present invention grows to a region sandwiched between the boundaries 12 and 14, but the depletion layer immediately before the avalanche breakdown (critical state) in the conventional technique. The depletion layer grows only up to the region between the boundaries 12 and 13. The reason is as described above.

The portion of the depletion layer where the electric field is most severe is near the surface of the P-type semiconductor substrate 1, and the electric field intensity distribution in this portion is shown in FIG.

The critical electric field shown in FIG. 3 is an electric field that causes avalanche breakdown, and the portion of the depletion layer where the electric field is most severe is near the surface of the P-type semiconductor substrate 1, and when the semiconductor substrate 1 is made of silicon. , Its critical electric field is 300-50
0 KV / cm.

In FIG. 3, the buried floating drain diffusion layer 5
The electric field intensity distribution in the present invention in which is formed is between 0 and C as shown by a curve 17, and is narrow as between 0 and B in the conventional technology in which the buried floating drain diffusion layer 5 is not formed.

In FIG. 3, the area surrounded by the electric field intensity distribution curve 16 or 17 and the horizontal axis is the breakdown voltage.
As is apparent from the above description, in the present invention, by forming the buried floating drain diffusion layer 5, it is possible to greatly improve the breakdown voltage.

According to the present invention, not only the depletion layer can be made to grow more, but also the uniformization of the electric field in the depletion layer is promoted. It is possible to improve the breakdown voltage.

In the prior art, in order to improve the breakdown voltage, the drain high-concentration diffusion layer 2 has a relatively low concentration and protrudes from the drain high-concentration diffusion layer 2 toward the region of the gate electrode 7 as shown in FIG. Although the middle-concentration extended drain diffusion layer 18 for reducing the electric field of the same conductivity type is additionally formed, in the first embodiment of the present invention, it is not necessary to additionally form the middle-concentration extended drain diffusion layer 18 for relaxing the electric field. Not something.

Further, if a medium-concentration extended drain diffusion layer 18 for relaxing the electric field is additionally formed as in the prior art, the breakdown voltage is improved, but the on-resistance and the area occupied by the transistor are increased. However, Embodiment 1 of the present invention
Then, the medium-concentration extended drain diffusion layer 18 for relaxing the electric field
Need not be additionally formed, it is possible to prevent an increase in the on-resistance and the area occupied by the transistor.

In the first embodiment of the present invention, in order to form the buried floating drain diffusion layer 5, it is necessary to add a mask step and a high-energy ion implantation step once each in the manufacturing process. Considering that the mask step and the ion implantation step are required once for improving the breakdown voltage by forming the medium-concentration extended drain diffusion layer 18 for alleviating the electric field also in the conventional example, it is necessary to improve the breakdown voltage in the present invention. Necessary manufacturing steps are not added as compared with the conventional example, and the number of manufacturing steps is not increased.

Therefore, in the first embodiment of the present invention, the depletion layer is expanded below the second conductivity type drain diffusion layer 2 and the electric field intensity near the surface of the first conductivity type semiconductor substrate 1 is made uniform. By enabling the breakdown voltage to be increased, the breakdown voltage can be greatly improved without increasing the number of manufacturing steps, the ON resistance, and the area occupied by the transistor.

In the first embodiment of the present invention, an N-type buried floating drain diffusion layer 5 is formed in an N-channel transistor widely used for CMOS logic having a rated voltage of 7 V and a breakdown voltage of about 10 to 12 V. The breakdown voltage is increased to about 15 to 18 V, and can be used as an output transistor for driving a load having a rated voltage of about 10 V.

(Embodiment 2) FIG. 6 shows Embodiment 2 of the present invention.
FIG. 7 is a cross-sectional view showing a semiconductor device according to the first embodiment, and FIG. 7 is a diagram showing a growth state of a depletion layer when a bias close to a critical state is applied between a drain and a source in an off state according to the second embodiment of the present invention.

In the first embodiment of the present invention, the case where the present invention is applied to a 7V-rated N-channel transistor for CMOS logic and can be applied to a higher rated voltage has been described as an example. It is not limited to the example.

That is, in the prior art, in order to improve the breakdown withstand voltage, as shown in FIG.
A middle-concentration extended drain diffusion layer 18 having a relatively low concentration and the same conductivity type as that of the drain high-concentration diffusion layer 2 is formed so as to protrude toward the region of the gate electrode 7. By applying the present invention to the structure shown in FIG. 4, it is possible to further improve the applicable rated voltage.

Next, the semiconductor device according to the present invention shown in FIG. 6 will be described. In the semiconductor device of the present invention shown in FIG. 6, a second conductivity type drain diffusion layer 2 is formed on a main surface of a first conductivity type semiconductor substrate 1, and a first conductivity type semiconductor separated from the second conductivity type drain diffusion layer 2. The second conductive type source diffusion layer 3 is formed on the main surface of the substrate 1, and the first conductive type semiconductor substrate 1 is sandwiched between the second conductive type drain diffusion layer 2 and the second conductive type source diffusion layer 3. A field effect transistor in which a gate insulating film 6 is formed on the surface and a gate electrode 7 is formed on the gate insulating film 6, wherein a depletion layer is expanded in a region below the second conductivity type drain diffusion layer 2, The configuration in which the electric field strength near the substrate surface is made uniform and the breakdown voltage can be increased has the commonality with the semiconductor device of the present invention shown in FIG.

The semiconductor device according to the present invention shown in FIG. 6 has a buried floating drain of the second conductivity type in a region below the second conductivity type drain diffusion layer 2 without contacting the second conductivity type drain diffusion layer 2. A diffusion layer 5 is formed, which has a function of expanding a depletion layer mainly in a region below the drain diffusion layer 2 of the second conductivity type. , And is formed so as to protrude toward the gate region side to provide an electric field relaxation effect.

A specific example of the semiconductor device according to the present invention shown in FIG. 6 will be described as a second embodiment. The second embodiment of the present invention shown in FIG. 6 is different from the first embodiment of the present invention shown in FIG. 1 in that it comprises an N-type high-concentration drain diffusion layer 2, a gate oxide film 6 and a gate electrode 7. Between the gate region
A donor concentration of about ¹⁷ / cm ² and a junction depth of 0.4
This is because the N-type medium-concentration extended drain diffusion layer 18 having a length of about 2 μm and a horizontal length of about 2 μm is formed.

The N-type medium-concentration extended drain diffusion layer 18 according to the second embodiment of the present invention
And is formed so as to protrude toward the gate region side so as to have an electric field relaxation effect, and play a role of improving the breakdown voltage between the drain and the source.

In the second embodiment of the present invention, the breakdown voltage in the absence of the N-type buried floating drain diffusion layer 5 is 10 to 12 V by providing the N-type medium-concentration extended drain diffusion layer 18. On the other hand, the breakdown voltage is 15 to 1
The voltage can be increased up to 8V, and application to a rated voltage of about 10V becomes possible.

Further, in the second embodiment of the present invention, the N-type buried floating drain diffusion layer 5 is provided by providing the N-type buried floating drain diffusion layer 5 in addition to the N-type medium-concentration extended drain diffusion layer 18. The breakdown voltage is improved by the combined use of the middle-concentration extended drain diffusion layer 18. By forming the N-type buried floating drain diffusion layer 5, only the N-type medium-concentration extended drain diffusion layer 18 is provided. 15 ~
Although the voltage is 18 V, the breakdown voltage can be improved to 23 to 27 V, and application to a rated voltage of about 10 V becomes possible.

In the second embodiment of the present invention, the improvement of the breakdown voltage by forming the N-type buried floating drain diffusion layer 5 is as follows.
As in the first embodiment of the present invention, this can be achieved without increasing the on-resistance and the area occupied by the chip.

The reason why the breakdown voltage is improved in the second embodiment of the present invention is that the electric field in the depletion layer near the surface of the semiconductor substrate 1 is made more uniform than the depletion layer can be grown more. The dominant factor is dominant.

That is, in FIG. 7, the gate electrode 7 is turned off, and a depletion layer which grows according to the voltage applied between the drain and the source is formed in the region below the drain diffusion layer 2 with the applied voltage. The depletion layer is expanded by contacting the buried floating drain diffusion layer 5 when a value determined by the buried floating drain diffusion layer 5 reaches the value determined by the diffusion layer structure of the buried floating drain diffusion layer 5. The free carrier trapped in the buried floating drain diffusion layer 5 is removed by contacting the layer 5 and eliminating the built-in potential barrier between the drain diffusion layer 2 and the buried drain diffusion layer 5.
The buried floating drain diffusion layer 5 is depleted by being drawn toward the drain diffusion layer 2 by the electric field of the depletion layer, and the space charge formed in the buried floating drain diffusion layer 5 by depletion of the buried floating drain diffusion layer 5 is reduced. The depletion layer is grown outward from the buried floating drain diffusion layer 5 until the total amount is neutralized (boundary 14).

The improvement of the breakdown voltage by providing the buried floating drain diffusion layer 5 is the same as the reason described with reference to FIGS. 2 and 3 in the present invention shown in FIG.

Further, in the present invention shown in FIG. 6, the depletion layer growing outward from the drain diffusion layer 2 comes into contact with the N-type buried floating drain diffusion layer 5 and at a stroke. Is further grown from the N-type buried floating drain diffusion layer 5 to the outside. At the depth of the buried floating drain diffusion layer 5, the depletion layer grows so as to extend to the gate region, and the semiconductor substrate surface The electric field in the depletion layer in the vicinity becomes more uniform.

Therefore, according to the present invention shown in FIG. 6, the depletion layer is formed in the depth portion of the buried floating drain diffusion layer 5 more than the growth of the depletion layer due to the provision of the N-type buried floating drain diffusion layer 5. By growing so as to extend to the gate region, the electric field in the depletion layer in the vicinity of the surface of the semiconductor substrate 1 becomes more uniform, so that the breakdown voltage can be improved.

Although the present invention shown in FIGS. 1 and 6 shows an example in which the second conductivity type drain diffusion layer 2 has a single-layer structure, the present invention is not limited to this. The drain diffusion layer 2 may be composed of at least two layers of a high concentration layer having a relatively high impurity concentration of the second conductivity type and a low concentration layer having a relatively low impurity concentration of the second conductivity type. .

[0078]

As described above, according to the present invention, a high breakdown voltage can be realized without increasing the on-resistance and the occupied area of the transistor.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a semiconductor device according to the present invention.

FIG. 2 is a cross-sectional view showing a depletion layer formation state immediately before avalanche breakdown (critical state) in an off state according to the present invention.

FIG. 3 is a cross-sectional view showing an electric field intensity distribution state in an off state according to the present invention.

FIG. 4 is a sectional view showing a semiconductor device according to a conventional example.

FIG. 5 is a cross-sectional view showing a state of formation of a depletion layer immediately before avalanche breakdown in an off state (critical state) in a conventional example.

FIG. 6 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.

FIG. 7 is a diagram illustrating a growth state of a depletion layer when a bias close to a critical state is applied between a drain and a source in an off state according to the second embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 P-type semiconductor substrate 2 N-type high-concentration drain diffusion layer 3 N-type high-concentration source diffusion layer 4 P-type high-concentration substrate contact diffusion layer 5 N-type buried floating drain diffusion layer 6 Gate oxide film 7 Gate electrode 8 Drain electrode 9 Source electrode 10 Field oxide film 11 Interlayer insulating film 12 Drain potential side depletion layer boundary in critical state 13 Source potential side depletion layer boundary in critical state 14 Source potential side depletion layer boundary in critical state 16 Electric field intensity distribution curve 17 Electric field intensity distribution Curve 18 N-type medium-concentration extended drain diffusion layer

Claims (11)

[Claims] A second conductive type drain diffusion layer formed on a main surface of the first conductive type semiconductor substrate; and a second conductive type drain diffusion layer separated from the second conductive type drain diffusion layer on a main surface of the first conductive type semiconductor substrate. A conductive type source diffusion layer is formed, and a gate insulating film is formed on a main surface of the first conductive type semiconductor substrate sandwiched between the second conductive type drain diffusion layer and the second conductive type source diffusion layer. In a field effect transistor having a gate electrode formed on the gate insulating film, a depletion layer is expanded particularly in a region below the second conductivity type drain diffusion layer, and an electric field intensity near a substrate surface is made uniform. A semiconductor device characterized in that the breakdown voltage can be increased. 2. A buried drain diffusion layer of the second conductivity type is formed directly under the drain diffusion layer of the second conductivity type without being in contact with the drain diffusion layer of the second conductivity type. 2. The semiconductor device according to 1. 3. The method according to claim 1, wherein the gate electrode is turned off, and a depletion layer grown from the second conductivity type drain diffusion layer is changed according to a voltage value applied between the drain and the source. When reaching a value determined by a diffusion layer structure extending from the two-conductivity-type drain diffusion layer to a second-conductivity-type buried drain diffusion layer formed in a region below the second-conductivity-type drain diffusion layer, The depletion layer is further formed by contacting the buried floating drain diffusion layer of the second conductivity type.
3. The semiconductor device according to claim 2, wherein the semiconductor device is expanded until the buried drain diffusion layer of the second conductivity type is completely contained. 4. 4. The expanded depletion layer contacts the second conductivity type buried floating drain diffusion layer to reduce the built-in potential between the second conductivity type drain diffusion layer and the second conductivity type buried drain diffusion layer. The barrier is eliminated, and the free carriers confined in the second conductive type buried floating drain diffusion layer are drawn into the second conductive type drain diffusion layer side by the electric field of the depletion layer, and the second conductive type buried floating drain diffusion layer is drawn. Depleting the drain diffusion layer and depleting the second-conductivity-type buried floating drain diffusion layer until the total amount of space charges formed in the second-conductivity-type buried floating drain diffusion layer is neutralized.
The semiconductor device according to claim 2, wherein the depletion layer is grown outward from the buried floating drain diffusion layer of the second conductivity type. 5. A donor of the second conductivity type drain diffusion layer.
Concentration 10¹⁹/ Cm ^TwoThe second conductive
Donor concentration of the type-buried floating drain diffusion layer is 10¹⁶/ Cm
^TwoThe semiconductor according to claim 4, wherein:
apparatus. 6. When the depth of the junction of the second conductivity type drain diffusion layer is about 0.5 μm, the depth of the junction of the second conductivity type buried floating drain diffusion layer is .0
The semiconductor device according to claim 4, wherein the thickness is about μm and the lower part is about 2.0 μm. 7. The electric field intensity near the surface of the semiconductor substrate is reduced by the influence of the growth of the depletion layer extending laterally in the direction of the gate region at the depth of the buried floating drain diffusion layer of the second conductivity type. 2. The semiconductor device according to claim 1, wherein the breakdown voltage is improved by the modification. 8. The drain layer of the second conductivity type, comprising:
2. The semiconductor device according to claim 1, wherein the semiconductor device comprises at least two layers of a high concentration layer having a relatively high conductivity type impurity concentration and a low concentration layer having a relatively low second conductivity type impurity concentration. . 9. A buried drain diffusion layer of the second conductivity type is formed immediately below the drain diffusion layer of the second conductivity type without being in contact with the drain diffusion layer of the second conductivity type. The depletion layer is expanded in a region below the drain diffusion layer, and the second-conductivity-type medium-concentration extension drain layer is formed so as to protrude from the second-conductivity-type drain diffusion layer toward the gate region to form an electric field near the substrate surface. 2. The semiconductor device according to claim 1, wherein the semiconductor device has a relaxing action and a promoting action of growth of a depletion layer. Wherein said second donor concentration of the conductive type drain diffusion layer 10 ¹⁹ / cm ² or so, the depth of the junction 0.
10. The method according to claim 9, wherein when the thickness is about 5 μm, the second-conductivity-type medium-concentration extended drain layer has a donor concentration of about 10 ¹⁷ / cm ² and a junction depth of about 0.4 μm. 13. The semiconductor device according to claim 1. 11. The semiconductor device according to claim 9, wherein the breakdown voltage is improved by making the electric field in the depletion layer near the surface of the semiconductor substrate more uniform than the expansion growth of the depletion layer.