JP2008130724A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress a deterioration in characteristic caused by an increase in temperature and a time lapse variation in threshold caused by electrical charges in a film and/or an interface of a MOS semiconductor element. <P>SOLUTION: FETs 1, 2, 3 are formed on an identical substrate. The identical gate voltage of the FET 1 is applied to the FET 2 by a switch 16. The fluctuation in the threshold voltage due to the elctrical charges in the film and/or the interface is detected by comparing the threshold voltages of the FET 2, 3 with a comprator 18 at the time of non-conductive condition of the FET 1. The temperature of the element is also detected by means of the threshold voltage of the FET 3. A gate voltage control circuit 22 controls the gate voltage of the FET 1 on the basis of the temperature of the element and the flucuation in the threshold voltage. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to suppression of threshold voltage fluctuation of an insulated gate element.

  In the field of power electronics, insulated gate type or MOS type power devices such as MOSFETs and IGBTs are often used, and switching of MOS type elements is performed by controlling gate voltage. A gate-source voltage at which a constant voltage VD is applied between the drain and source and the drain current becomes a set current value is referred to as a threshold voltage Vth. This threshold voltage changes depending on the in-film charge / interface charge generated in the gate oxide film by the gate electric field and the element temperature.

The threshold voltage fluctuation can be expressed by the following equation.
ΔVth = ΔVth _aging + ΔVth _temp (1)
Here, Δth _aging is a change over time due to the charge in the film and the interface charge, and Δth _temp is a temperature change of the threshold voltage. Since the generated in-film charges and interface charges are accumulated with time, Δth _aging does not become zero even when the gate electric field is removed, but Δth _temp becomes zero when the temperature returns to the reference temperature.

Incidentally, the current-voltage characteristic of the MOSFET can be expressed by the following equation.
ID = μCoxW / 2L · {2 (VG−Vth) VD−VD ² } (2)
As shown in Expression (2), the threshold voltage Vth plays an important role in the conduction characteristics of the FET. Conventionally, it is possible to capture the temperature characteristic ΔVth _temp of the threshold voltage in the system design. However, the threshold voltage fluctuation ΔVth _aging due to the charge in the film and the interface charge deviates from the original system design when the threshold voltage fluctuates due to the oxide film alteration due to the gate electric field, so that the element temperature is within the allowable range. May rise further.

  Further, when a void is generated in the solder material for fixing the power device to the mounting substrate or the thermal conductive grease is changed, the cooling characteristics are lowered, and the element performance is lowered as the element temperature is increased.

  In the following patent document, a technology is disclosed in which a power device such as an IGBT and a temperature detection element are integrated on the same semiconductor substrate to protect the IGBT by heating. A PN diode is used as the temperature detection element. A constant current that is weak from the constant current source is passed in the forward direction, and the temperature is detected by detecting the forward voltage of the PN diode.

JP-A-8-316471

However, the above-described conventional technology cannot cope with the threshold voltage fluctuation Δth _aging due to the charge in the film and the interface charge even though it can cope with the threshold voltage fluctuation ΔVth _temp due to the temperature rise.

  An object of the present invention is to provide a semiconductor device that can cope with threshold voltage fluctuations due to in-film charges and interface charges.

The present invention includes a first insulated gate element formed on a semiconductor substrate, a second insulated gate element formed on the semiconductor substrate and applied with the same gate voltage as the first insulated gate element,
A third insulated gate element formed on the semiconductor substrate; and a first insulated gate element based on a difference between a threshold voltage of the second insulated gate element and a threshold voltage of the third insulated gate element. Detecting means for detecting a time-dependent variation due to an in-film charge or an interface charge generated in a threshold voltage of the first and a control means for controlling a gate voltage of the first insulated gate element based on the detected time-dependent variation. It is characterized by having.

  The present invention also includes a first insulated gate element formed on a semiconductor substrate, a second insulated gate element formed on the semiconductor substrate and applied with the same gate voltage as the first insulated gate element, The first insulated gate element based on a difference between a threshold voltage of the second insulated gate element and a threshold voltage having no change over time based on an element temperature detected from a leakage current of the second insulated gate element. Detecting means for detecting a time-dependent variation due to an in-film charge or an interface charge generated in a threshold voltage of the first and a control means for controlling a gate voltage of the first insulated gate element based on the detected time-dependent variation. It is characterized by having.

  According to the present invention, the change in threshold voltage over time due to the in-film charge and interface charge of the insulated gate element is detected, and the gate voltage of the insulated gate element is controlled based on the detected threshold voltage fluctuation. Can be suppressed.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings, taking a MOSFET as an example of an insulated gate element.

<First Embodiment>
FIG. 1 shows the configuration of the semiconductor device according to this embodiment. Three FETs 1, 2, and 3 having the same characteristics are formed on the same semiconductor substrate (chip).

  The FET 1 is a main element (control target element), and has a P-body 10a, an n + channel region, a gate oxide film 10c, a gate electrode 10 and a source electrode 10e on a silicon substrate. The FET 2 is a fluctuation detecting element and is formed adjacent to the FET 1 on the same silicon substrate, and has a P− body region 12a, an n + channel region 12b, a gate oxide film 12c, a gate electrode 12d, a source electrode 12e, and a drain electrode 12f. . FET3 is a reference element, which is formed adjacent to FET1 and FET2 on the same silicon substrate, and includes a P-body region 14a, an n + channel region 14b, a gate oxide film 14c, a gate electrode 14d, a source electrode 14e, and a drain electrode 14f. Have. Since the three FETs 1, 2, and 3 are formed on the same chip, manufacturing variations between elements and temperature differences between elements are suppressed.

  FIG. 2 shows a circuit diagram of FIG. The source terminal of the FET 1 is connected to the power supply Vcc, and the drain terminal is set to the ground potential. The gate terminal is connected to the gate voltage control circuit 22, and the gate voltage control circuit 22 controls the gate voltage of the FET 1. Further, the source terminal of the FET 2 is connected to the constant voltage V +, the drain terminal is set to the ground potential, and the gate terminal is connected to the switch 16.

  The switch 16 has an a contact and a b contact. The a contact is connected to the gate voltage control circuit 22, and the b contact is connected to the comparator 18. When the switch 16 is switched to the a contact side, the same gate voltage is applied to the gate terminal of the FET 1 and the gate terminal of the FET 2. The FET 3 has a source terminal connected to a constant voltage V +, a drain terminal set to a ground potential, and a gate terminal connected to a comparator 18 and a processing circuit 20 having a threshold temperature characteristic database.

  The processing circuit 20 accesses a database storing the relationship between the threshold voltage and the temperature, and the temperature corresponding to the threshold voltage of the FET 3, that is, the gate-source voltage Vth3 at which the drain current of the FET 3 becomes the set current value. Tj is extracted. The threshold temperature characteristic database is configured by measuring the threshold voltage of the FET 3 at various temperatures in advance and storing it in a memory. In general, the threshold voltage decreases as the temperature increases. Since the temperature and the threshold voltage correspond to 1: 1, the temperature can be uniquely obtained by detecting the threshold voltage Vth3 of the FET3. Since the FETs 1, 2, and 3 are formed adjacent to each other on the same chip, the temperature of the FET 3 can be regarded as being equal to the temperature of the FET 1, and the temperature Tj detected by the processing circuit 20 can be regarded as the temperature of the FET 1. it can. The processing circuit 20 outputs the extracted temperature Tj to the gate voltage control circuit 22.

When the switch 16 is switched to the b contact side, the comparator 18 inputs the threshold voltage Vth2 of the FET2 and the threshold voltage Vth3 of the FET3, and compares both threshold voltages. The comparison result is the threshold voltage variation ΔVth _aging due to the charge in the film and the interface charge. That is, since the FETs 1 and 2 are arranged close to each other on the same chip, the element temperatures are equal to each other, and the threshold fluctuation Δth _temp due to the temperature is also equal. Further, when switching the switch 16 to a contact side, because equal gate voltage from the gate voltage control circuit 22 to the gate terminal of the gate terminal and the FET2 of the FET1 is applied, variation due to the film in the charge-interface charge .DELTA.th _aging Are also equal. On the other hand, the element temperature of the FET 3 is equal to the element temperature of the FETs 1 and 2 and has the same temperature variation Δth _temp as the FETs 1 and 2, but does not have Δth _aging because the gate voltage applied to the FETs 1 and 2 is not applied. . Therefore, by calculating the difference between the threshold voltage Vth3 of the threshold voltage Vth2 and FET3 of FET2, so that the fluctuation .DELTA.th _aging by film charges and interface charges contained in the FET2 is obtained.

Since the gate voltage at the time of measuring the threshold value Vth2 of the FET 2 is sufficiently lower than the gate voltage at the time of operation, the damage to the gate oxide film at the time of measuring the threshold value is very small compared with the time of operation and can be ignored. . The comparator 18 outputs Vth _aging detected by the comparison to the gate voltage control circuit 22.

The gate voltage control circuit 22 controls the gate voltage of the FET 1 based on the temperature Tj from the processing circuit 20 and Δth _aging from the comparator 18 and controls the operation of the FET 1.

FIG. 3 shows a processing flowchart of the present embodiment. First, when the FET 1 is conductive, the switch 16 is switched to the contact a side, and the same gate voltage as that of the FET 1 is applied to the gate terminal of the FET 2 (S101). In the FET 2, a threshold voltage variation Δth _aging due to the in-film charge / interface charge similar to the FET 1 occurs.

  Next, when the FET 1 is non-conductive, the switch 16 is switched to the b contact side, a set current is supplied to the FET 2 and FET 3, and the respective threshold voltages Vth2 and Vth3 are detected. The threshold voltages Vth2 and Vth3 are supplied to the comparator 18. The threshold voltage Vth3 is also supplied to the processing circuit 20.

  The processing circuit 20 calculates a temperature Tj corresponding to the detected threshold voltage Vth3 using the threshold temperature characteristic database. The temperature Tj is the temperature of the chip on which the FETs 1, 2, and 3 are formed, and is the element temperature of the FETs 1, 2, and 3. The calculated temperature Tj is supplied to the gate voltage control circuit 22.

  The gate voltage control circuit 22 compares the input temperature Tj with the element temperature upper limit Tjmax (S104). If Tj> Tjmax, the element temperature has exceeded the upper limit of the element temperature, and the gate voltage control circuit 22 immediately sets the gate voltage of the FET1 to zero and immediately stops the operation of the FET1 (S107). Thereby, the characteristic deterioration of FET1 by the temperature rise, or destruction of FET1 is prevented.

On the other hand, as a result of comparing the input temperature data Tj and Tjmax, when Tj ≦ Tjmax, the comparator 18 calculates ΔVth _aging by comparing Vth2 and Vth3. In particular,
Vth2 = Vth _init + ΔVth _aging + ΔVth _temp (3)
And
Vth3 = Vth _init + ΔVth _temp (4)
Because
ΔVth _aging = V2−V3 (5)
ΔVth _aging is calculated by (S105). Here, Vth _init is an initial threshold voltage (no variation with time) of FET2 and FET3. The gate voltage control circuit 22 receives ΔVth _aging from the comparator 20, and based on this, sets the gate voltage to be applied to the gate terminal of the FET 1 when the next FET 1 is turned on (S106). The gate voltage Vg is
Vg = Vg _init + ΔVth _aging (6)
Set by. Here, Vg _init is an initial gate voltage. Since the threshold voltage Vth fluctuates only [Delta] Vth _aging content, increasing the gate voltage by [Delta] Vth _aging component to compensate for this variation. This not only prevents device destruction due to temperature rise, but also suppresses threshold voltage fluctuations due to in-film charges and interface charges, thereby maintaining the initial set value.

  As described above, in this embodiment, the FET 2 and the FET 3 are formed on the same chip in addition to the FET 1, and a gate voltage similar to that of the FET 1 is applied to the FET 2 so that the threshold value due to the film charge / interface charge similar to the FET 1 A voltage variation and a temperature variation are applied, and only a temperature variation is applied to the FET 3 without applying an in-film charge / interfacial charge, the FET 3 is used as a temperature detection element using the FET 3 to detect the temperature, and By detecting the fluctuation of the charge in the film and the interface charge using the FET 2, it is possible to control the gate voltage of the FET 1 by detecting both the fluctuation due to the charge in the film and the interface charge of the FET 1 and the temperature fluctuation. In the present embodiment, since the FET 3 functions as a temperature detection element, it is not necessary to separately provide a temperature sensor having a different element structure (for example, a P / N diode).

<Second Embodiment>
FIG. 4 shows the configuration of the semiconductor device according to this embodiment. Two FETs 1 and 2 are formed on the same semiconductor substrate. FET1 is a main element, and FET2 is a fluctuation detecting element. The configuration of the FET 1 is the same as the configuration of the FET 1 in FIG. 1, and includes a P-body 10a, an n + channel region, a gate oxide film 10c, a gate electrode 10 and a source electrode 10e on a silicon substrate. The FET 2 has the same configuration as the FET 2 in FIG. 1 and is formed adjacent to the FET 1 on the same silicon substrate, and includes a P− body region 12a, an n + channel region 12b, a gate oxide film 12c, a gate electrode 12d, a source electrode 12e, and It has a drain electrode 12f. In FIG. 1, the fluctuation due to the film charge / interface charge is detected by the FET 2, and the temperature fluctuation is detected by the FET 3, but in this embodiment, the fluctuation due to the film charge / interface charge and the temperature fluctuation are detected by the FET 2. Are detected together. Specifically, the temperature fluctuation is detected by the leakage current of FET2.

  FIG. 5 shows the temperature dependence of the relationship between the gate voltage Vg of FET2 and the collector current Ic. Both the leak current and the threshold voltage increase with the element temperature of the FET 2. On the other hand, FIG. 6 shows the inter-film charge / interface charge dependency of the relationship between the gate voltage Vg of the FET 2 and the collector current Ic. The leakage current is hardly affected by the charge in the film and the interface charge, and the threshold voltage is affected by the charge in the film and the interface charge. 5 and 6, it is understood that the element temperature of the FET 2 can be detected by detecting the leakage current of the FET 2 regardless of the influence of the charge in the film and the interface charge.

  FIG. 7 shows a circuit diagram of FIG. The source terminal of the FET 1 is connected to the power supply Vcc, and the drain terminal is set to the ground potential. The gate terminal is connected to the gate voltage control circuit 22. The source terminal of the FET 2 is connected to the constant voltage V + and the ammeter 26, the drain terminal is set to the ground potential, and the gate terminal is connected to the switch 16. The switch 16 has an a contact and a b contact, the a contact is connected to the gate voltage control circuit 22, and the b contact is connected to the transformer and the voltmeter 28. The threshold voltage Vth2 detected by the voltmeter 28 is supplied to the comparator 24. The leak current detected by the ammeter 26 is supplied to the processing circuit 21.

  The processing circuit 21 has a temperature characteristic database of leakage current, reads the temperature Tj corresponding to the detected leakage current, outputs it to the processing circuit 20, and outputs it to the gate voltage control circuit 22.

  The processing circuit 20 has a threshold temperature characteristic database as in the first embodiment, reads the threshold voltage Vth ′ corresponding to the temperature Tj, and outputs it to the comparator 24. In the first embodiment, the processing circuit 20 calculates the temperature Tj from the threshold voltage Vth2. However, in this embodiment, it should be noted that the threshold voltage Vth ′ is calculated from the temperature Tj. . The threshold voltage Vth2 detected by the voltmeter 28 is a threshold voltage having both the fluctuation in the film charge / interfacial charge and the fluctuation in temperature, while the threshold voltage calculated by the processing circuit 20 is present. The voltage Vth ′ is a threshold voltage including only temperature fluctuation.

The comparator 24 compares the threshold voltage Vth2 from the voltmeter 28 with the threshold voltage Vth ′ from the processing circuit 20, calculates the variation ΔVth _aging due to the charge in the film and the interface charge, and controls the gate voltage. Output to the circuit 22.

  FIG. 8 shows a processing flowchart of the present embodiment. First, when the FET 1 is conductive, the switch 16 is switched to the contact a side, and the same gate voltage is applied to the FET 1 and FET 2 from the gate voltage control circuit 22 (S201). Accordingly, the FET 2 is given the same temperature fluctuation as the FET 1 and fluctuation due to the charge in the film and the interface charge.

  Next, when the FET 1 is non-conductive, the switch 16 is switched to the b-contact side to apply a voltage between the source and drain of the FET 2, and the voltage between the gate and source is changed by a transformer to obtain the threshold voltage Vth2. The leakage current IL2 is detected (S202). The leak current IL2 is supplied to the processing circuit 21, and the threshold voltage Vth2 is supplied to the comparator 24. The processing circuit 21 calculates the temperature Tj corresponding to the detected leak current IL2 using the temperature characteristic database of the leak current (S203). This temperature Tj is the chip temperature and is the element temperature of the FETs 1 and 2. The calculated temperature Tj is supplied to the gate voltage control circuit 22. The gate voltage control circuit 22 compares the temperature Tj with the element upper limit temperature Tjmax. If Tj> Tjmax, it means that the temperature has exceeded the upper limit temperature of the element, and therefore the gate voltage Vg applied to the FET 1 is set to zero and the operation of the FET 1 is immediately stopped (S208). As a result, the characteristic deterioration or element destruction due to the temperature rise of the FET 1 is prevented.

On the other hand, when Tj ≦ Tjmax, the processing circuit 20 calculates the threshold voltage Vth ′ at the temperature Tj using the threshold temperature characteristic database (S205). This Vth ′ is a threshold voltage that includes only the temperature variation without variation due to the charge in the film and the interface charge (no variation with time). The comparator 24 calculates a variation ΔVth _aging due to the charge in the film and the interface charge from the threshold voltage Vth2 detected by the FET 2 and the threshold voltage Vth ′ calculated by the processing circuit 20 (S206). That is,
Vth2 = Vth _init + ΔVth _aging + ΔVth _temp (7)
And
Vth ′ = Vth _init + ΔVth _temp (8)
Because
ΔVth _aging = Vth2−Vth ′ (9)
Calculated by The gate voltage control circuit 22 sets the gate voltage Vg applied to the FET 1 when the next FET 1 is conducting in order to compensate for the variation due to the calculated variation ΔVth _aging Vg = Vg _init + ΔVth _aging (10)
(S207). As a result, it is possible to prevent element destruction due to temperature rise and to suppress fluctuations due to in-film charges and interface charges.

As described above, in this embodiment, only two FETs 1 and 2 can suppress element breakdown due to temperature rise and threshold voltage fluctuation due to in-film charge / interface charge. In the first embodiment, the temperature is detected using the temperature characteristic of the threshold voltage of the FET 3, so that the temperature detection characteristic is close to linear. In the second embodiment, the temperature is adjusted using the leakage current of the FET 2. Since it detects, it has a temperature detection characteristic close to an exponential function. In the case of a temperature detection characteristic close to an exponential function, there is a concern that the detection accuracy may be lowered particularly in a low temperature region, but in the case of a power device such as this embodiment, the element temperature is driven at a relatively high temperature. The detection accuracy is not a problem. In a power device, ΔVth _aging particularly at a high temperature becomes a big problem, but it can be said that the present embodiment functions particularly effectively in such a high temperature region.

  As mentioned above, although embodiment of this invention was described, this invention is not limited to this, A various change is possible. For example, in the present embodiment, MOSFETs are exemplified as the FETs 1, 2, and 3, but an IGBT thyristor or the like may be used. The channel polarity of the FETs 1, 2, and 3 may be either P channel or N channel. The gate structure may be a planar or a trench.

It is a block diagram of 1st Embodiment. FIG. 2 is a circuit diagram of FIG. 1. It is a processing flowchart of a 1st embodiment. It is a block diagram of 2nd Embodiment. It is a graph which shows the relationship between leak current and threshold voltage, and temperature. It is a graph which shows the relationship between a threshold voltage and the charge in a film | membrane, and an interface charge. FIG. 5 is a circuit diagram of FIG. 4. It is a processing flowchart of a 2nd embodiment.

Explanation of symbols

  1 FET (main element), 2 FET (variation detecting element), 3 FET (reference element), 16 switch, 18 comparator, 20, 21 processing circuit, 22 gate voltage control circuit.

Claims (10)

A first insulated gate element formed on a semiconductor substrate;
A second insulated gate element formed on the semiconductor substrate and applied with the same gate voltage as the first insulated gate element;
A third insulated gate element formed on the semiconductor substrate;
Over time due to in-film charges or interface charges generated in the threshold voltage of the first insulated gate element based on the difference between the threshold voltage of the second insulated gate element and the threshold voltage of the third insulated gate element Detection means for detecting fluctuations;
Control means for controlling a gate voltage of the first insulated gate element based on the detected temporal variation;
A semiconductor device comprising: The apparatus of claim 1.
A semiconductor device comprising temperature detecting means for detecting an element temperature based on a threshold voltage of the third insulated gate element. The apparatus of claim 2.
The temperature detecting means has a database for storing a relationship between a threshold voltage and a temperature in advance, and detects the element temperature based on the database and the detected threshold voltage. apparatus. The apparatus according to any one of claims 2 and 3,
The control device controls the gate voltage of the first insulated gate element based on the detected element temperature and the variation with time. The apparatus of claim 4.
The control device controls the gate voltage so as to stop the operation of the first insulated gate element when the detected element temperature exceeds a predetermined upper limit temperature. A first insulated gate element formed on a semiconductor substrate;
A second insulated gate element formed on the semiconductor substrate and applied with the same gate voltage as the first insulated gate element;
The first insulated gate element based on a difference between a threshold voltage of the second insulated gate element and a threshold voltage having no change over time based on an element temperature detected from a leakage current of the second insulated gate element. Detecting means for detecting a change over time due to an in-film charge or an interface charge generated at a threshold voltage of
Control means for controlling a gate voltage of the first insulated gate element based on the detected temporal variation;
A semiconductor device comprising: The apparatus of claim 6.
The detection device includes a database that stores in advance a relationship between a leakage current and a temperature, and detects the element temperature based on the database and the detected leakage current. The device according to any one of claims 6 and 7,
The detection means has a database that stores in advance a relationship between the element temperature and a threshold voltage that does not vary with time, and the time variation of the second insulated gate element based on the database and the detected element temperature. A semiconductor device characterized by detecting a threshold voltage without minute. The device according to any one of claims 6 to 8,
The control device controls the gate voltage of the first insulated gate element based on the detected element temperature and the variation with time. The apparatus of claim 9.
The control device controls the gate voltage so as to stop the operation of the first insulated gate element when the detected element temperature exceeds a predetermined upper limit temperature.

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