JP2008129286A - Image data transfer device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a transfer device of image data in which the disturbance in image display is suppressed. <P>SOLUTION: A digital television 1 comprises a memory 14 which stores image data, processing sections 37, 38 which perform transfer of the image data with the memory 14, and a control circuit 36. The control circuit 36 generates a transfer start signal based on synchronizing signals VA, VB and outputs the signals to the processing sections 37, 38 and in this case, the control circuit executes the interruption processing to interrupt the transfer processing in the previous transfer processing when the previous transfer processing based on the previous generation timing is not yet finished in the generating timing of the transfer start signal. Upon ending of the interruption processing, the control circuit generates the next transfer start signal of the previous generation timing and outputs the signal to the processing sections 37, 38. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an image data transfer device, and more particularly to an image data transfer device that transfers image data between a memory and a transfer circuit.

  Conventionally, there are various apparatuses for processing image data to display an image, such as a digital television and a DVD recorder. For example, in a digital television, an image signal received by an antenna is demodulated to generate display image data, and an image is displayed on a screen such as a liquid crystal panel based on the image data. When displaying video on the screen of a display device such as a liquid crystal panel, the image data stored in the storage device is read, and the image data is output in accordance with the synchronization signal of the display device. By transferring image data for one screen from the storage device to the display device one after another in accordance with the vertical synchronization signal, the display device can correctly display the video.

  As one of the techniques for transferring such image data, there is an image data transfer apparatus disclosed in Patent Document 1. In order to solve the problem that the line synchronization signal is not input and the data transfer is interrupted when the image data transfer device performs DMA transfer of the printer image data line by line. And is configured to continue its data transfer. In addition, it has been proposed that when transfer for one line is not completed within one line cycle, the transfer is interrupted and image data of the next line is transferred.

However, if the technology related to the proposal is applied as it is to the video image data, the transfer side arbitrarily creates a synchronization signal for transfer, so the data transfer cannot be stopped or there is no input of the image data. Therefore, there is a problem that data is transferred, and as a result, the image display is disturbed.
Also, at the start of data transfer, the end of data transfer is confirmed. If the data transfer is in progress, the data transfer will be delayed if the data transfer is interrupted and the transfer is started. There was a problem that data for a period could not be transferred, and as a result, the image display was disturbed.
Japanese Patent Laid-Open No. 2002-318781

  The present invention has been made in view of the above problems, and an object of the present invention is to provide an image data transfer device that suppresses disturbance in image display.

  According to an aspect of the present invention, a memory for storing image data and a transfer start signal connected to the memory via a bus and indicating a transfer start timing of the image data are started. When generating the transfer start signal based on a synchronization signal and a transfer circuit that transfers the image data to and from the memory and outputting the signal to the transfer circuit, at the generation timing of the transfer start signal, When the previous transfer process based on the previous generation timing has not ended, the interruption process for interrupting the transfer process in the previous transfer process is executed, and when the interrupt process ends, the next generation timing next to the previous generation timing is executed. A transfer start signal output control circuit that generates a transfer start signal and outputs the transfer start signal to the transfer circuit.

  According to the present invention, it is possible to realize an image data transfer device that suppresses disturbance in image display.

Embodiments of the present invention will be described below with reference to the drawings.
First, the configuration of the image data transfer apparatus according to the present embodiment will be described with reference to FIG. FIG. 1 is a configuration diagram showing main components of a television receiver including an image data transfer apparatus according to the present embodiment. An example of a digital television is described here as an example of an apparatus that processes image data. However, an apparatus to which the image data transfer apparatus is applied may be a DVD recorder or the like.

  As shown in FIG. 1, a digital television 1 includes a receiving unit 12 that receives a broadcast signal input from an antenna 11 and demodulates the data, a data processing unit 13 that performs image processing and the like, which will be described later, image data, and the like. And a liquid crystal display device (hereinafter referred to as LCD) 15 as a display device for displaying video based on the image data. The memory 14 is connected to the memory control circuit 16.

The data processing unit 13 includes a plurality of image processing circuits that perform various types of image processing. In the present embodiment, the data processing unit 13 is a circuit including an MPEG decoder 21, a capture 22, and a video back-end processing unit 23, and is, for example, a one-chip semiconductor device.
The memory 14 is connected to the bus 24 via the memory control circuit 16. An MPEG decoder 21, a capture 22, and a video back end processing unit 23, each of which is an image processing unit, are also connected to the bus 24. The memory control circuit 16 reads data from the memory 14 via the bus 24 between each image processing unit and the memory 14 in response to commands from the MPEG decoder 21, the capture 22, and the video back-end processing unit 23. , And a circuit for controlling data writing to the memory 14.

  The MPEG decoder 21 is a circuit that decodes the image data from the receiving unit 12 and stores the image data obtained by the decoding in the memory 14. The capture 22 is a circuit that inputs image data from a playback device of a recording medium such as a DVD (Digital Versatile Disc) on which content data is recorded, and accumulates the obtained image data in the memory 14. The video back-end processing unit 23 performs processing such as image quality adjustment, conversion processing from interlace format to progressive format, display processing in a display format designated by a user or the like using a remote controller, etc. Further, this is a circuit for outputting image data to the LCD 15 in a predetermined data format for displaying an image on the LCD 15, for example, in the LVDS format.

  Although not shown, the television 1 includes a decoder that decodes audio data, an audio data processing unit that generates audio output data, and the like. The data processing unit 13 also includes an audio decoder, an audio output unit, and the like. The description is omitted here.

  FIG. 2 is a block diagram showing a detailed configuration of the video back-end processing unit 23. 2 also illustrates components other than the video back-end processing unit 23, such as the memory 14 and the MPEG decoder 21, in order to explain the operation of the video back-end processing unit 23. Also, the internal configurations of the MPEG decoder 21 and the capture 22 are the same as the internal configurations of the video back-end processing unit 23 described below, except for the processing units related to the functions unique to each unit.

  First, the overall configuration will be described. Three processing units, each of which is an image processing unit, an MPEG decoder 21, a capture 22, and a video back-end processing unit 23 perform processing according to the functions of the respective processing units. These three processing units are connected to the bus 24 as described above, and the memory 14 is also connected to the bus 24 via the memory control circuit 16. The memory control circuit 16 performs arbitration processing of commands from the three processing units and control of data transfer between the three processing units and the memory 14 via the bus 24.

  These three processing units operate based on the respective synchronization signals, that is, based on the respective vertical synchronization signals VA, VB, and VC. The MPEG decoder 21 operates on the basis of the vertical synchronization signal VA, the capture 22 operates on the basis of the vertical synchronization signal VB, and the video back-end processing unit 23 operates on the basis of the vertical synchronization signal VC. The vertical synchronization signals VA, VB, and VC are asynchronous. For example, the MPEG decoder 21 is NTSC compatible, the capture 22 is PAL compatible, and the video back end processing unit 23 employs a vertical synchronization signal VC for display, which is different from the vertical synchronization signals VA and VB. This is the case.

  Overall, the image data decoded by the MPEG decoder 21 and the image data obtained by the capture 22 are respectively stored in the memory 14, and the video back-end processing unit 23 writes the data into the memory 14, and In addition to processing such as reading of data from the memory 14, image data is generated in an output format designated by the user or the like using the image data stored in the memory 14, and the LCD 15 is connected via the output circuit 34. Process to output to.

  FIG. 3 is a diagram illustrating an example of a display screen on the LCD 15. The user can cause the television receiver to display a desired screen using a remote controller (not shown). FIG. 3 is a diagram illustrating an example in which the user displays two screens on the screen of the television receiver. In the example of FIG. 3, on the screen of the LCD 15, a second screen 102 for displaying a reproduction image such as a DVD is arranged in the first screen 101 for displaying a broadcast image. The first screen 101 is an image based on the image data from the MPEG decoder 21, and the second screen 102 is an image based on the image data from the capture 22. The first screen 101 is generated according to the synchronization signal of the MPEG decoder 21, that is, the vertical synchronization signal VA. The second screen 102 is generated according to the synchronization signal of the capture 22, that is, the vertical synchronization signal VB. The video back-end processing unit 23 generates a screen of the LCD 15 according to a synchronization signal for displaying an image on the LCD 15, that is, a vertical synchronization signal VC. Here, the MPEG decoder 21, the capture 22, and the video back end processing unit 23 operate based on mutually different synchronization signals. For example, the video back-end processing unit 23 includes image data generated by the MPEG decoder 21 and stored in the memory 14, and image data generated by the capture 22 and stored in the memory 14. A screen as shown in FIG. 3 is generated by performing processing by reading by transfer.

  As will be described later, the control circuit 36 receives the respective synchronization signals VA, VB, VC, and processes data corresponding to the respective synchronization signals of the MPEG decoder 21, the capture 22, and the video back-end processing unit 23. In addition, various timing signals as described later are generated and output so that data can be transferred.

Returning to FIG. 2, the configuration of the video back-end processing unit 23 will be described.
The video back-end processing unit 23 includes a command register 31, an accept command register 32, a data register 33, an output circuit 34, a command arbiter 35, a control circuit 36, an A processing unit 37, and a B processing unit 38. The command register 31, the accept command register 32 and the data register 33 are connected to the bus 24. The data register 33, the output circuit 34, the A processing unit 37 and the B processing unit 38 are connected to the internal bus 39.

  As described above, the video back-end processing unit 23 is a circuit that realizes functions such as image quality adjustment and conversion processing from the interlace format to the progressive format. In this embodiment, the A processing unit 37 is connected to the antenna 11. It is assumed that the received video signal is converted into a progressive format, vertical scaling filter processing, and the like, and the B processing unit 38 performs external signal capture input processing.

  In addition, here, in order to simplify the description, a case where the video back-end processing unit 23 includes only the A processing unit 37 and the B processing unit 38 as processing units will be described. 23 may have other processing units for realizing other functions.

  Therefore, in the video back-end processing unit 23, an A processing unit 37 that operates based on the vertical synchronization signal VA and a B processing unit 38 that operates based on the vertical synchronization signal VB are provided via the data register 33 and the bus 24. Are connected to the memory 14, and write image data to the memory 14 and read image data from the memory 14 in accordance with commands from the A processing unit 37 and the B processing unit 38. As described above, the control circuit 36 of the video back-end processing unit 23 receives the vertical synchronization signal VC at a timing different from the vertical synchronization signals VA and VB, and can operate based on the vertical synchronization signal VC. It has become. As described above, the vertical synchronization signal VC is a vertical synchronization signal for display on the LCD 15.

  The command register 31 is a register that stores various commands input from the A processing unit 37 and the B processing unit 38 through the command arbiter 35. The command register 31 can store a plurality of commands. The various commands include, for example, an image data transfer command from the memory 14 for displaying an image on the LCD 15 and information such as an address of the image data. Furthermore, if the command for writing data to the memory 14 is, for example, a command for writing data for noise reduction processing, or a command for reading data from the memory 14, the frame data before and after data complementing is read out. Is a command.

  The command arbiter 35 is a circuit that arbitrates commands from the A processing unit 37 and the B processing unit 38. The command arbiter 35 writes commands arbitrated according to a predetermined arbitration rule to the command register 31 in the order of arbitration.

  Accordingly, the command register 31 stores a plurality of commands as a result of the arbitration in order.

  The accept command register 33 is a register for storing a command accepted by the memory control circuit 16. The accept command register 33 can store a plurality of accept pro commands such as an accept command indicating permission of image data transfer. When the accept command register 32 receives an accept command from the memory control circuit 16, the accept command register 32 has a control circuit that reads and stores a command corresponding to the accept command from the command register 31.

  The command register 31 and the accept command register 33 will be specifically described. When the command arbiter 35 receives commands from the A processing unit 37 and the B processing unit 38, the command arbiter 35 performs arbitration processing according to a predetermined arbitration rule, and sequentially writes the arbitrated commands into the command register 31. For example, when the B processing unit 38 transfers the image data in the memory 14, the transfer command is supplied to the command arbiter 35. The command arbitrated by the command arbiter 35 is stored in the command register 31.

  The command written in the command register 31 is supplied to the memory control circuit 16 via the bus 24, and execution is permitted, that is, accepted by the memory control circuit 16. The accepted command is written from the memory control circuit 16 to the accepted command register 32 and stored.

  The command stored in the accept command register 32 is permitted to execute, but is not executed until a data transfer request based on the command from the memory control circuit 16 is received. That is, the accept command register 32 transmits the data transfer request to the B processing unit 38 until a data transfer request based on the accepted command is received. The B processing unit 38 performs another process without executing the data transfer process until the data transfer request is received.

  When receiving a data transfer request based on the command from the memory control circuit 16, the accept command register 32 transmits the data transfer request to the B processing unit 38. In the case of writing data to the memory 14, the B processing unit 38 outputs image data to the bus 24 via the internal bus 39 and the data register 33 in accordance with the data transfer request. When a command corresponding to the accept command is executed, the accept command register 32 deletes the accept command.

  When continuously transferring image data, such as when displaying video, the command register 31 stores a plurality of continuous transfer commands for transferring a plurality of image data. The accept command register 32 also stores a plurality of consecutive accept commands corresponding to the plurality of transfer commands. When the accepted commands are transferred in order, the screen image in the format as shown in FIG. 3 is displayed on the screen of the LCD 15. As a result, the user can view the two screens 101 and 102 having the format shown in FIG. The operation of the circuit of FIG. 2 will be described below using an example of image data transfer processing when the display of FIG. 3 is performed.

  The processing circuit such as the A processing unit 37, the command register 31, and the accept command register 32 constitute an image data transfer circuit.

  The A processing unit 37 and the B processing unit 38 operate asynchronously with each other. Each of the A processing unit 37 and the B processing unit 38 transfers image data for one screen, that is, image data for one frame, within the vertical synchronization period (in other words, between two consecutive vertical synchronization signals). To work. Specifically, the A processing unit 37 performs image data transfer processing for the screen 101 in FIG. 3 with reference to the vertical synchronization signal VA, and the B processing unit 38 performs reference to the vertical synchronization signal VA in FIG. Image data transfer processing for the screen 102 is performed, and the control circuit 36 performs image data transfer processing for displaying the screens 101 and 102 of FIG. 3 with reference to the vertical synchronization signal VC.

  Vertical synchronization signals VA, VB, and VC are input to the control circuit 36. The control circuit 36 generates a go (A) signal, a go (B) signal, and a go (C) signal, which are transfer start signals described later, based on the input vertical synchronization signals VA, VB, and VC. The control circuit 36 constitutes a transfer start signal output control circuit. Hereinafter, the go (A) signal, the go (B) signal, and the go (C) signal are collectively or referred to as any one of them.

  Specifically, the go (A) signal and the go (B) signal, which are transfer start signals, are generated in accordance with the respective vertical synchronization signals. As shown in FIG. 2, the control circuit 36 generates go (A) signal and go (B) signal from the vertical synchronization signals VA and VB, and outputs them to the A processing unit 37 and the B processing unit 38, respectively. ing.

  The go (A) signal and go (B) signal are signals related to the start of data transfer. The go (A) signal is a pulse signal generated in the control circuit 36 as described above, and is a synchronization signal generated based on the vertical synchronization signal VA. The go (A) signal and go (B) signal are output so as to become HIGH (hereinafter abbreviated as H) for a predetermined period D. Here, the predetermined period D in the go (A) signal and the go (B) signal is the same, but they may be different from each other.

  Specifically, the go (A) signal is a signal generated based on the vertical synchronization signal VA so that the image to be displayed does not include blanking period data. The go (B) signal is also a signal generated in the control circuit 36 as described above, and is a synchronization signal generated based on the vertical synchronization signal VB. Specifically, the go (B) signal is also a signal generated based on the vertical synchronization signal VB so that the displayed image does not include blanking period data.

  The control circuit 36 uses a go (C) signal generated from the vertical synchronization signal VC as a timing signal for video display on the LCD 15. The go (A) signal, go (B) signal, and go (C) signal are signals that become H for a predetermined period D, respectively. The predetermined period D is, for example, a period of 100 clocks.

  The control circuit 36 monitors the transfer processing of the A processing unit 37 and the B processing unit 38. The control circuit 36 monitors a run (A) signal and a run (B) signal, which are signals indicating the transfer period, that is, a period during which each of the A processing unit 37 and the B processing unit 38 performs data transfer. The run (A) signal and run (B) signal become H at the falling timing of the go (A) signal and go (B) signal, respectively, and LOW (hereinafter referred to as L) when the transfer of data in the transfer area is completed. This is a pulse signal. In other words, the run (A) signal and the run (B) signal are signals generated so as to be H when data transfer is started and to L when data transfer is ended. Hereinafter, the run (A) signal and the run (B) signal are collectively or referred to as any one when they are indicated.

  The control circuit 36 monitors whether or not the run (A) signal and the run (B) signal are H at the falling timing of each of the go (A) signal and the go (B) signal. At the monitoring timing, if at least one of the run (A) signal and the run (B) signal is H, the control circuit 36 performs processing corresponding to at least one of the H (A processing unit 37 and the processing unit 37). At least one of the B processing units 38) determines that the previous image data transfer process has not been completed. In order to start the transfer interruption process in the processing unit determined that the previous transfer process has not been completed, the control circuit 36 aborts the abort (A) signal or abort (B) corresponding to the processing unit. ) Generate a signal. Hereinafter, the abort (A) signal and the abort (B) signal are collectively or referred to as any one of them.

  The control circuit 36 starts interruption processing in response to the occurrence of the abort signal. In the interruption process, the command in the command register 31 related to the processing unit for which it has been determined that the previous image data transfer process has not been completed is deleted or deleted, and the processing unit for which the transfer process has been determined not to have been completed No more commands are stored in the command register 31. Further, the control circuit 36 monitors whether or not the command corresponding to the accept command related to the processing unit for which the transfer process is determined not to be completed in the accept command register 32, and outputs the abort signal to H until it becomes empty. Maintain the state. When the command corresponding to the accept command for the processing unit corresponding to the abort signal is executed and the accept command disappears, the control circuit 36 sets the abort signal to L, ends the interruption process, and then transfers the next transfer control signal. Output go signal. In other words, the control circuit 36 determines that the interruption process has ended when the previous transfer process corresponding to the accept command stored in the accept command register 32 is completed.

The data transfer timing will be described in more detail.
FIG. 4 is a timing chart showing data transfer timings of the A processing unit 37 and the B processing unit 38.
The data transfer start timing is the falling timing ST of each of the go (A) signal and the go (B) signal. Data transfer is started at the timing ST of the A processing unit 37 and the B processing unit 38. By starting the data transfer at the timing ST, data in the blanking period is removed, and only the image data of the display portion can be transferred. When the data transfer is started, the control circuit 36 generates a run (A) signal and a run (B) signal.

  In FIG. 4, the run (A) signal and the run (B) signal are signals indicating that data is being transferred. As described above, data transfer is being performed during the H period. Indicates. The period in which the run (A) signal and the run (B) signal are L is a period indicating that no data is transferred.

  Therefore, the run (A) signal and the run (B) signal are respectively H at the falling timing ST of each of the go (A) signal and the go (B) signal.

  When data is normally transferred, as shown in FIG. 4, data transfer is started in response to the fall of each go (A) signal go (B) signal, and the next go (A ) End before the generation of the signal go (B) signal. Since the generation timings of the vertical synchronization signals VA and VB are different, the generation timings of the go (A) signal go (B) signal are different, but the data transfer processing of the A processing unit 37 and the B processing unit 38 is reliably performed. Done. Therefore, since the image data is transferred by the A processing unit 37 and the B processing unit 38, the video display in the format as shown in FIG. 3 based on the vertical synchronization signal VC is appropriately performed, and the user You can watch the video without disturbing the display.

FIG. 5 is a timing chart showing data transfer timings of the A processing unit 37 and the B processing unit 38 when data transfer is delayed in the capture 22. FIG. 5 is a diagram for explaining a case where the processing of the present embodiment is not performed.
The B processing unit 38 performs processing at the same timing as the image data processed by the capture 22 and the vertical synchronization signal VB. However, for example, when a fast-forward operation of video is performed in the capture 22, the input to the control circuit 36 is performed. The generation timing of the generated vertical synchronization signal VB changes, and here the generation interval is shortened. As such, when the generation timing of the vertical synchronization signal VB changes, the generation timing of the go (B) signal also changes.

  As in case 5A shown in FIG. 5, the generation timing of the go (B) signal may change, and when the next go (B) signal is generated, the previous transfer process may not be completed yet. In that case, even if the abort signal is generated to execute the interruption process, the fall of the go (B) signal of the transfer start signal (hereinafter referred to as the synchronous transfer start signal) when the interruption process is not executed If the previous transfer process is completed by the timing ST, the next image data transfer process can be started.

  However, as in the case 5B shown in FIG. 5, the generation timing of the go (B) signal has changed, and when the next go (B) signal is generated, the transfer processing of the previous image data has not yet been completed. In addition, the transfer process of the previous image data may not be completed even at the timing ST of the fall of the go (B) signal. That is, the synchronous transfer start signal that the go (B) signal rises in synchronization with the vertical synchronization signal VB and falls after a predetermined period D (that is, the transfer start when the interruption process is not executed) Signal), the next data transfer cannot be started at the fall timing ST of the go (B) signal. Since the next image data is not transferred based on the go (B) signal generated based on the vertical synchronization signal VB, the displayed image on the screen 102 is disturbed.

  If the H period of the go (B) signal is set to be longer than the time required for the interruption process, and if an abnormal transfer is detected as described above, the next image data can be obtained. You can start the transfer process. However, depending on input image data, the vertical blanking period may be short. In that case, the H period of the go (B) signal cannot be made sufficiently long, and the end of the H period of abort (B) may be later than the falling timing of the go (B) signal. Then, during the period when the abort (B) signal is H, the run (B) signal remains L as a result, so that the falling timing of the go (B) signal is not detected. The image data corresponding to the synchronization signal cannot be transferred.

Therefore, according to the present embodiment, as shown in FIG. 6, the next image data is reliably transferred.
FIG. 6 is a timing chart showing data transfer timings of the A processing unit 37 and the B processing unit 38 when data transfer is delayed in the capture 22. FIG. 6 is a diagram for explaining the case where the processing of the present embodiment is performed.
As a result of the change in the generation timing of the vertical synchronization signal VB and the generation timing of the go (B) signal, the generation timing of the go (B) signal changes as in the case 6A shown in FIG. When the go (B) signal is generated, the transfer processing of the previous image data may not be completed yet. In that case, even if an abort signal is generated to execute the interruption process, the previous transfer process has been completed by the falling edge ST0 of the go (B) signal, so the transfer of the next image data is performed. Processing can be started. In this case, the go (B) signal is a synchronous transfer start signal that is generated based on the vertical synchronization signal VB, rises (ST0), becomes H for a predetermined period D, and then falls.

  In the case 6A, the control circuit 36 determines whether the run (B) signal is H when the go (B) signal is generated (at the time of rising), and generates an abort (B) signal as a result of the determination. To execute the interruption process. In the interruption process, the control circuit 36 removes or deletes the command from the B processing unit 38 stored in the command register 31, but does not remove the command from the A processing unit 37 stored in the accept command register 32. Not performed.

  Further, the control circuit 36 monitors whether or not execution of commands corresponding to the accept command related to the B processing unit 38 stored in the accept command register 32 has been completed, and all the accept commands related to the B processing unit 38 are detected. When the execution of the command corresponding to is finished, the interruption processing is finished and the abort (B) signal is set to L. The control circuit 36 does not monitor the execution of the command corresponding to the accept command related to the A processing unit 37.

  Even if the interruption process is performed in this way, in the case 6A, the previous transfer process has been completed by the fall timing ST of the go (B) signal, and therefore the transfer process of the next image data is started. Can do.

  In this case, all the image data of the displayed screen 102 may not be transferred due to the interruption process, but the image data that is not transferred is the last of the image data of one frame, so the image disturbance is It is limited to the outside of the display range of the screen 102 or the lower part of the screen 102, if any.

  Furthermore, as in the case 6B shown in FIG. 6, the generation timing of the go (B) signal is changed, and when the next go (B) signal is generated, the previous transfer processing is not yet completed. There may be a case where the previous transfer process has not ended even at the timing when the predetermined period D has elapsed from the rise of the go (B) signal. In that case, in the circuit that outputs the go (B) signal in the control circuit 36, the logical sum (OR) of the go (B) signal and the abort (B) signal so that the next data transfer can be started early. When the abort (B) signal is H (that is, during the interruption process), the go (B) signal is maintained so that the go (B) signal is maintained at the H state. To be output.

  In the interruption process, as described above, the command related to the B processing unit 37 in the command register 31 is deleted. Further, the control circuit 36 monitors whether all the commands related to the B processing unit 37 in the accept command register 32 have been executed, and after all the commands related to the B processing unit 37 have been executed, the abort (B) signal Set to L.

  At this time, only the command related to the B processing unit 38 is erased from the command register 31 in the interruption process, and the command related to the A processing unit 37 operating normally is not erased from the command register 31. Therefore, the execution of the accept command related to the A processing unit 37 in the accept command register 32 is not monitored.

  Then, the control circuit 36 sets the go (B) signal to the L state at timing ST1 when the abort (B) signal becomes L, that is, when the interruption process is completed. Before the go (B) signal goes to the L state, the run (B) signal is already at the L level, so the transfer processing of the next image data is started according to the fall of the go (B) signal. , Run (B) signal also becomes H. That is, the control circuit 36 maintains the go (B) signal in the H state until the interruption process ends, and when the interruption process ends, sets the go (B) signal to L and transfers the next image data. A signal indicating the start timing of the next transfer to be started, in this case, the falling edge of the go (B) signal is generated. As a result, the run (B) signal also falls for a moment and then becomes H in response to the fall of the go (B) signal.

  In other words, the control circuit 36 generates and outputs a go2 (B) signal that maintains the go (B) signal in the H state while the abort (B) signal is H (that is, during interruption processing). It can be said. In the case 6B of FIG. 6, the go (B) signal extends in addition to the predetermined period D by the time dt until the end of the interruption process after the predetermined period D has elapsed from the rising edge of the go (B) signal. After that, the go2 (B) signal becomes L at timing ST1.

FIG. 7 is a circuit diagram showing a configuration of a control circuit that takes a logical sum (OR) of a go (B) signal and an abort (B) signal. Note that the control circuit for calculating the logical sum (OR) of the go (A) signal and the abort (A) signal is also the same as that shown in FIG.
The control circuit 41 includes an OR circuit 42 that performs a logical sum (OR) of the go (B) signal and the abort (B) signal, and an output signal ORout of the OR circuit 42 and a go (B) signal according to the selection signal. It includes a selector 43 that selects and outputs these. Whether the output of the selector 43, which is a switching circuit, is the output signal ORout or the go (B) signal is set by a switching signal SW set from the outside. The switching signal is generated by, for example, a switch operated by the user. If the transfer processing of the image data related to the B processing unit 38 is started during the interruption process, the control circuit 41 may transfer the field data in the previous image data. The signal is prevented from falling. Note that the operation of the control circuit 41 has no effect on the A processing unit 37.

  Therefore, when the output of the selector 43 is set to the output signal ORout side of the OR circuit 42 by the switching signal SW, the operation of the B processing unit 38 is a transfer processing operation as shown in FIG. In the case 6B of FIG. 6, the go (B) signal is a go2 (B) signal that remains in the H state for a dt time period than the predetermined period D (in other words, the period when the interruption process is not executed). When the output of the selector 43 is set to the go (B) signal side, the operation of the B processing unit is a transfer processing operation as shown in FIG.

  Such a selector is effective when analyzing the circuit operation. For example, in maintenance, there is a case where it is desired to check how the circuit operates without changing the predetermined period D. In the circuit of FIG. 7, the selector 43 can select either the output signal ORout or the go signal, so that such a case can be dealt with.

  As described above, at the image data transfer timing (in the above example, the timing when the predetermined period D has elapsed from the rise of the go (B) signal), the transfer processing of the previous image data has been completed. Even if there is not, the delay of the generation of the signal indicating the start of the image data transfer (go (B) signal falling timing), the interruption process is performed, and the transfer of the previous image data is terminated halfway. The control circuit 36 generates a timing signal and an interruption signal. When the interruption process ends, a transfer timing signal (in the above example, the fall timing of the go (B) signal) that gives an instruction for starting the transfer process of the next image data is generated. As a result, after the transfer of the previous image data is finished, the transfer of the next image data is surely started, and the disturbance of the image display can be suppressed.

  As described above, according to the above-described image data transfer apparatus according to the present embodiment, the interruption process affects only the transfer of the previous minimum required image data, and the transfer of the minimum required previous image data is performed. After being reliably performed, the next image data is reliably transferred at a timing based on the next vertical synchronizing signal. Therefore, according to the image data transfer apparatus according to the present embodiment, it is possible to minimize the collapse or disorder of the displayed screen.

  The present invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the scope of the present invention.

It is a block diagram which shows the main components of the television receiver containing the image data transfer apparatus concerning embodiment of this invention. It is a block diagram which shows the detailed structure of the video back end process part concerning embodiment of this invention. It is a figure which shows the example of the display screen in LCD concerning embodiment of this invention. It is a timing chart which shows the timing of data transfer. It is a timing chart which shows the timing of data transfer. It is a timing chart which shows the timing of data transfer concerning an embodiment of the invention. It is a circuit diagram which shows the structure of the control circuit concerning embodiment of this invention.

Explanation of symbols

1 Digital TV, 13 Data processing unit, 41 Control circuit

Claims (5)

A memory for storing image data;
A transfer circuit that is connected to the memory via a bus and that starts the transfer of the image data upon receiving a transfer start signal indicating the transfer start timing of the image data, and transfers the image data to and from the memory When,
When generating the transfer start signal based on the synchronization signal and outputting it to the transfer circuit, when the previous transfer process based on the previous generation timing is not completed at the generation timing of the transfer start signal, A transfer start signal output control for executing a stop process for interrupting the transfer process in the previous transfer process and generating a transfer start signal next to the previous generation timing when the interrupt process ends, and outputting to the transfer circuit Circuit,
An image data transfer device comprising: The transfer circuit includes a command register that stores a command for transferring the image data,
The image data transfer apparatus according to claim 1, wherein the transfer start signal output control circuit erases the command related to the previous transfer process from the command register in the interruption process. The transfer circuit includes an accept command register that stores an accept command indicating permission to transfer the image data,
3. The transfer start signal output control circuit determines that the interruption process is ended when the previous transfer process corresponding to the accept command stored in the accept command register is completed. The image data transfer device described in 1. The transfer circuit has a plurality of image processing circuits for processing the image data,
The plurality of image processing circuits are circuits that perform the processing of the image data based on a plurality of different synchronization signals.
The transfer start signal output control circuit generates the transfer start signal corresponding to each of the plurality of synchronization signals and outputs the transfer start signal to each of the plurality of image processing circuits. The image data transfer device according to any one of the above. The transfer start signal output control circuit includes a transfer start signal generated when the interruption process is not executed and a transfer start signal next to the previous generation timing generated when the interruption process ends. A selection circuit for selecting one output and outputting to the transfer circuit;
5. The image data transfer apparatus according to claim 1, wherein one of the two outputs can be designated as a signal to be output to the transfer circuit. 6.

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