JP2008123333A5 - - Google Patents
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- Publication number
- JP2008123333A5 JP2008123333A5 JP2006307700A JP2006307700A JP2008123333A5 JP 2008123333 A5 JP2008123333 A5 JP 2008123333A5 JP 2006307700 A JP2006307700 A JP 2006307700A JP 2006307700 A JP2006307700 A JP 2006307700A JP 2008123333 A5 JP2008123333 A5 JP 2008123333A5
- Authority
- JP
- Japan
- Prior art keywords
- cache
- controller
- semiconductor integrated
- integrated circuit
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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- 239000004065 semiconductor Substances 0.000 claims description 65
- 230000015654 memory Effects 0.000 claims description 38
- 238000006243 chemical reaction Methods 0.000 claims description 10
- 230000000875 corresponding Effects 0.000 claims description 4
- 238000011022 operating instruction Methods 0.000 claims 1
- 238000000034 method Methods 0.000 description 42
- 238000010586 diagram Methods 0.000 description 19
- 230000002093 peripheral Effects 0.000 description 10
- 230000004044 response Effects 0.000 description 9
- 230000005012 migration Effects 0.000 description 6
- 230000001360 synchronised Effects 0.000 description 4
- 210000004759 MCP Anatomy 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000004059 degradation Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006011 modification reaction Methods 0.000 description 1
- 230000003252 repetitive Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006307700A JP4965974B2 (ja) | 2006-11-14 | 2006-11-14 | 半導体集積回路装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006307700A JP4965974B2 (ja) | 2006-11-14 | 2006-11-14 | 半導体集積回路装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2008123333A JP2008123333A (ja) | 2008-05-29 |
| JP2008123333A5 true JP2008123333A5 (fr) | 2009-12-24 |
| JP4965974B2 JP4965974B2 (ja) | 2012-07-04 |
Family
ID=39508013
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006307700A Active JP4965974B2 (ja) | 2006-11-14 | 2006-11-14 | 半導体集積回路装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4965974B2 (fr) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5348320B2 (ja) * | 2010-05-27 | 2013-11-20 | 富士通株式会社 | 情報処理システム及びシステムコントローラ |
| WO2011158320A1 (fr) * | 2010-06-14 | 2011-12-22 | 富士通株式会社 | Système de processeur multicœur, procédé de contrôle de cohérence de cache, et programme de contrôle de cohérence de cache |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04123151A (ja) * | 1990-09-13 | 1992-04-23 | Fujitsu Ltd | システムバス |
| JP3340047B2 (ja) * | 1997-03-11 | 2002-10-28 | 株式会社日立製作所 | マルチプロセッサシステムおよび複製タグの制御方法 |
| US6470437B1 (en) * | 1999-12-17 | 2002-10-22 | Hewlett-Packard Company | Updating and invalidating store data and removing stale cache lines in a prevalidated tag cache design |
| JP4695367B2 (ja) * | 2004-08-31 | 2011-06-08 | 富士通株式会社 | 情報処理装置，制御装置及び情報処理装置の制御方法 |
| JP2006185284A (ja) * | 2004-12-28 | 2006-07-13 | Renesas Technology Corp | データ処理装置 |
| JP4848771B2 (ja) * | 2006-01-04 | 2011-12-28 | 株式会社日立製作所 | キャッシュ一貫性制御方法およびチップセットおよびマルチプロセッサシステム |
| JP4297968B2 (ja) * | 2006-02-14 | 2009-07-15 | 富士通株式会社 | コヒーレンシ維持装置およびコヒーレンシ維持方法 |
-
2006
- 2006-11-14 JP JP2006307700A patent/JP4965974B2/ja active Active
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