JP2008118045A - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which a capacitance element made of high dielectric oxide having a perovskite structure, a capacitance element made of nitride and a resistance element made of high-resistive metallic material are integrated on the same compound semiconductor substrate, and to provide a method for manufacturing the same, wherein characteristics of the elements are not deteriorated and a process cost can be reduced. <P>SOLUTION: A lower electrode of a high dielectric capacitance element portion 20 which is a capacitance element made of high dielectric oxide and a nitride capacitance element portion 40 which is a capacitance element made of nitride, and a lower electrode of a metal resistance element 30 which is a resistance element made of high-resistive metallic material are concurrently formed with a laminated metal layer 103 made of the same material. In addition, a metallic material layer 107 which is a resistor of the metal resistance element 30 is formed so as to contact with the laminated metal layer 103 which is the lower electrode of the metal resistance element 30. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular, a capacitive element made of a high dielectric oxide having a perovskite structure, a capacitive element made of nitride, and a resistive element made of a high resistance metal material are integrated on the same compound semiconductor substrate. The present invention relates to a semiconductor device and a manufacturing method thereof.

  A field effect transistor (hereinafter referred to as GaAsFET) formed on a semi-insulating semiconductor substrate made of GaAs is used for power amplifiers and switches of communication devices, particularly mobile phone terminals, etc. due to its excellent performance. ing. A monolithic microwave integrated circuit (hereinafter referred to as GaAsMMIC) in which an active element such as GaAsFET and a passive element such as a resistance element and a capacitance element are integrated has been particularly widely used. In recent years, there is a demand for an integrated passive element (hereinafter referred to as GaAsIPD) in which active elements such as transistors are not formed on a semi-insulating semiconductor substrate made of GaAs, and only passive elements such as capacitive elements and resistive elements are integrated. Is also growing.

  In the GaAs MMIC, a large-capacity capacitive element is required for cutting a DC component and for a bypass capacitor to the ground line. However, a large area is required to form a large capacity capacitive element, and the capacitive element may occupy nearly 50% of the chip area.

Therefore, a GaAs MMIC equipped with a large capacity capacitor element (hereinafter referred to as STO capacity) made of a high dielectric oxide having a perovskite structure typified by SrTiO ₃ for reducing the chip area is known. These high dielectric oxides having a perovskite structure have a relative dielectric constant 10 times or more higher than that of conventionally used SiO ₂ (silicon oxide), SiN (silicon nitride), etc., and the area of the capacitive element is reduced to 1/10. There are the following merits. Therefore, a high-dielectric oxide having a perovskite structure is desirable as a material for a large-capacity capacitive element.

  In addition, the GaAs MMIC requires a high-accuracy and small-capacitance element used for a matching circuit, in addition to a large-capacity capacitor element used for cutting a DC component and a bypass capacitor. Such a capacitive element has a capacitance of several pF and a capacitance accuracy within 5%. Since a capacitive element using a high dielectric material has a high dielectric constant, it is difficult to form a capacitive element with high accuracy and a small capacity. For this reason, it is desirable that the GaAs MMIC be formed by coexisting a large-capacity capacitive element using a high dielectric material and a small-capacitance capacitive element with high accuracy. The same can be said for GaAsIPD.

  In addition, a resistor of a semiconductor device made of a compound semiconductor such as GaAs has a high resistance metal film made of a W system such as WSiN in order to realize linearity and stability at high frequencies, which are necessary characteristics as resistance. It is used as a resistor for resistance elements.

  In the aforementioned GaAsMMIC and GaAsIPD, further cost reduction has been demanded in recent years. In particular, there is a strong demand for process technology to simplify process steps without reducing the performance of elements such as GaAsMMIC and GaAsIPD, and to realize reduction in process costs.

In addition, there exists a thing of patent document 1, 2 as a technique corresponding to such a request, for example. Patent Document 1 has a large-capacity capacitive element using a high dielectric material and a small-capacitance capacitive element using SiO ₂ or SiN, and each lower electrode is a laminated metal in which Ti, Au, and Pt are laminated in order. (Hereinafter referred to as Ti / Au / Pt). The lower electrode is formed by an ion milling method, so that the lower electrode having the two types of capacitance described above is shared.

Further, in Patent Document 2, in order to ensure etching selectivity with the interlayer insulating film SiO ₂ on a resistor using WSiN, Au having etching selectivity is deposited in a region where a contact hole is formed above the resistor. Therefore, it is used as an etching stop film.
JP-A-8-340083 JP-A-5-82519

  However, in the semiconductor device described in Patent Document 1, Au, which is a noble metal, is deposited on the lower electrode. Au is difficult to process by dry etching with a chemical reaction mechanism (hereinafter referred to as chemical reactive dry etching). Therefore, to process the lower electrode on which Au is deposited, for example, an area other than the lower electrode is protected with a photoresist, and after performing an ion milling process of a physical mechanism with Ar, a process of removing the photoresist is added. It is necessary to increase the process man-hours. Further, in the semiconductor device described in Patent Document 2, the W-type resistance element is directly contacted. Therefore, it is necessary to form a contact hole by etching in the insulating film deposited on the upper part of the W-based resistance element, but it is necessary to always form a protective region of Au so as not to etch the W-based resistance element. Therefore, the process man-hour increases and the process cost increases. When the W-based resistive element is not provided with a protective region made of Au, the W-based resistive element is scraped away by etching, and the characteristics as the element are impaired.

  Accordingly, the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can reduce the process cost without deteriorating the characteristics of the element.

  A semiconductor device including first and second capacitor elements and a resistor element, wherein the first insulating layer formed on a semiconductor substrate and the first capacitor element as one electrode As a first laminated metal layer comprising a plurality of metal layers formed on an insulating layer, a high dielectric layer formed on the first laminated metal layer, and the other electrode of the first capacitor element A plurality of metal layers formed on the high dielectric layer, and a plurality of metal layers formed on the first insulating layer as one electrode of the second capacitor element. A third laminated metal layer made of a metal layer, a second insulating layer formed on the first laminated metal layer, and the other electrode of the second capacitor element on the second insulating layer A fourth laminated metal layer comprising a plurality of metal layers formed on the first insulating layer and a plurality of metal layers formed on the first insulating layer; 5th and 6th laminated metal layers comprising metal layers, and a first metal formed on the first insulating layer and between the fifth laminated metal layer and the sixth laminated metal layer And the first, third, fifth and sixth laminated metal layers are formed of the same material and in the same layer in the form of islands, and the fifth laminated metal layer is formed of the resistor. The sixth laminated metal layer is in contact with one end of the body, and is in contact with the other end of the resistor.

  According to this configuration, when integrating the capacitive element and the resistive element having different dielectric constants, the first laminated metal layer, the third laminated metal layer, and the resistive element, which are one electrode of the capacitive element, are connected to the capacitive element electrode. Since the fifth and sixth laminated metal layers, which are the metals that connect the two, can be formed simultaneously with the same material, the number of process steps can be reduced. When the resistance element is connected to the fifth and sixth laminated metal layers to form a contact with the resistance element, the fifth and sixth laminated metal layers to which the resistance element is connected. It is only necessary to form a contact, which not only impairs the characteristics of the element, but also reduces the number of process steps by an extra step such as forming a protective film on the resistance element. For example, when there is an insulating film formed on a resistive element, and a contact hole is formed by etching in the insulating film above the resistive element, and the resistive element and the contact are formed, the resistive element is also partially etched, The characteristic of the resistance element is not impaired.

The first, third, fifth, and sixth laminated metal layers may include the uppermost metal layer made of Pt.

  According to this configuration, the fifth and sixth laminated metal layers that are metals connecting the first laminated metal layer, the fourth laminated metal layer, and the resistance element are selectively processed by chemical reactive dry etching. Therefore, the number of process steps can be reduced as compared with the conventional technique in which only physical etching can be performed and it is necessary to increase the number of processes for protecting other than physical etching targets. Further, by increasing Pt, the resistance of the electrode of the capacitor can be reduced. In addition, for example, an insulating layer is formed on the fifth and sixth laminated metal layers, which are metals connecting the first laminated metal layer, the fourth laminated metal layer, and the resistance element, and the upper parts of these laminated metal layers are formed. When forming an opening in the insulating layer, Pt can also serve as an etching stop film by selecting a reaction gas used for dry etching, so it is not necessary to add Au as an etching stop film. , Process man-hours can be reduced.

  In the first, third, fifth and sixth laminated metal layers, the lowermost metal layer may be made of Ti.

According to this configuration, the laminated metal layer can be formed from a material having good adhesion to the insulating layer.
The first, third, fifth and sixth laminated metal layers may include an intermediate metal layer made of Al between the uppermost metal layer and the lowermost metal layer.

According to this configuration, the resistance of the laminated metal layer can be reduced by using Al. In addition, since Al can be easily chemically reactive dry etched with Cl ₂ , the dry etching speed of the laminated metal layer can be increased.

  The first, third, fifth and sixth laminated metal layers may further include a metal layer made of Ti between the intermediate metal layer and the uppermost metal layer.

  According to this configuration, the adhesion between the intermediate metal layer and the uppermost metal layer is improved by using Ti.

  The semiconductor device further includes a transistor element, and the transistor element includes a third insulating layer formed on the semiconductor substrate in the region where the first insulating layer is removed, and the third insulating layer. And a seventh laminated metal layer comprising a plurality of metal layers formed as electrodes of the transistor element through the insulating layer, the seventh laminated metal layer being the same as the fourth laminated metal layer It may be made of a material.

  According to this configuration, the electrodes of the semiconductor element and the fourth laminated metal layer can be formed simultaneously with the same material. Accordingly, the semiconductor element, the first capacitor element made of a high dielectric sandwiched between the first multilayer metal layer and the third multilayer metal layer, and the third multilayer metal layer and the fourth multilayer metal layer are sandwiched. Thus, the second capacitor element made of the second insulator and the resistor element can be integrated at low cost.

  The third insulating layer includes the fourth insulating layer formed in a portion penetrating the seventh laminated metal layer, and the fourth insulating layer includes the second insulating layer and the fourth insulating layer. The same material and the same layer may be used. At this time, the semiconductor element may include two field effect transistors having different threshold voltages.

  According to this configuration, when the source electrode, the drain electrode, and the gate electrode of the field effect transistor are formed in the opening of the third insulating layer, the fourth insulating film is formed on the side wall of the opening of the third insulating layer. By forming the layer, the contact area between the gate electrode and the semiconductor substrate is reduced, thereby realizing a short gate length. In addition, since the fourth insulating layer is formed on the side wall of the opening of the third insulating layer, the distance between the gate electrode, the source electrode, and the drain electrode is increased, and a high breakdown voltage of the field effect transistor is realized. The

  A method for manufacturing a semiconductor device according to the present invention is the method for manufacturing a semiconductor device according to claim 1, wherein a first step of forming a first insulating layer on a semiconductor substrate, the first, A second step of forming third, fifth and sixth laminated metal layers; a third step of forming a high dielectric layer on the first laminated metal layer; and on the high dielectric layer. A fourth step of forming a second laminated metal layer; and the fifth laminated metal layer on the first insulating layer and between the fifth laminated metal layer and the sixth laminated metal layer. A fifth step of forming a resistor made of a first metal material so as to contact the metal layer and the sixth laminated metal layer; and forming the second insulating layer on the third laminated metal layer. A sixth step and a seventh step of forming the fourth laminated metal layer on the second insulating layer are provided.

  According to this configuration, the first and third laminated metal layers, which are lower electrodes of the first capacitor element and the second capacitor element, can be simultaneously formed of the same material, and the process cost can be suppressed. In addition, since the resistance element is formed by being connected to the fifth and sixth laminated metal layers, when the contact with the resistance element is to be formed, the fifth and sixth connected to the resistance element. It is only necessary to form a contact with the laminated metal layer, which not only impairs the characteristics of the element but also reduces the number of process steps by an extra step such as forming a protective film on the resistance element. For example, when there is an insulating film formed on a resistive element, and a contact hole is formed by etching in the insulating film above the resistive element, and the resistive element and the contact are formed, the resistive element is also partially etched, The characteristic of the resistance element is not impaired.

  Further, in the method for manufacturing the semiconductor device, the semiconductor device may further include the first, second, third, fifth and sixth steps between the fifth step and the sixth step. An insulating layer forming step of forming a fourth insulating layer on the laminated metal layer; and an opening reaching the first, second, third, fifth and sixth laminated metal layers in the fourth insulating layer. And an opening step formed simultaneously.

  According to this, since the openings reaching the first, second, third, fifth and sixth laminated metal layers can be simultaneously formed by etching, the process cost can be reduced.

  The semiconductor device further includes a transistor element, and the transistor element includes a third insulating layer formed on the semiconductor substrate in the region where the first insulating layer is removed, and the third insulating layer. And a seventh laminated metal layer comprising a plurality of metal layers formed as electrodes of the transistor element through the insulating layer, the seventh laminated metal layer being the same as the fourth laminated metal layer 2. The semiconductor device according to claim 1, wherein the semiconductor device is manufactured by using the same layer as the material, wherein the method for manufacturing the semiconductor device is performed between the fifth step and the sixth step. Furthermore, a step of removing a part of the first insulating layer, the third insulating layer on the semiconductor substrate from which the first insulating layer has been removed, and the first, second, third, and fifth And the fourth insulating layer on the sixth laminated metal layer simultaneously with the same material Forming the insulating layer, forming the third insulating layer, opening the third insulating layer, and forming the fourth laminated metal layer in the opening of the third insulating layer. 7 steps may be included.

  According to this, in addition to the first capacitor element, the second capacitor element, and the resistor element, when the transistor element is formed on the same semiconductor substrate, the first capacitor element, the second capacitor element, and the resistor element are formed. A part of the process in the middle of forming and a part of the process in the middle of forming the transistor element can be formed by the same process. Therefore, it is possible to reduce and realize the process cost of integrating the two types of capacitance elements, resistance elements, and field effect transistors.

  In the sixth step, the second insulating layer may be further formed on the side wall of the opening of the third insulating layer.

  According to this, when the source electrode, the drain electrode, and the gate electrode of the field effect transistor are formed in the opening of the third insulating layer, the fourth insulating layer is formed on the side wall of the opening of the third insulating layer. As a result, the contact area between the gate electrode and the semiconductor substrate is reduced, thereby realizing a shorter gate length. In addition, since the fourth insulating layer is formed on the side wall of the opening of the third insulating layer, the distance between the gate electrode, the source electrode, and the drain electrode is increased, and the high breakdown voltage of the transistor element is realized. .

  According to the present invention, it is possible to realize a semiconductor device and a method for manufacturing the semiconductor device that can reduce the process cost without impairing the characteristics of the element. Therefore, according to the present invention, it is possible to realize GaAsIPD and GaAsMMIC which are reduced in cost as communication devices such as power amplifiers and switches such as mobile phone terminals, and the practical value is extremely high.

  Hereinafter, semiconductor devices according to embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
The semiconductor device according to the first embodiment of the present invention is, for example, a GaAsIPD in which a high dielectric capacitor element, a nitride capacitor element, and a metal resistor element are integrated, and the lower electrode of the high dielectric capacitor element is nitrided. The lower electrode of the physical capacitor and the lower electrode of the metal resistance element are formed simultaneously with a material that also serves as an etching stop film. Thereby, the process man-hour can be suppressed without impairing the characteristics of each element, and the process cost can be reduced.

FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to the first embodiment of the present invention.
In the semiconductor device 100 shown in FIG. 1, an insulating layer 102 made of SiO ₂ is formed on a semi-insulating semiconductor substrate 101 made of GaAs. On the insulating layer 102, a high dielectric capacitor element 20, a resistance An element portion 30 and a nitride capacitor element portion 40 are formed.

In the high dielectric element portion 20, a laminated metal layer 103 serving as a lower electrode, a high dielectric layer 104 composed of SrTiO _{3 serving as} a capacitor layer, and a metal material layer 105 serving as an upper electrode are formed on the insulating layer 102. It is formed in order. Further, a high dielectric layer 104 made of SrTiO _{3 serving as} a capacitor layer and an insulating layer 106 protecting the metal material layer 105 serving as an upper electrode are formed. In the resistance element portion 30, a resistance is formed between the stacked metal layers 103 on the insulating layer 102 made of SiO ₂ , that is, a region where the stacked metal layer 103 is not formed (hereinafter referred to as a contact formation region). A metal material layer 107 is formed as a body. At this time, the metal material layer 107 which is a resistor is formed so as to be in contact with the laminated metal layer 103. In the nitride capacitor element portion 40, a laminated metal layer 103 serving as a lower electrode, an insulating layer 109 made of SiN serving as a capacitive layer, and a laminated metal layer 110 serving as an upper electrode are formed on the insulating layer 102. Yes. The semiconductor device 100 further includes an insulating layer 108 that protects the high dielectric capacitor element 20, the resistor element 30, and the stacked metal layer 103, the high dielectric capacitor layer element 20, the resistor element 30, and the nitride capacitor. An insulating layer 111 that protects the element portion 40 and a metal material layer 112 that serves as an upper wiring are sequentially formed.

  Here, the laminated metal layer 103 which becomes the lower electrode in the high dielectric element portion 20 and the nitride capacitor element portion 40 is a lower layer wiring in the semiconductor device 100, and becomes the upper electrode in the nitride capacitor element portion 40. The laminated metal layer 110 is an intermediate layer wiring in the semiconductor device 100.

In addition, although GaAs is used as the semiconductor substrate 101 here, for example, InP may be used. In addition, here, the insulating layer 108 is composed of a stacked layer of SiN / SiO ₂ , but may be composed of, for example, only SiN or only SiO ₂ . Here, the metal material layer 107 is made of WSiN, but may be made of WSi or W, for example.

  FIG. 2 is a schematic cross-sectional view showing the structure of the lower layer wiring of the semiconductor device according to the first embodiment of the present invention.

In the semiconductor device 100, the laminated metal layer 103 which is a lower layer wiring is composed of two to four layers as shown in FIGS. 2 (a) to 2 (c). The lowermost layer 1031 of the laminated metal layer 103 in contact with the insulating layer 102 is made of a material having good adhesion to the insulating layer 102, and here Ti is used. Top metal layer 1034 laminated metal layer 103 in contact with the high dielectric layer 104 made of SrTiO ₃ is made easily align the crystal orientation of the hardly oxidized SrTiO ₃ material, Pt is used here. In addition, Pt can be chemically reactive by selecting a gas. As shown in FIG. 2A, the laminated metal layer 103 is composed of only two layers of a lowermost metal layer 1031 and an uppermost metal layer 1034 made of Ti and Pt (hereinafter referred to as Ti / Pt). Also good. By increasing the Pt film thickness and processing by chemical reactive dry etching, the laminated metal layer 103 can be formed as a low resistance lower wiring. At this time, Cl ₂ is used as a reactive gas for the chemical reactive dry etching of Ti and Pt. Further, as shown in FIG. 2B, a low resistance metal layer 1032 made of a low resistance metal may be formed between the lowermost metal layer 1031 made of Ti and the uppermost metal layer 1034 made of Pt. Here, Al that can be easily chemically reactive dry etched with Cl ₂ is used. By using Al, it is possible to increase the speed of dry etching and reduce the material cost. Further, as shown in FIG. 2C, a metal layer 1033 made of Ti is inserted between the low resistance metal layer 1032 made of Al and the uppermost metal layer 1034 made of Pt, and made of a Ti / Al / Ti / Pt layer. The laminated metal layer 103 may be formed. As a result, the adhesion between the low resistance metal layer 1032 made of Al and the uppermost metal layer 1034 made of Pt can be improved.

  Next, a method for manufacturing a semiconductor device having the above structure will be described in detail. The same elements as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted here.

  FIG. 3 is a cross-sectional view for explaining a method for manufacturing a semiconductor device having the above structure.

(1) First, as shown in FIG. 3A, an insulating layer 102 made of SiO _{2 is} formed on a semi-insulating semiconductor substrate 101 made of GaAs by P-CVD, and Ti / Al / Ti is formed by DC sputtering. A stacked metal layer 103 made of / Pt layer, a high dielectric layer 104 made of SrTiO ₃ by RF sputtering using O ₂ gas, and a metal material layer 105 made of Pt by DC sputtering are sequentially deposited.

(2) Next, as shown in FIG. 3B, a predetermined region is patterned by photolithography, and a metal material layer 105 made of Pt and SrTiO 3 by chemical reactive dry etching using Cl ₂ / Ar gas. _The high dielectric layer 104 made of 3 is etched. As a result, an upper electrode made of the metal material layer 105 of the high dielectric capacitor element portion 20 and a capacitor layer made of the high dielectric layer 104 are formed.

(3) Next, as shown in FIG. 3C, a predetermined region is patterned by photolithography, and from the Ti / Al / Ti / Pt layer by chemical reactive dry etching using Cl ₂ / Ar gas. The resulting laminated metal layer 103 is etched. As a result, the lower electrode made of the laminated metal layer 103 of the high dielectric capacitor element portion 20 and the nitride capacitor element portion 40, the contact formation region made of the region without the laminated metal layer 103 of the resistor element portion 30, and the semiconductor device A lower layer wiring composed of 100 laminated metal layers 103 is formed.

(4) Next, as shown in FIG. 3D, an insulating layer 106 made of SiO ₂ is deposited by P-CVD.

(5) Next, as shown in FIG. 3 (e), a predetermined region is patterned by photolithography, and wet etching using dilute hydrofluoric acid is used to start from SiO ₂ other than the sidewall of the high-dielectric capacitor element unit 20. By removing the insulating layer 106, the lower electrode composed of the multilayer metal layer 103 of the high dielectric capacitor element portion 20 and the nitride capacitor element portion 40 and the region where the multilayer metal layer 103 of the resistor element portion 30 is absent. The contact formation region is exposed.

  (6) Next, as shown in FIG. 3F, a metal material layer 107 made of WSiN is deposited by DC sputtering.

(7) Next, as shown in FIG. 3G, a predetermined region is patterned by photolithography, and a region without the laminated metal layer 103 is formed by chemical reactive dry etching using Cl ₂ / O ₂ gas. A metal material layer 107 made of WSiN is formed as a resistor connecting the contact regions made of. Thereby, the resistor of the resistance element unit 30 is formed.

(8) Next, as shown in FIG. 3 (h), an insulator 108 made of SiN / SiO ₂ is laminated by the P-CVD method.

(9) Next, as shown in FIG. 3 (i), a predetermined region is patterned by photolithography, and chemically reactive dry etching using CHF ₃ / SF ₆ gas is used to perform high dielectric capacitor element portion 20 The contact opening between the upper and lower electrodes, the laminated metal layer 103 of the resistance element section 30, and the lower electrode of the nitride capacitor element section 40 is exposed.

  Here, in the laminated metal layer 103, when the insulating layer 108 is etched, the uppermost layer 1034 of the laminated metal layer 103 made of Pt functions as an etching stop layer.

  (10) Next, as shown in FIG. 3J, an insulating layer 109 made of SiN to be a capacitor layer of the nitride capacitor element portion 40 is deposited by P-CVD.

(11) Next, as shown in FIG. 4 (k), a predetermined region is patterned by photolithography, and a chemical reactive dry etching using CHF ₃ / SF ₆ gas is used to form a nitride capacitor element portion 40. The insulating layer 109 made of SiN is removed leaving the region.

  (12) Next, as shown in FIG. 4L, a laminated metal layer 110 made of a Ti / Al / Ti layer is deposited by a deposition method.

  Here, the metal material layer 110 is made of Ti / Al / Ti, but may be made of WSiN / Ti / Al / Ti or W / Ti / Al / Ti, for example.

(13) Next, as shown in FIG. 4 (m), a predetermined region is patterned by photolithography, and the upper portion of the nitride capacitor element 40 is formed by chemical reactive dry etching using Cl ₂ / BCl ₃ gas. A laminated metal layer 110 to be an electrode and a middle layer wiring of the semiconductor device 100 is formed.

  (14) Next, as shown in FIG. 4 (n), an insulating layer 111 made of SiN is deposited by P-CVD.

(15) Next, as shown in FIG. 4 (o), a predetermined region is patterned by photolithography, and the upper portion of the nitride capacitor element 40 is subjected to chemical reactive dry etching using CHF ₃ / SF ₆ gas. The electrode and the opening for contact with the laminated metal layer 110 to be the middle layer wiring of the semiconductor device 100 are formed.

  (16) Next, as shown in FIG. 4 (p), a metal material layer 112 to be the upper wiring of the semiconductor device 100 is formed by selectively forming Au plating in the vicinity of the contact opening.

As described above, according to the semiconductor device and the manufacturing method thereof according to the first embodiment of the present invention, the insulating layer 108 on the laminated metal layer 103 having the uppermost layer 1034 made of Pt of the resistance element portion 30 is formed of CF _4. Chemically reactive dry etching using a system gas. When the contact opening of the resistance element 30 is formed, the laminated metal layer 103 having the uppermost layer 1034 made of Pt functions as an etching stop layer. For this reason, it is not necessary to form an Au-based etching stop film on a W-based resistor such as WSiN, so that the number of process steps can be reduced. That is, the process cost can be reduced.

  In addition, since the lower electrode of the high dielectric capacitor element unit 20 and the nitride capacitor element unit 40 and the lower electrode of the metal resistor element that also serves as an etching stop film are shared by the laminated metal layer 103, the same material is used. Man-hours can be reduced. That is, the process cost can be reduced.

  Therefore, according to the semiconductor device and the manufacturing method thereof according to the first embodiment of the present invention, the high dielectric capacitor element and the nitride capacitor element can be integrated. Thus, it is possible to realize a semiconductor device in which a high-accuracy and small-capacitance element used in a matching circuit or the like is integrated.

(Second Embodiment)
The semiconductor device according to the second embodiment of the present invention is, for example, a GaAs MMIC in which a GaAsFET, a high dielectric capacitor, a nitride capacitor, and a metal resistor are integrated, and the lower part of the high dielectric capacitor. The electrode, the lower electrode of the nitride capacitive element, and the lower electrode of the metal resistive element are simultaneously formed of the same material that also serves as an etching stop film, and the gate electrode and source electrode of the GaAsFET, the drain electrode, and the upper electrode of the nitride capacitive element Are simultaneously formed of the same material. Thereby, the process man-hour can be suppressed without impairing the characteristics of each element, and the process cost can be reduced.

  The configuration of the semiconductor device according to the second embodiment of the present invention will be described below with reference to the drawings.

  FIG. 5 is a cross-sectional view showing a configuration of a semiconductor device according to the second embodiment of the present invention. Here, the same elements as those in FIG. 1 are denoted by the same reference numerals.

  A semiconductor device 100 shown in FIG. 6 includes a high dielectric capacitor element 20, a resistor element portion 30, a nitride capacitor element portion 40, and a field effect transistor portion 50 formed on a semi-insulating semiconductor substrate 101 made of GaAs. Yes.

The high dielectric element 20 includes a semi-insulating semiconductor substrate 101 made of GaAs, an insulating layer 102 made of SiO ₂ , a laminated metal layer 103 serving as a lower electrode, and a high layer made of SrTiO _{3 serving as} a capacitor layer. A dielectric layer 104 and a metal material layer 105 serving as an upper electrode are sequentially formed. Further, an insulating layer 106 that protects the capacitor layer of the high dielectric layer 104 made of SrTiO ₃ and the upper electrode of the metal material layer 105 is formed.

In the resistance element portion 30, an insulating layer 102 made of, for example, SiO ₂ is formed on a semi-insulating semiconductor substrate 101 made of GaAs. The high dielectric element portion 20 and the nitride capacitor element 40 are connected to the lower electrode. A region in which the multilayer metal layer 103 is not formed in the region of the resistive element section 30 so that both ends thereof are in contact with the upper side and the side wall of the multilayer metal layer 103 as a resistor connecting the multilayer metal layer 103 to be formed, that is, the lower electrode. Hereinafter, a metal material 107 serving as a resistor is formed in the contact formation region. The nitride capacitor element section 40 is made of, for example, an insulating layer 102 made of SiO ₂ , a laminated metal layer 103 serving as a lower electrode, and SiN serving as a capacitor layer on a semi-insulating semiconductor substrate 101 made of GaAs. An insulating layer 109 and a laminated metal layer 110 serving as an upper electrode are formed. In the field effect transistor 50, an insulating film 108 made of SiO ₂ is formed on a semiconductor substrate 101, and a laminated metal layer 110 that becomes a gate electrode, a source electrode, and a drain electrode is formed in an opening of the formed insulating film 108. ing. An insulating layer 109 serving as a sidewall is formed on the sidewalls of the gate electrode, the source electrode, and the drain electrode. The substrate 101 includes a channel layer, an electron supply layer formed on the channel layer, and a Schottky layer formed on the electron supply layer. Furthermore, an element isolation region 208 for electrically insulating other elements is formed on the substrate 101 in the field effect transistor 50.

  The semiconductor device 100 further includes an insulating layer 108 that protects the high dielectric capacitor element 20, the resistor element 30, and the stacked metal layer 103, the high dielectric capacitor layer element 20, the resistor element 30, and the nitride capacitor. An insulating layer 111 that protects the element portion 40 and the field effect transistor portion 50 and a metal material layer 112 that serves as an upper wiring are formed.

  Here, the laminated metal layer 103 that becomes the lower electrode in the high dielectric element portion 20 and the nitride capacitor element portion 40 is a lower layer wiring in the semiconductor device 100, and the laminated metal that becomes the upper electrode in the nitride capacitor element portion 40. The layer 110 is an intermediate layer wiring in the semiconductor device 100.

In addition, although GaAs is used as the semiconductor substrate 101 here, for example, InP may be used. In addition, here, the insulating layer 108 is composed of a stacked layer of SiN / SiO ₂ , but may be composed of, for example, only SiN or only SiO ₂ . Here, the metal material layer 107 is made of WSiN, but may be made of WSi or W, for example.

  FIG. 6 is a schematic cross-sectional view showing the structure of the lower layer wiring of the semiconductor device according to the second embodiment of the present invention.

In the semiconductor device 100, the laminated metal layer 103 which is a lower layer wiring is composed of two to four layers as shown in FIGS. 6 (a) to 6 (c). The lowermost metal layer 1031 of the laminated metal layer 103 in contact with the insulating layer 102 is made of a material having good adhesion to the insulating layer 102, and here Ti is used. Top metal layer 1034 laminated metal layer 103 in contact with the high dielectric layer 104 made of SrTiO ₃ is not easily oxidized, consists material susceptible to align the crystal orientation of SrTiO _3, Pt is used here. In addition, Pt can be chemically reactive by selecting a gas. As shown in FIG. 6A, the laminated metal layer 103 may be composed of only two layers of a lowermost metal layer 1031 and an uppermost metal layer 1034 made of Ti / Pt. By increasing the Pt film thickness and processing by chemical reactive dry etching, it is possible to form the laminated metal layer 103 which is a lower resistance lower layer wiring. Chemical dry etching using Cl ₂ as a reactive gas is used for dry etching of Ti and Pt. Further, as shown in FIG. 6B, a low-resistance metal layer 1032 made of a low-resistance metal may be formed between the lowermost metal layer 1031 made of Ti and the uppermost metal layer 1034 made of Pt. Here, Al that can be easily chemically reactive dry etched with Cl ₂ is used. By using Al, it is possible to increase the speed of dry etching and reduce the material cost. Further, as shown in FIG. 6C, a metal layer 1033 made of Ti is inserted between a low-resistance metal layer 1032 made of Al and an uppermost layer 1034 made of Pt, and made of a Ti / Al / Ti / Pt layer. The laminated metal layer 103 may be formed. As a result, the adhesion between the low resistance metal layer 1032 made of Al and the uppermost layer 1034 made of Pt can be improved.

  Next, a method for manufacturing a semiconductor device having the above structure will be described in detail. The same elements as those in FIG. 5 are denoted by the same reference numerals, and detailed description thereof will be omitted here.

  7 and 8 are cross-sectional views for explaining a method for manufacturing a semiconductor device having the above structure.

(1) First, as shown in FIG. 7A, an insulating layer 102 made of SiO _{2 is} formed on a semi-insulating semiconductor substrate 101 made of GaAs by P-CVD, and Ti / Al / Ti is formed by DC sputtering. A stacked metal layer 103 made of / Pt layer, a high dielectric layer 104 made of SrTiO ₃ by RF sputtering using O ₂ gas, and a metal material layer 105 made of Pt by DC sputtering are sequentially deposited. Although not shown here, the semi-insulating semiconductor substrate 101 made of GaAs has a channel layer, an electron supply layer formed on the channel layer, and a Schottky layer formed on the electron supply layer. Yes.

(2) Next, as shown in FIG. 7B, a predetermined region is patterned by photolithography, and a high dielectric layer 104 made of SrTiO _{3 is formed} by chemical reactive dry etching using Cl ₂ / Ar gas. And the metal material layer 105 made of Pt are etched. As a result, the capacitor layer made of the high dielectric layer 104 and the upper electrode made of the metal material layer 105 of the high dielectric capacitor element portion 20 are formed.

(3) Next, as shown in FIG. 7C, a predetermined region is patterned by photolithography, and Ti / Al / Ti / Pt 4 is formed by chemical reactive dry etching using Cl ₂ / Ar gas. The laminated metal layer 103 composed of layers is etched. As a result, the lower electrode made of the laminated metal layer 103 of the high dielectric capacitor element portion 20 and the nitride capacitor element portion 40, the contact formation region made of the region without the laminated metal layer 103 of the resistor element portion 30, and the semiconductor device A lower layer wiring composed of 100 laminated metal layers 103 is formed.

(4) Next, as shown in FIG. 7D, an insulating layer 106 made of SiO ₂ is deposited by P-CVD.

(5) Next, as shown in FIG. 7 (e), a predetermined region is patterned by photolithography, and wet etching using dilute hydrofluoric acid is used to start from SiO ₂ other than the sidewalls of the high-dielectric capacitor element portion 20. By removing the insulating layer 106, the lower electrode made of the laminated metal layer 103 of the high dielectric capacitor element portion 20 and the nitride capacitor element portion 40, and the contact made of the region where the laminated metal layer 103 of the resistor element portion 30 is absent. The forming area is exposed.

  (6) Next, as shown in FIG. 7F, a metal material layer 107 made of WSiN is deposited by DC sputtering.

(7) Next, as shown in FIG. 7 (g), a predetermined region is patterned by photolithography, and a region without the laminated metal layer 103 is formed by chemical reactive dry etching using Cl ₂ / O ₂ gas. A metal material layer 107 made of WSiN is formed as a resistor in the contact formation region made of. Thereby, the resistor of the resistance element unit 30 is formed.

(8) Next, as shown in FIG. 7H, a predetermined region is patterned by photolithography, and the field effect transistor portion 50 is formed by SiO _{2 in} a region where the field effect transistor portion 50 is formed by wet etching using dilute hydrofluoric acid. The insulating layer 102 is removed, and the electron supply layer above the semiconductor substrate 101 is exposed.

  (9) Next, as shown in FIG. 7I, a predetermined region is patterned by photolithography, and the electron supply layer on the upper portion of the semiconductor substrate 101 is removed. Then, as shown in FIG. 9J, an element isolation region 208 that electrically isolates the field effect transistor portion 50 from other elements by ion implantation into the region of the semiconductor substrate 101 from which the electron supply layer has been removed. Form.

  (10) Next, as shown in FIG. 7K, a predetermined region is patterned by photolithography, the electron supply layer in a partial region of the semiconductor substrate 101 is removed, and the Schottky layer is exposed.

(11) Next, as shown in FIG. 8L, an insulating layer 108 made of SiN / SiO ₂ is deposited by P-CVD.

(12) Next, as shown in FIG. 8 (m), a predetermined region is patterned by photolithography, and chemically reactive dry etching using CHF ₃ / SF ₆ gas is used to perform high dielectric capacitor element portion 20 A semiconductor substrate in a region that exposes an opening for contact with the upper and lower electrodes, the laminated metal layer 103 of the resistive element portion 30, and the lower electrode of the nitride capacitive element portion 40 and serves as the gate of the field effect transistor portion 50 The Schottky layer 101 and the electron supply layer of the semiconductor substrate 101 in the regions to be the source and drain are exposed.

  Here, in the laminated metal layer 103, when the insulating layer 108 is etched, the uppermost layer 1034 of the laminated metal layer 20 made of Pt functions as an etching stop layer.

  (13) Next, as shown in FIG. 8 (n), an insulating layer 109 made of SiN to be a capacitive layer of the nitride capacitive element portion 40 is deposited by P-CVD.

(14) Next, as shown in FIG. 8 (o), a predetermined region is patterned by photolithography, and chemical reactive dry etching using CHF ₃ / SF ₆ gas is performed to form the nitride capacitor element portion 40. The insulating layer 109 made of SiN is removed leaving the region. At the same time, the insulating layer 109 made of SiN is formed on the side walls of the gate electrode, the source electrode, and the drain electrode of the field effect transistor section 50 as side walls.

  (15) Next, as shown in FIG. 8 (p), a laminated metal layer 110 made of a Ti / Al / Ti layer is deposited by a deposition method.

  Here, the metal material layer 110 is made of Ti / Al / Ti, but may be made of WSiN / Ti / Al / Ti or W / Ti / Al / Ti, for example.

(16) Next, as shown in FIG. 8 (q), a predetermined region is patterned by photolithography, and chemical reactive dry etching using Cl ₂ / BCl ₃ gas is used to form the nitride capacitor element portion 40. The upper electrode, the gate electrode, the source electrode, and the drain electrode of the field effect transistor unit 50, and the laminated metal layer 110 that forms the middle layer wiring in the semiconductor device 100 are formed.

  (17) Next, as shown in FIG. 8 (r), an insulating layer 111 made of SiN is deposited by P-CVD.

(18) Next, as shown in FIG. 8 (s), a predetermined region is patterned by photolithography, and chemical reactive dry etching using CHF ₃ / SF ₆ gas is used to form the nitride capacitor element portion 40. An opening for contact with the upper electrode and the laminated metal layer 110 to be an intermediate wiring in the semiconductor device 100 is formed.

  (19) Next, as shown in FIG. 8 (t), a metal material layer 112 to be the upper wiring of the semiconductor device 100 is formed by selectively forming Au plating in the vicinity of the contact opening.

As described above, according to the semiconductor device and the manufacturing method thereof according to the second embodiment of the present invention, the insulating layer 108 on the laminated metal layer 103 having the uppermost layer 1034 made of Pt of the resistance element portion 30 is formed of CF _4. When the contact opening of the resistance element 30 is formed by dry etching with a system gas, the laminated metal layer 103 having the uppermost layer 1034 made of Pt functions as an etching stop layer. For this reason, it is not necessary to form an Au-based etching stop film on a W-based resistor such as WSiN, so that the number of process steps can be reduced. That is, the process cost can be reduced.

  In addition, since the lower electrode of the high dielectric capacitor element 20 and the nitride capacitor element 30 and the lower electrode of the metal resistance element that also serves as an etching stop film can be shared by the laminated metal layer 103 with the same material. It becomes possible to suppress the process man-hours. That is, the process cost can be reduced.

  Further, the gate electrode, the source electrode, and the drain electrode of the field effect transistor portion 50 and the upper electrode of the nitride capacitor element portion 40 can be shared and formed by the same material by the laminated metal layer 110 made of Ti / Al / Ti. Therefore, it becomes possible to reduce the process man-hours. That is, the process cost can be reduced.

  Furthermore, an insulating film 109 serving as a sidewall is formed on the gate electrode, the source electrode, and the drain electrode of the field effect transistor unit 50. As a result, it is possible to shorten the gate length and increase the breakdown voltage of the field effect transistor, thereby realizing high performance. At this time, since the insulating film 109 serving as a sidewall formed in the field effect transistor portion is formed of the same material and simultaneously as the insulating film 109 serving as a capacitor layer formed in the nitride capacitor element portion 40, the process cost is reduced. Realized without an increase.

  As the integrated field effect transistor, the MESFET type has been described above, but it goes without saying that it may be a MOSFET type. In addition, for example, field effect transistors having different threshold voltages, which are an enhancement type and a depletion type, may be integrated.

  As described above, according to the semiconductor device and the manufacturing method thereof according to the second embodiment of the present invention, the field effect transistor, the high dielectric capacitor element, and the nitride capacitor element are integrated. A GaAs MMIC including a large-capacity capacitive element used and a high-accuracy small-capacitance capacitive element used in a matching circuit or the like can be realized.

  INDUSTRIAL APPLICABILITY The present invention can be applied to a semiconductor device and a manufacturing method thereof, and in particular, a large-capacity capacitive element, a small-capacitance capacitive element, and a resistive element formed on a semiconductor substrate made of semi-insulating GaAs are integrated. The present invention can be applied to a GaAs MMIC in which a field effect transistor formed on a semiconductor substrate made of semi-insulating GaAs, a large-capacity capacitive element, a small-capacitance capacitive element, and a resistive element are integrated. Further, the present invention can be applied to communication equipment using GaAsIPD or GaAsMMIC, and in particular, can be applied to power amplifiers and switches for mobile phone terminals and the like.

1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention. It is typical sectional drawing which shows the structure of the lower layer wiring of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device in connection with the 2nd Embodiment of this invention. It is typical sectional drawing which shows the structure of the lower layer wiring of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a figure which shows the structure in the manufacture process of the semiconductor device in connection with the 2nd Embodiment of this invention. It is a figure which shows the structure in the manufacture process of the semiconductor device in connection with the 2nd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 20 High dielectric capacitance element part 30 Resistance element part 40 Nitride capacitive element part 50 Field effect transistor part 100 Semiconductor device 101 Semiconductor substrate 102 Insulating layer 103 Laminated metal layer 1031 Bottom metal layer 1032 Metal layer 1033 Metal layer 1034 Uppermost metal layer 104 High dielectric layer 105 Metal material layer 106 Insulating layer 107 Metal material layer 108 Insulating layer 109 Insulating layer 110 Multilayer metal layer 111 Insulating layer 112 Metal material layer 208 Element isolation region

Claims (20)

A semiconductor device comprising first and second capacitive elements and a resistive element,
A first insulating layer formed on a semiconductor substrate;
A first laminated metal layer comprising a plurality of metal layers formed on the first insulating layer as one electrode of the first capacitive element;
A high dielectric layer formed on the first laminated metal layer;
A second laminated metal layer comprising a plurality of metal layers formed on the high dielectric layer as the other electrode of the first capacitive element;
A third laminated metal layer comprising a plurality of metal layers formed on the first insulating layer as one electrode of the second capacitive element;
A second insulating layer formed on the first laminated metal layer;
A fourth laminated metal layer composed of a plurality of metal layers formed on the second insulating layer as the other electrode of the second capacitive element;
Fifth and sixth laminated metal layers comprising a plurality of metal layers formed on the first insulating layer;
A resistor made of a first metal material formed between the fifth laminated metal layer and the sixth laminated metal layer on the first insulating layer;
The first, third, fifth and sixth laminated metal layers are formed of the same material and in the same layer in an island shape, the fifth laminated metal layer is in contact with one end of the resistor, and the sixth The laminated metal layer is in contact with the other end of the resistor. 2. The semiconductor device according to claim 1, wherein an uppermost metal layer of the first, third, fifth, and sixth stacked metal layers is made of Pt. 2. The semiconductor device according to claim 1, wherein a lowermost metal layer of the first, third, fifth, and sixth laminated metal layers is made of Ti. The said 1st, 3rd, 5th and 6th laminated metal layer contains the intermediate | middle metal layer which consists of Al between the uppermost metal layer and the lowermost metal layer. Semiconductor device. The first, third, fifth and sixth laminated metal layers further include a metal layer made of Ti between the intermediate metal layer and the uppermost metal layer. The semiconductor device described. The semiconductor device further includes a transistor element,
The transistor element includes a third insulating layer formed on the semiconductor substrate in a region where the first insulating layer is removed;
A seventh laminated metal layer comprising a plurality of metal layers penetrating the third insulating layer and formed as electrodes of the transistor element;
The semiconductor device according to claim 1, wherein the seventh laminated metal layer is formed of the same material as the fourth laminated metal layer. The third insulating layer has the fourth insulating layer formed in a portion penetrating the seventh laminated metal layer,
The semiconductor device according to claim 6, wherein the fourth insulating layer is formed of the same material and the same layer as the second insulating layer. The semiconductor device according to claim 6, wherein the semiconductor element includes two field effect transistors having different threshold voltages. The semiconductor device according to claim 1, wherein the semiconductor substrate is made of GaAs or InP. The semiconductor device according to claim 1, wherein the first insulating layer is made of SiO ₂ . The semiconductor device according to claim 1, wherein the high dielectric layer is made of a high dielectric oxide having a perovskite structure typified by SrTiO ₃ . The semiconductor device according to claim 1, wherein the second insulating layer is made of SiN. The semiconductor device according to claim 6, wherein the third insulating layer material is composed of SiN, SiO ₂ , or a stack of SiN and SiO ₂ . The semiconductor device according to claim 1, wherein the second laminated metal layer includes Pt, WSi, or WSiN. 2. The semiconductor device according to claim 1, wherein the resistor made of the first metal material includes WSiN, WSi, or W. 3. The fourth laminated metal layer is formed from a metal layer laminated on Ti, Al, Ti, WSi, Al, Ti, or WSiN, Ti, Al, Ti, or W, Ti, Al, Ti from the semiconductor substrate side. The semiconductor device according to claim 1, wherein: A method of manufacturing a semiconductor device according to claim 1,
A first step of forming a first insulating layer on a semiconductor substrate;
A second step of forming the first, third, fifth and sixth laminated metal layers;
A third step of forming a high dielectric layer on the first laminated metal layer;
A fourth step of forming a second laminated metal layer on the high dielectric layer;
On the first insulating layer and between the fifth stacked metal layer and the sixth stacked metal layer, the fifth stacked metal layer and the sixth stacked metal layer are in contact with each other. A fifth step of forming a resistor made of one metal material;
A sixth step of forming the second insulating layer on the third laminated metal layer;
And a seventh step of forming the fourth laminated metal layer on the second insulating layer. A method for manufacturing a semiconductor device, comprising: In the semiconductor device, a fourth insulating layer is further formed on the first, second, third, fifth and sixth laminated metal layers between the fifth step and the sixth step. An insulating layer forming step,
The opening process which forms simultaneously each opening which reaches the 1st, 2nd, 3rd, 5th, and 6th laminated metal layers in the 4th insulating layer. A method for manufacturing a semiconductor device. The semiconductor device further includes a transistor element,
The transistor element includes a third insulating layer formed on the semiconductor substrate in a region where the first insulating layer is removed;
A seventh laminated metal layer comprising a plurality of metal layers penetrating the third insulating layer and formed as electrodes of the transistor element;
The semiconductor device according to claim 1, wherein the seventh multilayer metal layer is formed of the same material and the same layer as the fourth multilayer metal layer.
The method for manufacturing a semiconductor device further includes a step of removing a part of the first insulating layer between the fifth step and the sixth step.
The third insulating layer on the semiconductor substrate from which the first insulating layer has been removed, and the fourth insulating layer on the first, second, third, fifth and sixth laminated metal layers. An insulating layer forming step of simultaneously forming the same material;
The opening step including the step of opening the third insulating layer;
The method of manufacturing a semiconductor device according to claim 17, further comprising: a seventh step including a step of forming the fourth laminated metal layer in an opening of the third insulating layer. The method of manufacturing a semiconductor device according to claim 18, wherein, in the sixth step, the second insulating layer is further formed on a sidewall of the opening of the third insulating layer.

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