JP2008118010A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2008118010A
JP2008118010A JP2006301370A JP2006301370A JP2008118010A JP 2008118010 A JP2008118010 A JP 2008118010A JP 2006301370 A JP2006301370 A JP 2006301370A JP 2006301370 A JP2006301370 A JP 2006301370A JP 2008118010 A JP2008118010 A JP 2008118010A
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lead frame
semiconductor device
insulating
main circuit
insulating substrate
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Yoshinari Ikeda
良成 池田
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Fuji Electric Co Ltd
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Fuji Electric Device Technology Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To perform overcurrent protection in a semiconductor device by providing a highly reliable fuse function in a lead frame being the wiring member of a main circuit. <P>SOLUTION: The lead frame 4 is laid, as a lead material for the wiring of the main circuit, between an upper surface main electrode of a semiconductor chip 3 mounted on an insulating substrate 2 and the conductive patterns 2b, 2c of the insulating substrate, so as to join both the ends of the lead frame with opposite joint members concerning the semiconductor device. The bar piece 10 of an insulating material, being different from the lead frame material in linear expansion coefficient, is superimposed on the middle part of the lead frame, so as to be integrally joined. By the bimetal effect, the middle part of the lead frame is bent for break when an overcurrent flows. The main circuit is opened, thereby interrupting the overcurrent. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、インバータ装置に適用するＩＧＢＴモジュールなどを対象とした電力用の半導体装置に関し、詳しくはその過電流保護対策に係わる。   The present invention relates to a power semiconductor device intended for an IGBT module or the like applied to an inverter device, and more particularly to measures for overcurrent protection.

最近では、半導体装置の容量拡大化に伴い、絶縁基板にマウントした半導体チップに接続する主回路の配線リード材として、ボンディングワイヤに変えて通電容量の大きなリードフレームを半導体チップの上面主電極と絶縁基板の導体パターン，入／出力端子との間に接続した配線構造が採用される傾向にあり（例えば、特許文献１参照）、次にＩＧＢＴモジュールを例にその組立構造を図３に示す。   Recently, as the capacity of semiconductor devices has increased, as a lead material for main circuits connected to a semiconductor chip mounted on an insulating substrate, a lead frame having a large current carrying capacity is insulated from the upper main electrode of the semiconductor chip instead of bonding wires. A wiring structure connected between the conductor pattern of the substrate and the input / output terminals tends to be employed (see, for example, Patent Document 1). Next, an assembly structure of the IGBT module is shown in FIG.

図３において、１は放熱用金属ベース、２はセラミック基板２ａの表，裏両面に銅箔を直接接合して導体パターン２ｂ，２ｃ，２ｄを形成した絶縁基板（ＤＢＣ基板）、３は絶縁基板２の導体パターン２ｂにマウントした半導体チップ（ＩＧＢＴ）、４は半導体チップ３の上面主電極（ＩＧＢＴのエミッタ電極）と絶縁基板２の導体パターン２ｃとの間に配線したリードフレーム、５は導体パターン２ｃと入／出力端子６との間に配線したリードフレーム、７は半導体チップ３の制御電極（ゲート電極）に接続したボンディングワイヤ、８は金属ベース／絶縁基板，絶縁基板／半導体チップ，半導体チップ／リードフレームの間の半田接合部、９は外囲樹脂ケースである。なお、半導体チップ３を保護するために、外囲樹脂ケース９にシリコーンゲルなどを充填して半導体チップ３，リードフレーム４，５の周域を樹脂封止している。   In FIG. 3, 1 is a heat-dissipating metal base, 2 is an insulating substrate (DBC substrate) in which conductor patterns 2b, 2c, and 2d are formed by directly bonding copper foil to the front and back surfaces of the ceramic substrate 2a, and 3 is an insulating substrate. 2 is a semiconductor chip (IGBT) mounted on the conductor pattern 2b, 4 is a lead frame wired between the upper main electrode (IGBT emitter electrode) of the semiconductor chip 3 and the conductor pattern 2c of the insulating substrate 2, and 5 is a conductor pattern. Lead frame wired between 2c and input / output terminal 6, 7 is a bonding wire connected to the control electrode (gate electrode) of semiconductor chip 3, 8 is a metal base / insulating substrate, insulating substrate / semiconductor chip, semiconductor chip / A solder joint between lead frames, 9 is an outer resin case. In order to protect the semiconductor chip 3, the surrounding resin case 9 is filled with silicone gel or the like, and the peripheral areas of the semiconductor chip 3 and the lead frames 4 and 5 are sealed with resin.

一方、前記の電力用半導体モジュールについて、サージなどにより過電流が流れると半導体チップが破壊されて短絡状態になり、この過電流が継続して流れると半導体モジュールのみならず、この半導体モジュールで回路を構成したインバータ装置にも故障が波及するおそれがある。
この場合に、主回路の配線リード材が細いワイヤであれば、過電流が流れた際のジュール熱でワイヤ自身が溶断し、これにより主回路が電気的にオープン状態となって過電流を遮断することができる。これに対して、図３のようにリボン状のリードフレーム４を採用した配線構造ではワイヤのように溶断する部分がないために、このままではオープン状態とならずに過電流を遮断することができない。 On the other hand, when an overcurrent flows due to a surge or the like with respect to the power semiconductor module, the semiconductor chip is destroyed and short-circuited, and if this overcurrent continues to flow, not only the semiconductor module but also the circuit is formed with this semiconductor module. There is also a possibility that a failure may spread to the configured inverter device.
In this case, if the wiring lead material of the main circuit is a thin wire, the wire itself is melted by Joule heat when overcurrent flows, and this causes the main circuit to become electrically open and cut off the overcurrent. can do. On the other hand, in the wiring structure employing the ribbon-like lead frame 4 as shown in FIG. 3, since there is no portion to be fused like a wire, the overcurrent cannot be cut off without being opened as it is. .

そこで、リードフレームを採用した半導体装置の過電流保護対策として、前記リードフレームの途中に断面縮小部を形成する、あるいはリードフレームを複数本の細いリードフレームに分けて配線するなどして電流ヒューズの機能を持たせて、過電流が流れた際にリードフレームを溶断して電流を遮断するようにした構成の半導体装置が知られている（例えば、特許文献２，特許文献３参照）。
特開２００１−１１０９５７号公報（図２） 特開２００３−１１００６４号公報（図１，図２） 特開２００６−１２０９７０号公報（図１，図２） Therefore, as a measure for overcurrent protection of a semiconductor device adopting a lead frame, a cross-sectional reduced portion is formed in the middle of the lead frame, or the lead frame is divided into a plurality of thin lead frames and wired. 2. Description of the Related Art A semiconductor device having a function and configured to cut off a current by fusing a lead frame when an overcurrent flows is known (see, for example, Patent Document 2 and Patent Document 3).
JP 2001-110957 A (FIG. 2) JP 2003-110064 (FIGS. 1 and 2) JP 2006-120970 A (FIGS. 1 and 2)

ところで、前記のようにリードフレーム自身にヒューズ機能を持たせて半導体素子を過電流から保護するには、その動作，機能面で高い信頼性が要求される。
すなわち、主回路の通電路であるリードフレームは、半導体装置の定格電流を連続し流す通電容量を確保し、一方では半導体素子の許容サージ電流，過電流耐量との保護協調を図りつつ、故障電流が流れた際には確実に溶断させ、かつ電流遮断後も回路のオープン状態を保持する必要がある。この要求に対して、先記した従来の構成では十分な過電流の保護機能が発揮できず、さらなる信頼性の向上が課題となる。 By the way, in order to protect the semiconductor element from overcurrent by providing the lead frame itself with a fuse function as described above, high reliability is required in terms of operation and function.
In other words, the lead frame, which is the current path of the main circuit, secures a current carrying capacity that allows the rated current of the semiconductor device to flow continuously, while at the same time protecting the fault current while maintaining protection coordination with the allowable surge current and overcurrent tolerance of the semiconductor element. When the current flows, it is necessary to blow out surely and to keep the circuit open even after the current is cut off. In response to this requirement, the above-described conventional configuration cannot exhibit a sufficient overcurrent protection function, and further improvement in reliability becomes an issue.

本発明は上記の点に鑑みなされたものであり、主回路の配線部材であるリードフレームに機能，動作面で信頼性の高いヒューズ機能を持たせて過電流保護が行えるようにした半導体装置を提供することを目的とする。   The present invention has been made in view of the above points, and provides a semiconductor device in which a lead frame which is a wiring member of a main circuit is provided with a fuse function that is highly reliable in function and operation so that overcurrent protection can be performed. The purpose is to provide.

上記目的を達成するために、本発明によれば、絶縁基板にマウントした半導体チップの上面主電極と絶縁基板の導体パターンとの間に主回路の配線用リード材としてリードフレームを布設し、該リードフレームの両端を接合相手部材に接合した半導体装置において、
（１）前記リードフレームの中間部位に線膨張係数がリードフレーム材と異なる絶縁材の条片を重ね合わせて一体結合し、そのバイメタル効果により過電流が流れた際にリードフレームの中間部位を撓ませて破断させるようにする（請求項１）。
（２）前項（１）の構造に加えて、リードフレームにおける絶縁材条片との重ね合わせ面域にヒューズエレメントとして機能する断面縮小部を形成し、前記バイメタル効果と集中発熱との相乗効果でリードフレームを確実に溶断させるようにする（請求項２）。
（３）前項（１），（２）において、リードフレームの材質が銅，アルミニウムないしその合金、絶縁材条片の材質がアルミナ，窒化アルミなどのセラミック系絶縁材で構成する（請求項３）。 In order to achieve the above object, according to the present invention, a lead frame is laid as a lead material for wiring of a main circuit between an upper surface main electrode of a semiconductor chip mounted on an insulating substrate and a conductor pattern of the insulating substrate, In a semiconductor device in which both ends of a lead frame are joined to a joining partner member,
(1) A strip of insulating material having a linear expansion coefficient different from that of the lead frame material is overlapped and integrally bonded to the intermediate portion of the lead frame, and the intermediate portion of the lead frame is bent when an overcurrent flows due to the bimetallic effect. It is made to break (Claim 1).
(2) In addition to the structure of (1) above, a cross-sectional reduced portion functioning as a fuse element is formed in the overlapping surface area of the lead frame with the insulating strip, and the synergistic effect of the bimetal effect and concentrated heat generation The lead frame is surely fused (Claim 2).
(3) In the preceding paragraphs (1) and (2), the lead frame is made of copper, aluminum or an alloy thereof, and the insulating strip is made of a ceramic insulating material such as alumina or aluminum nitride. .

上記のように両端を接合相手部材に接合して布設したリードフレームに対し、その中間部位に線膨張係数がリードフレーム材と異なる（線膨張係数が小さい）絶縁材の条片を重ね合わせて一体結合し、該部にバイメタル機能（両端固定）を持たせることにより、リードフレームに過電流が流れた際のジュール熱によるバイメタル効果によりリードフレームの中間部位が凸状に撓み変形するとともに、この撓み応力によりリードフレームを破断して主回路をオープン状態にすることができる。   For the lead frame that is laid with both ends joined to the mating member as described above, insulation strips with a different linear expansion coefficient from the lead frame material (small linear expansion coefficient) are overlapped and integrated in the middle part By combining and giving this part a bimetallic function (fixed at both ends), the intermediate part of the lead frame is bent and deformed in a convex shape due to the bimetallic effect due to Joule heat when overcurrent flows through the lead frame, and this bending The lead frame can be broken by stress to open the main circuit.

また、リードフレームにおける絶縁材条片との重ね合わせ面域にヒューズエレメントとして機能する断面縮小部を形成することにより、前記のバイメタル効果によるリードフレームの撓み変形と、断面縮小部によるジュール熱の集中発熱とが相乗的に作用して、リードフレームをその断面縮小部で確実に溶断させることかできる。   In addition, by forming a cross-sectional reduced portion that functions as a fuse element in the overlapping area of the lead frame with the insulating material strip, the bending deformation of the lead frame due to the bimetal effect and the concentration of Joule heat due to the cross-sectional reduced portion The heat generation acts synergistically, and the lead frame can be surely fused at the reduced cross-section.

以下、本発明の実施の形態を図１，図２に示す実施例に基づいて説明する。なお、実施例の図中で図３に対応する部材には同じ符号を付してその説明は省略する。   DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below based on the examples shown in FIGS. In addition, in the figure of an Example, the same code | symbol is attached | subjected to the member corresponding to FIG. 3, and the description is abbreviate | omitted.

図１は本発明の請求項１に係わる実施例を示すものである。この実施例においては、絶縁基板２の導体パターン２ｂにマウントした半導体チップ３の上面主電極と導体パターン２ｃとの間に布設して両端を接合した銅，アルミニウムないしその合金（例えば、Ｃｕ−Ｍｏ，Ａｌ−Ｍｏ合金を採用して脆性化させる）で作られたリードフレーム４に対し、その中間部位の裏側にはリードフレーム４の材質よりも線膨張係数が小さいアルミナ，窒化アルミなどのセラミック系絶縁材で作られた板状の条片１０を重ね合わせて一体結合している。なお、この絶縁材条片１０をリードフレーム４に一体結合するには、条片１０の接合面をメタライズしてリードフレーム４にろう付けする。あるいはクラッド加工法により一体化する。これにより、リードフレーム４の中間部位と絶縁材条片１０とで両端を固定したバイメタルの機能を持つようになる。   FIG. 1 shows an embodiment according to claim 1 of the present invention. In this embodiment, copper, aluminum or an alloy thereof (for example, Cu-Mo) laid between the upper surface main electrode of the semiconductor chip 3 mounted on the conductor pattern 2b of the insulating substrate 2 and the conductor pattern 2c and bonded at both ends. In contrast, the lead frame 4 made of Al-Mo alloy is made brittle, and the back side of the intermediate part has a ceramic system such as alumina or aluminum nitride whose linear expansion coefficient is smaller than the material of the lead frame 4 A plate-like strip 10 made of an insulating material is overlapped and integrally coupled. In order to integrally couple the insulating strip 10 to the lead frame 4, the joint surface of the strip 10 is metallized and brazed to the lead frame 4. Alternatively, they are integrated by a clad processing method. Thereby, it has a bimetal function in which both ends are fixed by the intermediate portion of the lead frame 4 and the insulating material strip 10.

上記構成で、半導体装置の通電状態で過電流が流れると、リードフレーム４に生じたジュール熱で前記の中間部位がバイメタル効果により凸状に湾曲して撓み、その撓み応力の作用でリードフレーム４が変形，破断して通電路をオープン状態にし、過電流を遮断する。なお、リードフレーム４が破断した後は、絶縁材条片１０が破断面の間を隔離して電流遮断後の絶縁を確保する。   With the above configuration, when an overcurrent flows while the semiconductor device is energized, the intermediate portion is bent and bent by the bimetal effect due to Joule heat generated in the lead frame 4, and the lead frame 4 is bent by the action of the bending stress. Deforms and breaks, opening the current path and interrupting overcurrent. In addition, after the lead frame 4 is broken, the insulating material strip 10 separates between the fractured surfaces to ensure insulation after current interruption.

次に、本発明の請求項２に対応する実施例を図２（ａ）〜（ｃ）で説明する。すなわち、この実施例ではリードフレーム４の中間部位に実施例１で述べた線膨張係数が小さい絶縁材の条片１０を重ね合わせて一体結合するとともに、さらにリードフレーム４における絶縁材条片１０との重ね合わせ面域にヒューズエレメントとして機能する断面縮小部４ａを形成している。この断面縮小部４ａは、図２（ａ）においてはリードフレーム４の上面中央を凹状にエッチングして形成している。また、図２（ｂ）のようにリードフレーム４の状面中央部を残してその左右側縁をトリミングして断面縮小部４ａ形成する、あるいは図２（ｃ）のようにリードフレーム４の板面にトリミング穴４ｃを穿孔して断面縮小部４ａを形成することもできる。   Next, an embodiment corresponding to claim 2 of the present invention will be described with reference to FIGS. That is, in this embodiment, the insulating material strip 10 having a small linear expansion coefficient described in the first embodiment is overlapped and integrally coupled to an intermediate portion of the lead frame 4 and is further combined with the insulating material strip 10 in the lead frame 4. A cross-sectional reduced portion 4a that functions as a fuse element is formed in the overlapping surface area. The cross-sectional reduced portion 4a is formed by etching the center of the upper surface of the lead frame 4 into a concave shape in FIG. Further, the left and right side edges of the lead frame 4 are trimmed by leaving the central portion of the shape surface of the lead frame 4 as shown in FIG. 2B to form a reduced cross-section 4a, or the plate of the lead frame 4 as shown in FIG. Trimming holes 4c may be drilled in the surface to form the cross-sectional reduced portion 4a.

上記の構成でリードフレーム４に過電流が流れると、先記したバイメタル効果によりリードフレーム４の断面縮小部４ａには撓み応力（引っ張り力）が作用することに加えて、断面縮小部４ａにジュール発熱が集中し、これによりリードフレーム４が断面縮小部４ａで確実に溶断して信頼性の高いヒューズ機能を発揮させることかできる。
なお、図示実施例では半導体チップ４の上面主電極に接続したリードフレーム４の中間部位にヒューズ機能部を構築しているが、例えば図３で入／出力端子６との間の主回路通電路に布設したリードフレーム５に形成して実施してもよい。 When an overcurrent flows through the lead frame 4 with the above configuration, in addition to the bending stress (tensile force) acting on the cross-sectional reduced portion 4a of the lead frame 4 due to the bimetal effect described above, a joule is applied to the cross-sectional reduced portion 4a. The heat generation is concentrated, so that the lead frame 4 can be surely melted at the cross-sectionally reduced portion 4a to exhibit a highly reliable fuse function.
In the illustrated embodiment, the fuse function unit is constructed at the intermediate portion of the lead frame 4 connected to the upper surface main electrode of the semiconductor chip 4. For example, the main circuit energization path between the input / output terminals 6 in FIG. It may be formed on the lead frame 5 laid on the board.

本発明の実施例１に係わる半導体装置の要部構造図Structure diagram of main part of semiconductor device according to Embodiment 1 of the present invention 本発明の実施例２に係わるリードフレームの断面縮小部を表す図で、（ａ），（ｂ），（ｃ）はそれぞれ形態の異なる構造図FIG. 5 is a diagram illustrating a cross-sectional reduced portion of a lead frame according to a second embodiment of the present invention, in which (a), (b), and (c) are structural diagrams having different forms. ＩＧＢＴモジュールを例示した半導体装置の従来構成図Conventional configuration diagram of semiconductor device exemplifying IGBT module

符号の説明Explanation of symbols

２ 絶縁基板
２ｂ，２ｃ 導体パターン
３ 半導体チップ（ＩＧＢＴ）
４，５ リードフレーム
４ａ 断面縮小部
１０ 絶縁材条片 2 Insulating substrate 2b, 2c Conductor pattern 3 Semiconductor chip (IGBT)
4,5 Lead frame 4a Reduced section 10 Insulation strip

Claims (3)

絶縁基板にマウントした半導体チップの上面主電極と絶縁基板の導体パターンとの間に主回路の配線用リード材としてリードフレームを布設し、該リードフレームの両端を接合相手部材に接合した半導体装置において、
前記リードフレームの中間部位に線膨張係数がリードフレーム材と異なる絶縁材の条片を重ね合わせて一体結合したことを特徴とする半導体装置。 In a semiconductor device in which a lead frame is laid as a lead material for wiring of a main circuit between an upper surface main electrode of a semiconductor chip mounted on an insulating substrate and a conductor pattern of the insulating substrate, and both ends of the lead frame are bonded to a bonding partner member ,
A semiconductor device, wherein a strip of an insulating material having a linear expansion coefficient different from that of the lead frame material is overlapped and integrally coupled to an intermediate portion of the lead frame. 請求項１に記載の半導体装置において、リードフレームにおける絶縁材条片との重ね合わせ面域にヒューズエレメントとして機能する断面縮小部を形成したことを特徴とする半導体装置。 2. The semiconductor device according to claim 1, wherein a cross-sectional reduced portion functioning as a fuse element is formed in a surface area of the lead frame overlapping with the insulating material strip. 請求項１に記載の半導体装置において、リードフレームの材質が銅，アルミニウムないしその合金、絶縁材条片の材質がアルミナ，窒化アルミなどのセラミック系絶縁材であることを特徴とする半導体装置。 2. The semiconductor device according to claim 1, wherein the material of the lead frame is copper, aluminum or an alloy thereof, and the material of the insulating strip is a ceramic insulating material such as alumina or aluminum nitride.
JP2006301370A 2006-11-07 2006-11-07 Semiconductor device Pending JP2008118010A (en)

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Publication number Priority date Publication date Assignee Title
JP2011185918A (en) * 2010-02-10 2011-09-22 Tdk Corp Electronic circuit board, magnetic sensor using the same, and method of protecting power supply of electronic circuit
US8482895B2 (en) 2010-02-10 2013-07-09 Tdk Corporation Electronic circuit board, magnetic sensor, and method for protecting power supply of electronic circuit
JP2018067611A (en) * 2016-10-19 2018-04-26 三菱電機株式会社 Semiconductor device and power conversion device
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JPWO2018193581A1 (en) * 2017-04-20 2019-11-07 三菱電機株式会社 Power converter
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