JP2008117068A - Information processing system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To optimize data transfer in an information processing system by dispersing access paths used for data transfer in a system bus. <P>SOLUTION: The system bus to which a variety of devices such as a CPU 2 are connected is divided into three, and the devices are connected to these system buses 20A, 20B, 20C in a dispersed manner. The system buses 20A to 20C are interconnected as devices capable of accessing one another. Each of the system buses 20A to 20C is provided with a bus monitor circuit for monitoring the status of access from each of the devices, and a regulating circuit 30 operates each bus monitor circuit for a certain period of time for each application run by the CPU 2, to determine whether or not there exists an overloaded path whose occupancy in access paths between the system buses 20A to 20C exceeds a threshold level; if an overloaded path is detected, a bypass route is set so that the occupancy of the access paths is reduced. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an information processing system capable of controlling access between devices connected via a system bus.

  Conventionally, a navigation device mounted on a vehicle includes an image captured by an in-vehicle camera in addition to the original control of the navigation device such as a map display for displaying a road map on a display and a travel guide for displaying a travel route on the display map. Display control that displays received images and television tuners on the display, audio playback control that generates audio signals by decoding received signals from receivers that receive encrypted music information, display image switching commands and selection There is known one that executes a control that realizes a function different from the original function of the navigation device, such as an operation control that receives a station command or the like and outputs it to another in-vehicle device such as an in-vehicle camera or a TV tuner.

  In an information processing system that executes many types of control as multifunctional functions, such as this type of navigation device, arithmetic processing (application software: A system bus 20 to which a CPU 2 for executing (hereinafter also referred to simply as an application) is connected is connected to a DMA controller 4, a serial communication controller 6, a cryptographic engine 8, an MPEG decoder 10, a memory 12, a graphic controller 14, a PCI-Ex interface 16,. Many devices are connected.

  By the way, the system bus 20 includes an arbiter that permits use of the bus to one of a plurality of devices in accordance with a request from a device connected to the system bus 20, and a device (master) that the arbiter has permitted use of the bus. A decoder is provided for selecting a device (slave) that is an access destination from () to connect the master / slave so that data can be transferred.

  9, M0, M1,... Represent master access from each device 2-16 connected to the system bus 20, and S0, S1,... Represent slave access to each device 2-16. .

  In addition, the arbiter selects a device that permits the use of the bus according to a preset priority, but if a device with a high priority is frequently accessed, the device with the low priority becomes the master. It becomes impossible to access other devices (slave).

Therefore, conventionally, in this type of information processing system, the occupancy state of the system bus 20 by each device (master) is monitored, and a device whose occupancy rate exceeds a threshold value is transferred from that device to the system bus 20. It is proposed that even the device (master) having a low priority can use the system bus 20 under the control of the arbiter (for example, see Patent Document 1). .
JP 2000-259547 A

  However, although the proposed technique can prevent the device (master) permitted to use the system bus by the arbiter from concentrating on a specific device, the slave side device selected by the decoder is not specified. It cannot prevent you from concentrating on the device.

  In other words, when the slave devices selected by the decoder are concentrated on a specific device, the data transfer speed on the access path becomes a bottleneck and it takes time to switch the master that occupies the system bus. In some cases, the data transfer necessary for executing each application cannot be realized. However, the above-mentioned proposed technique cannot prevent such a problem.

  The present invention has been made in view of such problems, and in an information processing system in which data transfer is performed between a plurality of devices via a system bus, an access path used for data transfer by the system bus is distributed, The purpose is to optimize data transfer.

  In the information processing system according to claim 1, which is made to achieve the above object, a system bus to which various devices are connected is divided into three or more, and the divided system buses are mutually accessible. Connected as a device.

  Each system bus has an arbiter that allows one device to use the system bus in response to a request from a device connected to the system bus, and a master side device that the arbiter has permitted to use. A decoder is provided that selects the slave device that is the access destination of the device and connects these devices via the system bus.

  Therefore, according to this information processing system, for each device constituting the information processing system, three or more system buses are used as an access path when the device becomes a master and accesses another device (slave). It is possible to select from a plurality of access paths that can be realized.

  Therefore, according to the information processing system of the present invention, the access path when each device becomes a master and accesses another slave device includes the path connecting the system buses, and one of the paths. By setting the slave side device that the decoder in each system bus selects according to the request from the master side device, the device that becomes the master and slave in the entire system, including each system bus, is set. By distributing the data, it is possible to optimize data transfer on the system bus.

  By the way, in the information processing system, the device with high access frequency is different for each application executed by the CPU for both the master and the slave. As described above, the slave device selected by the decoder in each system device is set in advance. Even so, if the application executed by the CPU changes, two specific system buses frequently operate as master / slave, and the path between the system buses may become a bottleneck.

  Therefore, in order to prevent such a problem, as described in claim 2, in the information processing system according to claim 1, the overload path detecting means monitors the access status between the system buses. When the overload path is detected by the overload path detection means, the path changeable device extraction means detects the overload path detected when the access path whose occupation ratio exceeds the set level is detected. From the master side device that accesses the slave side device via the load path, one of the master side devices that can access the slave side device by bypassing the overload path is extracted, and the access path changing means extracts the master side device. The device provided on the system bus is such that the route when the master device accesses the slave device is a bypass route that does not use the overload route. It may be configured to change the behavior of over da.

  In other words, in this way, even if the frequency of use of one of the access paths formed between the system buses increases depending on the type of application executed by the CPU, the path is detected as an overload path, Since a detour route that bypasses the route is automatically set, the access route between specific system buses becomes a bottleneck in a specific application, and data transfer between devices cannot be performed well. Can be prevented.

  Further, in this case, in order to enable the path changeable device extraction unit to accurately extract one of the master side devices that can bypass the overload path and access the slave side device, As described above, the path changeable device extraction means is provided with a path information storage means in which paths that can be used when a device connected to each system bus accesses another slave side device as a master side device are registered in advance. The path changeable device extraction means uses the path information stored in the path information storage means when extracting the master side device that can bypass the overload path and access the slave side device. You can do it.

  Further, when the path changeable device extraction unit extracts a master device that can bypass the overload route and can access the slave device, if there are a plurality of master devices that can be extracted, Among the master side devices, it is preferable to extract the master side device having the largest occupation rate of the overload path.

  For this purpose, as described in claim 4, the overload path detecting means includes an access between each system bus and a device connected to each system bus in addition to the access status between each system bus. The device is also configured to monitor the situation, and on the path changeable device extraction means side, the master with the highest occupation rate of the overload path is based on the access situation between the system bus and the device detected by the overload path detection means. The side device may be extracted.

  Next, in the information processing system according to any one of claims 2 to 4, in order to be able to always optimally set the access path used for data transfer, the overload detection means may be operated at all times. However, in this case, when the CPU is executing a specific application and the access route from each device is set to the optimum route corresponding to the application, the overload detection means is operated unnecessarily. It will end up.

  Therefore, in the information processing system according to claims 2 to 4, as described in claim 5, a plurality of information processing (that is, applications) that can be executed by the information processing system are further executed in order. Operating condition setting for setting the operating condition of each decoder suitable for execution of each information processing by operating the overload detecting means, the path changeable device extracting means, and the access path changing means at the time of information processing. Each time the information processing executed in the information processing system is changed, the operating conditions of each decoder suitable for the information processing after the change are selected from the operating conditions set by the operating condition setting means. The decoder operation switching means for changing the operation condition of each decoder may be provided.

  Then, when the application executed by the CPU of the information processing system is changed without always operating the overload detection means, the operating condition of each decoder is changed to the execution of the application. It becomes possible to switch to suitable operating conditions.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram showing the overall configuration of an information processing system according to an embodiment to which the present invention is applied.

  The information processing system of the present embodiment is similar to the conventional apparatus illustrated in FIG. 9 in that the CPU 2, the DMA controller 4, the serial communication controller 6, the cryptographic engine 8, the MPEG decoder 10, the memory 12, A number of devices such as a graphic controller 14 and a PCI-Ex interface 16 are provided.

  On the other hand, the system bus 20 to which these devices are connected is divided into three, and the three divided system buses 20A, 20B, and 20C are mutually connected as devices that are mutually accessible as a master / slave. It is connected.

  Of these three system buses 20A to 20C, the CPU 2 and the PCI-Ex interface 16 are connected to the system bus 20A, and the DMA controller 4, the serial communication controller 6, and the cryptographic engine 8 are connected to the system bus 20B. Then, the MPEG decoder 10, the memory 12, and the graphic controller 14 are connected to the system bus 20C.

  Further, as shown in FIG. 2, each system bus 20A to 20C has a permission signal ACKn (n) sent to one device in accordance with requests REQ0, REQ1, REQ2,... From devices connected to the bus. :, 0, 1, 2,. Select the device (slave Sk (k: 0, 1, 2,...)) That is the access destination from (j: 0, 1, 2,...)), And connect these master / slave so that data can be transferred. A decoder 24 is provided.

  As shown in FIG. 3, the decoder 24 includes a plurality of selectors 26 provided for each device that can be slaves S0, S1, S2,..., And through one of the selectors 26, masters M0, M1, M2..., One of the access signals from each device that can be selected, and output to one of the devices that can be slaves S0, S1, S2,..., And each selector 26 is controlled by a decoder control circuit 28. Driven.

  The decoder control circuit 28 also accesses the access destination from the device (master Mj) that the arbiter 22 has authorized to use the bus based on the permission signal ACKn output from the arbiter 22 and the preset operating conditions of the decoder 24. Each device (slave Sk) is specified, and the selector 26 corresponding to the slave Sk selects the access signal from the master Mj, and the other selector 26 does not select the access signal. 26 is driven.

  Note that the operating conditions of the decoder 24 used by the decoder control circuit 28 to drive each selector 26 in the decoder 24 are set by an adjustment circuit 40 which is a main part of the present invention.

  In addition, the system buses 20A to 20C have access states from the devices that can be masters M0, M1, M2,... To the bus, and access from the buses to devices that can be slaves S0, S1, S2,. A bus monitor circuit 30 for monitoring each state is provided.

  The bus monitor circuit 30 is provided for each device that can be a master M0, M1, M2,..., And a plurality of master access monitors that monitor the access state from each device (master M0, M1, M2,...) To the bus. .. And a plurality of slave access monitor units 36 that monitor the access state from the bus to each of these devices (slave S0, S1, S2,...). It consists of and.

  Then, as illustrated in FIG. 4A, the master access monitor unit 31 is set by a permission signal ACK0 output from the arbiter 22 to a master device to be monitored (master M0 in the figure) and is a counter enable signal. The flip-flop 32 that outputs CEN and the enable signals ACK1, ACK2,... Output from the arbiter 22 to other master side devices (masters M1, M2,. By receiving the OR gate 33 for stopping the output of the signal CEN and the counter enable signal CEN output from the flip-flop 32 and counting the system clock, the access time from the master device to be monitored to the bus is counted. Counter 34.

  Further, as illustrated in FIG. 4B, the slave access monitor unit 36 receives the select signal CS0 that is asserted when the slave device to be monitored (master S0 in the figure) is selected by the decoder 24. The counter 38 is configured to count the access time from the bus to the slave device to be monitored by counting the system clock.

  For this reason, in the bus monitor circuit 30, as shown in FIG. 4C, the system buses 20A to 20C are controlled via the bus under the control of the arbiter 22 and the decoder 24 (specifically, the decoder control circuit 28). Each time the master Mj and slave Sk connected to each other are switched, the access times t1, t2, t3,... Of the master Mj and slave Sk that have occupied the bus until then are timed. The bus monitor circuit 30 operates in accordance with a command from the adjustment circuit 40 and normally operates only for a certain monitoring period T.

  Next, when one of the devices constituting the information processing system accesses another device, the adjustment circuit 40 selects a device or system bus selected as the master Mj and the slave Sk in each of the system buses 20A to 20C. By measuring the access time via the bus monitor circuit 30 provided in each of the system buses 20A to 20C, the access path between each device and the system bus or between the system buses is determined for each application executed by the CPU 2. The occupancy rate is obtained, and the route (data flow) of data flowing between the devices is set so that the occupancy rate is distributed in each access route. For example, the occupancy rate is configured by a logic circuit such as an ASIC. Yes.

  In addition, as shown in FIG. 5, the adjustment circuit 40 can be realized by appropriately selecting three system buses 20 </ b> A to 20 </ b> C as route information when one of the devices accesses another device. The route information is registered in advance in a memory (not shown) as route information storage means, and the adjustment circuit 40 follows the registered route information, and a route (data flow) when one of the devices accesses another device. Set.

  That is, for example, as a path when an information device connected to the PCI-Ex interface 16 directly accesses the memory 12 via the PCI-Ex interface 16, the PCI-Ex interface 16 via the system buses 20A and 20C is used. Either a path for accessing the memory 12 or a path for accessing the memory 12 from the PCI-Ex interface 16 via the system buses 20A, 20B, and 20C can be selected.

Therefore, in this case, the path information between the devices (between the PCI-Ex interface 16 and the memory 12) is stored in the memory.
(1) In the system bus 20A, the decoder 24 selects the slave S2 (that is, the system bus 20C) according to the access request of the memory 12 from the master M3 (that is, the PCI-Ex interface 16), and the master M0 (that is, the system bus) in the system bus 20C. 20A) first path information that causes the decoder 24 to select the slave S3 (that is, the memory 12) in accordance with the access request of the memory 12 from 20A),
(2) In the system bus 20A, the decoder 24 selects the slave S1 (that is, the system bus 20B) according to the access request of the memory 12 from the master M3 (that is, the PCI-Ex interface 16), and the master M4 (that is, the system bus) in the system bus 20B. 20A) causes the decoder 24 to select the slave S3 (that is, the system bus 20C) according to the access request of the memory 12 from the memory 20A), and causes the decoder 24 to select the slave S3 according to the access request of the memory 12 from the master M1 (that is, the system bus 20B). Second path information for selecting (that is, the memory 12);
These two types of route information are registered.

  Then, the adjustment circuit 40 selects one of the two pieces of route information from the occupancy obtained for each access route during execution of each application so that the occupancy does not increase in a specific route, The operation of the decoder 24 of each system bus 20A to 20C (that is, the control operation of the decoder control circuit 28) is set.

  Hereinafter, the operation of the adjustment circuit 40 will be described. The adjustment circuit 40 of the present embodiment is configured by a logic circuit or the like. However, since the adjustment circuit 40 can be realized as one application executed by the CPU 2, the adjustment circuit 40 will be described in the following description. In order to make it easy to understand the operation of the above, it will be described with reference to the flowchart shown in FIG.

  As shown in FIG. 6, the adjustment circuit 40 receives an instruction from the outside and obtains an occupancy ratio of an access path between each device and the system bus or between the system buses for each application executed by the CPU 2. An access route setting process for changing the data flow setting so that the occupancy is distributed in each access route, and an access that sets an optimum access route according to the application executed by the CPU 2 during normal operation of the information processing system Two types of processing are executed: route change processing.

  First, in the access route setting process, in S110 (S represents a step), the CPU 2 is caused to execute the first application preset, and the decoder 24 is currently set for the application. The control operation of the decoder control circuit 28 is set so as to operate under conditions.

  In the subsequent S120, the bus monitor circuit 30 provided in each of the system buses 20A to 20C is operated for a predetermined monitoring period T, and in the subsequent S130, the bus monitor circuit of each of the system buses 20A to 20C during the monitoring period. The CPU 2 executes the first application by reading the count value (that is, access time) for each access route counted within 30 and obtaining the ratio of the read access time to the monitoring period T in S140. The occupancy ratio of the master / slave selected as the access path in each of the system buses 20A to 20C is calculated.

  As a result, for example, the CPU 2 transfers map data from the external device connected to the PCI-Ex interface 16 to the memory 12, performs calculation processing for road map display based on the map data, and displays the road map as a graphic. When an application for road map display to be displayed on the display via the controller 14 is executed, as shown in FIG. 7, access from the PCI-Ex interface 16 to the memory 12, access from the CPU 2 to the memory 12, Access from the CPU 2 to the graphic controller (GC) 14 and access from the graphic controller (GC) 14 to the memory 12 are sequentially performed. At each access time, the master / slave selected as the access path on each of the system buses 20A to 20C. Occupancy is required It will be.

  As described above, when the occupation ratio of the master / slave selected as the access path in each system bus 20A to 20C is obtained in S140, the process proceeds to S150, and the calculation result (monitor result) of the occupation ratio is obtained. Based on the above, it is determined whether or not there is an overload path in which the occupation ratio exceeds a set level (for example, 50%) among the three access paths that are formed between the system buses 20A to 20C and can be changed. Then, processing as an overload path detecting means is executed.

  If no overload path is detected in S150, the process proceeds to S190, which will be described later. If an overload path is detected in S150, the process proceeds to S160, and access processing (data A process as a path changeable device extraction unit that extracts an access process (data flow) having the largest occupation ratio of the overload path from the flow) is executed.

  In subsequent S170, the access path (data flow) used in the access process selected in S160 is changed to an access path different from the currently selected one based on the path information shown in FIG. Processing as an access route changing unit is executed, and in S180, the changed access route is stored in the built-in memory as an access route used by the application executed this time.

  Specifically, for example, the monitoring result is as shown in FIG. 7, and the occupation rate of the access path from the system bus 20A to the system bus 20C (that is, the occupation of the slave S2 of the system bus 20A and the master M0 of the system bus 20C) Rate) exceeds the set level, in S160, the occupancy is the highest among the access processes using the access path (access processes executed first to third of the application shown in FIG. 7). The access process from the CPU 2 to the memory 12 is selected.

  In S170, another access route different from the access route “1” set up to now is selected from the two access routes between “CPU → memory” shown in FIG. The access route “2” is selected, and the access route is changed as shown by a dotted line in FIG.

  In this case, as is apparent from the table of FIG. 8, in the system bus 20A, the access time to the slave S2 decreases and the access time to the slave S1 increases, and in the system bus 20B, the access time from the master M1. Since the access time to the slave S3 increases and the access time from the master M0 decreases and the access time from the master M1 increases in the system bus 20C, as a result, data is transferred between the system buses 20A to 20C. Access paths used for transfer are distributed.

  Next, in S190, it is determined whether or not the series of processing in S110 to S180 has been performed for all applications that can be executed by the CPU2. If the above-described series of processing is executed for all applications, the access route setting process is terminated. Conversely, if the above-described series of processing is not executed for all applications, in S200, One of the applications that have not executed the series of processes is selected as the next execution application, and the process proceeds to S110, whereby the series of processes of S110 to S180 is executed for the selected application.

  Therefore, according to the information processing system of the present embodiment, the access paths used for data transfer on the system buses 20A to 20C can be distributed for each application executed by the CPU 2. In the present embodiment, the processing of S180 to S200 realizes the function as the operating condition setting means of the present invention.

  On the other hand, the access path change process executed during normal operation of the information processing system determines whether or not the application executed by the CPU 2 has been changed in S310, and in S310, it is determined that the application has been changed. In S320, the access route corresponding to the application is selected from the latest access routes set by the access route setting process, and data transfer is performed on the system bus according to the selected access route. The control operation of the decoder control circuit 28 is set so that the control operation is performed.

  Therefore, when the application executed by the CPU 2 is changed, the data transfer path in the system buses 20A to 20C is appropriately changed according to the application, and the system buses 20A to 20C are connected. It is possible to prevent the data transfer efficiency from deteriorating due to a temporary increase in the frequency of use of the specific access route.

In this embodiment, the access path changing process shown in FIG. 6 corresponds to the decoder operation switching means of the present invention.
As mentioned above, although one Embodiment of this invention was described, this invention is not limited to the said embodiment, A various aspect can be taken in the range which does not deviate from the summary of this invention.

  For example, in the above-described embodiment, the system bus is divided into three, and the use frequency of the access path used for data transfer between these buses is distributed. However, the system bus may be divided into four or more.

  Further, for example, in the above embodiment, since there is one access path from the system bus 20C to the memory 12, the occupation ratio of this path is increased, but the bus is set so that there are a plurality of access paths to the memory 12. And the memory may be divided into banks so that the memory can be accessed simultaneously from each bus.

It is a block diagram showing the structure of the whole information processing system of embodiment. It is a block diagram showing the structure of a system bus. It is explanatory drawing explaining the structure of a decoder, and operation | movement of a decoder control circuit. It is explanatory drawing explaining the structure and its operation | movement of a bus monitor circuit. It is explanatory drawing explaining the path | route information stored in the built-in memory of an adjustment circuit. It is a flowchart explaining operation | movement of an adjustment circuit. It is explanatory drawing showing the calculation result of the access route at the time of the application execution for a road map display, and the occupation rate of each route. It is explanatory drawing showing the calculation result of the access path | route changed based on the calculation result shown in FIG. 7, and the occupation rate of each path | route. It is a block diagram showing the structure of the conventional information processing system.

Explanation of symbols

  2 ... CPU, 4 ... DMA controller, 6 ... serial communication controller, 8 ... serial communication controller, 8 ... cryptographic engine, 10 ... MPEG decoder, 12 ... memory, 14 ... graphic controller, 16 ... PCI-Ex interface, 20, 20A , 20B, 20C ... system bus, 22 ... arbiter, 24 ... decoder, 26 ... selector, 28 ... decoder control circuit, 30 ... bus monitor circuit, 31 ... master access monitor unit, 32 ... flip-flop, 33 ... OR gate, 34 ... Counter, 36 ... Slave access monitor, 38 ... Counter, 40 ... Adjustment circuit.

Claims (5)

The system bus,
A plurality of devices connected to the system bus;
An arbiter that permits one device to use the system bus in response to a request from each device;
A decoder that selects a slave-side device that is an access destination from a master-side device that the arbiter is permitted to use, and connects the devices via the system bus;
In an information processing system equipped with
An information processing system in which the system bus is divided into three or more, the system buses are connected to each other as mutually accessible devices, and the arbiter and the decoder are provided in the system buses, respectively. . Overload path detection means for monitoring the access status between the system buses and detecting as an overload path an access path whose occupation rate exceeds a set level;
When the overload path is detected by the overload path detecting means, the slave side device is accessed by bypassing the overload path from among the master side devices accessing the slave side device via the overload path. Reroutable device extraction means for extracting one of the possible master side devices;
The operation of the decoder provided in each system bus is performed so that the route when the master device extracted by the route changeable device extraction unit accesses the slave device becomes a bypass route that does not use the overload route. An access route changing means to be changed;
The information processing system according to claim 1, further comprising: The path changeable device extraction means includes:
A path information storage means in which a path that can be used when a device connected to each system bus accesses another slave side device as a master side device;
And extracting a master side device that can bypass the overload route and access the slave side device based on the route information stored in the route information storage means. Processing system. The overload path detecting means monitors the access status between the system buses and devices connected to the system buses in addition to the access status between the system buses,
When there are a plurality of master-side devices that can access the slave-side device by bypassing the overload path, the path-changeable device extraction unit includes a system bus and a device detected by the overload path detection unit, 4. The information processing system according to claim 2, wherein the master side device having the largest occupation ratio of the overload path is extracted based on an access state between the two. A plurality of information processing that can be executed in the information processing system is executed in order, and when each information processing is executed, each of the overload detection unit, the route changeable device extraction unit, and the access route change unit is operated, Operation condition setting means for setting operation conditions of each decoder suitable for execution of information processing;
Each time the type of information processing executed in the information processing system is changed, the operating condition of each decoder suitable for the information processing after the change is selected from the operating conditions set by the operating condition setting means. And decoder operation switching means for changing the operation condition of each decoder according to the extracted operation condition;
The information processing system according to any one of claims 2 to 4, further comprising:

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