JP2008109125A - Silicon single-crystal substrate, and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a silicon single-crystal substrate which guarantees sufficient strength of a silicon single-crystal substrate, while preventing effectively autodoping and reducing fully generating of particles in the manufacture of an epitaxial wafer. <P>SOLUTION: In a semiconductor wafer for epitaxial growth which has a main mirror surface and a rear surface, the wafer consists of a silicon single-crystal substrate and has a chamfering part, respectively between an outer peripheral side face of the silicon single-crystal substrate and the above main mirror surface and the rear surface. After imparting a process which grows up a CVD film onto at least the rear surface and the chamfering part of the rear surface side, the CVD film which wraps around the chamfering part by the side of the main mirror surface is removed mechanically. By this way, it is made possible to provide a semiconductor wafer for epitaxial growth wherein its mirror surface is finished having the maximum height roughness (Rz) of 0.3 μm or less. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a silicon single crystal substrate and a method for manufacturing the same, and more particularly to a silicon single crystal substrate used for vapor phase growth of an epitaxial layer and a method for manufacturing the same.

In general, a silicon single crystal substrate is formed by slicing, etching and polishing a substrate from a silicon single crystal ingot grown from molten silicon to which B as an acceptor or P, As or Sb as a donor is added. Manufactured by. It is also known to manufacture a silicon wafer by epitaxial growth of a silicon single crystal instead of from molten silicon. In such an epitaxial wafer, a low concentration dopant of about 1 × 10 ¹⁵ atoms / cm ³ is added on the above-described silicon single crystal substrate to which a high concentration dopant of about 7 × 10 ¹⁸ atoms / cm ³ is added. Some are formed by vapor phase epitaxy.

  In order to manufacture an epitaxial wafer, when a vapor phase growth is performed by heating a high concentration dopant-added silicon single crystal substrate as described above to a high temperature in a hydrogen atmosphere, the back surface of the substrate is mainly etched by hydrogen, The dopant added at a high concentration is released into the gas phase. The dopant released into the vapor phase is re-incorporated into the epitaxial layer undergoing vapor phase growth, causing a so-called auto-doping phenomenon and making the dopant concentration in the epitaxial layer non-uniform. Therefore, conventionally, in order to suppress this auto-doping phenomenon, a protective film made of silicon dioxide or silicon nitride is formed on the back surface of the silicon single crystal substrate to prevent the substrate from being etched by hydrogen.

  Such a protective film can be formed on the back surface of the silicon single crystal substrate by, for example, a CVD method (chemical vapor deposition method). In this CVD process, the main surface side and the peripheral portion of the silicon single crystal substrate are formed. The protective gas (CVD film) is formed in the same manner as the raw material gas flows around. It has been proposed to remove the CVD film formed around the main surface side and the peripheral edge of the substrate mechanically or chemically (Patent Document 1), for example, by tape polishing (Patent Document 3).

By the way, in the silicon single crystal substrate used for vapor phase growth of the above-described epitaxial layer, particles may be generated due to the chipping of the peripheral portion. Needless to say, it is desirable to reduce the number of particles generated due to the lack of the peripheral portion in the formation of the epitaxial growth layer. For this reason, an arc-shaped chamfered portion having a radius of about ½ t is formed in the peripheral portion of the wafer having a thickness t, and the maximum surface roughness (Rmax) is 0 at a portion of 500 μm along the surface adjacent to the main mirror surface. It has been proposed to form a mirror surface of 5 μm or less (Patent Document 2).
Japanese Patent No. 2757069 Japanese Patent Publication No. 7-82997 Japanese Patent Laid-Open No. 10-70080

  However, since these ideas are made on a one-time basis in order to obtain the respective effects, preferable characteristics as the whole silicon single crystal substrate are not obtained. Moreover, since silicon single crystal substrates are handled in large quantities in recent years, it is desired to keep the rate of breakage during handling of silicon single crystal substrates extremely low.

  For example, the CVD film formed around the main surface side and the peripheral portion of the silicon single crystal substrate can be removed by tape polishing to effectively prevent autodoping, but the chamfered portion at the peripheral portion The generation of particles cannot always be effectively prevented due to chipping or the like. On the other hand, even if the surface of the chamfered portion at the peripheral edge of the silicon single crystal substrate is formed into a mirror surface having a maximum surface roughness (Rz) of 0.5 μm or less and the generation of particles can be reduced to some extent, Autodoping due to dopant added to the concentration cannot be effectively prevented.

  Furthermore, if the surface roughness of the polished surface of the chamfered portion is a mirror surface having a maximum surface roughness (Rz) of 0.5 μm or less, it is difficult to ensure sufficient strength of the silicon single crystal substrate.

  In view of the above points, in manufacturing an epitaxial wafer, a method for manufacturing a silicon single crystal substrate that effectively prevents autodoping, sufficiently reduces generation of particles, and ensures sufficient strength of the silicon single crystal substrate is provided. It is an object of the present invention.

  According to the present invention, in an epitaxial growth semiconductor wafer having a main mirror surface and a back surface, the wafer is made of a silicon single crystal substrate, and a chamfered portion is provided between the outer peripheral side surface of the silicon single crystal substrate and the main mirror surface and the back surface, respectively. Provided, and after performing the step of growing the CVD film at least on the back surface and the chamfered portion on the back surface side, the CVD film that has wrapped around the chamfered portion on the main mirror surface side is mechanically removed, and the maximum surface roughness (Rz) is It is characterized by providing a semiconductor wafer for epitaxial growth characterized by having a mirror finish of 0.3 μm or less.

  More specifically, the following are provided.

(1) In an epitaxial growth semiconductor wafer having a primary mirror surface and a back surface, the wafer is made of a silicon single crystal substrate, and includes a chamfered portion between an outer peripheral side surface of the silicon single crystal substrate and the primary mirror surface and the back surface, After performing the step of growing the CVD film on the chamfered portion on the back surface and the back surface side, the CVD film wrapping around the chamfered portion on the main mirror surface side is mechanically removed, and the maximum surface roughness or the maximum height roughness ( It is possible to provide a semiconductor wafer for epitaxial growth characterized in that a mirror surface having a Rz) of 0.3 μm or less is finished.

  Here, the maximum surface roughness (Rz) is based on JIS B O601-2001, and the measurement length is 0.2 mm.

(2) The CVD film wrapping around the outer peripheral side surface is mechanically removed to finish a mirror surface having a maximum surface roughness or a maximum height roughness (Rz) of 0.3 μm or less (1) The semiconductor wafer for epitaxial growth described in the above can be provided.

  The mirror surface of the chamfered portion can be formed by a polishing apparatus using a polishing drum, but the mirror surface of the outer peripheral side surface can also be formed by the same apparatus. Either of these mirror surfaces may be performed first, or both may be polished little by little.

(3) The mirror finish of the chamfered portion on the main mirror surface side is a maximum surface roughness or a maximum height roughness (Rz) of 0.3 μm or less, and an arithmetic average roughness (Ra) of 0.01 μm or less, The peak of the amplitude distribution curve of the roughness is above the average line, and the semiconductor wafer for epitaxial growth described in (1) or (2) above can be provided.

  Here, the generation of particles due to chipping or the like can be influenced not only by the mere magnitude of the surface roughness but also by the shape (for example, the shape of the amplitude distribution curve of the roughness).

(4) The mirror finish of the outer peripheral side surface is a maximum surface roughness or a maximum height roughness (Rz) of 0.3 μm or less, an arithmetic average roughness (Ra) is 0.01 μm or less, and an amplitude of the roughness The peak of the distribution curve is above the average line, and the semiconductor wafer for epitaxial growth described in (2) above can be provided.

(5) A method of manufacturing a semiconductor wafer for epitaxial growth having a main mirror surface and a back surface, the wafer comprising a silicon single crystal substrate, and chamfering between the outer peripheral side surface of the silicon single crystal substrate and the main mirror surface and the back surface A step of forming a portion, a step of growing a CVD film on at least the back surface and the chamfered portion on the back surface side, a step of mechanically removing the CVD film that has wrapped around the chamfered portion on the main mirror surface side, and the chamfered portion It is possible to provide a method for manufacturing a semiconductor wafer for epitaxial growth, comprising a step of finishing a mirror surface having a maximum surface roughness or a maximum height roughness (Rz) of 0.3 μm or less.

(6) Furthermore, a step of mechanically removing the CVD film that has wrapped around the outer peripheral side surface, and a step of finishing the CVD film removal surface on the outer peripheral side surface to a mirror surface having a maximum surface roughness (Rz) of 0.3 μm or less, The method for producing a semiconductor wafer for epitaxial growth as described in (5) above can be provided.

(7) The mirror finish of the chamfered portion on the main mirror surface side has a maximum height or a maximum height roughness of 0.3 μm or less, an arithmetic average roughness (Ra) of 0.01 μm or less, and a roughness amplitude The method for producing a semiconductor wafer for epitaxial growth according to (5) or (6) above, wherein the peak of the distribution curve is above the average line.

(8) The mirror finish of the outer peripheral surface is a maximum surface roughness or a maximum height roughness of 0.3 μm or less, an arithmetic average roughness (Ra) is 0.01 μm or less, and an amplitude distribution curve of roughness The method for producing a semiconductor wafer for epitaxial growth according to (6) above, wherein the peak is above the average line.

  The evaluation of the surface roughness will be briefly described with reference to FIGS. FIG. 3 illustrates the definition of the maximum surface roughness or the maximum height roughness [Rz (JIS B O601-2001) or Ry (JIS B O601-1994) or Rmax (JIS B O601-1982)]. . From the vertical axis 100 representing the height direction of the roughness, a roughness curve 104 is drawn when the reference length l (110) is scanned for roughness measurement. At this time, the swell component is removed using a predetermined cutoff value. The sum of the height Yp from the average line 102 of the roughness curve 104 to the highest peak (height 106) and the depth Yv to the lowest valley bottom (height 108) is the maximum height (Ry). .

  As can be seen from this figure, if there is a conspicuously high peak or deep valley even at one place, it becomes a large value, and in general, variations in measured values tend to increase.

  FIG. 4 illustrates the definition of arithmetic average roughness [Ra (JIS B O601-2001)]. Similarly, from the vertical axis 100 representing the height direction of the roughness, a roughness curve 104 when the reference length (l) 110 is scanned for roughness measurement is drawn. At this time, the swell component is removed using a predetermined cutoff value. The absolute value of the deviation from the average line 102 of the roughness curve 104 to the measurement curve 104 is summed, and the average value is the arithmetic average roughness (Ra) 112.

  As can be seen from this figure, for example, even if there is a conspicuously high peak or deep valley, the influence on the measured value is very small, and a stable result is easily obtained.

  FIG. 5A illustrates the definition of the load length rate tp. The ratio of the sum of the cutting lengths (load length np) obtained when cutting the roughness curve 104 at the cutting level 114 parallel to the peak line 106 to the reference length (l) 110 is expressed as a percentage. Load length ratio.

  Generally, it is widely used for evaluation of wear resistance and slidability.

  FIG. 5B illustrates the definition of the load curve BAC. The load curve BAC is plotted with the value of the load length ratio tp on the horizontal axis 118 and the direction of the height (cutting height) of the measurement curve on the vertical axis (FIG. 5 (b1)). FIGS. 5 (c) to (f) illustrate load curves BAC 121, 123, 125, 127 obtained from the respective roughness curves 120, 122, 124, 126. In the case of the roughness curve 122 in which peaks and valleys are evenly projected from the average line, a graph with a downward slope is likely to be obtained (123), and in the case of the roughness curve 120 in which a protrusion protrudes from the plane, it is on the right shoulder. After suddenly falling, it changes gradually (121). Further, in the case of the roughness curve 126 in which a flaw is introduced from a flat surface, it gradually falls to the right after transitioning smoothly (127). From this, it is considered that the roughness as shown in (f) is preferable in order to effectively prevent the generation of particles.

  FIG. 6 illustrates the definition of the amplitude distribution curve ADC. The highest peak and the deepest valley bottom of the roughness curve 130 are divided at equal intervals, and the ratio of the number n of data existing in the region within two parallel lines to the number N of all data is plotted on the horizontal axis. The amplitude distribution curve ADC 132 plotted with the height direction of the roughness curve taken along the vertical axis is the amplitude distribution curve ADC (FIG. 6A). FIGS. 6B to 6D show respective amplitude distribution curves ADC for various roughness curves 130a, 130b, and 130c. The peak positions 134, 136, 138 of each amplitude distribution curve ADC are at approximately the same, higher, and lower positions as the average line. From this figure, it is considered that the roughness as shown in (c) is preferable in order to effectively prevent the generation of particles. Note that the horizontal axis (ratio of n and N) of the amplitude distribution curve ADC accumulated from above corresponds to the load curve BAC.

  As described above, even if it is rough, there are various regulations, and each represents a characteristic.

  As described above, according to the present invention, in the production of an epitaxial wafer, autodoping can be effectively prevented, the generation of particles can be sufficiently reduced, and sufficient strength of the silicon single crystal substrate can be ensured. .

  Embodiments of the present invention will be described below in more detail with reference to the drawings. In addition, the same code | symbol is used for the same element and the overlapping description is abbreviate | omitted.

A method for producing a silicon single crystal substrate for vapor phase growth will be described mainly with reference to FIG. First, an n-type silicon single crystal substrate 10 having about 3 × 10 ¹⁹ atoms / cm ³ of arsenic added as a dopant and having a diameter of 125 mm and a main surface plane orientation of (100) is prepared in a lapped state. . The dopant concentration added to the substrate for manufacturing a silicon wafer used for the power MOSFET for switching power supply is preferably in the range of 1 × 10 ^{19 to} 1.9 × 10 ²¹ atoms / cm ³ . A dopant concentration of 1 × 10 ¹⁹ atoms / cm ³ or more is necessary to sufficiently reduce the on-resistance, but adding arsenic to 1.9 × 10 ²¹ atoms / cm ³ or more in a silicon single crystal is not possible. It is not possible.

  Next, the side surface of the prepared lapping-treated silicon single crystal substrate 10 is chamfered to form a main surface chamfered portion 10a, an outer peripheral portion 10c, and a back surface chamfered portion 10b (FIGS. 1 and 7). The shape of the chamfered portion may be formed in an arc shape as shown in FIG. 2 as necessary. Further, the chamfering process may be performed before the lapping process.

  Further, after the chamfered substrate 10 is subjected to a chemical etching process for removing processing strain, the substrate 10 is processed by a CVD apparatus to prevent autodoping on the back surface and the side surface of the substrate 10. An oxide film CVD film 11 is formed. The CVD apparatus used in this example is a continuous processing type, and as the loaded substrate 10 moves, it is heated to 300 to 500 ° C. and sprayed with a raw material gas to have a thickness of 300 to 12000 nm on the substrate 10. A CVD film 11 is formed.

When monosilane (SiH ₄ ) is used as a source gas and reacted with oxygen, silicon dioxide (SiO ₂ ) grows as the CVD film 11. As a type other than the CVD apparatus used in this example, there are a horizontal type, a vertical type, a diffusion furnace type, etc. As the CVD film 11 while heating at a temperature of 700 to 900 ° C. under a reduced pressure of 0.1 to 10 Torr. Silicon dioxide (SiO ₂ ) grows.

  When the CVD film 11 is grown on the chamfered substrate 10, the source gas wraps around not only on the back surface of the substrate 10 but also reaches the main surface side of the chamfered portion, so that the CVD film 11 has a main surface side 10a of the chamfered portion. It grows around. This state is shown in FIG.

  Next, the silicon single crystal substrate 10 on which the CVD film 11 is grown is taken out of the CVD apparatus, and the portion of the CVD film 11 that has grown around the main surface side 10a of the chamfered portion is removed using a polishing machine. This state is shown in FIG. Polishing can be performed using a polishing machine 50 as shown in FIG. For example, a polishing drum 52 carrying free abrasive grains made of silicon oxide having a particle diameter of 10 to 60 μm can be used. The substrate 10 is chucked by the lower chuck 54 and pressed against the polishing drum 52 in the drum cover 56 for polishing. At this time, a polishing liquid containing an appropriate abrasive is supplied as a slurry 58. While the substrate 10 fixed by the lower chuck 54 is rotated at 500 to 900 rpm, the CVD film 11 is pressed against the portion of the polishing surface that has grown around the main surface 10a on the polishing drum.

  At this time, if the diameter of the fixed abrasive is larger than 9 μm, it is preferable to remove the strain by polishing with an alkaline aqueous solution such as KOH after polishing. On the other hand, if the diameter of the fixed abrasive is smaller than 3 μm, it takes a long time for polishing, which is not practical. Moreover, if the rotation speed of the board | substrate 10 is 500-900 rpm, it can grind | polish in 30-300 second per wafer.

  Finally, with respect to the silicon single crystal substrate 10 from which the portion of the CVD film 11 which has grown around the main surface side 10a of the chamfered portion is removed, the main surface is mirror-polished by a mechanochemical method to obtain a silicon single layer for vapor phase growth. A crystal substrate is used.

When the epitaxial layer 12 to which phosphorus (P) is added as a dopant at a concentration of 1 × 10 ¹⁶ atoms / cm ³ is vapor-grown to a thickness of 6 μm on the silicon single crystal substrate for vapor phase growth thus obtained. The epitaxial layer 12 is formed on the main surface of the silicon single crystal substrate 10 and on the main surface side 10a of the chamfered portion. This state is shown in FIG. In this silicon single crystal substrate for vapor phase growth, the CVD film which has grown around the main surface side 10a of the chamfered portion is surely removed by polishing, so that no nodule which causes a problem does not occur. Further, defects caused by processing defects such as stacking faults and slips do not occur. Furthermore, since the CVD film is reliably left on the other chamfered portions 10b and 10c and the back surface, the occurrence of auto-doping can be substantially prevented. On the other hand, when vapor phase growth is performed without removing the CVD film that has grown around the main surface side 10a of the chamfered portion, nodules are generated on the main surface side 10a.

  As another example, for a silicon single crystal substrate 10 having a side surface formed in an arc shape, a CVD film that has grown around the side surface of the main surface, that is, the side surface visible from the main surface side, is removed by tape polishing. Is shown in FIG. Also in this case, the CVD film 11 (FIG. 2A) grown around the main surface 10d on the side surface is reliably removed by polishing (FIG. 2B). Nodules are not generated even when the phase is grown, and autodoping can be substantially prevented (FIG. 2 (c)).

  With reference to FIG. 7, the mirror finishing of the chamfered portion and the like will be further described. FIG. 7A shows a state before mirror finishing. FIG. 7B shows a state where only the chamfered portion 10a is mirror-finished by removing the CVD film 11 by polishing. FIG. 7C shows a state in which the chamfered portion 10a and the outer peripheral side surface 10c are mirror-finished by removing the CVD film 11 by polishing. FIG. 7D shows a state in which the chamfered portion 10a, the outer peripheral side surface 10c, and the chamfered portion 10b on the rear surface side are mirror-finished by removing the CVD film 11 by polishing.

  The CVD film 11 is preferably maintained because it can effectively prevent autodoping. However, in order to prevent crowning and the like at the peripheral edge of the epitaxial layer, at least the mirror-side chamfered portion 10a is removed. Furthermore, it is more preferable that the CVD film 11 on the outer peripheral side surface 10c is also removed and the outer peripheral side surface 10c is formed as a mirror surface depending on the epitaxial growth conditions. This is because the removal of the CVD film 11 acts negatively for autodoping, but the adverse effect of particle generation may be greater than that of autodoping. Further, it is not preferable to remove the CVD film 11 from the chamfered portion 10b on the back side. This is because the adverse effect of autodoping increases.

  9 to 15 show the silicon single crystal substrate 10 in which the mirror-side chamfered portion 10a and the outer peripheral side surface 10c are actually formed on the mirror surface, and the evaluation results thereof. FIG. 9 shows a cross section of the silicon single crystal substrate 10. The thickness of the silicon substrate was about 520 μm, and the chamfering on the mirror surface side was performed at an angle of about 10 to 30 degrees about 100 to 500 μm from the peripheral edge. The chamfering on the back side was performed at an angle of about 10 to 30 degrees about 100 to 500 μm from the peripheral edge. The surfaces of the chamfered portions 10a and 10b were rounded with a radius of about 100 to 500 μm.

  As a comparative example, FIG. 10 shows a measured roughness curve of a conventional smooth surface. 10A and 10B show the roughness curves of the surfaces of the chamfered portions 10a and 10c, respectively. The maximum height Rmax (corresponding to Rz) at this time was 0.621 μm and 0.466 μm. The arithmetic average roughness Ra was 0.077 μm and 0.058 μm.

  FIG. 11 shows, as an example, a measured roughness curve of a mirror finished according to the present invention. FIGS. 11A and 11B show roughness curves of the surfaces of the chamfered portions 10a and 10c, respectively. The maximum height Rmax (corresponding to Rz) at this time was 0.243 μm and 0.239 μm. Moreover, arithmetic mean roughness Ra was 0.0069 micrometer and 0.0068 micrometer. Further, the amplitude distribution curve ADC at this time is shown in FIGS. The peak position of each amplitude distribution curve ADC was higher than the average line.

  Next, the results of examining the distribution and amount of particles generated from the silicon single crystal substrates of the above examples and comparative examples are shown in FIGS. From the silicon single crystal substrate according to the example, almost no particles having a particle diameter of 0.1 μm or more were generated. On the other hand, a considerable amount of particles (particle size of 0.1 μm or more) were generated from the silicon single crystal substrate of the comparative example, and the relative ratio thereof was about 1: 5. As can be seen from this figure, it is apparent that the amount of particles that can be counted is smaller in this embodiment.

  When compared with a predetermined strength index, the silicon single crystal substrate of the example was 1.3 times stronger than the comparative example.

  As mentioned above, although the embodiment of the invention made by the present inventor has been described, the present invention is not limited to such an embodiment, and it goes without saying that various modifications are possible without departing from the scope of the present invention. Nor.

It is a figure which shows the cross section of the silicon single crystal substrate for vapor phase growth concerning embodiment by this invention. It is a figure which shows the cross section of the silicon single crystal substrate for vapor phase growth concerning another embodiment by this invention. This illustrates the definition of the maximum surface roughness or the maximum height roughness Rz (JIS B O601-2001). It illustrates the definition of arithmetic average roughness Ra (JIS B O601-2001). (A) illustrates the definition of the load length rate tp. (B) illustrates the definition of the load curve BAC. 2 illustrates the definition of an amplitude distribution curve ADC. It is a figure which shows the cross section of the silicon single crystal substrate for vapor phase growth. It is the schematic which shows the polisher which can be used by this invention. 2 is a partial cross section of a silicon single crystal substrate 10. It is a figure which shows the roughness curve of the surface of the chamfering parts 10a and 10c of a comparative example. It is a figure which shows the roughness curve of the surface of the chamfering parts 10a and 10c of an Example. It is a figure which shows the particle generation condition of an Example. It is a figure which shows the particle generation condition of an Example. It is a figure which shows the particle generation condition of a comparative example. It is a figure which shows the particle generation condition of a comparative example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Silicon single crystal substrate 10a Main surface chamfer 10b Back surface chamfer 10c Outer peripheral side 11 CVD film 12 Epitaxial layer 50 Polishing apparatus

Claims (8)

In a semiconductor wafer for epitaxial growth having a main mirror surface and a back surface,
The wafer consists of a silicon single crystal substrate,
A chamfered portion is provided between the outer peripheral side surface of the silicon single crystal substrate and the main mirror surface and the back surface, respectively.
After performing a step of growing a CVD film on at least the back surface and the chamfered portion on the back surface side,
A semiconductor wafer for epitaxial growth, characterized in that a CVD film that wraps around a chamfered portion on the main mirror surface side is mechanically removed and finished to a mirror surface having a maximum height roughness (Rz) of 0.3 μm or less.   2. The semiconductor wafer for epitaxial growth according to claim 1, wherein the CVD film that has wrapped around the outer peripheral side surface is mechanically removed and finished to a mirror surface having a maximum height roughness (Rz) of 0.3 [mu] m or less. The mirror finish of the chamfered portion on the main mirror surface side is a maximum height roughness (Rz) of 0.3 μm or less,
Arithmetic mean roughness (Ra) is 0.01 μm or less,
3. The semiconductor wafer for epitaxial growth according to claim 1, wherein the peak of the roughness amplitude distribution curve is above the average line. The mirror finish of the outer peripheral side surface is a maximum height roughness (Rz) of 0.3 μm or less,
Arithmetic mean roughness (Ra) is 0.01 μm or less,
3. The semiconductor wafer for epitaxial growth according to claim 2, wherein the peak of the amplitude distribution curve of the roughness is above the average line. A method of manufacturing a semiconductor wafer for epitaxial growth having a main mirror surface and a back surface,
The wafer consists of a silicon single crystal substrate,
Forming a chamfer between the outer peripheral side surface of the silicon single crystal substrate and the main mirror surface and the back surface;
Growing a CVD film on at least the back surface and the chamfered portion on the back surface side; and
A step of mechanically removing the CVD film that has wrapped around the chamfered portion on the primary mirror side;
And a step of finishing the chamfered portion to a mirror surface having a maximum height roughness (Rz) of 0.3 μm or less. Furthermore, the step of mechanically removing the CVD film that wraps around the outer peripheral side surface;
6. The method for producing a semiconductor wafer for epitaxial growth according to claim 5, further comprising a step of finishing the CVD film removal surface on the outer peripheral side surface into a mirror surface having a maximum height roughness (Rz) of 0.3 [mu] m or less. The mirror finish of the chamfered portion on the main mirror surface side is a maximum height roughness (Rz) of 0.3 μm or less,
Arithmetic mean roughness (Ra) is 0.01 μm or less,
7. The method for producing a semiconductor wafer for epitaxial growth according to claim 5, wherein the peak of the roughness amplitude distribution curve is above the average line. The mirror finish of the outer peripheral side surface is a maximum height roughness (Rz) of 0.3 μm or less,
Arithmetic mean roughness (Ra) is 0.01 μm or less,
7. The method for producing a semiconductor wafer for epitaxial growth according to claim 6, wherein the peak of the amplitude distribution curve of the roughness is above the average line.

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