JP2008108825A - Semiconductor device - Google Patents

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JP2008108825A
JP2008108825A JP2006288715A JP2006288715A JP2008108825A JP 2008108825 A JP2008108825 A JP 2008108825A JP 2006288715 A JP2006288715 A JP 2006288715A JP 2006288715 A JP2006288715 A JP 2006288715A JP 2008108825 A JP2008108825 A JP 2008108825A
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electrode layer
layer
film
modulus
young
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Atsushi Komura
篤 小邑
Takayoshi Naruse
孝好 成瀬
Mitsutaka Katada
満孝 堅田
Takeshi Kuzuhara
葛原　　剛
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Denso Corp
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Denso Corp
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Priority to JP2006288715A priority Critical patent/JP2008108825A/en
Priority to US11/976,308 priority patent/US7642653B2/en
Priority to DE102007050610A priority patent/DE102007050610A1/en
Publication of JP2008108825A publication Critical patent/JP2008108825A/en
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  • Engineering & Computer Science (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device of such a structure as cracking can be prevented at the pad portion and the underlying interconnection, and destruction of a semiconductor element can be prevented. <P>SOLUTION: An electrode layer 58 is covered with a third insulating film 60 such that the electrode layer 58 is fixed by the third insulating film 60. Consequently, deformation of the electrode layer 58 by impact at the time of bonding can be suppressed more than before. In particular, a material having Young's modulus of 1×10<SP>4</SP>kg/mm<SP>2</SP>or above is employed in the electrode layer 58, and the film thickness of the electrode layer 58 is set at 0.3 μm or above, preferably at 1 μm or above. A material having Young's modulus of 8.0×10<SP>3</SP>kg/mm<SP>2</SP>or above is employed in the pad portion 62, and the film thickness of the pad portion 62 is set at 0.5 μm or above, preferably at 1 μm or above. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、半導体素子が形成されたセル部の上部においてワイヤボンディングを行うようにした半導体装置に関するものである。   The present invention relates to a semiconductor device in which wire bonding is performed on an upper portion of a cell portion in which a semiconductor element is formed.

従来、半導体素子が形成されたセル部の上部においてワイヤボンディングが行えるようにする技術として、例えば、特許文献１や特許文献２に示されるものがある。特許文献１では、ワイヤボンディングを行うパッド部分において絶縁膜や金属膜の膜厚を１〜２μｍにすること、特許文献２では、ワイヤボンディングを行うパッド部分において配線を多層化することにより、共に、クラックの発生や半導体素子の破壊を抑制することでワイヤボンディングが行えるようにしている。   Conventionally, as a technique for enabling wire bonding at an upper portion of a cell portion in which a semiconductor element is formed, for example, there are those shown in Patent Document 1 and Patent Document 2. In Patent Document 1, the film thickness of the insulating film or the metal film is set to 1 to 2 μm in the pad portion where wire bonding is performed, and in Patent Document 2, the wiring is multilayered in the pad portion where wire bonding is performed. Wire bonding can be performed by suppressing the occurrence of cracks and the destruction of semiconductor elements.

また、特許文献３では、ワイヤボンディングを行う部分の周辺にビアホールを形成し、ワイヤボンディングを行う部分の直下にはビアホールを形成しないようにする技術も提案されている。
特表２００３−５１８７３９号公報 特開平８−２３６７０６号公報 特許第３４３２２８４号公報 Patent Document 3 also proposes a technique in which a via hole is formed around a portion where wire bonding is performed, and a via hole is not formed immediately below the portion where wire bonding is performed.
Special table 2003-518739 gazette JP-A-8-236706 Japanese Patent No. 3432284

しかしながら、上記特許文献１や特許文献２に示される構造の場合、下地となるパターンに左右されやすく、必ずしもクラックの発生や半導体素子の破壊が防止できるという訳ではないことが確認された。   However, in the case of the structures shown in Patent Document 1 and Patent Document 2, it has been confirmed that the structure is easily influenced by the underlying pattern, and it is not always possible to prevent the occurrence of cracks and the destruction of the semiconductor element.

また、特許文献３の構造の場合、ワイヤボンディングを行う部分の周囲にのみビアホールを形成しているため、パワー素子のドレイン配線やソース配線をそこまで引き回さねばならない等、パターンの制約が大きく、設計の自由度が低くなり、チップサイズの縮小を図ることができない。   In the case of the structure of Patent Document 3, since the via hole is formed only around the portion where wire bonding is performed, there is a great restriction on the pattern, for example, the drain wiring and source wiring of the power element have to be routed there. Therefore, the degree of freedom in design is reduced, and the chip size cannot be reduced.

なお、これらの問題を解決するには、パッド部の下層に電極となる厚いＣｕ層を形成した後、上層にＡｌを配置することでＣｕ層を被覆するという構造が考えられる。しかしながら、このような構造の場合、下層のＣｕ層が上側に突出する凸形状（ＣＳＰ構造）となることから、厚くされたＣｕ層の周囲（両端）を固定することができない。このため、ボンディング時に、厚いＣｕ層が振動して衝撃を与えてしまい、下地にビアホールが形成されることを避けなければならなかったり、衝撃吸収梁を形成する必要が出るなど、パターンの制約ができ、上記問題を好適に解消することができなかった。   In order to solve these problems, a structure may be considered in which a thick Cu layer serving as an electrode is formed in the lower layer of the pad portion, and then the Cu layer is covered by disposing Al in the upper layer. However, in the case of such a structure, since the lower Cu layer has a convex shape (CSP structure) protruding upward, the periphery (both ends) of the thickened Cu layer cannot be fixed. For this reason, during bonding, the thick Cu layer vibrates and gives an impact, and it is necessary to avoid the formation of a via hole in the base, and there is a need to form a shock absorbing beam. The above problem could not be solved suitably.

本発明は上記点に鑑みて、パッド部や下層配線等のクラック、半導体素子の破壊を防止できる構造の半導体装置を提供することを第１の目的とする。さらに、パターンの制約が少なく、設計自由度を高くでき構造の半導体装置を提供することを第２の目的とする。   In view of the above points, the present invention has as its first object to provide a semiconductor device having a structure capable of preventing cracks in a pad portion and lower layer wiring, and destruction of a semiconductor element. It is a second object of the present invention to provide a semiconductor device having a structure in which there are few pattern restrictions and design freedom can be increased.

上記目的を達成するため、本発明では、配線層の上において、該配線層と電気的に接続されるように構成され、パッド部よりもヤング率が大きな材料で構成された電極層（５８）と、電極層を囲み、該電極層の側壁面を覆うように構成された絶縁膜（６０）と、を有し、電極層と、該電極層よりもヤング率が小さな材料となるパッド部との２層を含む多層構造により、パッド構造が構成されていることを特徴としている。   In order to achieve the above object, in the present invention, an electrode layer (58) configured to be electrically connected to the wiring layer on the wiring layer and made of a material having a Young's modulus larger than that of the pad portion. And an insulating film (60) configured to surround the electrode layer and cover the side wall surface of the electrode layer, the electrode layer, and a pad portion made of a material having a Young's modulus smaller than that of the electrode layer; A pad structure is formed by a multilayer structure including the two layers.

このように、電極層を絶縁膜にて覆うようにすることで、絶縁膜にて電極層が固定されるようにできる。このため、ボンディング時の衝撃により電極層が変形してしまうことを従来以上に抑制することが可能となる。したがって、パッド部や下層配線等のクラック、半導体素子の破壊を防止できる構造の半導体装置とすることができる。   Thus, by covering the electrode layer with the insulating film, the electrode layer can be fixed by the insulating film. For this reason, it becomes possible to suppress that an electrode layer deform | transforms by the impact at the time of bonding more than before. Therefore, it is possible to provide a semiconductor device having a structure capable of preventing cracks in the pad portion and lower layer wiring, and destruction of the semiconductor element.

具体的には、パッド部をボンディングにより塑性変形する材料にて構成すると好ましい。例えば、パッド部をヤング率が８．０×１０3ｋｇ／ｍｍ2以下の材料で構成すれば、ボンディングにより塑性変形するようにできる。この場合、パッド部を０．５μｍ以上、好ましくは１μｍ以上の膜厚で構成すれば、塑性変形によるボンディング時の衝撃吸収効果を得ることができる。 Specifically, the pad portion is preferably made of a material that is plastically deformed by bonding. For example, if the pad portion is made of a material having a Young's modulus of 8.0 × 10 3 kg / mm 2 or less, it can be plastically deformed by bonding. In this case, if the pad portion is formed with a film thickness of 0.5 μm or more, preferably 1 μm or more, an impact absorbing effect during bonding by plastic deformation can be obtained.

また、電極層をボンディングにより塑性変形しない材料にて構成すると好ましい。例えば、電極層をヤング率が１×１０4ｋｇ／ｍｍ2以上の材料で構成すれば、ボンディングにより塑性変形しないようにできる。この場合、電極層を０．３μｍ以上、好ましくは１μｍ以上の膜厚で構成すれば、電極層によるボンディング時の変形防止効果を十分に得ることができ、下地となる層間絶縁膜や素子などのクラック発生を防止することが可能となる。 Further, it is preferable that the electrode layer is made of a material that is not plastically deformed by bonding. For example, if the electrode layer is made of a material having a Young's modulus of 1 × 10 4 kg / mm 2 or more, it can be prevented from plastic deformation by bonding. In this case, if the electrode layer is formed with a film thickness of 0.3 μm or more, preferably 1 μm or more, a sufficient deformation preventing effect at the time of bonding by the electrode layer can be obtained, and an underlying interlayer insulating film, element, etc. It is possible to prevent the occurrence of cracks.

以上のような構造は、特に、パッド構造が半導体素子が形成されたセル部の直上に形成される場合に有効である。   The above structure is particularly effective when the pad structure is formed immediately above the cell portion where the semiconductor element is formed.

なお、上記各手段の括弧内の符号は、後述する実施形態に記載の具体的手段との対応関係を示すものである。   In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

以下、本発明の実施形態について図に基づいて説明する。なお、以下の各実施形態相互において、互いに同一もしくは均等である部分には、図中、同一符号を付してある。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

（第１実施形態）
図１は、本発明の第１実施形態が適用された半導体装置１の断面構造を示したものである。この半導体装置１は、ＬＤＭＯＳ１０、ＣＭＯＳ２０、バイポーラトランジスタ（以下、Ｂｉｐという）３０がセル部に一体的に形成された集積回路を備えたものである。この半導体装置１は、ＳＯＩ基板２を用いて形成されている。 (First embodiment)
FIG. 1 shows a cross-sectional structure of a semiconductor device 1 to which the first embodiment of the present invention is applied. The semiconductor device 1 includes an integrated circuit in which an LDMOS 10, a CMOS 20, and a bipolar transistor (hereinafter referred to as a Bip) 30 are integrally formed in a cell portion. The semiconductor device 1 is formed using an SOI substrate 2.

ＳＯＩ基板２は、支持基板となるシリコン基板３の表面にシリコン酸化膜などの絶縁膜４を介して活性層となるシリコン層５を配置したものである。このシリコン層５は、Ｎ+型層６およびこのＮ+型層６の表層部に形成されたＮ-型層７を有した構成とされ、ＬＤＭＯＳ１０、ＣＭＯＳ２０、Ｂｉｐ３０が配置される各領域ごとにトレンチ８およびトレンチ８内に配置された絶縁層９にて素子分離されている。このため、ＬＤＭＯＳ１０、ＣＭＯＳ２０、Ｂｉｐ３０が互いに電気的に分離されている。 The SOI substrate 2 has a silicon layer 5 as an active layer disposed on the surface of a silicon substrate 3 as a support substrate via an insulating film 4 such as a silicon oxide film. The silicon layer 5 has an N + type layer 6 and an N − type layer 7 formed on the surface layer portion of the N + type layer 6, and is provided for each region where the LDMOS 10, the CMOS 20, and the Bip 30 are arranged. The elements are isolated by the trench 8 and the insulating layer 9 disposed in the trench 8. For this reason, the LDMOS 10, the CMOS 20, and the Bip 30 are electrically isolated from each other.

ＬＤＭＯＳ１０は、シリコン層５におけるＮ-型層７の表層にそれぞれ位置するＮ型ドレイン領域１１、Ｐ型チャネル領域１２、Ｎ+型ソース領域１３とから構成されている。Ｎ型ドレイン領域１１の表層にはＮ+型コンタクト層１４が形成されており、Ｐ型チャネル領域１２の表層にはＰ型コンタクト層１５が形成されている。また、Ｎ型ドレイン領域１１とＰ型チャネル領域１２は、いわゆるＬＯＣＯＳ酸化膜１６により、絶縁分離されている。また、Ｐ型チャネル領域１２上には、ゲート絶縁膜１７を介して、ゲート電極１８が配置されている。 The LDMOS 10 is composed of an N-type drain region 11, a P-type channel region 12, and an N + -type source region 13 that are located on the surface layer of the N − -type layer 7 in the silicon layer 5. An N + -type contact layer 14 is formed on the surface layer of the N-type drain region 11, and a P-type contact layer 15 is formed on the surface layer of the P-type channel region 12. The N-type drain region 11 and the P-type channel region 12 are insulated and separated by a so-called LOCOS oxide film 16. A gate electrode 18 is disposed on the P-type channel region 12 via a gate insulating film 17.

ＣＭＯＳ２０は、シリコン層５におけるＮ-型層７中のＮ型ウェル層２１と、Ｎ型ウェル層２１の表層のＰ型層２２と、Ｐ型層２２の表層のＮ+型ソース領域２３およびＮ+型ドレイン領域２４とを有して構成されている。また、Ｐ型層２２のうち、Ｎ+型ソース領域２３とＮ+型ドレイン領域２４の間の領域上には、ゲート絶縁膜２５を介して、ゲート電極２６が配置されている。ここではＮチャネルＭＯＳＦＥＴのみ図示するが、ＰチャネルＭＯＳＦＥＴも配置されている。 The CMOS 20 includes an N-type well layer 21 in the N − -type layer 7 in the silicon layer 5, a P-type layer 22 on the surface of the N-type well layer 21, an N + -type source region 23 and an N-type source region 23 on the surface of the P-type layer 22. And a + -type drain region 24. In addition, a gate electrode 26 is disposed on the region of the P-type layer 22 between the N + -type source region 23 and the N + -type drain region 24 via a gate insulating film 25. Although only an N-channel MOSFET is shown here, a P-channel MOSFET is also arranged.

Ｂｉｐ３０は、シリコン層５に形成され、Ｎ-型層７を上下に貫通してＮ+型層６と接続されているＮ+型コレクタ領域３１と、シリコン層５におけるＮ-型層７の表層のＰ型ベース領域３２と、Ｐ型ベース領域３２の表層のＮ+型エミッタ層３３およびＰ+型コンタクト層３４とから構成されている。 Bip30 is formed in the silicon layer 5, N - and N + -type collector region 31 through the type layer 7 in the vertical and is connected to the N + -type layer 6, N in the silicon layer 5 - the surface of the mold layer 7 P-type base region 32, and N + -type emitter layer 33 and P + -type contact layer 34 on the surface layer of P-type base region 32.

そして、このように構成された各素子が形成されたＳＯＩ基板２の表面に、配線構造部５０が構成されている。   And the wiring structure part 50 is comprised on the surface of the SOI substrate 2 in which each element comprised in this way was formed.

配線構造部５０は、シリコン層５上にそれぞれ順に形成されているＢＰＳＧ膜５１と、１ｓｔ配線層５２と、ＢＰＳＧ膜５１のコンタクトホール内に埋設された第１コンタクト部５３と、第１絶縁膜５４と、２ｎｄ配線層５５と、第１絶縁膜５４のビアホールに埋設された第２コンタクト部５６と、第２絶縁膜５７と、電極層５８と、第２絶縁膜５７のビアホールに埋設された第３コンタクト部５９と、第３絶縁膜６０と、パッシベーション膜としてのＰ−ＳｉＮ膜６１と、Ｐ−ＳｉＮ膜６１に形成された開口部を通じて各電極層５８と電気的に接続されたパッド部６２を有している。   The wiring structure portion 50 includes a BPSG film 51 formed in order on the silicon layer 5, a first wiring layer 52, a first contact portion 53 embedded in a contact hole of the BPSG film 51, and a first insulating film 54, the 2nd wiring layer 55, the second contact portion 56 buried in the via hole of the first insulating film 54, the second insulating film 57, the electrode layer 58, and the via hole of the second insulating film 57. Third contact part 59, third insulating film 60, P-SiN film 61 as a passivation film, and pad part electrically connected to each electrode layer 58 through an opening formed in P-SiN film 61 62.

１ｓｔ配線層５２、２ｎｄ配線層５５は、ＬＤＭＯＳ１０、ＣＭＯＳ２０、Ｂｉｐ３０等の素子用の電源線やグラウンド線あるいは素子を電気的に接続する配線であり、本発明の配線層に該当する。   The 1st wiring layer 52 and the 2nd wiring layer 55 are wirings for electrically connecting power supply lines, ground lines, or elements for elements such as the LDMOS 10, CMOS 20, Bip 30, and the like, and correspond to the wiring layers of the present invention.

第１コンタクト部５３は、Ｔｉ／ＴｉＮもしくはＴａ／ＴａＮの積層膜からなるバリアメタル５３ａと、バリアメタル５３ａ上に配置されたＷプラグ５３ｂにて構成されている。この第１コンタクト部５３は、ＢＰＳＧ膜５１に形成されたコンタクトホールを通じてＬＤＭＯＳ１０、ＣＭＯＳ２０、Ｂｉｐ３０の各部と電気的に接続されている。   The first contact portion 53 includes a barrier metal 53a made of a laminated film of Ti / TiN or Ta / TaN, and a W plug 53b disposed on the barrier metal 53a. The first contact part 53 is electrically connected to each part of the LDMOS 10, the CMOS 20, and the Bip 30 through contact holes formed in the BPSG film 51.

１ｓｔ配線層５２および２ｎｄ配線層５５は、共に、Ｔｉ／ＴｉＮもしくはＴａ／ＴａＮの積層膜からなるバリアメタル５２ａ、５５ａと、バリアメタル５２ａ、５５ａ上に配置されたＣｕ層５２ｂ、５５ｂにて構成されている。１ｓｔ配線層５２は、第１絶縁膜５４における第１ＴＥＯＳ膜５４ａに形成された配線パターン用の溝内に埋め込まれている。そして、この１ｓｔ配線層５２上を全面覆うように、第１絶縁膜５４におけるシリコン窒化膜５４ｂおよび第２ＴＥＯＳ膜５４ｃが成膜されている。これらシリコン窒化膜５４ｂおよび第２ＴＥＯＳ膜５４ｃの所望位置に開口部が形成されており、各開口部を通じて第２コンタクト部５６が１ｓｔ配線層５２の所望位置と電気的に接続されている。   Both the 1st wiring layer 52 and the 2nd wiring layer 55 are constituted by barrier metals 52a and 55a made of a laminated film of Ti / TiN or Ta / TaN, and Cu layers 52b and 55b arranged on the barrier metals 52a and 55a. Has been. The first wiring layer 52 is embedded in a wiring pattern groove formed in the first TEOS film 54 a in the first insulating film 54. A silicon nitride film 54b and a second TEOS film 54c in the first insulating film 54 are formed so as to cover the entire surface of the first wiring layer 52. Openings are formed at desired positions of the silicon nitride film 54b and the second TEOS film 54c, and the second contact portion 56 is electrically connected to the desired position of the first wiring layer 52 through the openings.

第２コンタクト部５６は、Ｔｉ／ＴｉＮもしくはＴａ／ＴａＮの積層膜からなるバリアメタル５６ａと、バリアメタル５６ａ上に配置されたＣｕ層５６ｂにて構成されている。   The second contact portion 56 is configured by a barrier metal 56a made of a laminated film of Ti / TiN or Ta / TaN, and a Cu layer 56b disposed on the barrier metal 56a.

２ｎｄ配線層５５は、第２絶縁膜５７における第１ＴＥＯＳ膜５７ａに形成された配線パターン用の溝内に埋め込まれている。そして、この２ｎｄ配線層５５上を全面覆うように、第２絶縁膜５７におけるシリコン窒化膜５７ｂおよび第２ＴＥＯＳ膜５７ｃが成膜されている。これらシリコン窒化膜５７ｂおよび第２ＴＥＯＳ膜５７ｃの所望位置に開口部が形成されており、各開口部を通じて第３コンタクト部５９が２ｎｄ配線層５５の所望位置と電気的に接続されている。   The 2nd wiring layer 55 is embedded in a wiring pattern groove formed in the first TEOS film 57 a in the second insulating film 57. A silicon nitride film 57b and a second TEOS film 57c in the second insulating film 57 are formed so as to cover the entire surface of the 2nd wiring layer 55. Openings are formed at desired positions of the silicon nitride film 57b and the second TEOS film 57c, and the third contact portion 59 is electrically connected to the desired position of the 2nd wiring layer 55 through the openings.

第３コンタクト部５９は、Ｔｉ／ＴｉＮもしくはＴａ／ＴａＮの積層膜からなるバリアメタル５９ａと、バリアメタル５９ａ上に配置されたＣｕ層５９ｂにて構成されている。   The third contact portion 59 includes a barrier metal 59a made of a laminated film of Ti / TiN or Ta / TaN, and a Cu layer 59b disposed on the barrier metal 59a.

電極層５８は、Ｔｉ／ＴｉＮもしくはＴａ／ＴａＮの積層膜からなるバリアメタル５８ａと、バリアメタル５８ａ上に配置されたＣｕ層５８ｂにて構成されている。この電極層５８は、第３絶縁膜６０によって埋め込まれた状態、つまり側壁すべてが第３絶縁膜６０によって囲まれてた構造とされ、１ｓｔ配線層５２や２ｎｄ配線層５５と比べて厚く構成されている。特に、電極層５８のうち、素子の大電流が流される部位と電気的に接続されるものに関しては、上面から見たときの面積（体積）が他の電極層５８と比べて大きくされている。ここでは、電極層５８のうち、ＬＤＭＯＳ１０におけるＮ型ドレイン領域１１やＮ+型ソース領域１３に電気的に接続される部分は、他の部分と比べて大きな面積とされている。 The electrode layer 58 includes a barrier metal 58a made of a laminated film of Ti / TiN or Ta / TaN, and a Cu layer 58b disposed on the barrier metal 58a. The electrode layer 58 is embedded in the third insulating film 60, that is, has a structure in which all side walls are surrounded by the third insulating film 60, and is thicker than the first wiring layer 52 and the second wiring layer 55. ing. In particular, regarding the electrode layer 58 that is electrically connected to a portion through which a large current of the element flows, the area (volume) when viewed from above is set larger than that of the other electrode layers 58. . Here, a portion of the electrode layer 58 that is electrically connected to the N-type drain region 11 and the N + -type source region 13 in the LDMOS 10 has a larger area than the other portions.

また、この電極層５８は、パッド部６２の下層に位置する下層電極層としての役割も果たすため、ヤング率の大きい材質で構成してあり、ここではＣｕ層５８ｂを基材として用いているが、ヤング率が１．０×１０4ｋｇ／ｍ2以上の材料であれば良く、例えば、Ｃｕ合金、Ｔｉ、Ｗ、Ｎｉ、Ｃｒ、Ｐｄ、Ｐｔ、Ｍｎ、Ｚｎ、ドープトＳｉ、ドープトＰｏｌｙ−Ｓｉなどを用いることができる。このようなヤング率の大きい材質のものを第３絶縁膜６０で埋め込んだのは、ボンディング時の衝撃を受けたときの変形防止のためである。すなわち、ボンディング時の衝撃は、縦方向の衝撃と横方向の衝撃があるため、硬い材質を埋め込み固定することで下地となる電極層５８の変形を効果的に抑制することが可能となる。そして、このように電極層５８によるボンディング時の変形防止効果が得られるように、電極層５８の膜厚を０．３μｍ以上としており、好ましくは１μｍ以上としている。 In addition, since this electrode layer 58 also serves as a lower electrode layer located below the pad portion 62, it is made of a material having a large Young's modulus. Here, the Cu layer 58b is used as a base material. Any material having a Young's modulus of 1.0 × 10 4 kg / m 2 or more may be used. For example, Cu alloy, Ti, W, Ni, Cr, Pd, Pt, Mn, Zn, doped Si, doped Poly-Si Etc. can be used. The reason why such a material having a high Young's modulus is embedded in the third insulating film 60 is to prevent deformation when subjected to an impact during bonding. That is, since the impact during bonding includes a longitudinal impact and a lateral impact, it is possible to effectively suppress deformation of the underlying electrode layer 58 by embedding and fixing a hard material. The film thickness of the electrode layer 58 is set to 0.3 μm or more, preferably 1 μm or more so that the effect of preventing deformation during bonding by the electrode layer 58 can be obtained.

第３絶縁膜６０は、ＴＥＯＳ膜で構成されており、第２絶縁膜５７および第３コンタクト部５９の上に配置されている。第３絶縁膜６０は、電極層５８と同じ膜厚で構成されており、この第３絶縁膜６０に形成された溝内に電極層５８が埋め込まれた構造とされている。   The third insulating film 60 is composed of a TEOS film, and is disposed on the second insulating film 57 and the third contact portion 59. The third insulating film 60 has the same thickness as the electrode layer 58, and has a structure in which the electrode layer 58 is embedded in a groove formed in the third insulating film 60.

Ｐ−ＳｉＮ膜６１は、第３絶縁膜６０および電極層５８を覆うように構成されたものであり、パッド部６２が配置される部位に開口部が形成された構造とされている。   The P-SiN film 61 is configured to cover the third insulating film 60 and the electrode layer 58, and has a structure in which an opening is formed at a portion where the pad portion 62 is disposed.

パッド部６２は、Ｐ−ＳｉＮ膜６１に形成された開口部を通じて、電極層５８と電気的に接続されるものである。このパッド部６２にボンディングが為されることで、半導体装置１内に形成されたＬＤＭＯＳ１０、ＣＭＯＳ２０、Ｂｉｐ３０等の素子の各部と外部との電気的接続が図れるようになっている。   The pad part 62 is electrically connected to the electrode layer 58 through an opening formed in the P-SiN film 61. By bonding to the pad portion 62, each portion of elements such as the LDMOS 10, the CMOS 20, and the Bip 30 formed in the semiconductor device 1 can be electrically connected to the outside.

パッド部６２は、ヤング率が小さく、ボンディング時の衝撃にて塑性変形する材料、つまり電極層５８と比べてヤング率が小さな材料で構成されている。ここでは、パッド部６２は、Ａｌにより構成しているが、ヤング率が８．０×１０3ｋｇ／ｍ2以下の材料であれば良く、例えば、Ａｕ、Ａｇ、Ｐｂ、Ｓｎなどを用いることができる。このようにパッド部６２を塑性変形させることで、ボンディング時の衝撃を吸収できるようにしている。そして、このようにパッド部６２によるボンディング時の衝撃吸収効果が得られるように、パッド部６２の膜厚を０．５μｍ以上としており、好ましくは１μｍ以上としている。 The pad portion 62 is made of a material having a small Young's modulus and plastically deforming by an impact during bonding, that is, a material having a Young's modulus smaller than that of the electrode layer 58. Here, the pad portion 62 is made of Al, but may be any material having a Young's modulus of 8.0 × 10 3 kg / m 2 or less. For example, Au, Ag, Pb, Sn or the like is used. Can do. In this way, the pad portion 62 is plastically deformed to absorb an impact during bonding. The film thickness of the pad portion 62 is set to 0.5 μm or more, preferably 1 μm or more so that an impact absorbing effect during bonding by the pad portion 62 can be obtained.

本実施形態では、電極層５８およびパッド部６２にてパッド構造を構成している。これら電極層５８やパッド部６２がヤング率の大きな材料のみからなるようにした場合、ボンディング時の衝撃がそのまま下地に伝達されるため、層間絶縁膜クラックや素子破壊が起こる。これは、層間絶縁膜や配線層を構成する材料による衝撃吸収効果がほとんどないために生じる。逆に、電極層５８やパッド部６２がヤング率の小さな材料のみからなるようにした場合、ボンディング時の衝撃によって電極の塑性変形と同時に下地も塑性変形してしまい、層間絶縁膜クラックや素子破壊が起こる。このため、上層となるパッド部６２をヤング率が小さな材料とし、下層となる電極層５８をヤング率の大きな材料としている。   In the present embodiment, the electrode layer 58 and the pad portion 62 constitute a pad structure. When the electrode layer 58 and the pad portion 62 are made of only a material having a large Young's modulus, an impact at the time of bonding is transmitted as it is to the base, so that an interlayer insulating film crack or element destruction occurs. This occurs because there is almost no shock absorption effect by the material constituting the interlayer insulating film or the wiring layer. On the contrary, when the electrode layer 58 and the pad portion 62 are made of only a material having a small Young's modulus, the base material is also plastically deformed simultaneously with the plastic deformation of the electrode due to the impact during bonding, resulting in an interlayer insulating film crack or device breakdown. Happens. Therefore, the upper pad portion 62 is made of a material having a small Young's modulus, and the lower electrode layer 58 is made of a material having a large Young's modulus.

また、電極層５８は、ＬＤＭＯＳ１０、ＣＭＯＳ２０、Ｂｉｐ３０等の素子が形成されたセル部の直上（セル部の上部）に形成され、セル部の外部に各コンタクト部５３、５６、５７や配線層５２、５５が引き回されることなく、各素子と電極層５８、引いてはパッド部６２が電気的に接続される構造とされている。   The electrode layer 58 is formed immediately above the cell portion where elements such as the LDMOS 10, CMOS 20, and Bip 30 are formed (upper portion of the cell portion), and the contact portions 53, 56, 57 and the wiring layer 52 are formed outside the cell portion. 55, without being routed, each element and the electrode layer 58, and thus the pad portion 62 are electrically connected.

以上説明したように、本実施形態では、第３絶縁膜６０に埋め込むように電極層５８を配置している。さらに、電極層５８をヤング率の大きな材料、パッド部６２をヤング率の小さな材料で構成し、かつ、電極層５８やパッド部６２の膜厚を上記した値となるようにしている。これらの理由について説明する。   As described above, in this embodiment, the electrode layer 58 is disposed so as to be embedded in the third insulating film 60. Further, the electrode layer 58 is made of a material having a high Young's modulus, the pad portion 62 is made of a material having a low Young's modulus, and the film thicknesses of the electrode layer 58 and the pad portion 62 are set to the above values. These reasons will be described.

まず、第３絶縁膜６０に電極層５８を埋め込むことにより、電極層５８の膜厚を大きなものにすることが可能になると共に、第３絶縁膜６０にて電極層５８を固定することが可能となる。このため、ボンディング時における電極層５８の変形をより抑制することが可能となる。   First, it is possible to increase the thickness of the electrode layer 58 by embedding the electrode layer 58 in the third insulating film 60 and to fix the electrode layer 58 with the third insulating film 60. It becomes. For this reason, it becomes possible to suppress the deformation | transformation of the electrode layer 58 at the time of bonding more.

また、電極層５８の膜厚を０．３μｍ以上とし、好ましくは１μｍ以上としている。これは、以下に示す実験結果に基づくものである。図２は、第３コンタクト部５９の膜厚を１μｍ、パッド部６２の膜厚を１μｍで固定しつつ、電極層５８および第３絶縁膜６０の膜厚を様々に変化させたときのクラック発生率を調べた結果を示したグラフである。この図に示されるように、電極層５８および第３絶縁膜６０が薄いと変形抑制効果が十分に得られないが、膜厚が厚くなるに連れてその効果が徐々に得られるようになり、０．３μｍになるとクラック発生率が５％以下になる程度まで効果が得られ、０．７μｍ以上、より確実には１μｍになるとクラック発生率が０％になるまで効果が得られることが確認された。このため、電極層５８および第３絶縁膜６０の膜厚を０．３μｍ以上、好ましくは１μｍ以上としている。   The film thickness of the electrode layer 58 is set to 0.3 μm or more, preferably 1 μm or more. This is based on the experimental results shown below. FIG. 2 shows the occurrence of cracks when the film thickness of the electrode layer 58 and the third insulating film 60 is changed variously while the film thickness of the third contact part 59 is fixed at 1 μm and the film thickness of the pad part 62 is fixed at 1 μm. It is the graph which showed the result of having investigated the rate. As shown in this figure, if the electrode layer 58 and the third insulating film 60 are thin, the effect of suppressing deformation cannot be sufficiently obtained, but the effect is gradually obtained as the film thickness increases. When 0.3 μm, the effect is obtained until the crack occurrence rate becomes 5% or less, and when 0.7 μm or more, more surely 1 μm, the effect is obtained until the crack occurrence rate becomes 0%. It was. For this reason, the film thickness of the electrode layer 58 and the 3rd insulating film 60 is 0.3 micrometer or more, Preferably it is 1 micrometer or more.

なお、この電極層５８の膜厚の上限に関しては、電極層５８の成膜時間などの要因から決まると考えられるが、上記効果が得られるという意味では特に限界はない。実験によれば、電極層５８が５μｍの膜厚までは問題ないことを確認している。   The upper limit of the film thickness of the electrode layer 58 is considered to be determined by factors such as the film formation time of the electrode layer 58, but there is no particular limit in the sense that the above effect can be obtained. According to experiments, it has been confirmed that there is no problem until the electrode layer 58 has a thickness of 5 μm.

また、パッド部６２の膜厚を０．５μｍ以上とし、好ましくは１μｍ以上としている。これは、以下に示す実験結果に基づくものである。図３は、電極層５８の膜厚を２μｍ、第３コンタクト部５９の膜厚を１μｍで固定しつつ、パッド部６２の膜厚を様々に変化させたときのクラック発生率を調べた結果を示したグラフである。この図に示されるように、パッド部６２が薄いと衝撃吸収効果が十分に得られないが、膜厚が厚くなるに連れてその効果が徐々に得られるようになり、０．５μｍになるとクラック発生率が５％以下になる程度まで効果が得られ、１μｍになるとクラック発生率が０％になるまで効果が得られることが確認された。このため、パッド部６２の膜厚を０．５μｍ以上、好ましくは１μｍ以上としている。   The film thickness of the pad portion 62 is 0.5 μm or more, preferably 1 μm or more. This is based on the experimental results shown below. FIG. 3 shows the result of examining the crack occurrence rate when the thickness of the pad portion 62 is changed variously while the thickness of the electrode layer 58 is fixed at 2 μm and the thickness of the third contact portion 59 is fixed at 1 μm. It is the shown graph. As shown in this figure, if the pad portion 62 is thin, the impact absorbing effect cannot be obtained sufficiently, but as the film thickness increases, the effect is gradually obtained. It was confirmed that the effect was obtained to the extent that the occurrence rate was 5% or less, and that the effect was obtained until the crack occurrence rate was 0% when it was 1 μm. For this reason, the film thickness of the pad part 62 is 0.5 μm or more, preferably 1 μm or more.

なお、このパッド部６２の膜厚の上限に関しては、パッド部６２の成膜時間やパッド部６２のパターニングが的確に行えるか否かなどの要因から決まると考えられるが、上記効果が得られるという意味では特に限界はない。実験によれば、パッド部６２が３μｍの膜厚までは問題ないことを確認している。   The upper limit of the film thickness of the pad part 62 is considered to be determined by factors such as the film formation time of the pad part 62 and whether or not the patterning of the pad part 62 can be accurately performed, but the above effect can be obtained. There is no limit in meaning. According to experiments, it has been confirmed that there is no problem with the pad portion 62 having a thickness of 3 μm.

また、電極層５８をヤング率が１×１０4ｋｇ／ｍｍ2以上の材料としている。これは、以下に示す実験結果に基づくものである。図４は、第３コンタクト部５９の膜厚を１μｍ、パッド部６２の膜厚を１μｍで固定し、電極層５８の膜厚を２μｍとしながらその材料を様々に変化させたときのクラック発生率を調べた結果を示したグラフである。この図に示されるように、電極層５８の材質がＳｎやＡｌのようにヤング率が小さい材料の場合には、クラック発生率が高くなっているが、Ｔｉ、Ｃｕ、Ｗのようにヤング率が大きい材料の場合には、クラック発生率が０％に大幅に減少している。このとき、クラック発生率が０％になっている材料のうち、最もヤング率が小さなＴｉのヤング率が１×１０4ｋｇ／ｍｍ2であることから、このヤング率以上の材料であれば、クラック発生率を大幅に減少できると言える。このため、電極層５８をヤング率が１×１０4ｋｇ／ｍｍ2以上の材料としている。 The electrode layer 58 is made of a material having a Young's modulus of 1 × 10 4 kg / mm 2 or more. This is based on the experimental results shown below. FIG. 4 shows the crack generation rate when the thickness of the third contact portion 59 is fixed to 1 μm, the thickness of the pad portion 62 is fixed to 1 μm, and the material of the electrode layer 58 is changed to 2 μm while the material is changed variously. It is the graph which showed the result of having investigated. As shown in this figure, when the material of the electrode layer 58 is a material having a small Young's modulus such as Sn or Al, the crack generation rate is high, but the Young's modulus such as Ti, Cu, or W is high. In the case of a material having a large thickness, the crack occurrence rate is greatly reduced to 0%. At this time, among the materials having a crack occurrence rate of 0%, the Young's modulus of Ti having the smallest Young's modulus is 1 × 10 4 kg / mm 2 . It can be said that the crack occurrence rate can be greatly reduced. For this reason, the electrode layer 58 is made of a material having a Young's modulus of 1 × 10 4 kg / mm 2 or more.

さらに、パッド部６２をヤング率が８．０×１０3ｋｇ／ｍｍ2以下の材料としている。これは、以下に示す実験結果に基づくものである。図５は、電極層５８の膜厚を２μｍ、第３コンタクト部５９の膜厚を１μｍで固定し、パッド部６２の膜厚を１μｍとしながらその材料を様々に変化させたときのクラック発生率を調べた結果を示したグラフである。この図に示されるように、パッド部６２の材質がＳｎやＡｌのようにヤング率が小さい材料の場合には、クラック発生率が大幅に低く０％になっているが、Ｔｉ、Ｃｕ、Ｗのようにヤング率が大きい材料の場合には、クラック発生率が大きくなっている。このとき、クラック発生率が０％になっている材料のうち、最もヤング率が大きなＡｌのヤング率が８．０×１０3ｋｇ／ｍｍ2であることから、このヤング率以下の材料であれば、クラック発生率を大幅に減少できると言える。このため、パッド部６２をヤング率が８．０×１０3ｋｇ／ｍｍ2以下の材料としている。 Further, the pad portion 62 is made of a material having a Young's modulus of 8.0 × 10 3 kg / mm 2 or less. This is based on the experimental results shown below. FIG. 5 shows the crack generation rate when the thickness of the electrode layer 58 is fixed to 2 μm, the thickness of the third contact portion 59 is fixed to 1 μm, and the thickness of the pad portion 62 is 1 μm and the material is changed variously. It is the graph which showed the result of having investigated. As shown in this figure, when the material of the pad portion 62 is a material having a small Young's modulus such as Sn or Al, the crack occurrence rate is significantly low and 0%, but Ti, Cu, W In the case of a material having a large Young's modulus as described above, the crack generation rate is large. At this time, among the materials having a crack occurrence rate of 0%, the Young's modulus of Al having the largest Young's modulus is 8.0 × 10 3 kg / mm 2. Thus, it can be said that the crack occurrence rate can be greatly reduced. For this reason, the pad part 62 is made of a material having a Young's modulus of 8.0 × 10 3 kg / mm 2 or less.

なお、上記図４、図５に示すグラフでは、電極層５８やパッド部６２に採用できる材料のすべての実験結果を示していないが、基本的にはクラック発生率はヤング率と関係するため、各材料のヤング率次第で電極層５８やパッド部６２に採用できるか否かが決まる。参考として、図６に各材料とヤング率との関係について示しておく。   The graphs shown in FIGS. 4 and 5 do not show all the experimental results of materials that can be used for the electrode layer 58 and the pad portion 62, but basically the crack occurrence rate is related to the Young's modulus. Depending on the Young's modulus of each material, whether or not it can be used for the electrode layer 58 and the pad portion 62 is determined. For reference, FIG. 6 shows the relationship between each material and Young's modulus.

以上説明したように、本実施形態の半導体装置１によれば、電極層５８を第３絶縁膜６０にて覆うようにすることで、第３絶縁膜６０にて電極層５８が固定されるようにしている。このため、ボンディング時の衝撃により電極層５８が変形してしまうことを従来以上に抑制することが可能となる。   As described above, according to the semiconductor device 1 of the present embodiment, the electrode layer 58 is covered with the third insulating film 60 so that the electrode layer 58 is fixed by the third insulating film 60. I have to. For this reason, it becomes possible to suppress that the electrode layer 58 deform | transforms by the impact at the time of bonding more than before.

特に、電極層５８をヤング率が１×１０4ｋｇ／ｍｍ2以上の材料とし、かつ、電極層５８の膜厚を０．３μｍ以上、好ましくは１μｍ以上としている。このため、電極層５８によるボンディング時の変形防止効果を十分に得ることができ、下地となる層間絶縁膜や素子などのクラック発生を防止することが可能となる。 In particular, the electrode layer 58 is made of a material having a Young's modulus of 1 × 10 4 kg / mm 2 or more, and the film thickness of the electrode layer 58 is 0.3 μm or more, preferably 1 μm or more. For this reason, it is possible to sufficiently obtain the deformation preventing effect at the time of bonding by the electrode layer 58, and it is possible to prevent the occurrence of cracks in the underlying interlayer insulating film and elements.

また、パッド部６２をヤング率が８．０×１０3ｋｇ／ｍｍ2以上の材料とし、かつ、パッド部６２の膜厚を０．５μｍ以上、好ましくは１μｍ以上としている。このため、パッド部６２によるボンディング時の衝撃吸収効果を十分に得ることができ、下地となる層間絶縁膜や素子などのクラック発生を防止することが可能となる。 The pad part 62 is made of a material having a Young's modulus of 8.0 × 10 3 kg / mm 2 or more, and the film thickness of the pad part 62 is 0.5 μm or more, preferably 1 μm or more. For this reason, it is possible to sufficiently obtain an impact absorbing effect at the time of bonding by the pad portion 62, and it is possible to prevent occurrence of cracks in the underlying interlayer insulating film and elements.

さらに、上述したように、電極層５８をＬＤＭＯＳ１０、ＣＭＯＳ２０、Ｂｉｐ３０等の素子が形成されたセル部の直上に形成されるようにしている。このため、セル部の外部に各コンタクト部５３、５６、５７や配線層５２、５５が引き回されることなく、各素子と電極層５８、引いてはパッド部６２が電気的に接続される構造とすることが可能となる。したがって、パターンの制約が少なく、設計自由度を高くでき構造の半導体装置１とすることが可能となる。   Furthermore, as described above, the electrode layer 58 is formed immediately above the cell portion in which elements such as the LDMOS 10, the CMOS 20, and the Bip 30 are formed. For this reason, each element, the electrode layer 58, and the pad part 62 are electrically connected without the contact parts 53, 56, 57 and the wiring layers 52, 55 being routed outside the cell part. It becomes possible to set it as a structure. Therefore, there are few pattern restrictions, design freedom can be increased, and the semiconductor device 1 having a structure can be obtained.

続いて、本実施形態の半導体装置１の製造方法について説明する。ただし、ＳＯＩ基板２に対してＬＤＭＯＳ１０、ＣＭＯＳ２０、Ｂｉｐ３０などの形成工程や、配線構造部５０のうちのＢＰＳＧ膜５１、第１コンタクト部５３、１ｓｔ配線層５２、第１絶縁膜５４、第２コンタクト部５６等の形成工程に関しては、従来と同様であるため、それ以降の工程に関してのみ説明する。   Then, the manufacturing method of the semiconductor device 1 of this embodiment is demonstrated. However, the formation process of the LDMOS 10, the CMOS 20, the Bip 30, etc. with respect to the SOI substrate 2, the BPSG film 51, the first contact part 53, the first wiring layer 52, the first insulating film 54, the second contact in the wiring structure part 50. Since the formation process of the part 56 and the like is the same as the conventional process, only the subsequent processes will be described.

まず、第２コンタクト部５６まで形成したのち、第２絶縁膜５７における第１ＴＥＯＳ膜５７ａを成膜する。このとき、第１ＴＥＯＳ膜５７ａの膜厚を後で形成する２ｎｄ配線層５５の膜厚程度としている。そして、第１ＴＥＯＳ膜５７ａのうち２ｎｄ配線層５５の形成予定位置にフォト・エッチング工程により溝を形成する。そして、バリアメタル５５ａおよびＣｕ層５５ｂを成膜したのち、第１ＴＥＯＳ膜５７ａをストッパとしたＣＭＰ研磨等を行うことにより、第１ＴＥＯＳ膜５７ａの溝内に２ｎｄ配線層５５を配置する。その後、第１ＴＥＯＳ膜５７ａおよび２ｎｄ配線層５５の表面を覆うように、シリコン窒化膜５７ｂを成膜する。   First, after forming to the 2nd contact part 56, the 1st TEOS film | membrane 57a in the 2nd insulating film 57 is formed into a film. At this time, the thickness of the first TEOS film 57a is set to about the thickness of the 2nd wiring layer 55 to be formed later. Then, a groove is formed in the first TEOS film 57a at a position where the 2nd wiring layer 55 is to be formed by a photo-etching process. Then, after the barrier metal 55a and the Cu layer 55b are formed, the 2nd wiring layer 55 is disposed in the groove of the first TEOS film 57a by performing CMP polishing or the like using the first TEOS film 57a as a stopper. Thereafter, a silicon nitride film 57b is formed so as to cover the surfaces of the first TEOS film 57a and the 2nd wiring layer 55.

続いて、第２ＴＥＯＳ膜５７ｃを成膜する。このとき、第２ＴＥＯＳ膜５７ｃの膜厚を後で形成する第３コンタクト部５９の膜厚程度、例えば、１μｍ程度の膜厚としている。そして、第２ＴＥＯＳ膜５７ｃおよびシリコン窒化膜５７ｂのうち第３コンタクト部５９の形成予定位置にフォト・エッチング工程により溝を形成する。そして、バリアメタル５９ａおよびＣｕ層５９ｂを成膜したのち、第２ＴＥＯＳ膜５７ｃをストッパとしたＣＭＰ研磨等を行うことにより、第２ＴＥＯＳ膜５７ｃおよびシリコン窒化膜５７ｂの溝内に第３コンタクト部５９を配置する。   Subsequently, a second TEOS film 57c is formed. At this time, the thickness of the second TEOS film 57c is set to be about the thickness of the third contact portion 59 to be formed later, for example, about 1 μm. Then, a groove is formed in the second TEOS film 57c and the silicon nitride film 57b at a position where the third contact portion 59 is to be formed by a photo-etching process. Then, after the barrier metal 59a and the Cu layer 59b are formed, CMP polishing or the like using the second TEOS film 57c as a stopper is performed, so that the third contact portion 59 is formed in the groove of the second TEOS film 57c and the silicon nitride film 57b. Deploy.

その後、第３絶縁膜６０を成膜する。このとき、第３ＴＥＯＳ膜５９の膜厚を後で形成する電極層５８の膜厚程度、つまり０．５μｍ以上、好ましくは１μｍ以上の膜厚としている。そして、第３ＴＥＯＳ膜５９のうち電極層５８の形成予定位置にフォト・エッチング工程により溝を形成する。そして、バリアメタル５８ａおよびヤング率が大きなＣｕ層５８ｂを成膜したのち、第３絶縁膜６０をストッパとしたＣＭＰ研磨等を行うことにより、第３絶縁膜６０の溝内に電極層５８を配置する。これにより、第３絶縁膜６０にて囲まれた電極層５８が厚い膜厚で構成される。   Thereafter, a third insulating film 60 is formed. At this time, the film thickness of the third TEOS film 59 is set to about the film thickness of the electrode layer 58 to be formed later, that is, 0.5 μm or more, preferably 1 μm or more. Then, a groove is formed in the third TEOS film 59 at a position where the electrode layer 58 is to be formed by a photo-etching process. Then, after forming the barrier metal 58a and the Cu layer 58b having a large Young's modulus, the electrode layer 58 is disposed in the groove of the third insulating film 60 by performing CMP polishing or the like using the third insulating film 60 as a stopper. To do. Thereby, the electrode layer 58 surrounded by the third insulating film 60 is formed with a thick film thickness.

この後、Ｐ−ＳｉＮ膜６１を形成したのち、Ｐ−ＳｉＮ膜６１のうちパッド部６２の形成予定位置に開口部を設け、その後、パッド部６２を構成するためのヤング率が小さな金属材料を成膜したのち、それをパターニングすることで、パッド部６２を形成する。これにより、本実施形態の半導体装置１が完成する。   Thereafter, after the P-SiN film 61 is formed, an opening is provided in the P-SiN film 61 at a position where the pad portion 62 is to be formed, and then a metal material having a small Young's modulus for constituting the pad portion 62 is formed. After the film formation, the pad portion 62 is formed by patterning the film. Thereby, the semiconductor device 1 of this embodiment is completed.

（他の実施形態）
上記した実施形態では、素子としてのＬＤＭＯＳ１０、ＣＭＯＳ２０、Ｂｉｐ３０を有する半導体装置１を例として説明したが、これに限らず、他の大きな駆動電流（例えば１０アンペア以上）が要求される半導体デバイスや、他のパワーデバイスを備える半導体装置１においても、本発明を適用することができる。 (Other embodiments)
In the above-described embodiment, the semiconductor device 1 having the LDMOS 10, the CMOS 20, and the Bip 30 as elements has been described as an example. However, the present invention is not limited thereto, The present invention can also be applied to the semiconductor device 1 including other power devices.

上記した実施形態では、素子として、ＬＤＭＯＳ１０、ＣＭＯＳ２０、Ｂｉｐ３０等の半導体基板中に形成された素子を用いる場合を例として説明したが、素子は半導体基板中に形成されたものに限らず、素子として、受動素子等のように、半導体基板表面上に形成された素子を用いた半導体装置１に対しても本発明を適用することができる。   In the above-described embodiment, the case where an element formed in a semiconductor substrate such as LDMOS 10, CMOS 20, Bip 30 is used as an element has been described as an example. However, the element is not limited to the element formed in the semiconductor substrate. The present invention can also be applied to the semiconductor device 1 using elements formed on the surface of the semiconductor substrate, such as passive elements.

また、上記実施形態では、電極層５８の下層に位置する第３コンタクト部５９もヤング率の大きなＣｕなどで構成する場合について説明したが、ここはパッド部６２を構成する材料のようにヤング率の小さなで構成しても良い。さらに、上記実施形態では、電極層５８を基本的にヤング率が高いＣｕなどで構成する場合について説明したが、バリアメタル５８ａのように電極層５８の側壁に位置する部分に関してはヤング率の小さな材料で構成されていても良い。   In the above-described embodiment, the case where the third contact portion 59 located in the lower layer of the electrode layer 58 is also made of Cu having a large Young's modulus has been described, but here, the Young's modulus is similar to the material constituting the pad portion 62. It may be composed of small. Furthermore, in the above-described embodiment, the case where the electrode layer 58 is basically composed of Cu or the like having a high Young's modulus has been described. However, the portion located on the side wall of the electrode layer 58 such as the barrier metal 58a has a small Young's modulus. You may be comprised with material.

本発明の第１実施形態における半導体装置１の断面構成を示す図である。It is a figure showing the section composition of semiconductor device 1 in a 1st embodiment of the present invention. 電極層５８および第３絶縁膜６０の膜厚を様々に変化させたときのクラック発生率を調べた結果を示したグラフである。It is the graph which showed the result of having investigated the crack generation rate when the film thickness of the electrode layer 58 and the 3rd insulating film 60 is changed variously. パッド部６２の膜厚を様々に変化させたときのクラック発生率を調べた結果を示したグラフである。It is the graph which showed the result of having investigated the crack generation rate when changing the film thickness of the pad part 62 variously. 電極層５８の膜厚を２μｍとしながらその材料を様々に変化させたときのクラック発生率を調べた結果を示したグラフである。It is the graph which showed the result of having investigated the crack generation rate when changing the material variously, setting the film thickness of the electrode layer 58 to 2 micrometers. パッド部６２の膜厚を１μｍとしながらその材料を様々に変化させたときのクラック発生率を調べた結果を示したグラフである。It is the graph which showed the result of having investigated the crack generation rate when changing the material variously, setting the film thickness of the pad part 62 to 1 micrometer. 各材料とヤング率との関係について示した図表である。It is the graph shown about the relationship between each material and Young's modulus.

符号の説明Explanation of symbols

１…半導体装置１、２…ＳＯＩ基板、５０…配線構造部、５１…ＢＰＳＧ膜、５２…１ｓｔ配線層、５３…第１コンタクト部、５４…第１絶縁膜、５５…２ｎｄ配線層、５６…第２コンタクト部、５７…第２絶縁膜、５８…電極層、５９…第３コンタクト部、６０…第３絶縁膜、６１…Ｐ−ＳｉＮ膜、６２…パッド部。   DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 1, 2 ... SOI substrate, 50 ... Wiring structure part, 51 ... BPSG film | membrane, 52 ... 1st wiring layer, 53 ... 1st contact part, 54 ... 1st insulating film, 55 ... 2nd wiring layer, 56 ... 2nd contact part, 57 ... 2nd insulating film, 58 ... Electrode layer, 59 ... 3rd contact part, 60 ... 3rd insulating film, 61 ... P-SiN film, 62 ... Pad part.

Claims (8)

半導体素子（１０、２０、３０）が形成された半導体基板（２）と、
前記半導体基板上に形成された層間絶縁膜（５１、５４、５７）と、
前記層間絶縁膜を介して、前記半導体素子と電気的に接続された配線層（５２、５５）と、
前記配線層と電気的に接続され、ボンディングが行われるパッド部（６２）と、を有してなる半導体装置であって、
前記配線層の上において、該配線層と電気的に接続されるように構成され、前記パッド部よりもヤング率が大きな材料で構成された電極層（５８）と、
前記電極層を囲み、該電極層の側壁面を覆うように構成された絶縁膜（６０）と、を有し、
前記電極層と、該電極層よりもヤング率が小さな材料となる前記パッド部との２層を含む多層構造により、パッド構造が構成されていることを特徴とする半導体装置。 A semiconductor substrate (2) on which semiconductor elements (10, 20, 30) are formed;
Interlayer insulating films (51, 54, 57) formed on the semiconductor substrate;
A wiring layer (52, 55) electrically connected to the semiconductor element via the interlayer insulating film;
A pad part (62) that is electrically connected to the wiring layer and is bonded,
On the wiring layer, an electrode layer (58) configured to be electrically connected to the wiring layer and made of a material having a Young's modulus larger than that of the pad portion;
An insulating film (60) configured to surround the electrode layer and cover a side wall surface of the electrode layer;
A semiconductor device comprising a pad structure having a multilayer structure including two layers of the electrode layer and the pad portion made of a material having a Young's modulus smaller than that of the electrode layer. 前記パッド部は、前記ボンディングにより塑性変形する材料にて構成されていることを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the pad portion is made of a material that is plastically deformed by the bonding. 前記パッド部は、ヤング率が８．０×１０3ｋｇ／ｍｍ2以下の材料で構成されていることを特徴とする請求項２に記載の半導体装置。 The semiconductor device according to claim 2, wherein the pad portion is made of a material having a Young's modulus of 8.0 × 10 3 kg / mm 2 or less. 前記パッド部は、０．５μｍ以上の膜厚で構成されていることを特徴とする請求項１ないし３のいずれか１つに記載の半導体装置。 The semiconductor device according to claim 1, wherein the pad portion is formed with a film thickness of 0.5 μm or more. 前記電極層は、前記ボンディングにより塑性変形しない材料にて構成されていることを特徴とする請求項１ないし４のいずれか１つに記載の半導体装置。 The semiconductor device according to claim 1, wherein the electrode layer is made of a material that is not plastically deformed by the bonding. 前記電極層は、ヤング率が１．０×１０4ｋｇ／ｍｍ2以上の材料で構成されていることを特徴とする請求項５に記載の半導体装置。 The semiconductor device according to claim 5, wherein the electrode layer is made of a material having a Young's modulus of 1.0 × 10 4 kg / mm 2 or more. 前記電極層は、０．３μｍ以上の膜厚で構成されていることを特徴とする請求項１ないし６のいずれか１つに記載の半導体装置。 The semiconductor device according to claim 1, wherein the electrode layer has a thickness of 0.3 μm or more. 前記パッド構造は、前記半導体素子が形成されたセル部の直上に形成されていることを特徴とする請求項１ないし７のいずれか１つに記載の半導体装置。 The semiconductor device according to claim 1, wherein the pad structure is formed immediately above a cell portion in which the semiconductor element is formed.
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