JP2005166959A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP2005166959A
JP2005166959A JP2003403864A JP2003403864A JP2005166959A JP 2005166959 A JP2005166959 A JP 2005166959A JP 2003403864 A JP2003403864 A JP 2003403864A JP 2003403864 A JP2003403864 A JP 2003403864A JP 2005166959 A JP2005166959 A JP 2005166959A
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insulating layer
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semiconductor device
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Yoshifumi Nakamura
嘉文 中村
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To suppress characteristic variations in a gate oxide film region while forming a bonding pad to a semiconductor active region. <P>SOLUTION: Via-holes 16, 17 containing a filler are formed to other regions than a gate oxide film region 15 to relax a stress onto the gate oxide film region 15 under the bonding pad 3 while forming the bonding pad 3 to the semiconductor active region, thereby suppressing the characteristic variations in the gate oxide film region 15. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、半導体の能動領域にボンディングパッドを形成する半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device for forming a bonding pad in an active region of a semiconductor and a method for manufacturing the same.

近年、ノートパソコンや液晶型ＴＶの普及により液晶パネルの需要も大きく伸びてきている。その液晶パネルを動作させるための半導体装置の需要もまた同様に大きく伸び、さらに、ノートパソコンなど普及価格化のために液晶パネルや半導体装置のコストダウンの要求も強くなってきている。   In recent years, the demand for liquid crystal panels has increased greatly due to the spread of notebook computers and liquid crystal TVs. Similarly, the demand for semiconductor devices for operating the liquid crystal panel has also increased greatly, and the demand for cost reduction of liquid crystal panels and semiconductor devices has become stronger in order to popularize notebook computers and the like.

半導体装置のコストダウンの方法として、一枚のウエハからの半導体チップ取れ数を増やすことにより、半導体装置のコストを下げる方法がある。半導体チップの取れ数を増やすためにはウエハサイズを大きくするか、半導体チップサイズを小さくする方法がある。   As a method of reducing the cost of the semiconductor device, there is a method of reducing the cost of the semiconductor device by increasing the number of semiconductor chips obtained from one wafer. In order to increase the number of semiconductor chips obtained, there are methods of increasing the wafer size or decreasing the semiconductor chip size.

ウエハサイズを大きくする方法は、１５０ｍｍから２００ｍｍにウエハサイズを拡大する方法が一部とられている。また、半導体チップサイズを縮小する方法として、従来チップ周辺の半導体の能動領域外に形成されていたボンディングパッドを半導体の能動領域上に配置する方法が検討されている。   As a method for increasing the wafer size, a method for enlarging the wafer size from 150 mm to 200 mm is used in part. As a method for reducing the size of a semiconductor chip, a method in which bonding pads formed outside the active region of the semiconductor around the chip are arranged on the active region of the semiconductor has been studied.

この半導体素子上にボンディングパッドを配置する構造とすることにより、パッド分の面積を削減し小型化を図ることができる。
例えば、図３に示すように、従来の半導体装置によると、ボンディング領域２３の下にＰ型ベース領域、Ｎ型エミッタ領域および両領域の接合によりなる能動領域を有する構造が用いられている。さらに、ワイヤボンディング接続時の圧力による層間膜クラックを防止するために、ボンディング領域２３の下面から基板主面にほぼ垂直に絶縁層を貫通してＰ型ベース領域２９とのコンタクト領域２１２に達するコンタクト２１４とを具備している（例えば、特許文献１参照）。
特開昭６３−２８３０４０号公報 By adopting a structure in which bonding pads are arranged on this semiconductor element, the area of the pads can be reduced and the size can be reduced.
For example, as shown in FIG. 3, according to the conventional semiconductor device, a structure having a P-type base region, an N-type emitter region, and an active region formed by joining both regions under the bonding region 23 is used. Further, in order to prevent an interlayer film crack due to pressure at the time of wire bonding connection, the contact that reaches the contact region 212 with the P-type base region 29 through the insulating layer almost perpendicularly to the main surface of the substrate from the lower surface of the bonding region 23 214 (see, for example, Patent Document 1).
JP-A 63-283040

しかしながら、上記のような半導体素子上にボンディングパッドを配置する従来の半導体装置では、ボンディングの圧力による能動領域（ＭＯＳ型トランジスタではゲート酸化膜領域）の特性変動への考慮はされていない。前記従来の構造では、導電性コンタクトがゲート酸化膜領域にボンディングパッドから垂直に形成されているためにゲート酸化膜領域へボンディング時の圧力が直接かかることになり、ゲート酸化膜領域の特性変動を起こしやすくなる。全ての半導体素子が同時に特性変動する場合は、あまり問題にならないが、ボンディングパッドの下の半導体素子だけが特性変動すると、同時に動作するはずのトランジスタのスイッチングタイミングが変わってしまう可能性が高くなるという問題点があった。   However, in the conventional semiconductor device in which the bonding pad is arranged on the semiconductor element as described above, consideration is not given to the characteristic variation of the active region (the gate oxide film region in the MOS transistor) due to the bonding pressure. In the conventional structure, since the conductive contact is formed in the gate oxide region perpendicularly from the bonding pad, the pressure at the time of bonding is directly applied to the gate oxide region, which causes fluctuations in the characteristics of the gate oxide region. It is easy to wake up. If all the semiconductor elements change their characteristics at the same time, this is not a problem. There was a problem.

本発明の半導体装置およびその製造方法は、半導体の能動領域にボンディングパッドを形成しながら、ゲート酸化膜領域の特性変動を抑制することを目的とする。   An object of the semiconductor device and the manufacturing method thereof of the present invention is to suppress fluctuations in characteristics of a gate oxide film region while forming a bonding pad in an active region of the semiconductor.

上記目的を達成するために、本発明の請求項１記載の半導体装置は、能動領域と前記能動領域を分離する第１の絶縁層を形成する半導体基板と、前記能動領域と前記第１の絶縁層を含む前記半導体基板上に形成される第２の絶縁層と、前記第２の絶縁層上に形成される配線層と、前記第２の絶縁層上および前記配線層上に形成される第３の絶縁層と、前記能動領域と前記配線層を電気的に接続する導通ビアと、前記第１の絶縁層上または前記半導体基板上の前記第２の絶縁層までに形成される１または２以上の第１の強度補強用ビアと、前記能動領域上に形成されたパッシベーション層とボンディングパッドとを有することを特徴とする。   In order to achieve the above object, a semiconductor device according to claim 1 of the present invention includes a semiconductor substrate on which an active region and a first insulating layer separating the active region are formed, the active region and the first insulation. A second insulating layer formed on the semiconductor substrate including a layer; a wiring layer formed on the second insulating layer; and a second insulating layer formed on the second insulating layer and the wiring layer. 3 or 1, 2 formed on the first insulating layer or the second insulating layer on the semiconductor substrate, and a conductive via for electrically connecting the active region and the wiring layer. The first strength reinforcing via described above, a passivation layer formed on the active region, and a bonding pad are provided.

請求項２記載の半導体装置は、能動領域と前記能動領域を分離する第１の絶縁層を形成する半導体基板と、前記能動領域と前記第１の絶縁層を含む前記半導体基板上に形成される第２の絶縁層と、前記第２の絶縁層上に形成された配線層および絶縁層により成る１層または２層以上の配線領域と、前記能動領域と前記配線層を電気的に接続する導通ビアと、前記第１の絶縁層上または前記半導体基板上の前記第２の絶縁層までに形成される１または２以上の第１の強度補強用ビアと、前記配線領域に形成される１または２以上の第２の強度補強用ビアと、前記能動領域上に形成されたパッシベーション層とボンディングパッドとを有することを特徴とする。   The semiconductor device according to claim 2 is formed on the semiconductor substrate including an active region and a semiconductor substrate forming a first insulating layer separating the active region, and the active region and the first insulating layer. A second insulating layer; a wiring layer formed on the second insulating layer; and one or more wiring regions made of the insulating layer; and a continuity for electrically connecting the active region and the wiring layer Vias, one or more first strength reinforcing vias formed on the first insulating layer or the second insulating layer on the semiconductor substrate, and one or more formed in the wiring region It has two or more second strength reinforcing vias, a passivation layer formed on the active region, and a bonding pad.

請求項３記載の半導体装置は、請求項１または請求項２のいずれかに記載の半導体装置において、前記ボンディングパッド上に導電性のバンプを有することを特徴とする。
請求項４記載の半導体装置は、請求項１または請求項２のいずれかに記載の半導体装置において、前記補強用ビアが前記半導体基板上のゲート酸化膜領域以外に形成されていることを特徴とする。 A semiconductor device according to a third aspect is the semiconductor device according to the first or second aspect, wherein conductive bumps are provided on the bonding pads.
According to a fourth aspect of the present invention, in the semiconductor device according to the first or second aspect, the reinforcing via is formed in a region other than the gate oxide film region on the semiconductor substrate. To do.

請求項５記載の半導体装置は、請求項１または請求項２のいずれかに記載の半導体装置において、前記第１の強度補強用ビアおよび第２の強度補強用ビアのうち一部は電気的に開放されていることを特徴とする。   According to a fifth aspect of the present invention, in the semiconductor device according to the first or second aspect, a part of the first strength reinforcing via and the second strength reinforcing via is electrically electrically connected. It is characterized by being open.

請求項６記載の半導体装置は、請求項１または請求項２のいずれかに記載の半導体装置において、前記第１の強度補強用ビアおよび第２の強度補強用ビアが前記ボンディングパッドに対して電気的に開放されていることを特徴とする。   The semiconductor device according to claim 6 is the semiconductor device according to claim 1 or 2, wherein the first strength reinforcing via and the second strength reinforcing via are electrically connected to the bonding pad. It is characterized by being open to the public.

請求項７記載の半導体装置は、請求項６記載の半導体装置において、前記第２のビア上にパッシベーション層を有し、さらにその上にバンプを有することを特徴とする。
請求項８記載の半導体装置は、請求項１または請求項２のいずれかに記載の半導体装置において、前記第１の強度補強用ビアおよび第２の強度補強用ビアの材料におけるヤング率が前記第１の絶縁層および第２の絶縁層を形成する材料のヤング率よりも高いことを特徴とする。
請求項９記載の半導体装置は、請求項１または請求項２のいずれかに記載の半導体装置において、前記第１の強度補強用ビアと第２の強度補強用ビアが短絡することを特徴とする。 A semiconductor device according to a seventh aspect is the semiconductor device according to the sixth aspect, further comprising a passivation layer on the second via, and further a bump on the passivation layer.
The semiconductor device according to claim 8 is the semiconductor device according to claim 1 or 2, wherein the Young's modulus in the material of the first strength reinforcing via and the second strength reinforcing via is the first. The Young's modulus of the material forming the first insulating layer and the second insulating layer is higher.
The semiconductor device according to claim 9 is the semiconductor device according to claim 1 or 2, wherein the first strength reinforcing via and the second strength reinforcing via are short-circuited. .

請求項１０記載の半導体装置の製造方法は、半導体基板に能動領域と前記能動領域を分離する第１の絶縁層を形成する工程と、前記能動領域と前記第１の絶縁層を含む前記半導体基板上に第２の絶縁層を形成する工程と、前記能動領域上に導通ビアを形成する工程と、前記第１の絶縁層上または前記半導体基板上に１または２以上の強度補強用ビアを形成する工程と、前記第２の絶縁層上に前記能動領域と前記導通ビアを介して電気的に接続する配線層を形成する工程と、前記第２の絶縁層上および前記配線層上に第３の絶縁層を形成する工程と、前記能動領域上にボンディングパッドを形成する工程と、前記第３の絶縁層及び前記ボンディングパッド上の一部にパッシベーション層を形成する工程とを有することを特徴とする。   11. The method of manufacturing a semiconductor device according to claim 10, wherein a step of forming an active region and a first insulating layer separating the active region on a semiconductor substrate, and the semiconductor substrate including the active region and the first insulating layer. Forming a second insulating layer thereon; forming a conductive via on the active region; and forming one or more strength reinforcing vias on the first insulating layer or on the semiconductor substrate. A step of forming a wiring layer electrically connected to the active region via the conductive via on the second insulating layer, and a third layer on the second insulating layer and the wiring layer. A step of forming an insulating layer, a step of forming a bonding pad on the active region, and a step of forming a passivation layer on a part of the third insulating layer and the bonding pad. To do.

この前記ゲート酸化膜領域以外の充填物からなるビアが梁の役目を果たすことになり、ボンディング時のゲート酸化膜領域への圧力を緩和することが可能となるため、半導体の能動領域にボンディングパッドを形成しながら、ゲート酸化膜領域の特性変動を抑制することができる。   The via made of the filler other than the gate oxide film region serves as a beam, and the pressure on the gate oxide film region during bonding can be relieved. It is possible to suppress fluctuations in the characteristics of the gate oxide film region while forming.

以上のように、ゲート酸化膜領域以外にも充填物からなるビアを形成することにより、半導体の能動領域にボンディングパッドを形成しながら、ボンディングパッド下のゲート酸化膜領域への応力を緩和し、ゲート酸化膜領域の特性変動を抑制することができる。   As described above, by forming a via made of a filler other than the gate oxide region, the stress on the gate oxide region under the bonding pad is reduced while forming the bonding pad in the active region of the semiconductor, Variations in the characteristics of the gate oxide film region can be suppressed.

以下、本発明の実施の形態について図面を参照しながら説明する。
（実施例１）
図１は本発明の実施例１における半導体装置を示す断面図であり、１は導電性バンプ、２は密着強化用の導電層、３はボンディングパッド、４はパッシベーション層、５は第３の絶縁層、６は配線層、７は第２の絶縁層、８は半導体基板、９はウエル、１０は第１の絶縁層であるＬＯＣＯＳ、１１は拡散領域、１２はゲート電極、１３はゲート絶縁層、１４はゲート酸化膜領域以外に形成されたゲート用ビア、１５はゲート酸化膜領域、１６は第１の絶縁層上の充填物からなるビア、１７はゲート酸化膜領域以外の充填物からなるビア、１８はソース、ドレイン用ビアである。このうち、ビア１６およびビア１７は電気的な接続は行わず、構造的に応力の緩和に寄与する強度補強用のビアである。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Example 1)
FIG. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present invention, where 1 is a conductive bump, 2 is a conductive layer for adhesion enhancement, 3 is a bonding pad, 4 is a passivation layer, and 5 is a third insulation. 6 is a wiring layer, 7 is a second insulating layer, 8 is a semiconductor substrate, 9 is a well, 10 is a first insulating layer LOCOS, 11 is a diffusion region, 12 is a gate electrode, and 13 is a gate insulating layer. , 14 is a gate via formed outside the gate oxide film region, 15 is a gate oxide film region, 16 is a via made of a filler on the first insulating layer, and 17 is made of a filler other than the gate oxide film region. Vias 18 are source and drain vias. Among these, the via 16 and the via 17 are strength reinforcing vias that structurally contribute to stress relaxation without being electrically connected.

図１において、ゲート酸化膜領域１５および第１の絶縁層１０が形成された半導体基板８上に第２の絶縁層７を形成する。さらに、拡散領域１１，第１の絶縁層１０および半導体基板８上に電気的に接続されるようにフォトリソとドライエッチングにより絶縁層７に穴を形成し、穴に拡散防止用の膜（図示せず）を形成し、さらに導電性材料で充填したビア１６，ビア１７，ビア１８を形成する。ゲート用ビア１４はゲート酸化膜領域１５外までゲート電極で引き出してビアを形成する。   In FIG. 1, the second insulating layer 7 is formed on the semiconductor substrate 8 on which the gate oxide film region 15 and the first insulating layer 10 are formed. Further, a hole is formed in the insulating layer 7 by photolithography and dry etching so as to be electrically connected to the diffusion region 11, the first insulating layer 10 and the semiconductor substrate 8, and a film for preventing diffusion (not shown) is formed in the hole. And vias 16, 17 and 18 filled with a conductive material. The gate via 14 is drawn out to the outside of the gate oxide film region 15 with a gate electrode to form a via.

ここで、第２の絶縁層７の材料としては、例えばシリコン酸化膜、ＳＯＧ（Ｓｐｉｎ Ｏｎ Ｇｌａｓｓ ）膜、有機膜、フッ素を添加したＣＶＤ膜、窒化シリコン膜等からなる。拡散防止用の膜材料は、例えばタングステン、ＴｉＮ、Ｔｉ、Ｔａ、ＷＮ、ＷＳｉＮ、ＴｉＳｉＮ、ＴａＮまたはＴａＳｉＮ等からなる。また、穴を充填する導電性材料としては、例えばＡｌ、Ａｌ合金、Ｃｕ、タングステンまたはタングステン合金等のような低抵抗な材料からなる。今回は絶縁材料としてヤング率が７６０００Ｎ／ｍｍ２のシリコン酸化膜を使用し、拡散防止用の膜材料および穴を充填する導電性材料としてヤング率が２６２０００Ｎ／ｍｍ２のタングステンを使用した。ゲート酸化膜領域上に形成された絶縁層よりもヤング率の高いビアが、ビアの梁の役割からも望ましい。絶縁層２の厚みは約１０００ｎｍとした。   Here, the material of the second insulating layer 7 is, for example, a silicon oxide film, an SOG (Spin On Glass) film, an organic film, a CVD film added with fluorine, a silicon nitride film, or the like. The film material for preventing diffusion is made of, for example, tungsten, TiN, Ti, Ta, WN, WSiN, TiSiN, TaN, or TaSiN. The conductive material filling the hole is made of a low resistance material such as Al, Al alloy, Cu, tungsten or tungsten alloy. This time, a silicon oxide film having a Young's modulus of 76000 N / mm 2 was used as an insulating material, and a tungsten material having a Young's modulus of 262000 N / mm 2 was used as a diffusion preventing film material and a conductive material filling the hole. A via having a higher Young's modulus than the insulating layer formed on the gate oxide region is also desirable from the role of the via beam. The thickness of the insulating layer 2 was about 1000 nm.

次に、配線層６を所望のパターンで第２の絶縁層７上に形成する。配線層６は、ゲート酸化膜領域以外のビア１６，ビア１７上には形成しても良いが、形成しない方が望ましい。さらに、配線層６上に第３の絶縁層５を形成し、ボンディングパッド３と配線層６が電気的に接続するように第３の絶縁層５に穴をあける。この穴に拡散防止用の膜を形成し、さらに、導電性材料で充填しビアを形成する（図示せず）。ここでは、ビア１６およびビア１７の端面と第３の絶縁層とは接している。配線層６を形成しないことで配置の自由度が上がる。   Next, the wiring layer 6 is formed on the second insulating layer 7 in a desired pattern. The wiring layer 6 may be formed on the vias 16 and 17 other than the gate oxide film region, but it is preferable not to form them. Further, the third insulating layer 5 is formed on the wiring layer 6, and a hole is made in the third insulating layer 5 so that the bonding pad 3 and the wiring layer 6 are electrically connected. A film for preventing diffusion is formed in the hole and further filled with a conductive material to form a via (not shown). Here, the end surfaces of the via 16 and the via 17 are in contact with the third insulating layer. Since the wiring layer 6 is not formed, the degree of freedom in arrangement increases.

ここで、拡散防止用の膜材料は、例えば、タングステン、ＴｉＮ、Ｔｉ、Ｔａ、ＷＮ、ＷＳｉＮ、ＴｉＳｉＮ、ＴａＮまたはＴａＳｉＮ等からなる。また、穴を充填する導電性材料としては、例えばＡｌ、Ａｌ合金、Ｃｕ、タングステンまたはタングステン合金等のような低抵抗な材料からなる。ボンディングパッド３と配線層６の材料としては、Ａｌ、Ａｌ合金、Ｃｕ、タングステンまたはタングステン合金等のような低抵抗な材料からなる。今回は絶縁材料としてシリコン酸化膜を使用し、拡散防止用の膜材料および穴を充填する導電性材料としてタングステンを使用した。ボンディングパッド３と配線層６としては、Ａｌを使用した。ここで、ゲート酸化膜領域１５の上部において、ボンディングパッド３と配線層６をビアにより接続しなくてもよい。ここで必要であれば同様の構成にてさらに上層に絶縁層と配線層を複数層重ねてもよい(図示せず)。さらに、ボンディングパッド３上には保護用のパッシベーション層４を形成する。パッシベーション層４の材料としては、例えばシリコン酸化膜、ＳＯＧ（Ｓｐｉｎ Ｏｎ Ｇｌａｓｓ ）膜、有機膜、フッ素を添加したＣＶＤ膜、窒化シリコン膜等からなるが、今回は窒化シリコンを使用した。厚みは約１２００ｎｍである。さらに前記ボンディングパッド３上に密着強化用の導電層２を形成し、その上に導電性のバンプ１を形成する。密着強化用の導電層２の材料としては、Ｃｒ、タングステンまたはタングステン合金等からなり、ここではタングステンを使用した。また、バンプ１の材料としては、Ｎｉ、Ａｌ、Ｃｕ、Ａｕ等からなり、今回はＡｕを使用した。   Here, the film material for preventing diffusion is made of, for example, tungsten, TiN, Ti, Ta, WN, WSiN, TiSiN, TaN, or TaSiN. The conductive material filling the hole is made of a low resistance material such as Al, Al alloy, Cu, tungsten or tungsten alloy. The bonding pad 3 and the wiring layer 6 are made of a low resistance material such as Al, Al alloy, Cu, tungsten or tungsten alloy. This time, a silicon oxide film was used as an insulating material, and a tungsten material was used as a conductive material filling the hole and a film material for preventing diffusion. Al was used as the bonding pad 3 and the wiring layer 6. Here, in the upper part of the gate oxide film region 15, the bonding pad 3 and the wiring layer 6 need not be connected by vias. Here, if necessary, a plurality of insulating layers and wiring layers may be stacked on the upper layer with the same configuration (not shown). Further, a protective passivation layer 4 is formed on the bonding pad 3. The material of the passivation layer 4 is, for example, a silicon oxide film, an SOG (Spin On Glass) film, an organic film, a fluorine-added CVD film, a silicon nitride film, or the like, but this time, silicon nitride was used. The thickness is about 1200 nm. Further, a conductive layer 2 for adhesion enhancement is formed on the bonding pad 3, and a conductive bump 1 is formed thereon. The material of the conductive layer 2 for adhesion reinforcement is made of Cr, tungsten, tungsten alloy, or the like, and here tungsten was used. The bump 1 is made of Ni, Al, Cu, Au, or the like, and Au is used this time.

以上のように、ゲート酸化膜領域のみにビアを形成する場合に比べて、ゲート酸化膜領域にビアを形成し、ゲート酸化膜領域以外にも多数のビアを形成すると、ゲート酸化膜領域に形成されたトランジスタの特性が約１０％向上した。   As described above, when vias are formed in the gate oxide region compared to the case where vias are formed only in the gate oxide region, many vias other than the gate oxide region are formed in the gate oxide region. The characteristics of the fabricated transistor were improved by about 10%.

したがって、ゲート酸化膜領域１５に加えてゲート酸化膜領域１５以外にもビア１６，ビア１７といった多数のビアを形成することにより、半導体の能動領域にボンディングパッド３を形成しながら、ボンディングパッド下のゲート酸化膜領域１５への応力を緩和し、ゲート酸化膜領域１５の特性変動を抑制することができる。
（実施例２）
図２は本発明の実施例２における半導体装置を示す断面図であり、１は導電性バンプ、２は密着強化用の導電層、３はボンディングパッド、４はパッシベーション層、５は第３の絶縁層、６は配線層、７は第２の絶縁層、８は半導体基板、９はウエル、１０は第１の絶縁層であるＬＯＣＯＳ、１１は拡散領域、１２はゲート電極、１３はゲート絶縁層、１４はゲート酸化膜領域以外に形成されたゲート用ビア、１５はゲート酸化膜領域、１６は第１の絶縁層上の充填物からなるビア、１７はゲート酸化膜領域以外の充填物からなるビア、１８はソース、ドレイン用ビア、１９は第３の絶縁層のビア、２０はビア上のパッシベーション層４上にバンプがある領域である。このうち、ビア１６およびビア１７は電気的な接続は行わず、構造的に応力の緩和に寄与する強度補強用のビアである。 Therefore, by forming a large number of vias 16 and 17 in addition to the gate oxide film region 15 in addition to the gate oxide film region 15, the bonding pad 3 is formed in the active region of the semiconductor while the bonding pad 3 is formed under the bonding pad. The stress on the gate oxide film region 15 can be relieved, and the characteristic variation of the gate oxide film region 15 can be suppressed.
(Example 2)
FIG. 2 is a cross-sectional view showing a semiconductor device according to a second embodiment of the present invention, where 1 is a conductive bump, 2 is a conductive layer for adhesion enhancement, 3 is a bonding pad, 4 is a passivation layer, and 5 is a third insulation. 6 is a wiring layer, 7 is a second insulating layer, 8 is a semiconductor substrate, 9 is a well, 10 is a first insulating layer LOCOS, 11 is a diffusion region, 12 is a gate electrode, and 13 is a gate insulating layer. , 14 is a gate via formed outside the gate oxide film region, 15 is a gate oxide film region, 16 is a via made of a filler on the first insulating layer, and 17 is made of a filler other than the gate oxide film region. Vias 18 are source and drain vias, 19 are vias of the third insulating layer, and 20 is a region with bumps on the passivation layer 4 on the vias. Among these, the via 16 and the via 17 are strength reinforcing vias that structurally contribute to stress relaxation without being electrically connected.

図２において、ゲート酸化膜領域１５および第１の絶縁層１０が形成された半導体基板８上に第２の絶縁層７を形成する。さらに、ゲート酸化膜領域１５に穴を形成せず、さらに拡散領域１１上に電気的に接続されるようにフォトリソとドライエッチングにより穴を形成し、穴に拡散防止用の膜（図示せず）を形成し、さらに導電性材料で充填しビア１６，ビア１７，ビア１８を形成する。ゲート用ビア１４はゲート酸化膜領域１５外までゲート電極で引き出してビアを形成する。   In FIG. 2, the second insulating layer 7 is formed on the semiconductor substrate 8 on which the gate oxide film region 15 and the first insulating layer 10 are formed. Further, a hole is not formed in the gate oxide film region 15, and a hole is formed by photolithography and dry etching so as to be electrically connected to the diffusion region 11, and a diffusion preventing film (not shown) is formed in the hole. And is filled with a conductive material to form vias 16, 17, and 18. The gate via 14 is drawn out to the outside of the gate oxide film region 15 with a gate electrode to form a via.

ここで、第２の絶縁層７の材料としては、例えば、シリコン酸化膜、ＳＯＧ（Ｓｐｉｎ Ｏｎ Ｇｌａｓｓ ）膜、有機膜、フッ素を添加したＣＶＤ膜、窒化シリコン膜等からなる。拡散防止用の膜材料は、例えば、タングステン、ＴｉＮ、Ｔｉ、Ｔａ、ＷＮ、ＷＳｉＮ、ＴｉＳｉＮ、ＴａＮまたはＴａＳｉＮ等からなる。また、穴を充填する導電性材料としては、例えば、Ａｌ、Ａｌ合金、Ｃｕ、タングステンまたはタングステン合金等のような低抵抗な材料からなる。今回は絶縁材料としてヤング率が７６０００Ｎ／ｍｍ２のシリコン酸化膜を使用し、拡散防止用の膜材料および穴を充填する導電性材料としてヤング率が２６２０００Ｎ／ｍｍ２のタングステンを使用した。ゲート酸化膜領域上に形成された絶縁層よりもヤング率の高いビアが、ビアの梁の役割からも望ましい。絶縁層２の厚みは約１０００ｎｍとした。   Here, the material of the second insulating layer 7 is, for example, a silicon oxide film, a SOG (Spin On Glass) film, an organic film, a CVD film added with fluorine, a silicon nitride film, or the like. The film material for preventing diffusion is made of, for example, tungsten, TiN, Ti, Ta, WN, WSiN, TiSiN, TaN, or TaSiN. The conductive material filling the hole is made of a low resistance material such as Al, Al alloy, Cu, tungsten, or tungsten alloy. This time, a silicon oxide film having a Young's modulus of 76000 N / mm 2 was used as an insulating material, and a tungsten material having a Young's modulus of 262000 N / mm 2 was used as a diffusion preventing film material and a conductive material filling the hole. A via having a higher Young's modulus than the insulating layer formed on the gate oxide region is also desirable from the role of the via beam. The thickness of the insulating layer 2 was about 1000 nm.

次に、配線層６を所望のパターンで第２の絶縁層７上に形成する。配線層６は、ゲート酸化膜領域１５以外のビア１６，ビア１７上には形成しても良いが、形成しない方が望ましい。さらに、配線層６上に第３の絶縁層５を形成し、必要があればボンディングパッド３と配線層６が電気的に接続するように第３の絶縁層５に穴をあける。同様に、第２の絶縁層に形成したビア１７上に重なるように第３の絶縁層に穴を形成する。この穴に拡散防止用の膜（図示せず）を形成し、さらに導電性材料で充填しビア１９を形成する。このビア１９は、電気的に他の配線と接続されてもよいが、図２のように電気的に接続されなくてもよい。ここで必要であれば同様の構成にてさらに上層に絶縁層と配線層を複数層重ねてもよい(図示せず)。   Next, the wiring layer 6 is formed on the second insulating layer 7 in a desired pattern. The wiring layer 6 may be formed on the via 16 and the via 17 other than the gate oxide film region 15, but it is desirable not to form the wiring layer 6. Further, a third insulating layer 5 is formed on the wiring layer 6, and if necessary, a hole is made in the third insulating layer 5 so that the bonding pad 3 and the wiring layer 6 are electrically connected. Similarly, a hole is formed in the third insulating layer so as to overlap the via 17 formed in the second insulating layer. A film for preventing diffusion (not shown) is formed in the hole, and further filled with a conductive material to form a via 19. The via 19 may be electrically connected to other wiring, but may not be electrically connected as shown in FIG. If necessary, a plurality of insulating layers and wiring layers may be stacked on the upper layer with the same configuration (not shown).

次に、第３の絶縁層５に形成されたビア１９上にパッシベーション層４を形成する。さらに、その上に密着強化用の導電層２を形成し、導電性バンプ１を形成する。
これにより、バンプが加圧される時の圧力が、このビア上のパッシベーションにバンプがある領域２０にもかかるため、圧力を積層された能動素子上の絶縁層５と絶縁層７の材料よりもヤング率の高い、多数のビア１７とビア１９で支えることになり、ゲート酸化膜領域１５への圧力を軽減できるようになる。 Next, the passivation layer 4 is formed on the via 19 formed in the third insulating layer 5. Further, a conductive layer 2 for adhesion enhancement is formed thereon, and conductive bumps 1 are formed.
As a result, the pressure applied to the bumps is also applied to the region 20 where the bumps are present in the passivation on the via, so that the pressure is higher than that of the material of the insulating layers 5 and 7 on the active element on which the pressure is laminated. It is supported by a large number of vias 17 and vias 19 having a high Young's modulus, and the pressure on the gate oxide film region 15 can be reduced.

拡散防止用の膜材料としては、例えば、タングステン、ＴｉＮ、Ｔｉ、Ｔａ、ＷＮ、ＷＳｉＮ、ＴｉＳｉＮ、ＴａＮまたはＴａＳｉＮ等からなる。また、穴を充填する導電性材料としては、例えば、Ａｌ、Ａｌ合金、Ｃｕ、タングステンまたはタングステン合金等のような低抵抗な材料からなる。ボンディングパッド２と配線層６の材料としては、Ａｌ、Ａｌ合金、Ｃｕ、タングステンまたはタングステン合金等のような低抵抗な材料を用いる。今回は絶縁材料としてシリコン酸化膜を使用し、拡散防止用の膜材料および穴を充填する導電性材料としてタングステンを使用した。ボンディングパッド３と配線材料６としては、Ａｌを使用した。パッシベーション層４の材料としては、例えば、シリコン酸化膜、ＳＯＧ（Ｓｐｉｎ Ｏｎ Ｇｌａｓｓ ）膜、有機膜、フッ素を添加したＣＶＤ膜、窒化シリコン膜等を用いるが、今回は窒化シリコンを使用した。厚みは約１２００ｎｍである。密着強化用の導電層２の材料としては、Ｃｒ、タングステンまたはタングステン合金等からなり、タングステンを使用した。また、バンプ１の材料としては、Ｎｉ、Ａｌ、Ｃｕ、Ａｕ等を用い、今回はＡｕを使用した。   Examples of the film material for preventing diffusion include tungsten, TiN, Ti, Ta, WN, WSiN, TiSiN, TaN, and TaSiN. The conductive material filling the hole is made of a low resistance material such as Al, Al alloy, Cu, tungsten, or tungsten alloy. As a material of the bonding pad 2 and the wiring layer 6, a low resistance material such as Al, Al alloy, Cu, tungsten, or tungsten alloy is used. This time, a silicon oxide film was used as an insulating material, and a tungsten material was used as a conductive material filling the hole and a film material for preventing diffusion. Al was used as the bonding pad 3 and the wiring material 6. As a material of the passivation layer 4, for example, a silicon oxide film, an SOG (Spin On Glass) film, an organic film, a CVD film added with fluorine, a silicon nitride film, or the like is used, but this time, silicon nitride is used. The thickness is about 1200 nm. As a material of the conductive layer 2 for adhesion strengthening, it is made of Cr, tungsten, tungsten alloy or the like, and tungsten is used. Further, as the material of the bump 1, Ni, Al, Cu, Au or the like was used, and Au was used this time.

以上のように、ゲート酸化膜領域のみにビアを形成する場合に比べて、ゲート酸化膜領域にビアを形成し、ゲート酸化膜領域以外にも多数のビアを形成すると、ゲート酸化膜領域に形成されたトランジスタの特性が約１２％向上した。   As described above, if vias are formed in the gate oxide region compared to the case where vias are formed only in the gate oxide region, and many vias are formed in addition to the gate oxide region, they are formed in the gate oxide region. The transistor characteristics improved by about 12%.

したがって、ゲート酸化膜領域１５に加えてゲート酸化膜領域１５以外にもビア１６，ビア１７，ビア１９といった多数のビアを形成することにより、半導体の能動領域にボンディングパッド３を形成しながら、ボンディングパッド下のゲート酸化膜領域１５への応力を緩和し、ゲート酸化膜領域１５の特性変動を抑制することができる。   Therefore, in addition to the gate oxide film region 15, in addition to the gate oxide film region 15, a number of vias such as vias 16, 17, and 19 are formed so that the bonding pad 3 is formed in the semiconductor active region while bonding is performed. The stress on the gate oxide film region 15 under the pad can be relieved, and the characteristic variation of the gate oxide film region 15 can be suppressed.

以上の説明では、配線層が１層の場合について説明したが、配線層およびその絶縁層である酸化膜からなる配線領域が複数層ある場合でも、それぞれの層に強度補強用ビアを形成することも可能である。   In the above description, the case where the wiring layer is one layer has been described. However, even when there are a plurality of wiring regions consisting of the wiring layer and the oxide film which is the insulating layer, a strength reinforcing via is formed in each layer. Is also possible.

本発明の半導体装置およびその製造方法は、ゲート酸化膜領域の特性変動を抑制することができ、半導体の能動領域にボンディングパッドを形成する半導体装置およびその製造方法等に有用である。   The semiconductor device and the manufacturing method thereof of the present invention can suppress fluctuations in characteristics of the gate oxide film region, and are useful for a semiconductor device in which a bonding pad is formed in an active region of a semiconductor, a manufacturing method thereof, and the like.

本発明の実施例１における半導体装置を示す断面図Sectional drawing which shows the semiconductor device in Example 1 of this invention 本発明の実施例２における半導体装置を示す断面図Sectional drawing which shows the semiconductor device in Example 2 of this invention 従来の半導体装置を示す断面図Sectional view showing a conventional semiconductor device

符号の説明Explanation of symbols

１ 導電性バンプ
２ 密着強化用の導電層
３ ボンディングパッド
４ パッシベーション層
５ 第３の絶縁層
６ 配線層
７ 第２の絶縁層
８ 半導体基板
９ ウエル
１０ 第１の絶縁層（ＬＯＣＯＳ）
１１ 拡散領域
１２ ゲート電極
１３ ゲート絶縁層
１４ ゲート用ビア
１５ ゲート酸化膜領域
１６ ビア
１７ ビア
１８ ビア
１９ ビア
２０ ビア上のパッシベーションにバンプがある領域
２３ ボンディング領域
２９ Ｐ型ベース領域
２１２ コンタクト領域
２１４ コンタクト DESCRIPTION OF SYMBOLS 1 Conductive bump 2 Conductive layer for adhesion | attachment 3 Bonding pad 4 Passivation layer 5 3rd insulating layer 6 Wiring layer 7 2nd insulating layer 8 Semiconductor substrate 9 Well 10 1st insulating layer (LOCOS)
DESCRIPTION OF SYMBOLS 11 Diffusion area | region 12 Gate electrode 13 Gate insulating layer 14 Via for gate 15 Gate oxide film area | region 16 Via 17 Via 18 Via 19 Via 20 The area | region which has bump in the passivation on via 23 Bonding area 29 P type base area 212 Contact area 214 Contact

Claims (10)

能動領域と前記能動領域を分離する第１の絶縁層を形成する半導体基板と、
前記能動領域と前記第１の絶縁層を含む前記半導体基板上に形成される第２の絶縁層と、
前記第２の絶縁層上に形成される配線層と、
前記第２の絶縁層上および前記配線層上に形成される第３の絶縁層と、
前記能動領域と前記配線層を電気的に接続する導通ビアと、
前記第１の絶縁層上または前記半導体基板上の前記第２の絶縁層までに形成される１または２以上の第１の強度補強用ビアと、
前記能動領域上に形成されたパッシベーション層とボンディングパッドと
を有することを特徴とする半導体装置。 A semiconductor substrate forming an active region and a first insulating layer separating the active region;
A second insulating layer formed on the semiconductor substrate including the active region and the first insulating layer;
A wiring layer formed on the second insulating layer;
A third insulating layer formed on the second insulating layer and on the wiring layer;
A conductive via that electrically connects the active region and the wiring layer;
One or more first strength reinforcing vias formed on the first insulating layer or on the semiconductor substrate up to the second insulating layer;
A semiconductor device comprising a passivation layer and a bonding pad formed on the active region. 能動領域と前記能動領域を分離する第１の絶縁層を形成する半導体基板と、
前記能動領域と前記第１の絶縁層を含む前記半導体基板上に形成される第２の絶縁層と、
前記第２の絶縁層上に形成された配線層および絶縁層により成る１層または２層以上の配線領域と、
前記能動領域と前記配線層を電気的に接続する導通ビアと、
前記第１の絶縁層上または前記半導体基板上の前記第２の絶縁層までに形成される１または２以上の第１の強度補強用ビアと、
前記配線領域に形成される１または２以上の第２の強度補強用ビアと、
前記能動領域上に形成されたパッシベーション層とボンディングパッドと
を有することを特徴とする半導体装置。 A semiconductor substrate forming an active region and a first insulating layer separating the active region;
A second insulating layer formed on the semiconductor substrate including the active region and the first insulating layer;
A wiring region formed of the wiring layer and the insulating layer formed on the second insulating layer, or one or more wiring regions;
A conductive via that electrically connects the active region and the wiring layer;
One or more first strength reinforcing vias formed on the first insulating layer or on the semiconductor substrate up to the second insulating layer;
One or more second strength reinforcing vias formed in the wiring region;
A semiconductor device comprising a passivation layer and a bonding pad formed on the active region. 前記ボンディングパッド上に導電性のバンプを有することを特徴とする請求項１または請求項２のいずれかに記載の半導体装置。   3. The semiconductor device according to claim 1, further comprising conductive bumps on the bonding pads. 前記補強用ビアが前記半導体基板上のゲート酸化膜領域以外に形成されていることを特徴とする請求項１または請求項２のいずれかに記載の半導体装置。   3. The semiconductor device according to claim 1, wherein the reinforcing via is formed in a region other than the gate oxide film region on the semiconductor substrate. 前記第１の強度補強用ビアおよび第２の強度補強用ビアのうち一部は電気的に開放されていることを特徴とする請求項１または請求項２のいずれかに記載の半導体装置。   3. The semiconductor device according to claim 1, wherein a part of the first strength reinforcing via and the second strength reinforcing via is partially opened. 4. 前記第１の強度補強用ビアおよび第２の強度補強用ビアが前記ボンディングパッドに対して電気的に開放されていることを特徴とする請求項１または請求項２のいずれかに記載の半導体装置。   3. The semiconductor device according to claim 1, wherein the first strength reinforcing via and the second strength reinforcing via are electrically open to the bonding pad. 4. . 前記第２のビア上にパッシベーション層を有し、さらにその上にバンプを有することを特徴とする請求項６に記載の半導体装置。   The semiconductor device according to claim 6, further comprising: a passivation layer on the second via, and further a bump on the passivation layer. 前記第１の強度補強用ビアおよび第２の強度補強用ビアの材料におけるヤング率が前記第１の絶縁層および第２の絶縁層を形成する材料のヤング率よりも高いことを特徴とする請求項１または請求項２のいずれかに記載の半導体装置。   The Young's modulus in the material of the first strength reinforcing via and the second strength reinforcing via is higher than the Young's modulus of the material forming the first insulating layer and the second insulating layer. The semiconductor device according to claim 1 or 2. 前記第１の強度補強用ビアと第２の強度補強用ビアが短絡することを特徴とする請求項１または請求項２のいずれかに記載の半導体装置。   3. The semiconductor device according to claim 1, wherein the first strength reinforcing via and the second strength reinforcing via are short-circuited. 半導体基板に能動領域と前記能動領域を分離する第１の絶縁層を形成する工程と、
前記能動領域と前記第１の絶縁層を含む前記半導体基板上に第２の絶縁層を形成する工程と、
前記能動領域上に導通ビアを形成する工程と、
前記第１の絶縁層上または前記半導体基板上に１または２以上の強度補強用ビアを形成する工程と、
前記第２の絶縁層上に前記能動領域と前記導通ビアを介して電気的に接続する配線層を形成する工程と、
前記第２の絶縁層上および前記配線層上に第３の絶縁層を形成する工程と、
前記能動領域上にボンディングパッドを形成する工程と、
前記第３の絶縁層及び前記ボンディングパッド上の一部にパッシベーション層を形成する工程と
を有することを特徴とする半導体装置の製造方法。 Forming an active region and a first insulating layer separating the active region on a semiconductor substrate;
Forming a second insulating layer on the semiconductor substrate including the active region and the first insulating layer;
Forming a conductive via on the active region;
Forming one or more strength reinforcing vias on the first insulating layer or on the semiconductor substrate;
Forming a wiring layer electrically connected to the active region via the conductive via on the second insulating layer;
Forming a third insulating layer on the second insulating layer and the wiring layer;
Forming a bonding pad on the active region;
Forming a passivation layer on part of the third insulating layer and the bonding pad. A method of manufacturing a semiconductor device, comprising:
JP2003403864A 2003-12-03 2003-12-03 Semiconductor device and manufacturing method thereof Pending JP2005166959A (en)

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JP2008294135A (en) * 2007-05-23 2008-12-04 Sharp Corp Semiconductor device and its manufacturing method
JP2009124042A (en) * 2007-11-16 2009-06-04 Rohm Co Ltd Semiconductor device
US7884478B2 (en) 2006-02-27 2011-02-08 Elpida Memory, Inc. Semiconductor apparatus
US9093432B2 (en) 2011-09-23 2015-07-28 Sanken Electric Co., Ltd. Semiconductor device

Cited By (8)

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Publication number Priority date Publication date Assignee Title
US7884478B2 (en) 2006-02-27 2011-02-08 Elpida Memory, Inc. Semiconductor apparatus
JP2008294135A (en) * 2007-05-23 2008-12-04 Sharp Corp Semiconductor device and its manufacturing method
JP2009124042A (en) * 2007-11-16 2009-06-04 Rohm Co Ltd Semiconductor device
US9035455B2 (en) 2007-11-16 2015-05-19 Rohm Co., Ltd. Semiconductor device
US9437544B2 (en) 2007-11-16 2016-09-06 Rohm Co., Ltd. Semiconductor device
US9607957B2 (en) 2007-11-16 2017-03-28 Rohm Co., Ltd. Semiconductor device
US9941231B2 (en) 2007-11-16 2018-04-10 Rohm Co., Ltd. Semiconductor device
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