JP5477599B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device.

  Conventionally, if a semiconductor element such as a MOS transistor is disposed under a pad, the characteristics of the semiconductor element such as a MOS transistor may be impaired due to stress during bonding. In a semiconductor chip, the pad forming portion and the semiconductor element are The region to be formed is provided separately in plan view. However, with the recent miniaturization and higher integration of semiconductor chips, there has been a demand for disposing semiconductor elements below the pads. An example of such a technique is disclosed in Japanese Patent Laid-Open No. 2002-319587.

JP 2002-319587 A

  An object of the present invention is to provide a highly reliable semiconductor device in which a semiconductor element can be provided below an electrode pad.

(1) The semiconductor device of the present invention
A semiconductor layer having an element formation region and an element isolation region provided around the element formation region;
An element formed in the element forming region;
An interlayer insulating layer provided above the semiconductor layer;
An electrode pad provided above the interlayer insulating layer and having a rectangular shape having a short side and a long side in plan view, and the electrode pad partially overlapping with the element in plan view,
In the semiconductor layer, a predetermined range located outside from the vertically lower side of the short side of the electrode pad is an element prohibited region.

  In the semiconductor device of the present invention, at least a part of the semiconductor layer located below the electrode pad is an element formation region, and an element prohibition region is provided in a predetermined region located outward from the end of the electrode pad. It has been. The predetermined region located outward from the end of the electrode pad is easily stressed by forming the electrode pad, and stress is likely to occur. For this reason, cracks are likely to occur in the interlayer insulating layer disposed above this region. For example, when a semiconductor element such as a MOS transistor is provided in this region, it may be a cause of deteriorating the characteristics of the MOS transistor. Therefore, in the semiconductor device according to the present invention, the above-mentioned problem is avoided by setting this predetermined region as an element prohibited region. In addition, an element formation region is provided in the semiconductor layer located below the electrode pad, and the semiconductor element is arranged in a place where there is no problem even if the semiconductor element is provided under the electrode pad. In other words, according to the present invention, the semiconductor element is positively disposed in a place below the electrode pad and does not affect the reliability even if the semiconductor element is provided. On the other hand, the reliability is impaired. A semiconductor device in which miniaturization and improvement in reliability are achieved can be provided by not arranging a semiconductor element in a conceivable place.

In the present invention, the element region refers to a region where various elements such as a MIS transistor, a diode, and a resistor are formed. In the present invention, when a specific B layer (hereinafter referred to as “B layer”) provided above a specific A layer (hereinafter referred to as “A layer”) is referred to as “B” directly on the A layer. This includes the case where the layer is provided and the case where the B layer is provided on the A layer via another layer.

  The semiconductor device according to the present invention can further take the following aspects.

(2) In the semiconductor device according to the present invention,
The element prohibited region may be a range having a distance of 1.0 μm to 2.5 μm from the vertically lower side to the outer side of the short side of the electrode pad.

(3) In the semiconductor device according to the present invention,
A passivation layer above the electrode pad and having an opening exposing at least a portion of the electrode pad;
The element forbidden region may be a range having a distance corresponding to the thickness of the passivation layer from the vertically lower side to the outer side of the short side of the electrode pad.

(4) In the semiconductor device according to the present invention,
A bump provided in the opening may be included.

(5) A semiconductor device according to the present invention includes:
A semiconductor layer having an element formation region and an element isolation region provided around the element formation region;
An element formed in the element forming region;
An interlayer insulating layer provided above the semiconductor layer;
An electrode pad that is provided above the interlayer insulating layer and overlaps the element in plan view, and in the semiconductor layer, the predetermined range located outside the electrode pad from the vertically lower side is an element prohibited region It is.

  In the semiconductor device according to the present invention, the semiconductor layer located below the electrode pad is an element region, and a forbidden region is provided in a predetermined region located outward from the end of the electrode pad. In other words, according to the present invention, the semiconductor device has the same advantages as those of the semiconductor device described above, and the semiconductor device is positively disposed in a place below the electrode pad and does not affect the reliability even if the semiconductor element is provided. On the other hand, a semiconductor device in which miniaturization and improvement in reliability are achieved can be provided by disposing a semiconductor element in a place where the element is disposed and reliability is considered to be impaired.

(6) In the semiconductor device according to the present invention,
The element forbidden region may be a range having a distance of 1.0 μm to 2.5 μm from the vertically lower side to the outer side of the end of the electrode pad.

(7) In the semiconductor device according to the present invention,
A passivation layer above the electrode pad and having an opening exposing at least a portion of the electrode pad;
The element forbidden region may be a range having a distance corresponding to the thickness of the passivation layer from the vertically lower side to the outer side of the end of the electrode pad.

(8) In the semiconductor device according to the present invention,
A bump provided in the opening may be included.

(9) In the semiconductor device according to the present invention,
The element may be a transistor.

(10) In the semiconductor device according to the present invention,
The element prohibited region may be a prohibited region of a low voltage driving transistor.

(11) In the semiconductor device according to the invention,
A high breakdown voltage transistor may be provided in the element prohibited region.

1A and 1B illustrate a semiconductor device according to a first embodiment. 1A and 1B illustrate a semiconductor device according to a first embodiment. 1A and 1B illustrate a semiconductor device according to a first embodiment. 6A and 6B illustrate a semiconductor device according to a second embodiment. 6A and 6B illustrate a semiconductor device according to a modification example of the first and second embodiments. 6A and 6B illustrate a semiconductor device according to a modification example of the first and second embodiments.

  Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings.

1. First Embodiment FIG. 1 is a cross-sectional view schematically showing a semiconductor device according to the present embodiment, and FIG. 2 shows the shape of the electrode pad and the prohibited region in the semiconductor device according to the present embodiment. It is a top view which shows typically the relationship. FIG. 3 is a plan view for explaining the element formation region 10A. In addition, the cross section of FIG. 1 is a cross section along the XX line of FIG.

  As shown in FIG. 1, the semiconductor device according to the present embodiment includes a semiconductor layer 10. As the semiconductor layer 10, a single crystal silicon substrate, a semiconductor layer (SOI: Silicon on Insulator) provided over an insulating layer, and the semiconductor layer is a silicon layer, a germanium layer, and a silicon germanium layer, or the like is used. Can do.

  The semiconductor layer 10 is provided with an element isolation insulating layer 20. The element isolation insulating layer 20 can be formed by the STI method, the LOCOS method, and the semi-recessed LOCOS method. FIG. 1 shows an element isolation insulating layer 20 formed by the STI method. Thus, by providing the element isolation insulating layer 20, the element formation region 10A and the element prohibition region 12 in which elements are formed are defined. As will be described later, the element formation region 10A is a region provided below the electrode pad. The element prohibited region 12 is a gray area in FIG. 1 and is a semiconductor layer 10 in a predetermined range outside from the end of the electrode pad. This area will also be described later. In the semiconductor device according to the present embodiment, the element formation region 10B is further provided outside the element prohibition region 12.

  In the element formation region 10A, a low voltage drive MIS (Metal Insulator Semiconductor) transistor 30 in which an insulating layer is not provided in the offset region is provided. Also in the element formation region 10B, the MIS transistor 40 is provided as in the element formation region 10A. The MIS transistor 30 includes a gate insulating layer 32, a gate electrode 34 provided on the gate insulating layer 32, and an impurity region 36 provided in the semiconductor layer 10. The impurity region 36 becomes a source region or a drain region. The MIS transistor 40 has a structure similar to that of the MIS transistor 30 and includes a gate insulating layer 42, a gate electrode 44, and an impurity region 46, and is a low-voltage driven transistor in which no insulating layer is provided in the offset region. In addition, as shown in FIG. 3, the element formation region 10A in the present invention is a region (a region indicated by oblique lines) surrounded by the element isolation insulating layer 20 in a plan view. The same applies to the element formation region 10B.

  Above the MIS transistors 30 and 40, an interlayer insulating layer 50 and an interlayer insulating layer 60 provided so as to cover the MIS transistors 30 and 40 are sequentially provided. For the interlayer insulating layer 50 and the interlayer insulating layer 60, a known general material can be used. A wiring layer 52 having a predetermined pattern is provided on the interlayer insulating layer 50, and the wiring layer 52 and the impurity region 36 of the MIS transistor 30 are electrically connected by a contact layer 54.

An electrode pad 62 is provided on the interlayer insulating layer 60. The electrode pad 62 can be electrically connected to the wiring layer 52 and the contact layer 64. The electrode pad 62 can be formed of a metal such as aluminum or copper.

The semiconductor device according to the present embodiment further includes a passivation layer 70 as shown in FIG. The passivation layer 70 is formed with an opening 72 that exposes at least a part of the electrode pad 62. As shown in FIGS. 1 and 2, the opening 72 may be formed so as to expose only the central region of the electrode pad 62. That is, the passivation layer 70 can be formed so as to cover the peripheral edge of the electrode pad 62. The passivation layer can be formed of, for example, SiO ₂ , SiN, polyimide resin, or the like. In the semiconductor device according to the present embodiment, the electrode pad includes a region where the opening 72 is provided and is wider than the wiring portion.

  In the semiconductor device according to the present embodiment, bumps 80 are provided at least in the openings 72. That is, the bump 80 is provided on the exposed surface of the electrode pad 62. In the semiconductor device according to the present embodiment, a case where the bump 80 is formed so as to reach the passivation layer 70 is illustrated. The bump 80 is formed of one layer or a plurality of layers, and can be formed of a metal such as gold, nickel, or copper. The outer shape of the bump 80 is not particularly limited, but may be a rectangle (including a square and a rectangle) or a circle. Further, the outer shape of the bump 80 may be smaller than the electrode pad 62. At this time, the bump 80 may be formed only in a region overlapping with the electrode pad 62.

  Although not shown, a barrier layer may be provided in the lowermost layer of the bump 80. The barrier layer is for preventing diffusion of both the electrode pad 62 and the bump 80. The barrier layer can be formed of one layer or a plurality of layers. The barrier layer may be formed by sputtering. Further, the barrier layer may further have a function of improving the adhesion between the electrode pad 62 and the bump 80. The barrier layer may have a titanium tungsten (TiW) layer. In the case of a plurality of layers, the outermost surface of the barrier layer may be an electroplating power supply metal layer (for example, an Au layer) on which the bumps 80 are deposited.

  Next, the element prohibited region 12 will be described. As described above, the element prohibition region 12 is the semiconductor layer 10 located outside from the vertically lower side of the end of the electrode pad 62 and is a region in a predetermined range. In the element forbidden area 12, it is prohibited to arrange an element forming area.

  The range of the element prohibited region 12 may be a range having a distance corresponding to the thickness of the passivation layer 70 from the end of the electrode pad 62 toward the outside (opposite to the opening 72). For example, it may be a range having a distance of 1.5 μm to 2.0 μm from the end of the electrode pad 62 toward the outside. The reason why the range of the element prohibited region 12 is defined in this way is as follows.

  First, the provision of the electrode pad 62 causes stress in the interlayer insulating layer 60 where the end of the electrode pad 62 is located. After that, as shown in FIG. 1, the bump 80 provided on the electrode pad 62 is provided, so that continuous stress due to the internal stress of the bump 80 is further applied. Under the influence of these stresses, cracks may occur in the interlayer insulating layers 50 and 60 from the positions where these stresses are generated (the ends of the electrode pads 62). Such cracks sometimes reach the lowermost interlayer insulating layer, and change the characteristics of the semiconductor element provided in that region. For example, if the MIS transistor is provided, the gate insulating layer and the like are deteriorated, and a leak current is generated.

  Further, the passivation layer 70 is not provided on a surface having a uniform upper surface, and a step is generated according to the shape of the electrode pad 62. At the step, as described above, for example, when COF is mounted, stress due to contact / bonding is easily concentrated when connecting to the bump 80 via a connection line (lead wire) provided on the film. This can also contribute to the generation of cracks in the interlayer insulating layers 50 and 60. This step is likely to occur at a position having a distance substantially corresponding to the thickness of the passivation layer 70 from the end of the electrode pad 62 to the outside. In consideration of the above problem, the range of the element prohibited region 12 is defined.

  In the semiconductor device according to the present embodiment, the semiconductor layer located below the electrode pad 62 is the element formation region 10A, and the element prohibition region 12 is formed in a predetermined region from the end of the electrode pad 62 to the outside. Is provided. A predetermined region from the end of the electrode pad 62 to the outside is likely to be stressed and stress is likely to occur. Therefore, cracks are likely to occur in the interlayer insulating layers 50 and 60 disposed above the element prohibited region 12. For example, when a semiconductor element such as a MOS transistor is provided in this region, the characteristics of the MOS transistor are deteriorated. It can contribute. Therefore, in the semiconductor device according to the present embodiment, the above-described problem is avoided by setting the element prohibited region 12 in the predetermined range. In addition, the semiconductor layer 10 located below the electrode pad 62 is used as an element formation region 10A, and the semiconductor element is arranged in a place where there is no problem even if the semiconductor element is provided under the electrode pad 62. In other words, according to the present embodiment, the semiconductor element is positively disposed in a place below the electrode pad and does not affect the reliability even if the semiconductor element is provided, while the reliability is impaired. By not arranging the semiconductor device in a place where it is considered that the semiconductor device can be miniaturized, it is possible to provide a semiconductor device that can be miniaturized and maintain reliability.

  Further, the conductive layer constituting the gate electrode 34 may be used as a wiring for connecting to another element, for example, the MIS transistor 40, and the part of the conductive layer used as the wiring is formed in the element prohibited region 12. May be.

2. Second Embodiment Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 4 is a cross-sectional view schematically showing the semiconductor device according to the second embodiment. The semiconductor device according to the second embodiment is an example different from the semiconductor device according to the first embodiment in that a semiconductor element is provided in the element prohibited region 12. In the following description, differences from the semiconductor device according to the first embodiment will be described.

As shown in FIG. 4, the semiconductor device according to the second embodiment includes an element formation region 10A and an element prohibition region 12 provided around the element formation region 10A. In the semiconductor device according to the present embodiment, although not shown in FIG. 4, an element formation region 10 </ b> B is further formed outside the element inhibition region 12, as in the semiconductor device according to the first embodiment. .

  In the semiconductor device according to the present embodiment, a high breakdown voltage MOS transistor is provided in the element prohibited region 12. Specifically, a MOS transistor 100 having a LOCOS offset structure is provided. The MOS transistor 100 is provided in the semiconductor layer 10, and includes an offset insulating layer 22 for electric field relaxation, a gate insulating layer 102 provided on the semiconductor layer 10, a part of the offset insulating layer 22, and a gate insulating layer. A gate electrode 104 provided on the gate electrode 102; and an impurity region 106 serving as a source region or a drain region provided in the semiconductor layer outside the gate electrode 104. Under the offset insulating layer 22, an offset impurity region 108 having the same conductivity type as the impurity region 106 and having a low impurity concentration is provided.

  In the semiconductor device according to the present embodiment, some of the components of the MOS transistor 100 are provided in the semiconductor layer 10 of the element prohibited region 12. In the MIS transistor 100, the end portion of the gate electrode 104 is provided on the offset insulating layer 22. That is, the element prohibited region 12 is not provided with a structure in which the end portion of the gate electrode 104, which is the first conductive layer, is disposed above the semiconductor layer 10 with a thin insulating layer interposed therebetween. It becomes. Here, a problem when it is assumed that the MIS transistor 30 having the structure provided in the element region is provided in the element prohibited region 12 will be described. Unlike the MIS transistor 100, the MIS transistor 30 has a structure in which the end of the gate electrode 34 is provided on the semiconductor layer 10. Therefore, stress is likely to occur in the semiconductor layer 10 where the end of the gate electrode 34 is located. As described in the first embodiment, cracks are likely to occur in the interlayer insulating layers 50 and 60 above the element prohibited region 12, and film deterioration is likely to occur. This influence and deterioration of the gate insulating layer 32 may be caused to the end of the gate electrode 34 where the stress is generated. A leak current may flow in the MIS transistor 30.

  However, according to the semiconductor device of the second embodiment, since the end portion of the gate electrode 104 is disposed on the offset insulating layer 22 in the element prohibited region 12, the stress as described above is applied to the semiconductor. Deterioration of the gate insulating layer 102 can be suppressed without being generated in the layer 10. Therefore, not only the element formation region 10A provided under the electrode pad 62 but also a semiconductor element having a predetermined structure can be disposed in the element prohibition region 12, and further miniaturization of the semiconductor chip can be achieved. Will be able to. This can increase the number of semiconductor chips obtained from one semiconductor wafer, and can also reduce the manufacturing cost.

  Although FIG. 4 illustrates the case where the MOS transistor 100 is provided in the element prohibited region 12, the present invention is not limited to this, and includes a case where a part of the configuration of the MOS transistor 100 is included. . In that case, a MOS transistor having a one-side offset structure may be used.

3. Modified Example Next, a modified example of the semiconductor device according to the first embodiment and the second embodiment will be described with reference to FIG. The present modification is characterized in that the shape of the bump 80 is a rectangular shape having a short side and a long side, and FIG. 5 schematically shows the positional relationship among the bump 80, the electrode pad 62, and the element prohibited region 12. It is a top view. In the following description, only differences from the semiconductor device according to the first embodiment and the second embodiment will be described.

  In the semiconductor device according to this modification, as shown in FIGS. 1 and 4, the bumps 80 are provided in the openings 72 on the electrode pads 62. In this modification, the electrode pad 62 has a rectangular shape. An opening 72 is provided in part on the upper surface of the electrode pad 62, and a bump 80 is provided in the opening 72. The bump 80 has a pattern smaller than that of the electrode pad 62, and is preferably provided inside the electrode pad 62 when viewed in plan as shown in FIG. In the present modification, the element prohibited region 12 is provided in a region located outside from the short side end of the electrode pad 62. According to this aspect, for example, when mounting by the TAB technique, when the extending direction of the connecting wire (lead wire) 13 provided on the film made of polyimide resin or the like is the direction along the long side of the electrode pad 62 There are the following advantages. In this case, the electrode pad 62 is pulled in the extending direction of the connection line, and stress is particularly applied to the short side of the electrode pad 62. Therefore, as described above, at the end of the short side of the electrode pad 62, the problem that cracks occur particularly in the interlayer insulating layers 50 and 60 easily occurs. In this modification, by providing the element prohibition region 12 on the short side of the electrode pad 62, it is possible to reliably prohibit the semiconductor element from being provided in a place where reliability is lowered. Further, since the element prohibition region 12 is not provided in the semiconductor layer below the long side of the electrode pad 62, a semiconductor element can be provided in the semiconductor layer below the long side of the electrode pad 62, and miniaturization is facilitated. The provided semiconductor device can be provided.

  In particular, as shown in FIG. 6, a semiconductor chip 200 that is miniaturized may require a structure in which a large number of openings 72 are provided by making the shapes of the openings 72 and the bumps 80 rectangular. In this modification, even in the semiconductor device having the rectangular electrode pad 62 (bump 80) as described above, the element forbidden region 12 is provided in an appropriate region, so that miniaturization and improvement in reliability can be achieved. A semiconductor device can be provided.

  In the above-described embodiment, the case where the two-layer interlayer insulating layers 50 and 60 are provided and the one-layer wiring layer 52 is provided between them is illustrated, but the present invention is not limited to this. It may have a structure in which more than one interlayer insulating layer is stacked and a plurality of wiring layers corresponding to the number of interlayer insulating layers are provided.

  The present invention is not limited to the above-described embodiments, and various modifications can be made. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same purposes and results). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

DESCRIPTION OF SYMBOLS 10 ... Semiconductor layer, 10A, 10B ... Element formation area, 12 ... Element prohibition area | region, 20 ... Element isolation insulation layer, 22 ... Offset insulation layer, 30, 40 ... MIS transistor, 32, 42 ... Gate insulation layer, 34, 44 DESCRIPTION OF SYMBOLS ... Gate electrode 36, 46 ... Impurity region 50 ... Interlayer insulation layer 52 ... Wiring layer 60 ... Interlayer insulation layer 62 ... Electrode pad 62 ... Electrode pad 70 ... Passivation layer 72 ... Opening 80 ... Bump 100 MIS transistor 102 Gate insulating layer 104 Gate electrode 106 Impurity region 108 Offset impurity region

Claims (6)

A semiconductor layer having a first region, an element isolation region provided around the first region, and a second region provided around the element isolation region;
A first element formed in the first region;
A second element formed in the second region;
An interlayer insulating layer provided above the semiconductor layer;
The electrode pad provided above the interlayer insulating layer and at least partially overlapping with the first element in plan view,
The second region is located in a predetermined range outside vertically from the end of the electrode pad,
The first element includes a first transistor;
The second element includes a second transistor,
The second transistor includes a gate electrode and an offset insulating layer,
An end of the gate electrode of the second transistor is located above the offset insulating layer ,
The first transistor includes a gate electrode and does not include an offset insulating layer . In claim 1,
The second region is a semiconductor device having a distance of 1.0 μm to 2.5 μm from the vertically lower side to the outer side of the end of the electrode pad. In claim 1,
A passivation layer above the electrode pad and having an opening exposing at least a portion of the electrode pad;
The second region is a semiconductor device having a distance corresponding to the thickness of the passivation layer from the vertically lower side to the outer side of the end of the electrode pad. In claim 3,
A semiconductor device including a bump provided in the opening. In any of claims 1 to 4,
The semiconductor device, wherein the offset insulating layer is LOCOS. In any of claims 1 to 5,
The semiconductor device, wherein the first region is located below the electrode pad.