JP2008108404A - Integrated semiconductor circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an integrated semiconductor circuit which can reduce the power consumption even when using transistors connecting memory cells and sense amplifiers. <P>SOLUTION: The operation of the control signal A is stopped when column operations are not needed in the integrated semiconductor circuit operating the control signal A of the transistors connecting memory cells and sense amplifiers during access. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a transistor for connecting a memory cell and a sense amplifier.

  A semiconductor integrated circuit device having a transistor for connecting a memory cell and a sense amplifier is described in, for example, Patent Document 1.

  This transistor is called a transfer gate or a fight (φt) gate. The φt gate is turned off when a minute potential difference (cell data) between the bit line pair is differentially amplified by the sense amplifier. As a result, the amplification node pair of the sense amplifier is disconnected from the bit line pair, the capacitance of the amplification node of the sense amplifier is reduced, and the differential amplification can be speeded up.

  The control signal for controlling the φt gate changes, for example, as follows during access of the semiconductor integrated circuit device.

<Amplified cell data transfer: Data refresh or data restore>
High potential (potential V1)
<Differential amplification of cell data: Data sense>
Low potential (potential V3)
<When cell data is transferred: Data read>
An intermediate potential between the high potential and the low potential (potential V2)
The order of operations is, for example, as follows.

  The control signal is set to an intermediate potential V2, and a minute potential difference read from the memory cell to the bit line pair is transferred from the bit line pair to the amplification node pair via the transistor pair (data read).

  Next, the control signal is set to the low potential V3, and the amplification node pair and the bit line pair are blocked by the transistor pair. In the blocked state, the minute potential difference transferred to the amplification node pair by the sense amplifier is differentially amplified (data sense).

  Next, the control signal is set to the high potential V1, the data amplified by the sense amplifier is transferred from the amplification node pair to the bit line pair through the transistor pair, and the data is written to the memory cell selected by the word line, or the data Write back.

The control signal for controlling the φt gate constantly repeats the above potential change during the access of the semiconductor integrated circuit device. For this reason, a semiconductor integrated circuit device having a φt gate consumes a large amount of current, which prevents a reduction in power consumption.
JP2000-11654

  The present invention provides a semiconductor integrated circuit device that can promote low power consumption while having a transistor that connects a memory cell and a sense amplifier.

  The semiconductor integrated circuit device according to the first aspect of the present invention is a semiconductor integrated circuit device that operates a control signal of a transistor that connects a memory cell and a sense amplifier during an access, and does not require a column operation. The operation of the control signal is stopped.

  A semiconductor integrated circuit device according to a second aspect of the present invention includes a memory cell array in which memory cells are integrated, a bit line pair connected to the memory cell, a sense amplifier, and an amplification node pair connected to the sense amplifier. A transistor pair that connects the bit line pair and the amplification node pair, and a control circuit that generates a control signal for controlling the transistor pair, and the control circuit outputs the control signal during column operation. Clocking is performed, and the control signal is not clocked during an operation other than the column operation.

  A semiconductor integrated circuit device according to a third aspect of the present invention includes a memory cell array in which memory cells are integrated, a bit line pair connected to the memory cell, a sense amplifier, and an amplification node pair connected to the sense amplifier. A transistor pair for connecting the bit line pair and the amplification node pair, a control signal for controlling the transistor pair, a signal for enabling / disabling the control circuit, and controlling the potential of the control signal to a high potential And a control circuit that generates a signal based on the logic of a signal that controls the potential of the control signal to a low potential, a signal that controls the potential of the control signal to a low potential, a signal that instructs column operation, and a column And a signal generation circuit that generates based on the logic of a signal that instructs an operation other than the operation.

  The present invention can provide a semiconductor integrated circuit device that can promote low power consumption while having a transistor for connecting a memory cell and a sense amplifier.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings.

  In one embodiment, a semiconductor integrated circuit device having a dynamic type semiconductor memory cell, for example, a DRAM or a pseudo SRAM is shown as an example of a semiconductor integrated circuit device having a transistor connecting a memory cell and a sense amplifier. The present invention is not limited to a semiconductor integrated circuit device having a dynamic semiconductor memory cell, but can be applied to any semiconductor integrated circuit device having a transistor for connecting a memory cell and a sense amplifier. It is.

  FIG. 1 is a block diagram showing a configuration example of a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 2 is a block diagram showing a configuration example of the periphery of the memory cell array 1 and the sense amplifier 2 shown in FIG. .

  As shown in FIGS. 1 and 2, a semiconductor integrated circuit device according to an embodiment includes a memory cell array in which memory cells 1 are integrated, a pair of bit lines B and / B connected to the memory cells 1, and a sense amplifier. 2, an amplification node pair C and / C connected to the sense amplifier 2, a transistor pair 3 connecting the bit line pair B and / B and the amplification node pair C and / C, and a control for controlling the transistor pair 3 And a control circuit 4 for generating the signal A.

  Further, as shown in FIG. 1, the sense amplifier of the semiconductor integrated circuit device according to one embodiment is a so-called shared sense amplifier that is shared between the adjacent memory cell arrays. An example of a semiconductor integrated circuit device having a shared sense amplifier is shown in FIG. 3A.

  As shown in FIG. 3A, a semiconductor integrated circuit device having a shared sense amplifier includes a first memory cell array (L1 or L2) in which first memory cells (1L) are integrated, and a second memory cell ( 1R) integrated second memory cell array (R1), first bit line pair (BL, / BL) connected to first memory cell (1L), and second memory cell (1R) Amplifying node connected to second bit line pair (BR, / BR) connected to, sense amplifier (2-1, 2-2), and sense amplifier (2-1, 2-2) The first pair that connects the pair (C1, / C1, or C2, / C2), the first bit line pair (BL, / BL), and the amplification node pair (C1, / C1, or C2, / C2) Transistor pair (3L1 or 3L2), second bit line pair (BR, / BR) and amplification node (C1, / C1, or C2, / C2) connecting the second transistor pair (3R1, or 3R2) and the first control signal (AL1) for controlling the first transistor pair (3L1, or 3L2) Or AL2) and a control circuit (4-1 or 4-2) for generating a second control signal (AR1 or AR2) for controlling the second transistor pair (3R1 or 3R2). .

  A semiconductor integrated circuit device having a shared sense amplifier has a first control signal (for example, AL1) or a left memory cell array (for example, L1) and a right memory cell array (for example, R1) that is not accessed. The second control signal (for example, AR1) is used to disconnect from the shared amplification node pair C1, / C1. The accessed person uses the first control signal (for example, AL1) or the second control signal (for example, AR1) to control the same as the semiconductor integrated circuit device shown in FIG. Is done.

  The embodiment is not limited to a semiconductor integrated circuit device having a shared sense amplifier.

  FIG. 3B shows an example of a sense amplifier, and FIG. 3C shows an example of a memory cell.

  As shown in FIG. 3B, an example of the sense amplifier is a differential amplifier circuit that differentially amplifies the potential difference between the amplification node C and the amplification node / C. The differential amplifier circuit of this example is a latch circuit connected between the amplification node C and the amplification node / C. As the shared sense amplifier, the sense amplifier shown in FIG. 3B is used.

  As shown in FIG. 3C, an example of the memory cell is a dynamic memory cell. A switching transistor in which the gate is connected to the word line and one end of the current path is connected to the bit line B (or / B), one electrode is connected to the other end of the current path of the switching transistor, and the other electrode is grounded. And a capacitor receiving a potential VPL intermediate between the power supply potential.

  The control circuit 4 of the semiconductor integrated circuit device according to the embodiment causes the control signal A to be clocked during the column operation, and does not cause the control signal A to be clocked during an operation other than the column operation.

  Clocking means that when a minute potential difference between the bit line pair B and / B is differentially amplified by the sense amplifier 2, the amplification node pair C and / C is changed from the bit line pair B and / B to the transistor pair 3. It is the action of detaching.

  In this example, the column operation time indicates an operation time including a data read operation from the memory cell 1 and a data write operation to the memory cell 1. In the present example, the operation other than the column operation indicates an operation including at least one of a data refresh operation and a configuration mode setting operation. The data refresh operation is an operation of refreshing data every refresh cycle when the memory cell 1 is a volatile semiconductor memory cell, for example, a dynamic memory cell. The configuration mode setting operation refers to, for example, transferring chip-specific information recorded in a ROM in a chip or a rewritable ROM, such as redundancy information of the chip, to a register (redundancy information set register). This is the operation to set. The configuration mode setting operation is executed immediately after the power is turned on, for example.

  As shown in FIG. 2, the control circuit 4 is a signal for enabling / disabling the control circuit 4 (hereinafter referred to as an enable signal E) and a signal for controlling the potential of the control signal A to a high potential (V1) (hereinafter referred to as V1). Based on the logic of the signal F) and the signal for controlling the potential of the control signal A to the low potential (V3) (hereinafter referred to as V3 signal D), the potential of the control signal A is set to the high potential V1, the low potential V3, or the high potential. The potential is controlled to any one of potential V2 that is intermediate to the low potential.

  The high potential V1 is a potential at which data amplified by the sense amplifier 2 can be transferred from the amplification node pair C, / C to the bit line pair B, / B via the transistor pair 3. An example of the voltage is 3.2V.

  The intermediate potential V2 is a potential at which a minute potential difference appearing between the bit line pair B and / B can be transferred from the bit line pair B and / B to the amplification node pair C and / C via the transistor pair 3. An example of the voltage is 2.3V.

  The low potential V3 is a potential at which the transistor pair 3 can cut off the amplifier node pair C, / C and the bit line pair B, / B when the potential of the amplifier node pair C, / C is amplified by the sense amplifier 2. It is. An example of the voltage is 0.7V.

  Further, the V3 signal D is generated based on the logic of a signal instructing a column operation and a signal instructing an operation other than the column operation in this example. For this purpose, this example includes a signal generation circuit 5 that generates the V3 signal D based on the logic of these signals. The signal instructing the column operation is “G (hereinafter, column operation signal G)” in this example, and the signals instructing operations other than the column operation are “H” and “I” in this example. The signal H is a signal instructing a data refresh operation (hereinafter referred to as a refresh operation signal H) in this example, and the signal I is a signal instructing a configuration mode setting operation (hereinafter referred to as a configuration mode setting signal I in this example). ). The signal generation circuit 5 of this example generates the V3 signal D based on the logic of the column operation signal G, the refresh operation signal H, and the configuration mode setting signal I.

  Hereinafter, specific circuit examples of the control circuit 4 and the signal generation circuit 5 will be described.

  FIG. 4 is a circuit diagram showing a circuit example of the control circuit 4.

  As shown in FIG. 4, the control circuit 4 according to one circuit example includes an enable / disable circuit 31, a high potential V1 supply circuit 32, an intermediate voltage V2 supply circuit 33, a low voltage V3 supply circuit 34, including.

  The enable / disable circuit 31 of this example determines whether to enable or disable the control circuit 4 according to the enable signal E. Further, the enable / disable circuit 31 of this example supplies the in-circuit ground potential Vss to the output of the control circuit 4 when the control circuit 4 is disabled.

  The high potential V1 supply circuit 32 of this example has a high potential V1 output to the output of the control circuit 4 when the enable / disable circuit 31 enables the control circuit 4 and the V1 signal F is at the high potential V1. Supply.

  In the intermediate potential V2 supply circuit 33 of this example, the enable / disable circuit 31 enables the control circuit 4, the V1 signal F does not become the high potential V1, and the V3 signal D does not become the low potential V3. At some time, an intermediate voltage V 2 is supplied to the output of the control circuit 4.

  The low potential V3 supply circuit 34 of the present example is in a state where the enable / disable circuit 31 enables the control circuit 4, the V1 signal F is not set to the high potential V1, and the V3 signal D is set to the low potential V3. At some time, the low voltage V3 is supplied to the output of the control circuit 4.

  An example of a specific circuit configuration will be described together with its operation.

(Enable / Disable circuit 31)
The enable / disable circuit 31 includes an inverter 101 that receives an enable signal E, an inverter 102 that receives the output of the inverter 101, and an N-channel insulated gate transistor (hereinafter, NMOS) that receives the output of the inverter 102 at the gate. 103. The source of the NMOS 103 is connected to the in-circuit ground potential Vss, and its drain is connected to the output of the control circuit 4.

  In this example, the logic of the enable signal E is “High” level = disabled state and “Low” level = enabled state.

  While the enable signal E is at the “High” level, the output of the “High” level is supplied from the inverter 102 to the gate of the NMOS 103, and the NMOS 103 is turned on. As a result of the NMOS 103 being turned on, the output of the control circuit 4 is supplied with the in-circuit ground potential Vss.

  On the contrary, while the enable signal E is at the “Low” level, the output of the “Low” level is supplied from the inverter 102 to the gate of the NMOS 103, so that the NMOS 103 is turned off.

  The enable / disable circuit 31 includes an NMOS 104 that receives an enable signal E at its gate, and a P-channel insulated gate transistor (hereinafter referred to as PMOS) 105. The source of the NMOS 104 is connected to the in-circuit ground potential Vss, and the drain thereof is connected to the drain of the PMOS 105 and to the control output 106 of the enable / disable circuit 31. Further, the enable / disable circuit 31 has an NMOS 107 that receives the output of the inverter 101 at its gate. The source of the NMOS 107 is connected to the control output 106. That is, the NMOS 107 constitutes a CMOS type transfer gate 108 together with the PMOS 105. The transfer gate 108 connects the output of the inverter 109 in the V1 supply circuit 32 and the control output 106 of the enable / disable circuit 31.

  While the enable signal E is at the “High” level, the transfer gate 108 (PMOS 105 and NMOS 107) is turned off and the NMOS 104 is turned on. As a result, the control output 106 is supplied with the in-circuit ground potential Vss.

  Conversely, while the enable signal E is at the “Low” level, the transfer gate 108 is turned on and the NMOS 104 is turned on. As a result, the control output 106 is connected to the output of the inverter 109 in the V1 supply circuit 32, and the output of the inverter 109 is supplied to the control output 106.

  As described above, the enable / disable circuit 31 supplies the in-circuit ground potential Vss to the output of the control circuit 4 while the control circuit 4 is in the “disabled state” in accordance with the enable signal E, and the output (control signal) of the control circuit 4. In this example, A) is set to the Vss level. At the same time, the logic level of the control output 106 is set to “Low” level in this example, and the V2 supply circuit 33 and the V3 supply circuit 34 are disabled.

  On the contrary, the enable / disable circuit 31 supplies the output of the control circuit 4 (control signal A) to the V1 supply circuit 32 or V2 in this example while the control circuit 4 is in the “enable state” according to the enable signal E. The level supplied from either the circuit 33 or the V3 supply circuit 34 can be set. At the same time, the logic level of the control output 106 can be set according to the logic level of the V1 signal F, and the V2 supply circuit 33 and the V3 supply circuit 34 can be disabled or enabled according to the V1 signal F. And

(High potential V1 supply circuit 32)
High potential V1 supply circuit 32 includes inverter 109 that receives V1 signal F at its input and PMOS 110 that receives the output of inverter 109 at its gate.

  While the V1 signal F is at the “Low” level, the output of the inverter 109 is at the “High” level, and the PMOS 110 is turned off. At the same time, one end of the current path of the transfer gate 108 is set to the “High” level. If the transfer gate 108 is on, the "High" level output from the inverter 109 is transferred to the control output 106 of the enable / disable circuit 31, and the V2 supply circuit 33 and the V3 supply circuit 34 are enabled. .

  Conversely, while the V1 signal F is at the “High” level, the output of the inverter 109 is at the “Low” level, so that the PMOS 110 is turned on and the high potential V1 is supplied to the output of the control circuit 4. As a result, the output (control signal A) of the control circuit 4 becomes the high potential V1. At the same time, one end of the current path of the transfer gate 108 becomes “Low” level. Therefore, if the transfer gate 108 is turned on, the control output 106 of the enable / disable circuit 31 becomes “Low” level, and the V2 supply circuit 33 and the V3 supply circuit 34 are in a disabled state.

(Intermediate potential V2 supply circuit 33)
The intermediate potential V2 supply circuit 33 receives the V3 signal D at the first input, the two-input NAND gate circuit 111 that receives the potential of the control output 106 at the second input, and the PMOS 112 that receives the output of the NAND gate circuit 111 at the gate. And have.

  Whether the V2 supply circuit 33 is enabled or disabled is determined according to the potential of the control output 106 of the enable / disable circuit 31. In this example, as an example, the control output 106 is enabled when the potential of the control output 106 is “High” level, and is disabled when the potential of the control output 106 is “Low”.

  During the disabled state, the V2 supply circuit 33 does not supply the intermediate potential V2 to the output of the control circuit 4 regardless of the logic level of the V3 signal D.

  On the contrary, the V2 supply circuit 33 supplies the intermediate potential V2 to the output of the control circuit 4 according to the logic level of the V3 signal D during the enable state. In this example, since the output of the NAND gate circuit 111 is at the “Low” level while the V3 signal D is in the enable state and the V3 signal D is at the “High” level, the PMOS 112 is turned on and the output of the control circuit 4 has an intermediate potential V2 Is supplied. As a result, the output (control signal A) of the control circuit 4 becomes an intermediate potential V2.

(Low potential V3 supply circuit 34)
The low potential V3 supply circuit 34 receives the V3 signal D at the first input, receives the potential obtained by inverting the potential of the control output 106 at the second input, and outputs the NOR gate circuit 113. NMOS 114 received at the gate.

  Similar to the V2 supply circuit 32, the V3 supply circuit 34 is determined to be enabled or disabled according to the potential of the control output 106 of the enable / disable circuit 31. In this example, as an example, the control output 106 is enabled when the potential of the control output 106 is “High” level, and is disabled when the potential of the control output 106 is “Low”.

  During the disabled state, the V3 supply circuit 34 does not supply the low potential V3 to the output of the control circuit 4 regardless of the logic level of the V3 signal D.

  On the contrary, the V3 supply circuit 34 supplies the low potential V3 to the output of the control circuit 4 according to the logic level of the V3 signal D during the enable state. In this example, since the output of the NOR gate circuit 113 is at the “High” level while the V3 signal D is in the enable state and the V3 signal D is at the “Low” level, the NMOS 114 is turned on and the low potential V3 is applied to the output of the control circuit 4. Supplied. As a result, the output of the control circuit 4 (control signal A) becomes the low potential V3.

  FIG. 5A is a circuit diagram showing one circuit example of the signal generation circuit 5.

  As shown in FIG. 5A, the signal generation circuit 5 according to one circuit example basically has a V3 signal D and a control signal A at a low potential V3 when the column operation signal G indicates a column operation. It is a circuit to generate. However, in this example, a function for forcibly controlling the V3 signal D is added to such a signal generation circuit 5 so that the column operation signal G does not become the low potential V3 even if the column operation signal G instructs the column operation. Yes.

  Therefore, in this example, a V3 suppression signal generation circuit 41 that generates a V3 suppression signal J is provided. When the V3 suppression signal J indicates V3 suppression, even if the column operation signal G indicates column operation, the logic level of the V3 signal D is forcibly controlled to a logic level that is not the low potential V3. The In this example, the V3 suppression signal J is generated based on the refresh operation signal H and the configuration mode setting signal G. Further, in this example, the suppression signal J instructs the V3 suppression while at least one of the refresh operation and the configuration mode setting operation is instructed.

  As an example of a specific circuit, the V3 suppression signal generation circuit 41 includes a two-input type NOR gate circuit 200 that receives a refresh operation signal H at a first input and a configuration mode setting signal I at a second input. The NOR gate circuit 200 outputs a V3 suppression signal J. Specifically, the V3 suppression signal generation circuit 41 sets the V3 suppression signal J to the “Low” level while at least one of the refresh operation signal H and the configuration mode setting signal G is at the “High” level. In this example, while the V3 suppression signal J is at the “Low” level, the logic level of the V3 signal D is forcibly controlled to a logic level that is not the low potential V3.

  The signal generation circuit 5 receives the column operation signal G at the first input and receives the V3 suppression signal J at the second input, and the inverter 202 receives the output of the NAND gate circuit 201 at the input. And a level shifter 203 that receives the output of the inverter 202 as an input. The level shifter 203 outputs a V3 signal D with the “High” level potential set to the high potential V1. The level shifter of this example is an inverting type level shifter as shown in FIG. 5B, for example, and the logic is the same as that of the inverter.

  The NAND gate circuit 201 inverts and outputs the logic level of the column operation signal G while the V3 suppression signal J is at the “High” level. Therefore, the V3 signal D changes according to the logic level of the column operation signal G. On the contrary, while the V3 suppression signal J is at the “Low” level, the NAND gate circuit 201 fixes the output logic level to the “High” level regardless of the logic level of the column operation signal G. Accordingly, the V3 signal D is fixed to the “High” level regardless of the logical level of the column operation signal G. For this reason, the logic level of the V3 signal D is forcibly controlled to a logic level not set to the low potential V3.

  Next, an example of a specific operation will be described.

(During column operation)
FIG. 6 is an operation waveform diagram showing an operation example in the column operation of the semiconductor integrated circuit device according to one embodiment of the present invention.

  This operation is, for example, a data read operation.

  As shown in FIG. 6, first, in the initial state, each signal is at the following level.

Refresh signal H = "Low"
Configuration mode setting signal I = "Low"
Enable / disable signal E = "High"
Column operation signal G = "Low"
V3 signal D = "High"
V1 signal F = "Low"
In this state, since the enable / disable signal E = “High”, the NMOS 103 is turned on and the potential of the control signal A becomes Vss.

  Thereafter, at time t1, the enable / disable signal E changes from the “High” level to the “Low” level. The control circuit 4 changes from the disabled state to the enabled state. Since the V3 signal is at the “High” level and the V1 signal F is at the “Low” level, the two inputs of the NAND gate circuit 111 of the V2 supply circuit 33 are both at the “High” level, and the PMOS 112 is turned on and the control signal A Becomes an intermediate potential V2.

  In this state, since the bit line pair B, / B and the amplification node pair C, / C are connected via the transistor pair 3, the minute potential difference (cell data) read from the memory cell 1 is a bit. Transfer is performed from the line pair B, / B to the amplification node pair C, / C.

  Next, the column operation signal G changes from the “Low” level to the “High” level, and in response to this, the V3 signal D changes from the “High” level to the “Low” level. At time t2, the two inputs of the NOR gate circuit 113 of the V3 supply circuit 34 are both at the “Low” level, the NMOS 114 is turned on, and the potential of the control signal A becomes the low potential V3.

  In this state, the bit line pair B and / B and the amplification node pair C and / C are in a state of being cut off by the transistor pair 3, so that the sense amplifier 2 has a small potential difference between the amplification node pair C and / C. Amplify differentially. At the time of data read, the capacity of the bit line pair B and / B is separated from the capacity of the amplification node pair C and / C, so that the capacity of the differentially amplified portion is reduced and the differential amplification is performed at high speed. . For this reason, at the time of data reading, data that is differentially amplified at high speed, that is, data that appears as a potential difference at the amplification node pair C, / C is not shown through a column gate and a data line (not shown). Transferred to the circuit. For this reason, the data read operation from the memory cell to the I / O circuit is fast.

  Next, the V1 signal F changes from the “Low” level to the “High” level, the V2 supply circuit 33 and the V3 supply circuit 34 are disabled, the PMOS 110 is turned on, and the potential of the control signal A becomes the high potential V1. Become.

  In this state, since the bit line pair B, / B and the amplification node pair C, / C are reconnected via the transistor pair 3, the sense amplifier 2 is connected to the bit line pair B from the amplification node pair C, / C. , / B is amplified. Thereafter, the read cell data is written back to the read-out memory cell (data restore).

  In the present specification, as described above, the operation of lowering the potential of the control signal A from the intermediate potential V2 to the low potential V3 and further increasing the potential from the low potential V3 to the high potential V1 causes the control signal A to be clocked. It is called.

(Except during column operation)
FIG. 7 is an operation waveform diagram showing an operation example other than the column operation of the semiconductor integrated circuit device according to one embodiment of the present invention.

  For example, this operation is a data refresh operation.

  As shown in FIG. 7, the difference between the initial state and the column operation is that the refresh signal H is at the “High” level and the data refresh operation is instructed. The rest is the same as in the column operation (data read operation).

  Even when the configuration mode setting signal I is set to the “High” level, the same operation as described below is performed.

  The flow from time t1 to time t3 is also substantially the same as in the column operation (data read operation), but is different in that the control signal A is not clocked.

  During the column operation (data read operation), the column operation signal G changes from the “Low” level to the “High” level, and in response to this, the V3 signal D changes from the “High” level to the “Low” level. However, since the refresh signal H is at the “H” level except during the column operation (during the data refresh operation), the signal generation circuit 5 fixes the V3 signal D at the “High” level. For this reason, the V3 supply circuit 34 does not set the control signal A to the low potential V3, and the V2 supply circuit 33 continues to maintain the state in which the control signal A is set to the intermediate potential V2.

  In this state, since the bit line pair B, / B remains connected by the amplification node pair C and / C by the transistor pair 3, the sense amplifier 2 is connected to the bit line pair B, / C from the amplification node pair C, / C. The minute potential difference up to B is differentially amplified. During the data refresh operation, it is not necessary to transfer data that appears as a potential difference between the amplification node pair C and / C to the outside of the column gate (not shown). Therefore, during the data refresh operation, the minute potential difference between the amplification node pair C and / C may not be differentially amplified at high speed.

  Next, the V1 signal F changes from the “Low” level to the “High” level, the V2 supply circuit 33 and the V3 supply circuit 34 are disabled, the PMOS 110 is turned on, and the potential of the control signal A becomes the high potential V1. Become.

  In this state, since the bit line pair B, / B and the amplification node pair C, / C are reconnected via the transistor pair 3, the sense amplifier 2 is connected to the bit line pair B from the amplification node pair C, / C. , / B is amplified. Thereafter, the read cell data is written back to the read-out memory cell (data refresh).

  The capacity of the bit line pair B, / B is much larger than the capacity of the amplification node pair C, / C. For this reason, even if it is considered that the total capacity of the capacity of the bit line pair B, / B and the capacity of the amplification node pair C, / C is almost the same as the capacity of the bit line pair B, / B. There is no problem.

  That is, it can be considered that the time required for data restoration during the data read operation and the time required for data refresh during the data refresh operation are substantially the same. Therefore, the operation speed of the semiconductor integrated circuit device according to this embodiment in which the control signal A is not clocked during the data refresh operation is the same as the operation speed of the conventional semiconductor integrated circuit device in which the control signal A is clocked during the data refresh operation. Compared with nothing inferior.

  Further, when the control signal A is clocked, a large amount of current is consumed particularly when the control signal A is boosted from the low potential V1 to the high potential V3. Since the conventional semiconductor integrated circuit device has no idea that the operation of the control signal A is stopped, for example, the control signal A is not clocked, the control signal A is always clocked. For this reason, current consumption is large.

  On the other hand, in the present embodiment, the control signal A is clocked at the time of column operation, for example, at the time of data read operation, but the operation of the control signal A is not at the time of column operation, for example, at the time of data refresh operation and configuration mode setting operation. I tried to stop. In this example, the control signal A is not clocked during the data refresh operation and the configuration mode setting operation, and the boost of the control signal A is from the intermediate potential V2 to the high potential V1. Thereby, current consumption can be reduced as compared with the case where the control signal A is boosted from the low potential V1 to the high potential V3.

  In addition, in this example, since the control signal A is not always clocked, the amount of current consumption is reduced compared to the conventional semiconductor integrated circuit device in which the control signal A is always clocked.

  In addition, in the semiconductor integrated circuit device that performs the refresh operation, in light of the fact that, for example, 80% of the time may be spent at least when the power is turned on, the present embodiment is This means that power consumption is saved in 80% of the time when the power is on. For this reason, it is possible to expect a reduction in current consumption of 50% to 60% per signal line through which the control signal A flows.

  Further, as a device in one circuit example, basically, a control signal A that takes three potentials of a low potential V1, an intermediate potential V2, and a high potential V3, a V1 signal that controls the high potential V1, and a low potential V3 are used. This means that the control is based on the logic with the V3 signal to be controlled.

  That is, when the logic of the V1 signal and the V3 signal is “not set to the high potential V1” and “not set to the low potential V3”, it is set to “middle potential V2.” Thus, when the logic of the V3 signal is “set to low potential V3”, if it is forcibly changed to the logic “not set to low potential V3”, it is set to “middle potential V2”. You can get logic. As a result, it is possible to obtain an advantage that it is possible to easily obtain a circuit that does not clock the control signal A, that is, generates a state that maintains the intermediate potential V2. This leads to an advantage that an increase in the number of elements of the control circuit 4 can be suppressed.

  Further, when the logic of the V3 signal is “set to low potential V3”, forcibly changing the logic to “not set to low potential V3”, the state of “not set to low potential V3” is set. There is an advantage that there is a degree of freedom when choosing. For example, in the present embodiment, the control signal A is controlled so as not to be clocked during the data refresh operation and the configuration operation. For example, the V3 suppression signal generation circuit 41 shown in FIG. If a signal instructing another operation is added in addition to I, it is possible to prevent the control signal A from being clocked even in another operation instructed by this signal. Furthermore, it is possible to remove one of the signals H and I. In addition, it is not necessary to change the control circuit 4 in such a change.

  As described above, according to the semiconductor integrated circuit device according to the embodiment, the control signal A for controlling the transistor pair 3 is stopped during the operation other than the column operation, for example, the control signal A is not clocked. Current consumption during access of the integrated circuit device can be reduced.

  As a result, the semiconductor integrated circuit device according to the embodiment can promote low power consumption while having a transistor connecting the memory cell and the sense amplifier.

  Further, the semiconductor integrated circuit device according to the embodiment does not stop the control signal A during the column operation, for example, the control signal A is clocked, which hinders speeding up of differential amplification in the amplification node pair. There is no.

  As described above, since the speeding up of the differential amplification is not hindered in order to reduce the power consumption, the effect of promoting the low power consumption can be obtained while maintaining the high speed operation.

  A semiconductor integrated circuit device having a memory cell with high-speed operation and low power consumption can be used as long as it is an electronic device, but is optimal as a memory for an electronic device that can be operated by a battery, for example, a portable electronic device. is there. Examples of portable electronic devices include personal computers, personal digital assistants (PDAs), digital cameras (still cameras, movie cameras, still / movie cameras), mobile phones, portable music players, portable game devices, electronic books, etc. Can do.

  The semiconductor integrated circuit device according to the one embodiment further includes the following aspects.

(1) a memory cell array in which memory cells are integrated;
A pair of bit lines connected to the memory cell;
A sense amplifier,
An amplification node pair connected to the sense amplifier;
A transistor pair connecting the bit line pair and the amplification node pair;
A control circuit for generating a control signal for controlling the transistor pair,
The semiconductor integrated circuit device, wherein the control circuit clocks the control signal during a column operation and does not clock the control signal during an operation other than the column operation.

(2) In the semiconductor integrated circuit device according to the aspect of (1),
The clocking is an operation of separating the amplification node pair from the bit line pair using the transistor pair when a minute potential difference between the bit line pair is differentially amplified by the sense amplifier.

(3) In the semiconductor integrated circuit device according to any one of (1) and (2),
The column operation includes a data read operation from the memory cell and a data write operation to the memory cell,
The operation other than the column operation includes a data refresh operation and a configuration mode setting operation.

(4) In the semiconductor integrated circuit device according to the aspect of (3),
The control circuit includes:
A signal to enable / disable this control circuit,
Based on the logic of the signal for controlling the potential of the control signal to a high potential (V1) and the signal for controlling the potential of the control signal to a low potential (V3), the potential of the control signal is changed to the high potential (V1). ), The low potential (V3) and an intermediate potential (V2) between the high potential and the low potential,
The signal for controlling the potential of the control signal to a low potential (V3) includes a signal for instructing the data read operation and the data write operation, a signal for instructing the data refresh operation, and a signal for instructing the configuration mode setting operation Generate based on the logic.

(5) In the semiconductor integrated circuit device according to the aspect of (4),
The high potential (V1) is a potential at which data amplified by the sense amplifier can be transferred from the amplification node pair to the bit line pair via the transistor pair.
The intermediate potential (V2) is a potential at which a minute potential difference appearing between the bit line pair can be transferred from the bit line pair to the amplification node pair via the transistor pair.
The low potential (V3) is a potential at which the amplification node pair and the bit line pair can be blocked by the transistor pair when the potential of the amplification node pair is amplified by the sense amplifier.

(6) In the semiconductor integrated circuit device according to any one of (4) and (5),
The control circuit includes:
An enable / disable circuit that determines whether to enable or disable the control circuit according to a signal that enables / disables the control circuit;
When the enable / disable circuit is in the enabled state and the signal for controlling the potential of the control signal to the high potential (V1) is the high potential, the output of the control circuit has the high potential (V1). ) For supplying a high potential (V1),
The enable / disable circuit is enabled, the signal for controlling the potential of the control signal to the high potential (V1) is not set to the high potential, and the potential of the control signal is controlled to the low potential (V3). An intermediate voltage (V2) supply circuit that supplies the intermediate voltage (V2) to the output of the control circuit when the signal to be output is not in the low potential state;
The enable / disable circuit is enabled, the signal for controlling the potential of the control signal to the high potential (V1) is not set to the high potential, and the potential of the control signal is controlled to the low potential (V3). A low voltage (V3) supply circuit that supplies the low voltage (V3) to the output of the control circuit when the signal to be output is in the state of the low potential.

(7) In the semiconductor integrated circuit device according to the aspect of (6),
The enable / disable circuit supplies an in-circuit ground potential to the output of the control circuit when in the disabled state.

(8) In the semiconductor integrated circuit device according to any one of (4) to (7),
Based on the logic of the signal instructing the data read operation and the data write operation, the signal instructing the data refresh operation, and the signal instructing the configuration mode setting operation, the potential of the control signal is set to a low potential (V3). A signal generation circuit for generating a signal to be controlled.

(9) a memory cell array in which memory cells are integrated;
A pair of bit lines connected to the memory cell;
A sense amplifier,
An amplification node pair connected to the sense amplifier;
A transistor pair connecting the bit line pair and the amplification node pair;
A control signal for controlling the transistor pair includes a signal for enabling / disabling the control circuit, a signal for controlling the potential of the control signal to a high potential (V1), and a potential of the control signal to a low potential (V3). A control circuit that is generated based on the logic of the signal to be controlled;
A semiconductor integrated circuit comprising: a signal generation circuit that generates a signal for controlling the potential of the control signal to a low potential (V3) based on a logic of a signal for instructing a column operation and a signal for instructing an operation other than the column operation; Circuit device.

(10) In the semiconductor integrated circuit device according to the aspect of (9),
The control circuit clocks the control signal during the column operation and does not clock the control signal during an operation other than the column operation.

(11) In the semiconductor integrated circuit device according to the aspect of (10),
The clocking is an operation of separating the amplification node pair from the bit line pair using the transistor pair when a minute potential difference between the bit line pair is differentially amplified by the sense amplifier.

(12) In the semiconductor integrated circuit device according to any one of (9) to (11),
The column operation includes a data read operation from the memory cell and a data write operation to the memory cell,
Operations other than the column operation include a data refresh operation and a configuration mode setting operation.

(13) In the semiconductor integrated circuit device according to the aspect of (12),
The signal generation circuit controls a signal for controlling the potential of the control signal to a low potential (V3), a signal for instructing the data read operation and the data write operation, a signal for instructing the data refresh operation, and the configuration mode It is generated based on the logic of the signal that instructs the setting operation.

(14) In the semiconductor integrated circuit device according to any one of (9) to (13),
The high potential (V1) is a potential at which data amplified by the sense amplifier can be transferred from the amplification node pair to the bit line pair via the transistor pair.
The intermediate potential (V2) is a potential at which a minute potential difference appearing between the bit line pair can be transferred from the bit line pair to the amplification node pair via the transistor pair.
The low potential (V3) is a potential at which the amplification node pair and the bit line pair can be blocked by the transistor pair when the potential of the amplification node pair is amplified by the sense amplifier.

(15) In the semiconductor integrated circuit device according to any one of (9) to (14),
The control circuit includes:
An enable / disable circuit that determines whether to enable or disable the control circuit according to a signal that enables / disables the control circuit;
When the enable / disable circuit is in the enabled state and the signal for controlling the potential of the control signal to the high potential (V1) is the high potential, the output of the control circuit has the high potential (V1). ) For supplying a high potential (V1),
The enable / disable circuit is enabled, the signal for controlling the potential of the control signal to the high potential (V1) is not set to the high potential, and the potential of the control signal is controlled to the low potential (V3). An intermediate voltage (V2) supply circuit that supplies the intermediate voltage (V2) to the output of the control circuit when the signal to be output is not in the low potential state;
The enable / disable circuit is enabled, the signal for controlling the potential of the control signal to the high potential (V1) is not set to the high potential, and the potential of the control signal is controlled to the low potential (V3). A low voltage (V3) supply circuit that supplies the low voltage (V3) to the output of the control circuit when the signal to be output is in the state of the low potential.

(16) In the semiconductor integrated circuit device according to the aspect of (15),
The enable / disable circuit supplies an in-circuit ground potential to the output of the control circuit when in the disabled state.

(17) a first memory cell array in which the first memory cells are integrated;
A second memory cell array in which second memory cells are integrated;
A first bit line connected to the first memory cell;
A second bit line connected to the second memory cell;
A sense amplifier,
An amplification node connected to the sense amplifier;
A first transistor connecting the first bit line and the amplification node;
A second transistor connecting the second bit line and the amplification node;
A control circuit for generating a first control signal for controlling the first transistor and a second control signal for controlling the second transistor;
The semiconductor integrated circuit device, wherein the control circuit clocks the first and second control signals during a column operation and does not clock the first and second control signals during an operation other than the column operation.

(18) a first memory cell array in which the first memory cells are integrated;
A second memory cell array in which second memory cells are integrated;
A first bit line connected to the first memory cell;
A second bit line connected to the second memory cell;
A sense amplifier,
An amplification node connected to the sense amplifier;
A first transistor connecting the first bit line and the amplification node;
A second transistor connecting the second bit line and the amplification node;
The first and second control signals for controlling the first and second transistors, the signal for enabling / disabling the control circuit, and the potentials of the first and second control signals to a high potential (V1). A control circuit that generates a signal to be controlled based on the logic of a signal that controls the potential of the first and second control signals to a low potential (V2); and the potential of the first and second control signals is a low potential A semiconductor integrated circuit device comprising: a signal generation circuit that generates a signal to be controlled to (V3) based on a logic of a signal that instructs a column operation and a signal that instructs an operation other than the column operation.

(19) In a semiconductor integrated circuit device that operates a control signal of a transistor connecting a memory cell and a sense amplifier during access,
When the column operation is not required, the operation of the control signal is stopped.

(20) In a semiconductor integrated circuit device that operates a control signal of a transistor connecting a memory cell and a sense amplifier during access,
The operation of the control signal is stopped during the data refresh operation.

(21) In a semiconductor integrated circuit device that operates a control signal of a transistor connecting a memory cell and a sense amplifier during access,
When the configuration mode is set, the operation of the control signal is stopped.

(22) An electronic device using the semiconductor integrated circuit device according to any one of (1) to (21) as a memory.

(23) The electronic device according to the aspect of (22) is an electronic device operable with a battery.

(24) The electronic device operable with the battery according to the aspect of (23) is a portable electronic device.

(25) A portable electronic device according to the aspect of (24) includes a personal computer, a personal digital assistant (PDA), a digital camera (still camera, movie camera, still / movie camera), a mobile phone, a portable music player, and a portable game device. , Including e-books.

  As mentioned above, although this invention was demonstrated by one Embodiment, this invention is not limited to one Embodiment, In the implementation, it can change variously in the range which does not deviate from the summary of invention. Further, the embodiment of the present invention is not the only one described above.

  In addition, the above-described embodiment includes various stages of the invention, and the invention of various stages can be extracted by appropriately combining a plurality of constituent elements disclosed in the above-described embodiment.

FIG. 1 is a block diagram showing a configuration example of a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 2 is a block diagram showing a configuration example of the periphery of the memory cell array and the sense amplifier. 3A is a diagram illustrating an example of a semiconductor integrated circuit device having a shared sense amplifier, FIG. 3B is a circuit diagram illustrating an example of a sense amplifier, and FIG. 3C is a circuit diagram illustrating an example of a memory cell. FIG. 4 is a circuit diagram showing an example of the control circuit 4. 5A is a circuit diagram showing an example of the signal generation circuit 5, and FIG. 5B is a circuit diagram showing an example of the level shifter. FIG. 6 is an operation waveform diagram showing an operation example in the column operation of the semiconductor integrated circuit device according to one embodiment of the present invention. FIG. 7 is an operation waveform diagram showing an operation example other than the column operation of the semiconductor integrated circuit device according to the embodiment of the present invention.

Explanation of symbols

    DESCRIPTION OF SYMBOLS 1 ... Memory cell, 2 ... Sense amplifier, 3 ... Transistor pair, 4 ... Control circuit, 5 ... Signal generation circuit

Claims (5)

In a semiconductor integrated circuit device that operates a control signal of a transistor connecting a memory cell and a sense amplifier during access,
A semiconductor integrated circuit device, wherein the operation of the control signal is stopped when a column operation is not required.   2. The semiconductor integrated circuit device according to claim 1, wherein the operation when the column operation is not required is a data refresh operation.   2. The semiconductor integrated circuit device according to claim 1, wherein the operation when the column operation is not required is a configuration mode setting operation. A memory cell array in which memory cells are integrated;
A pair of bit lines connected to the memory cell;
A sense amplifier,
An amplification node pair connected to the sense amplifier;
A transistor pair connecting the bit line pair and the amplification node pair;
A control circuit for generating a control signal for controlling the transistor pair,
The semiconductor integrated circuit device, wherein the control circuit clocks the control signal during a column operation and does not clock the control signal during an operation other than the column operation. A memory cell array in which memory cells are integrated;
A pair of bit lines connected to the memory cell;
A sense amplifier,
An amplification node pair connected to the sense amplifier;
A transistor pair connecting the bit line pair and the amplification node pair;
The control signal for controlling the transistor pair is changed to a logic of a signal for enabling / disabling the control circuit, a signal for controlling the potential of the control signal to a high potential, and a signal for controlling the potential of the control signal to a low potential. A control circuit to generate based on,
A semiconductor integrated circuit device comprising: a signal generation circuit configured to generate a signal for controlling a potential of the control signal to a low potential based on a logic of a signal for instructing a column operation and a signal for instructing an operation other than the column operation.

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