JP2008108379A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of reducing power consumption. <P>SOLUTION: The semiconductor integrated circuit device is equipped with: an internal power supply generating circuit; a semiconductor memory; a storage circuit 33 for recording the defective information of the semiconductor memory; and a control circuit 39 constituted so as to stop internal power generated from the internal power supply generating circuit when the defective information is read out. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device and is applied to, for example, a multi-chip package (MCP) in which a plurality of semiconductor chips such as a NAND flash memory are mounted.

  With increasing demand for memory such as NAND flash memory in recent years, Multi-Chip-Package (MCP), system-in-package (SiP), etc. with multiple memory chips mounted There is an increasing demand for semiconductor integrated circuit devices (see, for example, Patent Document 1).

  In the MCP, after a NAND flash memory is assembled into a package, a function test is performed to determine whether the NAND flash memory or the like operates normally.

  Here, it is necessary to stop the operation of only the NAND flash memory in which a malfunction has been found by this functional test in which some malfunction has been found, and to operate other chips and circuits. However, in a conventional semiconductor integrated circuit device, a NAND flash memory in which some trouble has been found is put into a standby state using an existing circuit. In general, after the standby state is released, quick response is required, so that power is consumed by an input buffer or the like even in a NAND flash memory in which a defect is found.

  However, since the NAND flash memory in which a defect is found during the function test is not used thereafter, the power consumed by the NAND flash memory in which the defect is found was wasted.

Therefore, the conventional semiconductor integrated circuit device has a problem that power consumption increases.
JP 2004-228323 A

  The present invention provides a semiconductor integrated circuit capable of reducing power consumption.

  According to one aspect of the present invention, an internal power generation circuit, a semiconductor memory, a storage circuit for recording defect information of the semiconductor memory, and the internal power generation circuit when the defect information is read are generated. And a control circuit configured to stop an internal power supply.

  According to one aspect of the present invention, each is configured to control an internal power generation circuit, a semiconductor memory, a storage circuit that records defect information of the semiconductor memory, and a voltage value of the internal power generation circuit. A plurality of semiconductor chips provided with a control circuit, and the control circuit of the semiconductor chip from which the defect information is read out of the control circuits of the plurality of semiconductor chips is included in the read defect information. A semiconductor integrated circuit device that stops the internal power generated from the internal power generation circuit can be provided.

  According to the present invention, a semiconductor integrated circuit device capable of reducing power consumption can be obtained.

  Embodiments of the present invention will be described below with reference to the drawings. In this description, common parts are denoted by common reference symbols throughout the drawings.

[First embodiment]
First, a semiconductor integrated circuit device according to a first embodiment of the present invention will be described with reference to FIGS. In this embodiment, a multi-chip package (MCP) in which a plurality of semiconductor chips such as a NAND flash memory are mounted will be described as an example. The MCP is used as a memory for a host device such as a mobile phone.

  As shown in the figure, the semiconductor integrated circuit device 10 includes a binary NAND flash memory (chip 2) 14, a spacer 27-1, a multi-value NAND flash memory (chip 1) 12, and a spacer 27- 2. An SDRAM (Synchronous Dynamic Random Access Memory) 11 and a controller 13 are mounted in the same package.

  The semiconductor integrated circuit device 10 is solder-mounted on a printed circuit board or the like, and performs data transfer with a host device such as a mobile phone (not shown).

  The SDRAM 11 is configured to be temporarily shadowed on the RAM 11 when a program code such as firmware read from the binary NAND flash memory 14 is used by the host device. Unlike the NOR flash memory, the NAND flash memory 14 as in this example reads data serially without random access. Therefore, when the host device reads a program code such as firmware, it is necessary to temporarily develop it on the RAM 11 so that it can be accessed randomly.

  The multi-level NAND flash memory (chip 1) 12 is a NAND flash memory capable of storing a plurality of multi-bit data in one memory cell.

  The binary NAND flash memory (chip 2) 14 is a NAND flash memory capable of recording 1-bit data in one memory cell.

  The controller 13 has a physical state inside the multi-level NAND flash memory 12 (for example, which physical block address includes what logical sector address data, or which block is in the erased state). Is configured to manage. The controller 13 also adds an error correction code (ECC) to the multi-level NAND flash memory 12 for data input / output control, data management, and data writing, and also for error correction code reading. Analyze and process (ECC).

  Further, as shown in FIGS. 2 and 3, the RAM 11 is bonded to the substrate 31 by the wires 25, is conducted to the SDRAM I / F (not shown) on the back surface of the substrate 31, and is mounted by the solder balls 28.

  The multi-value NAND flash memory (chip 1) 12 is bonded to the substrate 31 by wires 25 and mounted by solder balls 28.

  The controller 13 is bonded to the substrate 31 by a wire 25, is conducted to an SD card I / F (not shown) on the back surface of the substrate 31, and is mounted by solder balls 28.

  The binary NAND flash memory (chip 2) 14 is bonded to the substrate 31 by wires 25 and mounted by solder balls 28.

  In the above description, the SD card I / F, SDRAM I / F, and the like have been described as examples of interfaces. However, the interface is not limited to this, and other predetermined memory interfaces such as NAND I / F and host interfaces can be applied.

<Configuration example of NAND flash memory>
Next, the configuration and operation of the NAND flash memories 12 and 14 according to this example will be described with reference to FIGS. Here, the multi-level NAND flash memory (chip 1) 12 will be described as an example.

  As shown in the figure, the multi-value NAND flash memory 12 (chip 1) includes a memory cell array 32, a storage circuit 33, a bit line decoder / sense amplifier 34, a word line decoder 35, a data latch circuit 36, an input / output buffer 37, an internal power supply. A generation circuit 38, a control circuit 39, an address latch circuit 40, an address buffer 41, a control signal latch circuit 43, and a control signal buffer 44 are provided.

  The memory cell array 32 includes a plurality of memory cells MC arranged in a matrix at intersections between the word lines WL and the bit lines BL. Each of the memory cells MC includes a tunnel insulating film provided on the semiconductor substrate, a floating electrode FG provided on the tunnel insulating film, an inter-gate insulating film provided on the floating electrode FG, and an inter-gate insulating film. The laminated structure includes the control electrode CG. The memory cells MC adjacent along the bit line BL direction share a source / drain which is a current path, and are arranged so that one end and the other end of each current path are connected in series.

  The memory cell MC and the select transistor ST, in which one end and the other end of the current path are connected in series, constitute a NAND cell string. One end of the current path of the NAND cell string is connected to the bit line decoder / sense amplifier 34, and the other end of the current path is connected to a source line (not shown).

  Further, there is one page (PAGE) for each word line WL. Data is written and read for each page.

  The memory circuit 33 is one of the above pages, and includes a memory cell MC that stores defect information (defective information) 54 and a memory cell MC that stores a parameter 56 that determines operating conditions.

  Here, as shown in FIG. 5, the defect information 54 and the parameter 56 are written in the memory cell MC in the function test after the NAND flash memory (chip 1) 12 is assembled.

  The memory cell MC can store a large amount of data in a nonvolatile manner. Therefore, it is advantageous in that data such as the number of defective cells 55 and addresses after assembly can be easily stored, and it can be dealt with due to problems caused after assembly.

  In the defect information 54, when a defective cell 55 is found in the function test and the NAND flash memory (chip 1) 12 is determined to be a defective chip, the number, address, etc. of the defective cell 55 are written. It is the information which shows that it is.

  As will be described later, the parameter 56 is taken into the parameter register 45 in the control circuit 39 when the NAND flash memory (chip 1) 12 is activated. The control circuit 39 operates the NAND flash memory (chip 1) 12 so as to enter the deep standby mode based on the parameter 56.

  The bit line decoder and word line decoder 35 selects the bit line BL and the word line WL in the memory cell array 32.

  The sense amplifier 34 amplifies and reads data read from the memory cell MC.

  The data latch circuit 36 temporarily holds read data and write data received by the input / output buffer 37.

  The address latch circuit 40 temporarily holds the address received by the address buffer 41.

  The control signal latch circuit 43 temporarily holds the control signal received by the control signal buffer 44.

  The internal power supply generation circuit 38 is configured to generate an internal power supply for supplying to the circuits in the NAND flash memory 14 such as the memory cell array 32.

  The control circuit 39 is configured to control the value of the internal power supply generated from the internal power supply generation circuit 38. For example, as will be described later, the control circuit 39 controls the value of the internal power supply generated from the internal power supply generation circuit 38 in accordance with the parameter 56, and operates the NAND flash memory (chip 2) 14 so as to enter the deep standby mode. .

  The control circuit 39 includes a parameter register 45, a deep standby mode control circuit 46, and a deep standby mode control signal buffer 47, as shown in FIG.

  The parameter register 45 is configured to set the defect information 54 and the parameter 56 in the storage circuit 33 when the chip 14 is activated.

  The deep standby mode control circuit 46 controls the internal power generated from the internal power generation circuit 38 according to the parameter 56, and shifts the multi-level NAND flash memory (chip1) 12 to the deep standby mode.

  Here, the deep standby mode is different from the normal standby mode in that the generation of the internal power supply voltage VDD is stopped. In the normal standby mode, quick response after cancellation is required, so that power is continuously supplied from the internal power supply 38 to some circuits such as the address buffer 41 and the control signal buffer 44 of FIG. On the other hand, in the deep standby mode in which quick response after release is not required, it is not necessary to supply power from the internal power supply 38 to the circuits such as the address buffer 41 and the control signal buffer 44. Electric power can be reduced.

  The deep standby mode control signal buffer 47 receives an external power source generated by an external power source 50 provided outside the multi-level NAND flash memory (chip 1) 12.

  Therefore, even during the deep standby mode, power is supplied to the deep standby mode control circuit 46 from the external power supply 50, and the deep standby control signal buffer 47 and the like are also supplied with external power and operate in the same manner. . For this reason, even when the internal power generation circuit 38 is stopped in the deep standby mode, the control circuit 39 is operating, so that the deep standby mode can be canceled.

<Driving method>
Next, a method for driving the semiconductor integrated circuit device according to this embodiment will be described with reference to FIG.

  First, at the time t0, the control circuit 39 in a plurality of semiconductor chips such as the multi-level NAND flash memory (chip 1) 12 and the binary NAND flash memory (chip 2) 14 causes each internal power generation circuit 38 to operate. Drive to internal power supply VDD.

  Subsequently, at time t1, the deep standby mode control circuit 46 of chip 1 (multi-level NAND flash memory 12) stores data in the memory cell MC in the storage circuit 33 via the sense amplifier 34 and the data latch circuit 36. The defect information 54 and the parameter 56 thus set are set in the parameter register 45. Further, the deep standby mode control circuit 46 of chip 1 reads the parameter 56 set in the parameter register 45 and executes power-on read.

  On the other hand, at this time, the deep standby mode control circuit 46 of chip 2 (binary NAND flash memory 14) does not store the defect information 54 and the parameter 56 in the memory cell MC in the storage circuit 33. The parameter 56 is not read.

  Subsequently, at time t2, the deep standby mode control circuit 46 of chip 1 (multi-level NAND flash memory 12) stops the generation of the internal power generated from the internal power generation circuit 38 according to the parameter 56, and The voltage value is controlled to be 0 V, and the multi-level NAND flash memory 12 (chip 1) is shifted to the deep standby mode.

  Here, during the deep standby mode, the internal power generation circuit 38 is stopped, but power is supplied to the deep standby control circuit 46 from the external power supply 50. Therefore, the deep standby control signal buffer 47 and the like are also operated by being supplied with power from the external power supply 50. Therefore, even when the internal power generation circuit 38 is stopped, the circuit relating to the deep standby control is operating, and the control circuit 39 can cancel the deep standby mode.

  For example, when the deep standby mode control buffer 46 receives a deep standby control signal transmitted from an external controller 13 or a host device (not shown), the deep standby mode control circuit 46 causes the internal power generation circuit 38 to Control and cancel deep standby mode.

  Specifically, this deep standby control signal has a method of canceling deep standby using an existing signal, for example, a chip enable (CE: ChipEnable) signal. In this case, only the buffer that receives this signal is external. Make sure it works with the power supply. There is also a method of providing a signal dedicated to deep standby control. In this case, a dedicated control signal buffer such as the deep standby mode control signal buffer 47 is operated by an external power source.

  On the other hand, at this time, the deep standby mode control circuit 46 of chip 2 (binary NAND flash memory 14) does not operate. Therefore, the internal power supply VDD is supplied from the internal power generation circuit 38 of the chip 2 (binary NAND flash memory 14), and the chip 2 (binary NAND flash memory 14) is driven in a read / write operation mode.

  Subsequently, at time t3, the internal power supplied to the chip 1 (multi-level NAND flash memory 12) is completely reduced to 0V as the voltage value thereof is lowered to the deep standby mode. Thus, the deep standby mode is different from the normal standby mode in that the generation of the internal power supply voltage VDD is stopped.

  On the other hand, at this time, the internal power supply supplied to chip 2 (binary NAND flash memory 14) is the voltage value VDD, and chip 1 is driven in the operation mode.

  In the operation of this example, the deep standby mode is the multi-level NAND flash memory 12 (chip 1). Therefore, even if the multi-level NAND flash memory 12 (chip 1) is in the deep standby mode, the binary NAND flash memory 14 (chip 2) that stores information necessary for the operation of firmware and the like is operating. The operation stop of the semiconductor integrated circuit device (whole device) 10 is prevented.

  According to the semiconductor integrated circuit device of this embodiment, the following effects (1) and (2) can be obtained.

(1) Power consumption can be reduced.

  As described above, the multi-level NAND flash memory (chip 1) 12 of the semiconductor integrated circuit device according to this example includes the memory circuit 33 having the plurality of memory cells MC in which the parameter 56 and the defect information 54 are recorded. . The defect information 54 and the parameter 56 are written into the memory cell MC in the function test after the multi-level NAND flash memory (chip 1) 12 is assembled.

  Further, the deep standby mode control circuit 46 of the multi-level NAND flash memory (chip 1) 12 sets the defect information 54 and the parameter 56 in the parameter register 45, reads the parameter 56 set in the parameter register 45, and performs power-on read. Execute (time t1). Subsequently, the deep standby mode control circuit 46 of the multi-level NAND flash memory (chip1) 12 controls the value of the internal power supply generated from the internal power supply generation circuit 38 to 0 V according to the parameter 56 (time t2). ).

  Therefore, the multi-value NAND flash memory (chip 1) 12 having the defect information 54 and determined as a defective chip during the function test after assembly can be shifted to the deep standby mode.

  On the other hand, as indicated by a broken line 59 in FIG. 7, conventionally, a circuit corresponding to the internal power generation circuit 38 of all chips is driven regardless of a chip failure, so that a current also flows in the circuit of the defective chip. Electric power was continuously consumed, and power consumption increased.

  However, in the case of this example, the power consumed by the multi-level NAND flash memory (chip 1) 12 is only the power consumed by the control circuit 39 driven by the power supplied from the external power supply 50. Power consumption can be reduced as compared with the chip (broken line 59 in FIG. 7) that shifts to the standby mode. For example, in the case of this example, the power consumption can be reduced to about 1/100 compared to the conventional case.

  On the other hand, in the operation of this example, only the multi-level NAND flash memory 12 (chip 1) is in the deep standby mode. Therefore, even if the multi-level NAND flash memory 12 (chip 1) is in the deep standby mode, the binary NAND flash memory 14 (chip 2) that stores information necessary for the operation of firmware and the like is operating. The operation stop of the semiconductor integrated circuit device (whole device) 10 can be prevented.

(2) It is possible to deal with inconveniences that occur after assembly.

  The memory circuit 33 has a plurality of memory cells MC that can be programmed such as erase / rewrite. Therefore, even if a failure occurs in the NAND flash memories 12 and 14 (chip 1 and chip 2) after assembly, the information is recorded in the memory cell MC as new failure information (failure information 54 and parameter 56). be able to.

  For example, defect information 54 such as the number and address of a new defective cell 55 and a parameter 56 are further written into the memory cell MC in the multi-level NAND flash memory (chip 1) 12, and the multi-value is calculated based on the new defect information 54. It is also possible to set the NAND flash memory (chip 1) 12 to the deep standby mode.

  In this way, it is possible to deal with inconveniences such as deterioration of the flash memory and deterioration of peripheral circuits that occur after assembly as necessary.

[Second Embodiment (an example in which an antifuse circuit is applied)]
Next, a semiconductor memory device according to the second embodiment will be described with reference to FIG. This embodiment relates to an example in which an antifuse circuit is applied as the memory circuit 33. In this description, detailed description of the same parts as those in the first embodiment is omitted.

  As shown in the figure, the semiconductor integrated circuit device according to this example is different from the first embodiment in that an antifuse circuit 51 is provided as the memory circuit 33 of the NAND flash memory 14.

  The antifuse circuit 51 has a plurality of antifuses. The antifuse is, for example, a MOS transistor whose gate is connected to the program node and whose source and drain are grounded.

  For example, in the case of a functional test after assembly, the MOS transistor program that is an antifuse is to apply a high voltage to the program node to break the gate insulating film and to make the gate and the source / drain conductive. Etc. Therefore, it is different from the memory cell MC in that once it becomes conductive, it cannot be restored and cannot be erased / rewritten.

  Other configurations and operations are substantially the same as those in the first embodiment.

  As described above, according to the semiconductor integrated circuit device of this embodiment, the same effect as the above (1) can be obtained.

  Further, as in this example, the antifuse circuit 51 can be adapted as the memory circuit 33 as necessary.

[Modification (an example with a plurality of chips)]
Next, a semiconductor memory device according to a modification will be described with reference to FIG. This modification relates to an example in which a plurality of NAND flash memory chips (chip1 to chipN) are further mounted. In this description, detailed description of the same parts as those in the first embodiment is omitted.

  As shown in the drawing, the semiconductor memory device 10 according to the present modification is different from the first and second embodiments in that a plurality of NAND flash memories (chip 1 to chip N) are further mounted.

  Other structures and operations are substantially the same as those in the first and second embodiments.

  According to the semiconductor integrated circuit device of this modification, the same effect as the above (1) can be obtained.

  In the first and second embodiments, the MCP on which the semiconductor chips such as the two NAND flash memories 12 and 14 (chip 1 and chip 2) are mounted has been described as an example. However, the present invention can be similarly applied even when a plurality of NAND flash memories (chip 1 to chip N) are mounted as necessary, as in this example.

  Therefore, the configuration according to this modification is effective in that the storage capacity can be increased. Furthermore, it is effective in that power consumption can be reduced by shifting to the deep standby mode for all defective chips.

  In the first and second embodiments and the modifications described above, the binary NAND flash memory 14 can be replaced with the multi-value NAND flash memory 12.

  Further, the present invention is not limited to the MCP, and the same effect can be obtained even when applied to, for example, a semiconductor integrated circuit device having a plurality of logic circuits. For example, an example in which similar defect information 54 and parameters 56 are recorded in a fuse circuit included in a logic circuit can be considered. The defect information 54 and the parameter 56 are taken into the parameter register when the chip is activated. Similarly, the control circuit can operate the internal power generation circuit so as to shift the logic circuit to the deep standby mode based on the defect information.

  As described above, the present invention has been described using the first and second embodiments and modifications. However, the present invention is not limited to the above-described embodiments and modifications, and departs from the gist at the implementation stage. Various modifications can be made without departing from the scope. Each of the above embodiments and modifications includes inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent elements are deleted from all the constituent elements shown in the embodiments and modifications, at least one of the problems described in the column of the problem to be solved by the invention can be solved, and the column of the effect of the invention In the case where at least one of the effects described in (1) is obtained, a configuration in which this configuration requirement is deleted can be extracted as an invention.

1 is a plan view showing a semiconductor integrated circuit device (MCP) according to a first embodiment of the present invention. Sectional drawing along II-II in FIG. Sectional drawing along III-III in FIG. 1 is a circuit diagram showing a NAND flash memory of a semiconductor integrated circuit device according to a first embodiment. 1 is a block diagram for explaining a memory cell array of a NAND flash memory according to a first embodiment. FIG. FIG. 2 is a block diagram for explaining a control circuit of the NAND flash memory according to the first embodiment. (A) is a timing chart showing the voltage value of the internal power supply of the binary NAND flash memory (chip 2) according to the first embodiment, and (b) is a multi-value NAND flash according to the first embodiment. The timing chart figure which shows the voltage value of the internal power supply of memory (chip1). A circuit diagram showing a NAND flash memory of a semiconductor integrated circuit device concerning a 2nd embodiment. Sectional drawing which shows the semiconductor integrated circuit device which concerns on a modification.

Explanation of symbols

DESCRIPTION OF SYMBOLS 14 ... NAND type flash memory, 32 ... Memory cell array, 33 ... Memory circuit, 34 ... Bit line decoder / sense amplifier, 35 ... Word line decoder, 36 ... Data latch circuit, 37 ... Input / output buffer, 38 ... Internal power generation circuit , 39 ... control circuit, 40 ... address latch circuit, 41 ... address buffer, 43 ... control signal latch circuit, 44 ... control signal buffer.

Claims (5)

An internal power generation circuit;
Semiconductor memory,
A storage circuit for recording defect information of the semiconductor memory;
And a control circuit configured to stop an internal power supply generated from the internal power supply generation circuit when the defect information is read out. Each includes a plurality of internal power generation circuits, a semiconductor memory, a storage circuit for recording defect information of the semiconductor memory, and a control circuit configured to control a voltage value of the internal power generation circuit Comprising a semiconductor chip,
Of the control circuits of the plurality of semiconductor chips, the control circuit of the semiconductor chip from which the defect information has been read stops internal power generated from the internal power generation circuit based on the read defect information. A semiconductor integrated circuit device. The control circuit includes a deep standby mode control signal buffer;
A parameter register in which the defect information is set at startup;
The semiconductor integrated circuit device according to claim 1, further comprising: a deep standby mode control circuit that shifts an internal power source generated from the internal power source generation circuit to a deep standby mode in accordance with the read defect information. 4. The memory circuit according to claim 1, wherein the memory circuit is a read unit or a write unit including a plurality of memory cells, or an antifuse circuit including a plurality of antifuses. The semiconductor integrated circuit device described. The semiconductor integrated circuit device according to claim 1, wherein stopping the internal power generated from the internal power generation circuit is in a deep standby mode.

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