JP2008104160A - Transmission circuit and communication device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a transmission circuit which is small in size, operates with high efficiency, and outputs a transmission signal having high linearity. <P>SOLUTION: A signal generation section 11 generates an amplitude signal m(t) and a phase signal. An angle modulation section 17 angle-modulates the phase signal to output an angle-modulated signal. An amplitude calculation section 12 outputs a discrete value signal V(t) having a plurality of discrete values corresponding to a magnitude of the amplitude signal m(t). A dividing section 13 divides the amplitude signal m(t) by the discrete value signal V(t) to output an amplitude signal M(t). A delta-sigma modulation section 14 delta-sigma modulates the amplitude signal M(t) to output a delta-sigma modulated signal. A variable gain amplifier section 15 amplifies the delta-sigma modulated signal by a gain corresponding to the discrete value signal V(t). An amplitude amplifying section 16 supplies, to an amplitude modulation section 18, a voltage corresponding to a magnitude of the delta-sigma modulated signal. The amplitude modulation section 18 amplitude-modulates the angle-modulated signal by the voltage supplied from the amplitude amplifying section 16, to output a modulation signal. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a transmission circuit used in a communication device such as a mobile phone or a wireless LAN, and more specifically, a transmission circuit that operates with a small size and high efficiency and outputs a highly linear transmission signal, and uses the same. Related to communication equipment.

  Communication devices such as mobile phones and wireless LANs are required to operate with low power consumption while ensuring the accuracy of transmission signals regardless of the magnitude of output power. In such a communication device, a transmission circuit that operates with a small size and high efficiency and outputs a highly linear transmission signal is used. A conventional transmission circuit will be described below.

  As a conventional transmission circuit, for example, there is a transmission circuit disclosed in FIG. FIG. 22 is a block diagram illustrating an example of a configuration of a conventional transmission circuit 700 disclosed in Patent Document 1. In FIG. In FIG. 22, a conventional transmission circuit 700 includes a signal generation unit 71, a delta sigma modulation unit 72, an angle modulation unit 73, a multiplication unit 74, a band pass filter 75, an output terminal 76, and a variable gain amplification unit 77.

  In the conventional transmission circuit 700, the signal generation unit 71 generates an amplitude signal and a phase signal. The amplitude signal is input to the delta sigma modulation unit 72. The delta sigma modulation unit 72 performs delta sigma modulation on the input amplitude signal and outputs it as a delta sigma modulation signal. The delta sigma modulation signal is input to the variable gain amplification unit 77. The variable gain amplifying unit 77 amplifies the delta-sigma modulated signal with a gain corresponding to power information indicating the magnitude of output power of the transmission circuit. The delta sigma modulation signal amplified by the variable gain amplification unit 77 is input to the multiplication unit 74.

  The phase signal is input to the angle modulation unit 73. The angle modulation unit 73 angle-modulates the phase signal and outputs it as an angle modulation signal. The angle modulation signal is input to the multiplication unit 74. The multiplication unit 74 multiplies the delta-sigma modulation signal and the angle modulation signal and outputs the result as a modulation signal. The bandpass filter 75 removes quantization noise included in the modulation signal. The modulated signal from which the quantization noise has been removed by the bandpass filter 75 is output from the output terminal 76 as a transmission signal.

  As a conventional transmission circuit, for example, there is a transmission circuit disclosed in FIGS. FIG. 23A is a block diagram illustrating an example of a configuration of a conventional transmission circuit 800 disclosed in Patent Document 2. In FIG. In FIG. 23A, a conventional transmission circuit 800 includes a data generation unit 81, a vector modulation unit 82, an amplification unit 83, a bandpass filter 84, and an antenna 85.

  In the conventional transmission circuit 800, the data generation unit 81 generates first data and second data that are orthogonal to each other. Details of the data generation unit 81 will be described later. The vector modulation unit 82 vector-modulates the first data and the second data and outputs the result as a modulation signal. The amplifying unit 83 amplifies the modulated signal. The band pass filter 84 removes quantization noise included in the modulation signal. The modulated signal from which the quantization noise has been removed by the band pass filter 84 is output from the antenna 85 as a transmission signal.

  FIG. 23B is a block diagram illustrating an exemplary configuration of the data generation unit 81. In FIG. 23B, the data generation unit 81 includes an original data generation unit 811, a delta sigma modulation unit 812, a multiplication unit 813, and a multiplication unit 814. The original data generation unit 811 generates an amplitude signal, a normalized I signal, and a normalized Q signal based on the baseband signal. The normalized I signal is calculated by dividing an I signal (in-phase signal) that is a baseband signal by an amplitude signal. Similarly, the normalized Q signal is calculated by dividing a Q signal (quadrature-phase signal) which is a baseband signal by an amplitude signal.

  The amplitude signal is input to the delta sigma modulation unit 812. The delta sigma modulation unit 812 performs delta sigma modulation on the input amplitude signal and outputs it as a delta sigma modulation signal. The multiplier 813 multiplies the standardized I signal and the delta-sigma modulated signal, and outputs the multiplied signal as first data. The multiplication unit 814 multiplies the standardized Q signal and the delta-sigma modulated signal, and outputs the multiplied signal as second data.

  Moreover, as a conventional transmission circuit, there exists a transmission circuit currently disclosed by FIG. 24A of patent document 3, for example. FIG. 24A is a block diagram showing an example of the configuration of a conventional transmission circuit 900 disclosed in Patent Document 3. As shown in FIG. In FIG. 24A, a conventional transmission circuit 900 includes a data generation unit 91, a data conversion unit 92, a modulation unit 93, an amplification unit 94, a bandpass filter 95, and an antenna 96.

  In the conventional transmission circuit 900, the data generation unit 91 generates an I signal and a Q signal. The I signal and the Q signal are input to the data conversion unit 92. The data converter 92 converts the input I signal and Q signal into a binary quantized signal. Details of the data conversion unit 92 will be described later. The modulator 93 modulates the quantized signal and outputs it as a modulated signal. The amplifying unit 94 amplifies the modulation signal. The band pass filter 95 removes quantization noise included in the modulation signal amplified by the amplification unit 94. The modulated signal from which the quantization noise has been removed by the bandpass filter 95 is output from the antenna 96 as a transmission signal.

FIG. 24B is a block diagram illustrating an exemplary configuration of the data conversion unit 92. In FIG. 24B, the data conversion unit 92 includes a vector subtraction unit 921, a vector integration unit 922, and a vector quantization unit 923. The data conversion unit 92 receives the I signal and the Q signal from the data generation unit 91. The I signal and the Q signal are input to the vector integration unit 922 via the vector subtraction unit 921. The vector integration unit 922 integrates the I signal and the Q signal, respectively. The signal output from the vector integration unit 922 is input to the vector quantization unit 923. The vector quantization unit 923 quantizes the input signal and outputs it as a binary quantized signal. The vector subtraction unit 921 subtracts the quantized signal from the input I signal and Q signal, and stabilizes the output of the quantized signal.
JP 2004-0487703 A JP 2004-072734 A JP 2004-159319 A

  However, in the conventional transmission circuit 700 shown in FIG. 22, since the envelope of the amplitude signal generated by the signal generation unit 71 fluctuates greatly, a large amount of quantization noise is generated in the delta-sigma modulation unit 72. For this reason, the bandpass filter 75 is required to have a steep characteristic in order to remove quantization noise, and power consumption and size are large. Therefore, the conventional transmission circuit 700 has a problem that power efficiency as a transmission circuit is reduced and a circuit scale is increased. Further, there is a possibility that the transmission signal is deteriorated due to quantization noise that is not removed by the bandpass filter 75.

  Further, in the conventional transmission circuit 800 shown in FIG. 23A and FIG. 23B, since the envelope of the amplitude signal generated by the original data generation unit 811 fluctuates greatly, a large amount of quantization noise is generated in the delta-sigma modulation unit 812. It was. For this reason, the band pass filter 84 is required to have a steep characteristic in order to remove quantization noise, and power consumption and size are large. Therefore, the conventional transmission circuit 800 has a problem that power efficiency as a transmission circuit is reduced and a circuit scale is increased. Further, there is a possibility that the transmission signal is deteriorated due to quantization noise that is not removed by the bandpass filter 84.

  Further, in the conventional transmission circuit 900 shown in FIGS. 24A and 24B, since the envelope of the signal input to the vector quantization unit 923 fluctuates greatly, the vector quantization unit 923 generates a lot of quantization noise. It was. For this reason, the bandpass filter 95 is required to have a steep characteristic in order to remove quantization noise, and power consumption and size are large. Therefore, the conventional transmission circuit 900 has a problem that power efficiency as a transmission circuit is lowered and a circuit scale is increased. Further, there is a possibility that the transmission signal is deteriorated due to quantization noise that is not removed by the bandpass filter 95.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to solve the above-described problems, provide a transmission circuit that operates in a small size and high efficiency, and outputs a highly linear transmission signal, and a communication device using the transmission circuit.

  The present invention is directed to a transmission circuit that generates and outputs a transmission signal based on input data. In order to achieve the above object, the transmission circuit of the present invention performs a predetermined signal processing on input data to generate an amplitude signal and an angle modulation signal, and a predetermined arithmetic processing on the amplitude signal. The amplitude calculation unit that outputs a discrete value signal having a plurality of discrete values corresponding to the magnitude of the amplitude signal, and delta-sigma modulates the amplitude signal based on the discrete value signal, and outputs it as a delta-sigma modulated signal A delta-sigma modulation signal generation unit, an amplitude amplification unit that outputs a signal corresponding to the magnitude of the delta-sigma modulation signal, and an angle modulation signal by amplifying the angle modulation signal according to the signal output from the amplitude amplification unit And an amplitude modulation unit that outputs the signal as a transmission signal subjected to angle modulation and amplitude modulation. The amplitude calculation unit holds at least one threshold value and two or more discrete values corresponding to the threshold value, and whether the amplitude signal exceeds one or more threshold values every predetermined time It determines whether or not, selects a discrete value to be output based on the determination result, and outputs the selected discrete value as a discrete value signal.

  Preferably, the delta-sigma modulation signal generation unit divides the amplitude signal by the discrete value signal and outputs the amplitude signal with a small envelope variation, and the delta-sigma modulation of the amplitude signal output by the division unit The delta sigma modulation unit that outputs the delta sigma modulation signal and the variable gain amplification unit that amplifies the delta sigma modulation signal with a gain corresponding to the magnitude of the discrete value signal.

  Further, the delta signal modulation signal generation unit may include a delta sigma modulation unit that delta-sigma modulates the amplitude signal and outputs the delta sigma modulation signal. The delta-sigma modulation unit changes the magnitude of the output delta-sigma modulation signal so that the magnitude of the discrete-value signal and the positive characteristic have a relationship.

  Preferably, the delta-sigma modulation unit changes the magnitude of the output delta-sigma modulation signal so that the magnitude of the discrete-value signal is directly proportional.

  The delta sigma modulation unit changes the magnitude of the output delta sigma modulation signal with reference to a lookup table in which optimum values are set in advance according to the magnitude of the discrete value signal.

  Preferably, the signal generation unit includes a polar signal generation unit that generates an amplitude signal and a phase signal based on an amplitude component and a phase component obtained by performing signal processing on input data, and angle-modulates the phase signal to obtain an angle And an angle modulation unit that outputs the modulated signal.

  In addition, the signal generation unit performs signal processing on the input data, thereby generating an orthogonal signal generation unit that generates a vector signal composed of I and Q signals orthogonal to each other, a vector modulation unit that vector-modulates the vector signal, and vector modulation The envelope component of the signal output from the unit is detected, the detected envelope component is output as the amplitude signal, and the envelope component of the signal output from the vector modulation unit is set to a certain size. And a limiter that outputs a signal having a limited size and a limited size as the angle modulation signal.

  Preferably, the amplitude calculation unit includes a maximum amplitude detection unit that detects a maximum value of the amplitude signal every predetermined time, at least one threshold value, and two or more discrete values corresponding to the threshold value. And determining whether or not the maximum value of the amplitude signal exceeds one or more threshold values every predetermined time, selecting a discrete value to be output based on the determination result, and selecting the selected discrete value And a quantization unit that outputs the discrete value signal.

  Preferably, the transmission circuit further includes a band-pass filter connected to a subsequent stage of the amplitude modulation unit and configured to remove quantization noise from the transmission signal output from the amplitude modulation unit.

  The transmission circuit may further include a low-pass filter that is connected between the amplitude amplification unit and the amplitude modulation unit and removes quantization noise from the signal output from the amplitude amplification unit. The transmission circuit may further include a low-pass filter that is connected between the delta-sigma modulation signal generation unit and the amplitude amplification unit and removes quantization noise from the delta-sigma modulation signal.

  The amplitude amplifying unit includes a switching regulator, and supplies a voltage corresponding to the magnitude of the delta sigma modulation signal generated by the delta sigma modulation signal generation unit to the amplitude modulation unit. The amplitude amplifying unit may be configured by a series regulator, and may supply a voltage corresponding to the magnitude of the delta sigma modulation signal generated by the delta sigma modulation signal generation unit to the amplitude modulation unit. Alternatively, the amplitude amplifying unit may be configured by a current driven regulator, and may be configured to supply a current corresponding to the magnitude of the delta sigma modulation signal generated by the delta sigma modulation signal generation unit to the amplitude modulation unit.

  Preferably, the amplitude amplification unit includes a series regulator that supplies a voltage corresponding to the magnitude of the delta sigma modulation signal generated by the delta sigma modulation signal generation unit to the amplitude modulation unit, and a discrete value signal output from the amplitude calculation unit. And a switching regulator that supplies a voltage according to the magnitude of the series regulator to the series regulator.

  Preferably, the transmission circuit is connected between the amplitude calculation unit and the switching regulator, and controls the timing at which the discrete value signal output from the amplitude calculation unit is input to the switching regulator so as to compensate for the rising of the switching regulator. A timing control unit is further provided.

  In addition, the transmission circuit may be configured to further include a multiplication unit that is connected to the subsequent stage of the signal generation unit and receives power information indicating the magnitude of output power of the transmission circuit. The multiplying unit multiplies the amplitude information generated by the signal generating unit by the power information. The amplitude signal is input from the multiplier to the amplitude calculator and the delta-sigma modulated signal generator.

  The transmission circuit may be configured to further include a multiplication unit that is connected to the subsequent stage of the amplitude calculation unit and that receives power information indicating the magnitude of output power of the transmission circuit. The amplitude amplification unit includes a series regulator that supplies a voltage corresponding to the magnitude of the delta-sigma modulation signal generated by the delta-sigma modulation signal generation unit to the amplitude modulation unit, and a voltage according to the magnitude of the output signal of the multiplication unit. Including a switching regulator that supplies the series regulator. The multiplication unit multiplies the discrete value signal output from the amplitude calculation unit by the power information. A discrete value signal multiplied by power information is input from the multiplier to the switching regulator and the variable gain amplifier.

  The transmission circuit may be configured to further include a multiplication unit that is connected to the subsequent stage of the amplitude calculation unit and that receives power information indicating the magnitude of output power of the transmission circuit. The amplitude amplifier is a series regulator that supplies a voltage according to the magnitude of the delta-sigma modulated signal generated by the delta-sigma modulated signal generator to the amplitude modulator, and a switching that supplies a voltage according to the power information to the series regulator. Including a regulator. The multiplication unit multiplies the discrete value signal output from the amplitude calculation unit by the power information. A discrete value signal is input from the multiplier to the variable gain amplifier.

  The amplitude amplifying unit includes a plurality of series regulators that supply a voltage corresponding to the magnitude of the delta sigma modulation signal generated by the delta sigma modulation signal generation unit to the amplitude modulation unit, a plurality of series regulators, and an amplitude modulation unit, And a switching regulator that supplies a voltage according to the magnitude of the discrete value signal output from the amplitude calculation unit to a plurality of series regulators, and the plurality of series regulators have an amplitude via the switch. The configuration may include a first series regulator connected to the modulation unit and a second series regulator having a size larger than that of the first series regulator and connected to the amplitude modulation unit via a switch. . In such a case, the amplitude amplifying unit switches the switch so that the first series regulator and the amplitude modulating unit are connected when the magnitude of the delta-sigma modulated signal is smaller than a predetermined threshold value. When the magnitude of the sigma modulation signal is equal to or greater than a predetermined threshold, the switch is switched so that the second series regulator and the amplitude modulation unit are connected.

  The amplitude amplifying unit includes a switching regulator that supplies a voltage corresponding to the magnitude of the delta sigma modulation signal generated by the delta sigma modulation signal generation unit to the amplitude modulation unit, and a discrete value signal output from the amplitude calculation unit. A configuration including a switching regulator that supplies a voltage corresponding to the magnitude to the switching regulator may be employed.

  The amplitude amplification unit includes a plurality of switching regulators that supply the amplitude modulation unit with a voltage corresponding to the magnitude of the delta sigma modulation signal generated by the delta sigma modulation signal generation unit, and a connection between the plurality of switching regulators and the amplitude modulation unit. And a switching regulator that supplies a voltage corresponding to the magnitude of the discrete value signal output from the amplitude calculation unit to the plurality of switching regulators, the plurality of switching regulators via the switch, the amplitude modulation unit A configuration including a first switching regulator connected to the first switching regulator and a second switching regulator having a size larger than that of the first switching regulator and connected to the amplitude modulation unit via a switch may be employed. In such a case, the amplitude amplifying unit switches the switch so that the first switching regulator and the amplitude modulating unit are connected when the magnitude of the delta-sigma modulated signal is smaller than a predetermined threshold value. When the magnitude of the sigma modulation signal is equal to or greater than a predetermined threshold, the switch is switched so that the second switching regulator and the amplitude modulation unit are connected.

  In addition, the transmission circuit of the present invention includes a signal generation unit that generates a vector signal composed of an I signal and a Q signal that are orthogonal to each other based on input data, an amplitude signal that represents the magnitude of the vector signal, and an amplitude signal. A predetermined arithmetic process is performed to output a discrete value signal having a plurality of discrete values corresponding to the magnitude of the amplitude signal, and a vector signal is modulated based on the discrete value signal to generate a modulated signal A modulation signal generation unit; an amplitude amplification unit that outputs a signal corresponding to the magnitude of the discrete value signal; and an amplification unit that amplifies the modulation signal according to the signal output from the amplitude amplification unit and outputs the signal as a transmission signal. The structure provided may be sufficient. The amplitude calculation unit holds at least one threshold value and two or more discrete values corresponding to the threshold value, and whether the amplitude signal exceeds one or more threshold values every predetermined time It determines whether or not, selects a discrete value to be output based on the determination result, and outputs the selected discrete value as a discrete value signal.

  Preferably, the modulation signal generation unit divides the vector signal by the discrete value signal, quantizes the vector signal divided by the division unit by performing predetermined signal processing, and outputs the quantized signal. A signal processing unit that performs vector modulation on the quantized signal and outputs the modulated signal, and variable gain amplification that amplifies the modulation signal output by the vector modulation unit with a gain corresponding to the magnitude of the discrete value signal Part.

  The modulation signal generation unit includes a division unit that divides the vector signal by the discrete value signal, a signal processing unit that performs predetermined signal processing on the divided vector signal, quantizes the signal, and outputs the quantized signal. A variable gain amplifying unit that amplifies the quantized signal with a gain corresponding to the magnitude of the discrete value signal; a vector modulating unit that vector-modulates the quantized signal amplified by the variable gain amplifying unit and outputs the modulated signal; The structure containing these may be sufficient.

  Further, the modulation signal generating unit performs predetermined signal processing on the vector signal, quantizes the signal, and outputs a quantized signal, and a vector modulation unit that vector-modulates the quantized signal and outputs the modulated signal. The structure containing these may be sufficient. The signal processing unit changes the magnitude of the quantized signal so that the relationship between the magnitude of the discrete value signal and the positive characteristic is obtained.

  Preferably, the signal processing unit changes the magnitude of the quantized signal so that the magnitude of the discrete value signal is directly proportional.

  The signal processing unit changes the size of the quantized signal with reference to a lookup table in which an optimum value is set in advance according to the size of the discrete value signal.

  Preferably, the signal processing unit receives the vector signal divided by the division unit, receives the input vector signal, the signal representing the magnitude of the input vector signal, and the input vector signal. A signal conversion unit that converts the signal into a normalized vector signal calculated by dividing by a signal that represents the magnitude of the vector signal, and delta-sigma modulation that modulates the signal that represents the magnitude of the input vector signal And a multiplication unit that multiplies the delta-sigma modulated signal and the normalized vector signal and outputs the result as a quantized signal.

  The signal processing unit includes a vector operation unit to which the vector signal divided by the division unit is input, and a vector quantization unit that quantizes the output signal of the vector operation unit and outputs the quantized signal. The vector operation unit includes a vector subtraction unit that subtracts the quantized signal from the input signal, and a vector integration unit that integrates and outputs the signal input via the vector subtraction unit.

  Preferably, the signal processing unit further includes one or more vector calculation units at the output of the vector calculation unit.

  Preferably, the transmission circuit further includes a band-pass filter that removes quantization noise from the transmission signal output from the amplification unit.

  Alternatively, the transmission circuit may further include a low-pass filter that removes quantization noise from the signal output from the amplitude amplification unit.

  The predetermined time is a time shorter than the time for controlling the output power of the transmission circuit. Preferably, the amplitude calculator changes the length of the predetermined time according to the fluctuation range of the envelope of the transmission signal. Specifically, the amplitude calculation unit changes the predetermined time short when the fluctuation range of the envelope of the transmission signal is small, and changes the predetermined time longer when the fluctuation range of the envelope of the transmission signal is large.

  Alternatively, the amplitude calculation unit may change the length of the predetermined time according to the modulation mode of the transmission signal.

  Preferably, the transmission circuit further includes a distortion compensation unit that compensates at least one of the amplitude signal and the phase signal at the output of the signal generation unit so that distortion generated at least by the amplitude modulation unit is suppressed. Prepare.

  Alternatively, the transmission circuit further includes a distortion compensation unit that compensates at least one of the amplitude signal and the vector signal at the output of the signal generation unit so that distortion generated at least by the amplification unit is suppressed.

  The present invention is also directed to a communication device including the above-described transmission circuit. The communication device includes a transmission circuit that generates a transmission signal and an antenna that outputs the transmission signal generated by the transmission circuit. In addition, the communication device includes a reception circuit that processes a reception signal received from the antenna, and an antenna sharing unit that outputs the transmission signal generated by the transmission circuit to the antenna and outputs the reception signal received from the antenna to the reception circuit. The structure further provided may be sufficient.

  As described above, according to the transmission circuit of the present invention, the delta-sigma modulation unit delta-sigma-modulates an amplitude signal with a small envelope variation, and therefore it is possible to reduce quantization noise generated during delta-sigma modulation. . For this reason, a steep characteristic is not required for a filter for reducing quantization noise, and power consumption and size can be reduced. As a result, the transmission circuit operates in a small size and high efficiency, and can output a transmission signal with high linearity.

  In the transmission circuit, the amplitude amplifying unit includes a series regulator and a switching regulator, and supplies a voltage corresponding to the magnitude of the delta-sigma modulation signal to the amplitude modulating unit using characteristics of the series regulator and the switching regulator. . As a result, the transmission circuit can operate with higher efficiency and lower distortion.

  In addition, the transmission circuit includes a timing control unit subsequent to the amplitude calculation unit, thereby eliminating the instability of rising of the switching regulator and realizing an operation with lower distortion. Further, the transmission circuit adjusts the voltage supplied from the amplitude amplifying unit to the amplitude modulating unit based on the power information indicating the magnitude of the output power, thereby further improving the efficiency and reducing the distortion. Can be realized.

  In addition, since the signal processing unit quantizes the Iv signal and the Qv signal calculated by dividing the I signal and the Q signal by the discrete value signal, the transmission circuit reduces the quantization noise generated during the quantization. can do. For this reason, a steep characteristic is not required for a filter for reducing quantization noise, and power consumption and size can be reduced. As a result, the transmission circuit operates in a small size and high efficiency, and can output a transmission signal with high linearity.

  In addition, the transmission circuit of the present invention can realize a lower distortion operation by further including a distortion compensation unit for compensating for distortion generated at least in the amplitude modulation unit or the amplification unit. Furthermore, by using the above-described transmission circuit, the communication device can operate with low power consumption while ensuring the accuracy of the transmission signal regardless of the magnitude of the output power.

  These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.

(First embodiment)
FIG. 1 is a block diagram showing an example of the configuration of the transmission circuit 1 according to the first embodiment of the present invention. In FIG. 1, a transmission circuit 1 includes a signal generation unit 11, an amplitude calculation unit 12, a division unit 13, a delta sigma modulation unit 14, a variable gain amplification unit 15, an amplitude amplification unit 16, an angle modulation unit 17, and an amplitude modulation unit 18. , A band pass filter (BPF) 19, a power supply terminal 20, and an output terminal 21. The signal generator 11 generates an amplitude signal m (t) and a phase signal based on the amplitude component and the phase component obtained by performing signal processing on the input data. The signal generation unit 11 generates the amplitude signal m (t) and the phase signal, which are polar coordinate system signals, and may be referred to as a polar coordinate signal generation unit.

The amplitude signal m (t) is input to the amplitude calculation unit 12 and the division unit 13. The amplitude calculation unit 12 performs a predetermined calculation process on the amplitude signal m (t) and generates a discrete value signal V (t) having a plurality of discrete values controlled according to the magnitude of the amplitude signal m (t). Output. Details of the amplitude calculator 12 will be described later. The discrete value signal V (t) is input to the division unit 13 and the variable gain amplification unit 15. The division unit 13 divides the amplitude signal m (t) by the discrete value signal V (t) and outputs it as the amplitude signal M (t). Since the amplitude signal M (t) is divided by the discrete value signal V (t), the envelope fluctuation is smaller than that of the amplitude signal m (t). Typically, the amplitude signal M (t) is a signal having a substantially constant envelope size regardless of the magnitude of the amplitude signal m (t). Here, the amplitude signal M (t) can be expressed using Expression (1).
M (t) = m (t) / V (t) (Formula 1)

  The amplitude signal M (t) is input to the delta sigma modulation unit 14. The delta sigma modulation unit 14 performs delta sigma modulation on the amplitude signal M (t) and outputs it as a delta sigma modulation signal D1 (see FIG. 2A). Since the delta-sigma modulation unit 14 performs delta-sigma modulation on the amplitude signal M (t) having a small envelope variation, it is possible to suppress quantization noise generated during delta-sigma modulation. The delta sigma modulation signal D1 is input to the variable gain amplification unit 15. The variable gain amplifying unit 15 amplifies the delta sigma modulation signal D1 with a gain corresponding to the magnitude of the discrete value signal V (t), and outputs it as the delta sigma modulation signal D2 (see FIG. 2B). The delta-sigma modulation signal D2 is amplified by the variable gain amplification unit 15 and becomes a signal in which the maximum value of the envelope varies according to the amplitude signal m (t) as shown in FIG. 2B. A DC voltage is supplied from the power supply terminal 20 to the amplitude amplifying unit 16. The amplitude amplifying unit 16 supplies a voltage corresponding to the magnitude of the delta-sigma modulated signal D2 input via the variable gain amplifying unit 15 to the amplitude modulating unit 18. Typically, the amplitude amplifying unit 16 supplies a voltage proportional to the magnitude of the input delta-sigma modulated signal D2 to the amplitude modulating unit 18. The amplitude amplifying unit 16 may supply a current proportional to the magnitude of the input delta-sigma modulated signal D2 to the amplitude modulating unit 18.

  On the other hand, the phase signal is input to the angle modulation unit 17. The angle modulation unit 17 angle-modulates the phase signal and outputs it as an angle modulation signal. The angle modulation signal is input to the amplitude modulation unit 18. The amplitude modulation unit 18 amplifies the angle modulation signal in accordance with the voltage supplied from the amplitude amplification unit 16, thereby amplitude-modulating the angle modulation signal and outputting it as a modulation signal subjected to angle modulation and amplitude modulation. The band pass filter 19 removes quantization noise included in the modulation signal. The modulated signal from which the quantization noise has been removed by the bandpass filter 19 is output from the output terminal 21 as a transmission signal.

  In the transmission circuit 1, the division unit 13, the delta-sigma modulation unit 14, and the variable gain amplification unit 15 are based on the amplitude signal m (t) and the discrete value signal V (t) as shown in FIG. 2B. Since there is a configuration for generating a simple delta-sigma modulation signal D2, it can be collectively referred to as a delta-sigma modulation signal generation unit.

  Next, details of the amplitude calculator 12 will be described. An amplitude signal m (t) is input from the signal generator 11 to the amplitude calculator 12. The amplitude calculator 12 holds at least one threshold value and two or more discrete values corresponding to the one or more threshold values. The amplitude calculation unit 12 determines whether or not the maximum value of the amplitude signal m (t) exceeds one or more threshold values for each predetermined detection time T, and outputs a discrete value based on the determination result. select. Note that the amplitude calculation unit 12 determines whether any value included in the amplitude signal m (t) exceeds one or more threshold values at every predetermined detection time T, and based on the determination result. The discrete value to be output may be selected.

  FIG. 3 is a block diagram illustrating an example of the configuration of the amplitude calculation unit 12. In FIG. 3, the amplitude calculation unit 12 includes a maximum amplitude detection unit 121 and a quantization unit 122. In this case, the amplitude signal m (t) is input to the maximum amplitude detector 121 from the signal generator 11. The maximum amplitude detection unit 121 detects the maximum value of the amplitude signal m (t) every predetermined detection time T. FIG. 4A is a diagram illustrating an example of a waveform of the amplitude signal m (t) input to the maximum amplitude detection unit 121. Referring to FIG. 4A, detection time T is longer than the symbol time of the waveform of amplitude signal m (t) and shorter than the time for controlling the average output power of transmission circuit 1 (hereinafter referred to as slot time). Set to time. The maximum amplitude detector 121 detects the maximum value of the sampling points of the amplitude signal m (t) every detection time T. For example, if the detection time T is 16 times the symbol time and the sampling time is 8 times the symbol time, there are 1024 sampling points in the detection time T.

  The quantization unit 122 holds at least one threshold value and two or more discrete values corresponding to the one or more threshold values. The quantization unit 122 determines whether or not the maximum value of the amplitude signal m (t) exceeds one or more threshold values, and selects a discrete value to be output based on the determination result. FIG. 4B is a diagram illustrating an example of the waveform of the output signal of the quantization unit 122. In this example, it is assumed that the quantization unit 122 holds one threshold value A and two discrete values B1 and B2 corresponding to the threshold value A. However, B1> B2. As shown in FIG. 4B, the quantization unit 122 determines the discrete value B1 when the magnitude of the maximum value of the amplitude signal m (t) exceeds the threshold A, and discretes when the magnitude does not exceed the threshold A. The value B2 is selected and output as a discrete value signal V (t).

  In the above description, for the sake of simplification, the quantization unit 122 sets one threshold value A and outputs two discrete values B1 and B2. However, the quantization unit 122 has 2 It is possible to set three threshold values and output three discrete values, or set more threshold values and output many discrete values.

  FIG. 5 is a diagram illustrating the relationship between the amplitude signal m (t) and the discrete value signal V (t). However, the dotted line shows the discrete value signal output when the slot time is used instead of the detection time T for reference. As shown in FIG. 5, the amplitude calculation unit 12 sets the detection time T to a time shorter than the slot time, so that the time is shorter than the slot time according to the magnitude of the amplitude signal m (t). A controlled discrete value signal V (t) can be output. Thereby, the transmission circuit 1 can control the power of the transmission signal every time shorter than the slot time, and can reduce the power consumption as compared with the case where the power of the transmission signal is controlled every slot time. .

  Here, a method for determining the detection time T in the transmission circuit 1 according to the first embodiment will be described in a little more detail. As described above, the detection time T is set to a time longer than the symbol time of the waveform of the amplitude signal m (t) and shorter than the slot time. Is done. In the case of the W-CDMA system, the symbol time is set to 0.26 μs (1 / 3.84 MHz), and the slot time is set to 666 μs.

  The transmission circuit 1 is required by the amplitude amplifying unit 16 when the detection time T is set longer in a range that is longer than the symbol time of the waveform of the amplitude signal m (t) and satisfies the time shorter than the slot time. The speed is relatively low. For this reason, especially when the amplitude amplifying unit 16 is configured by a switching regulator, there is an advantage that the efficiency of the amplitude amplifying unit 16 is increased. However, by setting the detection time T longer, even if the amplitude signal m (t) is small, the section where the output signal of the amplitude amplifying unit 16 remains high increases, so that the loss as the transmission circuit 1 increases. become.

  On the other hand, when the transmission circuit 1 sets the detection time T shorter than the symbol time of the waveform of the amplitude signal m (t) and satisfies the time shorter than the slot time, the transmission circuit 1 Since the output signal is finely controlled according to the magnitude of the amplitude signal m (t), there is an advantage that the loss as the transmission circuit 1 is reduced. However, by setting the detection time T short, the speed required for the amplitude amplifying unit 16 becomes relatively high, and the efficiency of the amplitude amplifying unit 16 decreases. That is, the detection time T is set so that the transmission circuit 1 operates most efficiently in consideration of these trade-off relationships.

  Next, details of the amplitude amplifying unit 16 will be described. In order to supply a stable voltage to the amplitude modulating unit 18, the amplitude amplifying unit 16 is constituted by, for example, a series regulator or a switching regulator. FIG. 6A is a block diagram illustrating an example of the configuration of the series regulator 16a. 6A, the series regulator 16a includes an input terminal 161a, a comparator 162, a power supply terminal 163a, a transistor 164, and an output terminal 165a. Here, the transistor 164 is a field-effect transistor. The delta-sigma modulation signal D2 is input to the input terminal 161a via the variable gain amplifier 15. The delta sigma modulation signal D2 is input to the gate terminal of the transistor 164 via the comparator 162. A DC voltage is supplied to the drain terminal of the transistor 164 from the power supply terminal 163a.

  The transistor 164 outputs a voltage proportional to the magnitude of the input delta-sigma modulation signal D2 from the source terminal. The voltage output from the source terminal of the transistor 164 is fed back to the comparator 162. The comparator 162 adjusts the magnitude of the delta-sigma modulation signal D2 input to the gate terminal of the transistor 164 based on the fed back voltage. In this way, the series regulator 16a can stably supply a voltage corresponding to the magnitude of the delta-sigma modulation signal D2 from the output terminal 165a. Note that even if the transistor 164 is a bipolar transistor, the same effect can be obtained.

  FIG. 6B is a block diagram illustrating an example of the configuration of the switching regulator 16b. 6B, the switching regulator 16b includes an input terminal 161b, a signal conversion unit 166, a power supply terminal 163b, an amplifier 167, a low-pass filter 168, and an output terminal 165b. The delta-sigma modulation signal D2 is input to the input terminal 161b via the variable gain amplifier 15. The signal converter 166 converts the signal input via the input terminal 161b into a switching signal such as PWM. The signal converted by the signal conversion unit 166 is input to the amplifier 167. The amplifier 167 amplifies the input signal and outputs it. Note that a DC voltage is supplied to the amplifier 167 from the power supply terminal 163b. The amplifier 167 is a high efficiency switching amplifier such as a class D amplifier.

  The signal output from the amplifier 167 is input to the low pass filter 168. The low-pass filter 168 removes spurious components such as quantization noise and switching noise from the signal output from the amplifier 167. The signal from which the spurious component has been removed by the low-pass filter 168 is output from the output terminal 165b as a voltage corresponding to the magnitude of the delta-sigma modulation signal D2. Note that the switching regulator 16b may feed back the signal output from the low-pass filter 168 to the signal converter 166 in order to stabilize the output voltage.

  Further, since the delta-sigma modulation signal D2 whose magnitude changes discretely as shown in FIG. 2B is input to the switching regulator, it can also be configured as a switching regulator 16c shown in FIG. 6C. FIG. 6C is a block diagram illustrating an example of the configuration of the switching regulator 16c. In FIG. 6C, the switching regulator 16c does not include the signal conversion unit 166 and the low-pass filter 168, as compared with the switching regulator 16b illustrated in FIG. 6B. The amplifier 167 amplifies and outputs the delta sigma modulation signal D2 input via the input terminal 161b. The amplifier 167 is a high efficiency switching amplifier such as a class D amplifier.

  Further, the amplitude amplifying unit 16 may be configured by a current drive type regulator. FIG. 6D is a block diagram illustrating an example of the configuration of the current-driven regulator 16d. 6D, the current drive type regulator 16d includes an input terminal 161d, a power supply terminal 163d, a variable current source 169, a transistor 164x, a transistor 164y, and an output terminal 165d. The delta-sigma modulation signal D2 is input from the variable gain amplifier 15 to the input terminal 161d. A DC voltage is supplied to the power supply terminal 163d. The delta sigma modulation signal D2 input via the input terminal 161d is output from the output terminal 165d as a current corresponding to the magnitude of the delta sigma modulation signal D2 via the variable current source 169, the transistor 164x, and the transistor 164y. Is done. Such a current drive type regulator 16d is useful when the amplitude modulation section 18 is composed of a bipolar transistor. Note that the transistor 164x and the transistor 164y can obtain the same effects regardless of whether they are field effect transistors or bipolar transistors.

  FIG. 7A is a block diagram illustrating an example of the configuration of the amplitude modulation unit 18. 7A, the amplitude modulation unit 18 includes an input terminal 181, a matching circuit 182, a bias circuit 183, a power supply terminal 184, a power supply terminal 185, a bias circuit 186, a transistor 187, a matching circuit 188, and an output terminal 189. Here, the transistor 187 is a bipolar transistor. An angle modulation signal is input from the angle modulation unit 17 to the input terminal 181. The angle modulation signal is input to the base terminal of the transistor 187 via the matching circuit 182.

  A DC voltage is applied to the power supply terminal 184. That is, a bias voltage is supplied to the base terminal of the transistor 187 via the power supply terminal 184 and the bias circuit 183. A voltage corresponding to the magnitude of the delta-sigma modulation signal D2 is supplied from the amplitude amplifying unit 16 to the power supply terminal 185. A voltage corresponding to the magnitude of the delta-sigma modulation signal D2 is supplied to the collector terminal of the transistor 187 via the bias circuit 186. The transistor 187 amplifies and outputs the angle modulation signal with a voltage corresponding to the magnitude of the delta sigma modulation signal D2.

The modulation signal output from the transistor 187 is output as a transmission signal from the output terminal 189 via the matching circuit 188. Note that the transistor 187 is a field effect transistor, and the same effect can be obtained. The amplitude modulation unit 18 a includes a power supply terminal 184 may be interchanged voltage input to the power supply terminal 185, also in this case, it is possible to obtain the same effect. When the amplitude amplifying unit 16 is configured by a current-driven regulator 16d, a current corresponding to the magnitude of the delta-sigma modulation signal D2 is input from the current-driven regulator 16d to the power supply terminal 185. In this case, a current corresponding to the magnitude of the delta-sigma modulation signal D2 is input to the collector terminal of the transistor 187 via the bias circuit 186. The transistor 187 amplifies the angle modulation signal with a current corresponding to the magnitude of the delta sigma modulation signal D2, and outputs the amplified signal.

  The amplitude modulation unit 18 may have a configuration different from the amplitude modulation unit 18a described above. FIG. 7B is a block diagram illustrating an example of the configuration of the amplitude modulation unit 18b. In FIG. 7B, the amplitude modulation unit 18b basically has a configuration in which two of the above-described amplitude modulation units 18a are connected in series. Here, the transistor 187 and the transistor 191 are bipolar transistors. A bias voltage is supplied from the power supply terminal 184 to the base terminal of the transistor 187 via the bias circuit 183. A bias voltage is supplied from the power supply terminal 190 to the base terminal of the transistor 191 through the bias circuit 194.

  A voltage corresponding to the magnitude of the delta-sigma modulation signal D2 is supplied from the amplitude amplifying unit 16 to the collector terminal of the transistor 187 via the power supply terminal 185 and the bias circuit 186. In addition, a voltage corresponding to the magnitude of the delta-sigma modulation signal D2 is supplied from the amplitude amplifying unit 16 to the collector terminal of the transistor 191 via the power supply terminal 185 and the bias circuit 192. With such a configuration, the amplitude modulation unit 18b can output a modulation signal having a larger dynamic range as compared with the amplitude modulation unit 18a illustrated in FIG. 7A. Note that the same effect can be obtained when the transistor 187 and the transistor 191 are field-effect transistors. Further, the voltages supplied to the two bias circuits 186 and 192 need not be exactly the same. That is, the voltage supplied to one bias circuit may be a fixed voltage, and only the voltage supplied to the other bias circuit may be a voltage corresponding to the magnitude of the delta-sigma modulation signal D2.

  Note that the transmission circuit 1 described above may be configured not to include the bandpass filter 19 when the output signal of the amplitude modulation unit 18 does not include much quantization noise. Further, the transmission circuit 1 is configured to include a low-pass filter (LPF) 19a between the amplitude amplification unit 16 and the amplitude modulation unit 18 instead of the bandpass filter 19 as in the transmission circuit 1a illustrated in FIG. 8A. May be. FIG. 8A is a block diagram showing an example of the configuration of the transmission circuit 1a according to the first embodiment of the present invention. In FIG. 8A, the low-pass filter 19a removes quantization noise from the signal output from the amplitude amplifying unit 16. Although not shown, the transmission circuit 1 may be configured to include a low-pass filter 19 a between the delta-sigma modulation signal generation unit and the amplitude amplification unit 16. In this case, the low pass filter 19a removes quantization noise from the delta sigma modulation signal output from the delta sigma modulation signal generation unit.

  Here, the difference between the transmission circuit 1 shown in FIG. 1 and the transmission circuit 1a shown in FIG. 8A will be described in a little more detail. As shown in FIG. 1, when the band pass filter 19 is provided in the subsequent stage of the amplitude modulation unit 18, the band pass filter 19 needs to control the frequency band to pass through according to the frequency of the modulation signal. On the other hand, when the low-pass filter 19a is provided in the previous stage of the amplitude modulation unit 18 as shown in FIG. 8A, the low-pass filter 19a does not need to control the frequency band to pass according to the frequency of the modulation signal. That is, it is possible to remove the quantization noise with simpler control if the low-pass filter 19a is provided in the previous stage of the amplitude modulation unit 18.

  However, when the low-pass filter 19a is provided in the previous stage of the amplitude modulation unit 18 as shown in FIG. 8A, the amplitude modulation unit 18 needs to perform amplitude modulation linearly using a signal input via the low-pass filter 19a. Thus, the amplitude modulation unit 18 is required to have high linearity. On the other hand, when the band-pass filter 19 is provided in the subsequent stage of the amplitude modulation unit 18 as shown in FIG. 1, a signal whose magnitude varies discretely from the amplitude amplification unit 16 is input to the amplitude modulation unit 18. The linearity required for the amplitude modulation unit 18 is alleviated. In consideration of such merits and demerits, the transmission circuit is designed.

  Further, the transmission circuit 1 described above may have a different configuration of the delta-sigma modulation signal generation unit, like the transmission circuit 1b illustrated in FIG. 8B. FIG. 8B is a block diagram showing an example of the configuration of the transmission circuit 1b according to the first embodiment of the present invention. 8B, the transmission circuit 1b includes a signal generation unit 11, an amplitude calculation unit 12, a delta sigma modulation unit 14b, an amplitude amplification unit 16, an angle modulation unit 17, an amplitude modulation unit 18, a band pass filter 19, a power supply terminal 20, and An output terminal 21 is provided. The delta sigma modulation signal generation unit includes a delta sigma modulation unit 14b. The amplitude signal m (t) and the discrete value signal V (t) are input to the delta sigma modulation unit 14b.

  The delta sigma modulation unit 14b changes the magnitude of the output delta sigma modulation signal so that the magnitude of the discrete value signal V (t) is positively related. Typically, the delta sigma modulation unit 14b changes the magnitude of the output delta sigma modulation signal so that the magnitude of the discrete value signal V (t) is directly proportional. Specifically, the delta sigma modulation unit 14b refers to a lookup table in which an optimum value is set in advance, or performs predetermined arithmetic processing based on the discrete value signal V (t) to output the delta sigma output. The magnitude of the modulation signal is calculated. Thereby, the delta-sigma modulation signal generation unit can output the same delta-sigma modulation signal as in FIG. 2B. As a specific example of changing the magnitude of the output delta sigma modulation signal, for example, when the discrete value signal V (t) is small, the input of the quantizer included in the delta sigma modulation unit 14b is 1 1 is output in the above case, otherwise 0 is output. When the discrete value signal V (t) is large, the quantizer included in the delta-sigma modulation unit 14b has an input of 2 or more. In some cases, 2 may be output, and 0 may be output otherwise.

  Further, the transmission circuit 1 described above may be configured such that the signal generation unit 11c generates an angle modulation signal instead of the angle modulation unit, like the transmission circuit 1c illustrated in FIG. 8C. FIG. 8C is a block diagram showing an example of the configuration of the transmission circuit 1c according to the first embodiment of the present invention. In FIG. 8C, the signal generation unit 11c performs predetermined signal processing on the input data to generate an amplitude signal m (t) and an angle modulation signal. FIG. 8D is a block diagram illustrating an example of the configuration of the signal generation unit 11c. 8D, the signal generation unit 11c includes an orthogonal signal generation unit 111, a vector modulation unit 112, an envelope detection unit 113, and a limiter 114. The orthogonal signal generation unit 111 performs signal processing on input data to generate a vector signal composed of an I signal and a Q signal that are orthogonal to each other. The vector signal is input to the vector modulation unit 112.

  The vector modulation unit 112 performs vector modulation on the vector signal. For example, a quadrature modulator is used for the vector modulation unit 112. The signal output from the vector modulation unit 112 is input to the envelope detection unit 113 and the limiter 114. The envelope detector 113 detects the envelope component of the signal output from the vector modulator 112, and outputs the detected envelope component as an amplitude signal m (t). The limiter 114 limits the envelope component of the signal output from the vector modulation unit 112 to a certain size, and outputs a signal whose size is limited as an angle modulation signal. The subsequent operation is the same as the operation of the transmission circuit 1.

  As described above, according to the transmission circuit 1 according to the first embodiment of the present invention, the delta sigma modulation unit 14 performs delta sigma modulation on the amplitude signal M (t) with a small envelope variation. Quantization noise generated during modulation can be reduced. For this reason, a steep characteristic is not required for a filter for reducing quantization noise, and power consumption and size can be reduced. As a result, the transmission circuit 1 can operate with small size and high efficiency, and can output a highly linear transmission signal.

(Second Embodiment)
FIG. 9 is a block diagram showing an example of the configuration of the transmission circuit 2 according to the second embodiment of the present invention. 9, the transmission circuit 2 includes a signal generation unit 11, an amplitude calculation unit 12, a division unit 13, a delta sigma modulation unit 14, a variable gain amplification unit 15, an amplitude amplification unit 26, an angle modulation unit 17, and an amplitude modulation unit 18. A band pass filter 19, a power supply terminal 20, and an output terminal 21. The transmission circuit 2 is different from the first embodiment in the configuration of the amplitude amplifying unit 26. The amplitude amplifying unit 26 includes a series regulator 26a and a switching regulator 26b. In the transmission circuit 2, the same components as those of the transmission circuit 1 are denoted by the same reference numerals and description thereof is omitted.

  The discrete value signal V (t) is input from the amplitude calculator 12 to the switching regulator 26b. The switching regulator 26 b is supplied with a DC voltage from the power supply terminal 20. The switching regulator 26b supplies a voltage corresponding to the magnitude of the discrete value signal V (t) to the series regulator 26a. The series regulator 26a receives the delta sigma modulation signal D2 from the variable gain amplifier 15. The series regulator 26a amplifies the input delta sigma modulation signal D2 with the voltage supplied from the switching regulator 26b, thereby supplying a voltage corresponding to the magnitude of the delta sigma modulation signal D2 to the amplitude modulation unit 18.

  Since the voltage supplied from the switching regulator 26b is controlled according to the magnitude of the discrete value signal V (t), the series regulator 26a can operate with high efficiency. The series regulator 26a can be configured similarly to the series regulator 16a shown in FIG. 6A. The switching regulator 26b can be configured similarly to the switching regulator 16b shown in FIG. 6B or the switching regulator 16c shown in FIG. 6C. The above-described amplitude amplifying unit 26 can be applied to any of the transmission circuits illustrated in FIGS. 8A, 8B, and 8C.

  Further, the transmission circuit 2 may be configured to further include a timing control unit 25a as in the transmission circuit 2a illustrated in FIG. 10A. FIG. 10A is a block diagram showing an example of the configuration of the transmission circuit 2a according to the second embodiment of the present invention. In FIG. 10A, the timing controller 25a is connected between the amplitude calculator 12 and the switching regulator 26b. The timing controller 25a controls the timing at which the discrete value signal V (t) output from the amplitude calculator 12 is input to the switching regulator 26b so as to compensate for the rise of the switching regulator 26b.

  FIG. 10B is a diagram illustrating an example of a timing chart of signals handled by the transmission circuit 2a. Hereinafter, the operation of the transmission circuit 2a will be described with reference to FIG. 10B. The amplitude calculator 12 receives the amplitude signal m (t) from the signal generator 11 (see FIG. 10B (a)). The amplitude calculator 12 performs the same processing as in the first embodiment and outputs a discrete value signal V (t) (see FIG. 10B (b)). The discrete value signal V (t) is input to the timing control unit 25a.

  The timing controller 25a advances the timing for outputting the discrete value signal V (t) by Δtx to compensate for the rise of the switching regulator 26b, and outputs it as a discrete value signal Vx (t) (FIG. 10B (c)). reference). The discrete value signal Vx (t) is input to the switching regulator 26b. The switching regulator 26b supplies a voltage Vy (t) corresponding to the magnitude of the discrete value signal Vx (t) to the series regulator 26a (see FIG. 10B (d)). The series regulator 26a supplies a voltage Vz (t) corresponding to the magnitude of the delta-sigma modulation signal D2 to the amplitude modulator 18 (see FIG. 10B (e)).

  As described above, the transmission circuit 2a includes the timing control unit 25a between the amplitude calculation unit 12 and the switching regulator 26b, thereby eliminating the instability of the rising of the switching regulator 26b and performing further low-distortion operation. Can be realized. Instead of the timing control unit 25a advancing the timing of outputting the discrete value signal V (t) by Δtx, the amplitude signal m (t) output from the signal generation unit 11 to the division unit 13 side and the angle modulation unit The phase signal output to 17 may be delayed by Δtx.

  Further, the transmission circuit 2 may have a configuration in which the series regulator 26a included in the amplitude amplifying unit 26 is replaced with a switching regulator 26c as in the transmission circuit 2b illustrated in FIG. 11A or the transmission circuit 2b illustrated in FIG. 11B. FIG. 11A is a block diagram showing an example of the configuration of the transmission circuit 2b according to the second embodiment of the present invention. FIG. 11B is a block diagram showing an example of the configuration of the transmission circuit 2c according to the second embodiment of the present invention. 11A and 11B, the switching regulator 26c can be configured similarly to the switching regulator 16b shown in FIG. 6B or the switching regulator 16c shown in FIG. 6C. The transmission circuit 2 can operate with high efficiency by including the switching regulator 26c instead of the series regulator 26a.

  Further, the transmission circuit 2 may have a configuration including an amplitude amplifying unit 26 including a series regulator 26a1, a series regulator 26a2, a switching regulator 26b, and a switch, like the transmission circuit 2d illustrated in FIG. 11C. Good. The series regulator 26a1 and the series regulator 26a2 are different in size. Here, the size of the series regulator 26a1 is smaller than that of the series regulator 26a2. The amplitude amplifying unit 26 switches the connection between the series regulators 26a1 and 26a2 and the amplitude modulating unit 18 according to the magnitude of the discrete value signal V (t) output from the amplitude calculating unit 12.

  The operation of the amplitude amplifying unit 26 at this time will be specifically described with reference to FIG. 11D. FIG. 11D is a diagram illustrating an example of a waveform of the delta-sigma modulation signal D2 (t) output from the variable gain amplification unit 15. Since the delta-sigma modulation signal D2 (t) and the discrete value signal V (t) are proportional to each other, in the example shown in FIG. 11D, the magnitude of the discrete value signal V (t) is small in the section T1, It is large in the section T2 and small in the section T3. When the magnitude of the discrete value signal V (t) is smaller than a predetermined threshold (that is, in the sections T1 and T3), the amplitude amplifying unit 26 is connected to the series regulator 26a1 and the amplitude amplifying unit 18. When the magnitude of the discrete value signal V (t) is equal to or greater than a predetermined threshold (that is, in the section T2), the switch is set so that the series regulator 26a2 and the amplitude amplifying unit 18 are connected. Switch. As a result, the transmission circuit 2d can select a series regulator having an optimal size according to the magnitude of the discrete value signal V (t), and thus can operate with higher efficiency.

  Further, the transmission circuit 2d may have a configuration in which the series regulators 26a1 and 26a2 are replaced with switching regulators 26c1 and 26c2 as in the transmission circuit 2e illustrated in FIG. 11E. Although not shown, the transmission circuits 2d and 2e may further include a timing control unit 25a.

  As described above, according to the transmission circuit 2 according to the second embodiment of the present invention, the amplitude amplifying unit 26 includes the series regulator 26a and the switching regulator 26b, and uses the characteristics of the series regulator 26a and the switching regulator 26b. Then, a voltage corresponding to the magnitude of the delta-sigma modulation signal D2 is supplied to the amplitude modulation unit 18. As a result, the transmission circuit 2 can operate with higher efficiency and lower distortion.

  Further, the transmission circuit 2 includes the timing control unit 25a in the subsequent stage of the amplitude calculation unit 12, thereby eliminating the instability of rising of the switching regulator 26b and realizing an operation with lower distortion.

(Third embodiment)
FIG. 12 is a block diagram showing an example of the configuration of the transmission circuit 3 according to the third embodiment of the present invention. In FIG. 12, the transmission circuit 3 includes a multiplication unit 27 in the subsequent stage of the signal generation unit 11 compared to the transmission circuit 1 according to the first embodiment. FIG. 13 is a diagram for explaining the operation of the transmission circuit 3 according to the third embodiment of the present invention. The multiplier 27 receives power information P output from the baseband and indicating the magnitude of the output power of the transmission circuit (see FIG. 13A). For example, in the case of a W-CDMA system, the power information P is controlled by a base station, and transmission power control with the base station is performed every slot time. Note that the transmission circuit 3 may be configured such that the signal generation unit 11 outputs the power information P based on information from the base station.

  The multiplier 27 multiplies the power information P and the amplitude signal m (t) and outputs the result as a power-controlled amplitude signal mp (t) (see FIG. 13B). The amplitude calculation unit 12 performs the same processing as in the first embodiment, selects a discrete value according to the maximum value of the amplitude signal mp (t) for each predetermined time, and discretes the selected discrete value. A value signal Vp (t) is output (see FIG. 13C). In this example, the amplitude calculation unit 12 holds three threshold values and four discrete values. Since the subsequent operation of the transmission circuit 3 is the same as that of the first embodiment, the description thereof is omitted. Although not shown, such a multiplication unit 27 can be applied to any of the transmission circuits shown in FIGS. 8A, 8B, and 8C.

  Further, the transmission circuit 3 according to the third embodiment can be applied to the transmission circuit 2 according to the second embodiment as in the transmission circuit 3a illustrated in FIG. 14A. FIG. 14A is a block diagram showing an example of the configuration of the transmission circuit 3a according to the third embodiment of the present invention. In FIG. 14A, the transmission circuit 3a further includes a multiplication unit 27a in the subsequent stage of the signal generation unit 11, as compared with the transmission circuit 2 according to the second embodiment. The operations of the multiplication unit 27a and the amplitude calculation unit 12 are the same as those of the transmission circuit 3 described above.

  Moreover, the transmission circuit 3a described above may be configured to include a multiplication unit 27b between the amplitude calculation unit 12 and the switching regulator 26b, as in the transmission circuit 3b illustrated in FIG. 14B. FIG. 14B is a block diagram showing an example of the configuration of the transmission circuit 3b according to the third embodiment of the present invention. In FIG. 14B, the multiplication unit 27b multiplies the discrete value signal V (t) and the power information P, and outputs the result as a power-controlled discrete value signal Vp (t). The discrete value signal Vp (t) is input to the variable gain amplifier 15 and the switching regulator 26b. Since the subsequent operation of the transmission circuit 3a is the same as that of the second embodiment, the description thereof is omitted.

  Further, the transmission circuit 3a described above may be configured to include a multiplication unit 27c between the amplitude calculation unit 12 and the variable gain amplification unit 15 as in the transmission circuit 3c illustrated in FIG. 14C. FIG. 14C is a block diagram showing an example of the configuration of the transmission circuit 3c according to the third embodiment of the present invention. In FIG. 14C, the multiplication unit 27c multiplies the discrete value signal V (t) and the power information P, and outputs the result as a power-controlled discrete value signal Vp (t). The discrete value signal Vp (t) is input to the variable gain amplifier 15. In addition, power information P is input to the switching regulator 26b. The switching regulator 26b supplies a voltage corresponding to the power information P to the series regulator 26a. Since the voltage supplied from the switching regulator 26b is controlled by the power information P, the series regulator 26a can operate with high efficiency. Although not shown, such multiplication units 27a to 27c are applicable to any of the transmission circuits in FIGS. 10A, 11A, 11B, 11C, and 11E.

  As described above, according to the transmission circuit 3 according to the third embodiment of the present invention, the amplitude amplifying units 16 and 26 are based on the power information P indicating the magnitude of the output power of the transmission circuit. By adjusting the voltage to be supplied to the optimum level for the amplitude modulation section 18, it is possible to realize an operation with higher efficiency and lower distortion.

(Fourth embodiment)
FIG. 15 is a block diagram showing an example of the configuration of the transmission circuit 4 according to the fourth embodiment of the present invention. In FIG. 15, the transmission circuit 4 includes a signal generation unit 41, an amplitude calculation unit 42, a division unit 43, a signal processing unit 44, a vector modulation unit 45, a variable gain amplification unit 46, an amplitude amplification unit 47, a power supply terminal 48, and an amplification. Part 49, band-pass filter 50, and output terminal 51. The signal generation unit 41 generates an amplitude signal m (t) and a vector signal composed of an I signal and a Q signal orthogonal to each other based on the input data. The amplitude signal m (t) can be expressed using (Expression 2). The amplitude signal m (t) is input to the amplitude calculation unit 42. The I signal and the Q signal are input to the division unit 43.
m (t) = (I ² + Q ² ) ^1/2 (Formula 2)

The amplitude calculator 42 performs the same operation as the amplitude calculator 12 described above, and outputs a discrete value signal V (t). The discrete value signal V (t) is input to the division unit 43, the variable gain amplification unit 46, and the amplitude amplification unit 47. The division unit 43 divides the I signal and the Q signal by the discrete value signal V (t) and outputs the result as an Iv signal and a Qv signal. The Iv signal and the Qv signal can be expressed using (Equation 3).
Iv, Qv = I / V (t), Q / V (t) (Formula 3)

  The Iv signal and Qv signal output from the division unit 43 are input to the signal processing unit 44. The signal processing unit 44 quantizes the input Iv signal and Qv signal based on predetermined signal processing, and outputs the quantized signal. Details of the signal processing unit 44 will be described later. The quantized signal output from the signal processing unit 44 is input to the vector modulation unit 45. The vector modulation unit 45 vector-modulates the input quantized signal and outputs it as a modulated signal. The modulation signal output from the vector modulation unit 45 is input to the variable gain amplification unit 46. The variable gain amplifier 46 amplifies the modulated signal with a gain corresponding to the magnitude of the discrete value signal V (t). The modulated signal amplified by the variable gain amplifier 46 is input to the amplifier 49.

  A DC voltage is supplied from the power supply terminal 48 to the amplitude amplifying unit 47. The amplitude amplifying unit 47 supplies a voltage corresponding to the magnitude of the discrete value signal V (t) input from the amplitude calculating unit 42 to the amplifying unit 49. Typically, the amplitude amplifying unit 47 supplies a voltage proportional to the magnitude of the discrete value signal V (t) to the amplifying unit 49. Note that the amplitude amplifying unit 47 may supply a current proportional to the magnitude of the discrete value signal V (t) to the amplifying unit 49. The amplifying unit 49 amplifies the input modulation signal according to the voltage supplied from the amplitude amplifying unit 47. The band pass filter 50 removes quantization noise included in the modulation signal. The signal from which the quantization noise has been removed by the bandpass filter 50 is output from the output terminal 51 as a transmission signal.

  As the amplitude amplifying unit 47, a series regulator, a switching regulator, a current drive type regulator, or the like can be used. The series regulator can be configured similarly to the series regulator 16a shown in FIG. 6A. The switching regulator can have the same configuration as the switching regulator 16b shown in FIG. 6B or the switching regulator 16c shown in FIG. 6C. The current drive regulator can be configured in the same manner as the current drive regulator 16d shown in FIG. 6D. The amplification unit 49 can be configured in the same manner as the amplitude modulation units 18a and 18b shown in FIG. 7A or 7B.

  In the transmission circuit 4, the division unit 43, the signal processing unit 44, the vector modulation unit 45, and the variable gain amplification unit 46 modulate and amplify the I signal and the Q signal based on the discrete value signal V (t). Since this is a configuration for generating the modulation signal input to the unit 49, it can be collectively referred to as a modulation signal generation unit.

Next, details of the signal processing unit 44a will be described. FIG. 16A is a block diagram illustrating an example of the configuration of the signal processing unit 44a. 16A, the signal processing unit 44a includes a signal conversion unit 441, a delta-sigma modulation unit 442, a multiplication unit 443, and a multiplication unit 444. The Iv signal and the Qv signal are input from the division unit 43 to the signal conversion unit 441. Based on the input Iv signal and Qv signal, the signal conversion unit 441 outputs an amplitude signal mv (t) indicating the magnitude of the Iv signal and the Qv signal, a normalized Iv signal, and a normalized Qv signal. The amplitude signal mv (t) can be expressed using (Equation 4).
mv (t) = (Iv ² + Qv ² ) ^1/2 (Formula 4)

  The normalized Iv signal is calculated by dividing the input Iv signal by the amplitude signal mv (t). Similarly, the normalized Qv signal is calculated by dividing the input Qv signal by the amplitude signal mv (t). Note that the normalized Iv signal and the normalized Qv signal may be referred to as a normalized vector signal.

  The amplitude signal mv (t) is input to the delta sigma modulation unit 442. The delta sigma modulation unit 442 performs delta sigma modulation on the amplitude signal mv (t) and outputs it as a delta sigma modulation signal. The multiplication unit 443 multiplies the normalized Iv signal and the delta-sigma modulation signal, and outputs the multiplied signal as first data. The multiplication unit 444 multiplies the normalized Qv signal and the delta sigma modulation signal, and outputs the multiplied signal as second data. The first data and the second data are output from the signal processing unit 44a as quantized signals.

  FIG. 16B is a block diagram illustrating an example of the configuration of the signal processing unit 44b. In FIG. 16B, the signal processing unit 44b includes a vector subtraction unit 445, a vector integration unit 446, and a vector quantization unit 447. In FIG. 16B, the Iv signal and the Qv signal are input from the division unit 43 to the signal processing unit 44b. The Iv signal and the Qv signal are input to the vector integration unit 446 via the vector subtraction unit 445. The vector integration unit 446 integrates and outputs the Iv signal and the Qv signal. The signal output from the vector integration unit 446 is input to the vector quantization unit 447. The vector quantization unit 447 quantizes the input signal and outputs it as a quantized signal. The vector subtraction unit 445 subtracts the output of the vector quantization unit 447 from the Iv signal and Qv signal and outputs the result to the vector integration unit 446. The vector subtraction unit 445 and the vector integration unit 446 may be collectively referred to as a vector calculation unit.

  FIG. 16C is a block diagram illustrating an example of the configuration of the signal processing unit 44c. 16C, the signal processing unit 44c includes a plurality of vector subtraction units 445, a plurality of vector integration units 446, and a vector quantization unit 447. Since the operations of the vector subtraction unit 445, the vector integration unit 446, and the vector quantization unit 447 are the same as those described with reference to FIG. 16B, detailed description thereof is omitted.

  Further, the transmission circuit 4 described above may be configured not to include the band pass filter 50 when the output signal of the amplification unit 49 does not include much quantization noise. Further, as illustrated in FIG. 17A, the transmission circuit 4 may be configured to include a low-pass filter 50 a between the amplitude amplifying unit 47 and the amplifying unit 49 instead of the band-pass filter 50. FIG. 17A is a block diagram showing an example of a configuration of a transmission circuit 4a according to the fourth embodiment of the present invention. In FIG. 17A, the low pass filter 50a removes quantization noise from the signal output from the amplitude amplifying unit 47.

  Further, the transmission circuit 4 described above may have a configuration in which the positions of the vector modulation unit 45 and the variable gain amplification unit 46 are interchanged as in the transmission circuit 4b illustrated in FIG. 17B. FIG. 17B is a block diagram showing an example of the configuration of the transmission circuit 4b according to the fourth embodiment of the present invention. In FIG. 17B, the quantized signal is input from the signal processing unit 44 to the variable gain amplification unit 46. The variable gain amplifier 46 amplifies the quantized signal with a gain corresponding to the magnitude of the discrete value signal V (t). The vector modulation unit 45 vector-modulates the quantized signal amplified by the variable gain amplification unit 46 and outputs it as a modulation signal. In the transmission circuit 4b, the operations other than the variable gain amplification unit 46 and the vector modulation unit 45 are the same as those of the transmission circuit 4.

  Further, the transmission circuit 4 described above may be configured as a transmission circuit 4c shown in FIG. 17C. FIG. 17C is a block diagram illustrating an example of a configuration of a transmission circuit 4c according to the fourth embodiment of the present invention. 17C, the transmission circuit 4c includes a signal generation unit 41, an amplitude calculation unit 42, a signal processing unit 44c, a vector modulation unit 45, an amplitude amplification unit 47, a power supply terminal 48, an amplification unit 49, a bandpass filter 50, and an output terminal. 51 is provided. The signal processing unit 44c receives the I and Q signals and the discrete value signal V (t). The signal processing unit 44c changes the magnitude of the output signal so that the magnitude of the discrete value signal V (t) is positively related. Typically, the signal processing unit 44c changes the magnitude of the output signal so that the magnitude of the discrete value signal V (t) is directly proportional. As the signal processing unit 44c, the signal processing unit 44a shown in FIG. 16A or the signal processing unit 44b shown in FIG. 16B can be used.

  As described above, according to the transmission circuit 4 according to the fourth embodiment of the present invention, the signal processing unit 44 is calculated by dividing the I signal and the Q signal by the discrete value signal V (t). Since the Iv signal and the Qv signal are quantized, the quantization noise generated at the time of quantization can be reduced. For this reason, a steep characteristic is not required for a filter for reducing quantization noise, and power consumption and size can be reduced. As a result, the transmission circuit 4 can operate with a small size and high efficiency, and can output a highly linear transmission signal.

  In the transmission circuits according to the first to fourth embodiments described above, the amplitude calculation units 12 and 42 have a length of the predetermined time T depending on the modulation mode of the transmission signal in order to further reduce the power consumption of the transmission circuit. May be changed. FIG. 18 is a diagram for explaining the effect of reducing power consumption when the length of the predetermined time T is changed. As shown in FIG. 18A, when the fluctuation of the envelope of the transmission signal is small, the amplitude calculators 12 and 42 have little effect of reducing power consumption even if the predetermined time T is shortened. For this reason, the amplitude calculation units 12 and 42 change the predetermined time T longer. On the other hand, as shown in FIG. 18B, when the fluctuation of the envelope of the transmission signal is large, the signal processing units 12 and 42 can increase the power consumption reduction effect by shortening the predetermined time T. it can. For example, the amplitude calculators 12 and 42 shorten the predetermined time T in the 16QAM modulation mode because the envelope variation is larger in the 16QAM modulation mode than in the QPSK modulation mode. Thereby, the amplitude calculators 12 and 42 can further reduce the power consumption of the transmission circuit.

  Further, the transmission circuit according to the first to third embodiments described above compensates for distortion of the amplitude signal and / or the phase signal at the output of the signal generation unit 11 in order to compensate at least the nonlinearity of the amplitude modulation unit 18. The distortion compensation unit 22 may be further provided. For example, the transmission circuit 1 according to the first embodiment can be configured as a transmission circuit 1d shown in FIG. FIG. 19 is a block diagram illustrating an example of the configuration of the transmission circuit 1 d including the distortion compensation unit 22. In FIG. 19, the distortion compensator 22 compensates the amplitude signal and / or the phase signal generated by the signal generator 11 so that at least the distortion generated in the amplitude modulator 18 is suppressed. Thereby, the transmission circuit 1d can improve the linearity of the transmission signal as compared with the transmission circuit described above.

  The transmission circuit according to the fourth embodiment described above compensates for distortion of the amplitude signal and / or the I and Q signals at the output of the signal generation unit 41 in order to compensate at least the nonlinearity of the amplification unit 49. You may further provide the distortion compensation part 52. FIG. FIG. 20 is a block diagram illustrating an example of the configuration of the transmission circuit 4 d including the distortion compensation unit 52. In FIG. 20, the distortion compensation unit 52 compensates the amplitude signal generated by the signal generation unit 41 and / or the I and Q signals so that at least distortion generated in the amplification unit 49 is suppressed. Accordingly, the transmission circuit 4d can improve the linearity of the transmission signal as compared with the transmission circuit described above.

(Fifth embodiment)
FIG. 21 is a block diagram showing an example of the configuration of a communication device according to the fifth embodiment of the present invention. Referring to FIG. 21, the communication device 200 according to the fifth embodiment includes a transmission circuit 210, a reception circuit 220, an antenna sharing unit 230, and an antenna 240. The transmission circuit 210 is the transmission circuit according to any one of the first to fourth aspects described above. The antenna sharing unit 230 transmits the transmission signal output from the transmission circuit 210 to the antenna 240 and prevents the transmission signal from leaking to the reception circuit 220. The antenna sharing unit 230 transmits the reception signal input from the antenna 240 to the reception circuit 220 and prevents the reception signal from leaking to the transmission circuit 210.

  Therefore, the transmission signal is output from the transmission circuit 210 and emitted from the antenna 240 to the space via the antenna sharing unit 230. The received signal is received by the antenna 240 and received by the receiving circuit 220 via the antenna sharing unit 230. The communication device 200 according to the fifth embodiment can achieve low distortion as a wireless device while ensuring the linearity of the transmission signal by using the transmission circuit according to the first to fourth embodiments. it can. Further, since there is no branch such as a directional coupler in the output of the transmission circuit 210, loss from the transmission circuit 210 to the antenna 240 can be reduced, power consumption during transmission can be reduced, and wireless As a communication device, it can be used for a long time. Note that the communication device 200 may include only the transmission circuit 210 and the antenna 240.

  Although the present invention has been described in detail above, the above description is merely illustrative of the present invention in all respects and is not intended to limit the scope thereof. It goes without saying that various improvements and modifications can be made without departing from the scope of the present invention.

  The transmission circuit according to the present invention can be applied to communication devices such as mobile phones and wireless LANs.

1 is a block diagram showing an example of a configuration of a transmission circuit 1 according to a first embodiment of the present invention. The figure which shows an example of the waveform of the delta-sigma modulation signal D1 which the delta-sigma modulation part 14 outputs The figure which shows an example of the waveform of the delta-sigma modulation signal D2 which the variable gain amplifier 15 outputs The block diagram which shows an example of a structure of the amplitude calculating part 12 The figure which shows an example of the waveform of the amplitude signal m (t) input into the maximum amplitude detection part 121 The figure which shows an example of the waveform of the output signal of the quantization part 122 The figure which shows the relationship between amplitude signal m (t) and discrete value signal V (t) Block diagram showing an example of the configuration of the series regulator 16a Block diagram showing an example of the configuration of the switching regulator 16b Block diagram showing an example of the configuration of the switching regulator 16c The block diagram which shows an example of a structure of the current drive type regulator 16d The block diagram which shows an example of a structure of the amplitude modulation part 18a The block diagram which shows an example of a structure of the amplitude modulation part 18b The block diagram which shows an example of a structure of the transmission circuit 1a which concerns on the 1st Embodiment of this invention. The block diagram which shows an example of a structure of the transmission circuit 1b which concerns on the 1st Embodiment of this invention. The block diagram which shows an example of a structure of the transmission circuit 1c which concerns on the 1st Embodiment of this invention. The block diagram which shows an example of a structure of the signal generation part 11c. It is a block diagram which shows an example of a structure of the transmission circuit 2 which concerns on the 2nd Embodiment of this invention, The block diagram which shows an example of a structure of the transmission circuit 2a which concerns on the 2nd Embodiment of this invention. The figure which shows an example of the timing chart of the signal which the transmission circuit 2a handles The block diagram which shows an example of a structure of the transmission circuit 2b which concerns on the 2nd Embodiment of this invention. The block diagram which shows an example of a structure of the transmission circuit 2c which concerns on the 2nd Embodiment of this invention. The block diagram which shows an example of a structure of the transmission circuit 2d which concerns on the 2nd Embodiment of this invention. The figure which shows an example of the waveform of the delta-sigma modulation signal D2 which the variable gain amplifier 15 outputs The block diagram which shows an example of a structure of the transmission circuit 2e which concerns on the 2nd Embodiment of this invention. The block diagram which shows an example of a structure of the transmission circuit 3 which concerns on the 3rd Embodiment of this invention. The figure explaining operation | movement of the transmission circuit 3 which concerns on the 3rd Embodiment of this invention. The block diagram which shows an example of a structure of the transmission circuit 3a which concerns on the 3rd Embodiment of this invention. The block diagram which shows an example of a structure of the transmission circuit 3b which concerns on the 3rd Embodiment of this invention. The block diagram which shows an example of a structure of the transmission circuit 3c which concerns on the 3rd Embodiment of this invention. The block diagram which shows an example of a structure of the transmission circuit 4 which concerns on the 4th Embodiment of this invention. The block diagram which shows an example of a structure of the signal processing part 44a. The block diagram which shows an example of a structure of the signal processing part 44b. The block diagram which shows an example of a structure of the signal processing part 44c. The block diagram which shows an example of a structure of the transmission circuit 4a which concerns on the 4th Embodiment of this invention. The block diagram which shows an example of a structure of the transmission circuit 4b which concerns on the 4th Embodiment of this invention. The block diagram which shows an example of a structure of the transmission circuit 4c which concerns on the 4th Embodiment of this invention. The figure explaining the reduction effect of the power consumption at the time of changing the length of the predetermined time T The block diagram which shows an example of a structure of the transmission circuit 1d provided with the distortion compensation part 22. The block diagram which shows an example of a structure of the transmission circuit 4d provided with the distortion compensation part 52 The block diagram which shows an example of a structure of the communication apparatus which concerns on the 5th Embodiment of this invention. A block diagram showing an example of a configuration of a conventional transmission circuit 700 A block diagram showing an example of a configuration of a conventional transmission circuit 800 The block diagram which shows an example of a structure of the data generation part 81 A block diagram showing an example of a configuration of a conventional transmission circuit 900 The block diagram which shows an example of a structure of the data conversion part 92

Explanation of symbols

1 to 4 Transmitter circuit 11, 11c Signal generator 111 Orthogonal signal generator 112 Vector modulator 113 Envelope detector 114 Limiter 12 Amplitude calculator 121 Maximum amplitude detector 122 Quantizer 123 DA converter (DAC)
13 Division Unit 14 Delta Sigma Modulation Unit 15 Variable Gain Amplification Unit 16, 26 Regulator 16a Series Regulator 16b Switching Regulator 16c Current Drive Type Regulator 161 Input Terminal 162 Comparator 163 Power Supply Terminal 164 Transistor 165 Output Terminal 166 Signal Conversion Unit 167 Amplifier 168 Low-pass filter 169 Variable current source 17 Angle modulation unit 18 Amplitude modulation unit 181 Input terminal 182, 188, 193 Matching circuit 183, 186, 192, 194 Bias circuit 184, 185, 190 Power supply terminal 187, 191 Transistor 189 Output terminal 19 Band pass Filter (BPF)
19a Low-pass filter (LPF)
20 power supply terminal 21 output terminal 22 distortion compensation unit 27 multiplication unit 41 signal generation unit 42 amplitude calculation unit 43 division unit 44 signal processing unit 441 signal conversion unit 442 delta-sigma modulation unit 443 and 444 multiplication unit 445 vector subtraction unit 446 vector integration Section 447 Vector quantization section 45 Vector modulation section 47 Regulator 48 Power supply terminal 49 Amplifier section 50 Band pass filter (BPF)
50a Low-pass filter (LPF)
51 Output Terminal 52 Distortion Compensation Unit 200 Communication Device 210 Transmission Circuit 220 Reception Circuit 230 Antenna Sharing Unit 240 Antenna

Claims (41)

A transmission circuit that generates and outputs a transmission signal based on input data,
A signal generation unit that performs predetermined signal processing on the input data to generate an amplitude signal and an angle modulation signal;
An amplitude calculation unit that performs predetermined calculation processing on the amplitude signal and outputs a discrete value signal having a plurality of discrete values according to the magnitude of the amplitude signal;
A delta-sigma modulation signal generator that delta-sigma-modulates the amplitude signal based on the discrete-value signal and outputs the delta-sigma modulation signal;
An amplitude amplifying unit that outputs a signal corresponding to the magnitude of the delta-sigma modulated signal;
An amplitude modulation unit that amplifies the angle modulation signal according to the signal output from the amplitude amplification unit, and amplitude-modulates the angle modulation signal, and outputs the angle-modulated and amplitude-modulated transmission signal;
The amplitude calculator is
Holding at least one threshold value and two or more discrete values corresponding to the threshold value;
It is determined whether the amplitude signal exceeds the one or more thresholds every predetermined time, a discrete value to be output is selected based on the determination result, and the selected discrete value is used as the discrete value signal. A transmission circuit characterized by outputting. The delta-sigma modulation signal generator is
A division unit that divides the amplitude signal by the discrete value signal and outputs the amplitude signal as an amplitude signal with a small variation in an envelope;
A delta-sigma modulation unit that delta-sigma-modulates the amplitude signal output by the division unit and outputs the delta-sigma modulation signal;
The transmission circuit according to claim 1, further comprising: a variable gain amplifying unit that amplifies the delta-sigma modulation signal with a gain corresponding to the magnitude of the discrete value signal. The delta-sigma modulation signal generation unit includes a delta-sigma modulation unit that delta-sigma-modulates the amplitude signal and outputs it as a delta-sigma modulation signal,
2. The transmission circuit according to claim 1, wherein the delta-sigma modulation unit changes the magnitude of the output delta-sigma modulation signal so that the magnitude of the discrete-value signal has a positive characteristic relationship.   The transmission circuit according to claim 3, wherein the delta sigma modulation unit changes the magnitude of the output delta sigma modulation signal so that the magnitude of the discrete value signal is directly proportional to the magnitude of the discrete value signal.   The delta-sigma modulation unit changes the magnitude of the output delta-sigma modulation signal by referring to a lookup table in which an optimum value is set in advance according to the magnitude of the discrete value signal. The transmission circuit according to claim 3. The signal generator is
A polar coordinate signal generation unit that generates an amplitude signal and a phase signal based on an amplitude component and a phase component obtained by performing signal processing on the input data;
The transmission circuit according to claim 1, further comprising: an angle modulation unit that angle-modulates the phase signal and outputs the angle-modulated signal. The signal generator is
An orthogonal signal generation unit that generates a vector signal composed of an I signal and a Q signal orthogonal to each other by performing signal processing on the input data;
A vector modulation unit for vector-modulating the vector signal;
An envelope detector that detects an envelope component of the signal output from the vector modulator, and outputs the detected envelope component as the amplitude signal;
2. A limiter that limits an envelope component of a signal output from the vector modulation unit to a certain magnitude and outputs a signal with the magnitude restricted as the angle modulation signal. The transmitting circuit described. The amplitude calculator is
A maximum amplitude detector for detecting a maximum value of the amplitude signal at each predetermined time;
Holds at least one threshold value and two or more discrete values corresponding to the threshold value, and the maximum value of the amplitude signal exceeds the one or more threshold values at each predetermined time And a quantization unit that selects a discrete value to be output based on the determination result and outputs the selected discrete value as the discrete value signal. The transmitting circuit described.   2. The transmission circuit according to claim 1, further comprising a bandpass filter connected to a subsequent stage of the amplitude modulation unit and configured to remove quantization noise from a transmission signal output from the amplitude modulation unit.   The transmission according to claim 1, further comprising a low-pass filter connected between the amplitude amplifying unit and the amplitude modulating unit and configured to remove quantization noise from a signal output from the amplitude amplifying unit. circuit.   The transmission circuit according to claim 1, further comprising a low-pass filter connected between the delta-sigma modulation signal generation unit and the amplitude amplification unit and configured to remove quantization noise from the delta-sigma modulation signal. .   The amplitude amplifying unit includes a switching regulator, and supplies a voltage corresponding to the magnitude of the delta-sigma modulation signal generated by the delta-sigma modulation signal generation unit to the amplitude modulation unit. The transmission circuit according to 1.   The amplitude amplifying unit includes a series regulator and supplies a voltage corresponding to the magnitude of the delta-sigma modulation signal generated by the delta-sigma modulation signal generation unit to the amplitude modulation unit. The transmission circuit according to 1.   The amplitude amplifying unit includes a current-driven regulator, and supplies the current according to the magnitude of the delta-sigma modulation signal generated by the delta-sigma modulation signal generation unit to the amplitude modulation unit. The transmission circuit according to claim 1. The amplitude amplification unit is
A series regulator that supplies a voltage corresponding to the magnitude of the delta-sigma modulation signal generated by the delta-sigma modulation signal generation unit to the amplitude modulation unit;
The transmission circuit according to claim 1, further comprising: a switching regulator that supplies a voltage corresponding to a magnitude of a discrete value signal output from the amplitude calculation unit to the series regulator.   Timing control that is connected between the amplitude calculation unit and the switching regulator and controls the timing at which the discrete value signal output from the amplitude calculation unit is input to the switching regulator so as to compensate for the rise of the switching regulator. The transmission circuit according to claim 15, further comprising a unit. A multiplier that is connected to a subsequent stage of the signal generator and receives power information indicating the magnitude of output power of the transmission circuit;
The multiplication unit multiplies the power information by the amplitude signal generated by the signal generation unit,
The transmission circuit according to claim 1, wherein an amplitude signal is input from the multiplication unit to the amplitude calculation unit and the delta-sigma modulation signal generation unit. A multiplier that is connected to the subsequent stage of the amplitude calculator and receives power information indicating the magnitude of output power of the transmission circuit;
The amplitude amplification unit is
A series regulator that supplies a voltage corresponding to the magnitude of the delta-sigma modulation signal generated by the delta-sigma modulation signal generation unit to the amplitude modulation unit;
A switching regulator that supplies a voltage according to the magnitude of the output signal of the multiplication unit to the series regulator,
The multiplying unit multiplies the power information by the discrete value signal output from the amplitude calculating unit,
The transmission circuit according to claim 2, wherein the switching regulator and the variable gain amplifying unit receive a discrete value signal multiplied by the power information from the multiplication unit. A multiplier that is connected to the subsequent stage of the amplitude calculator and receives power information indicating the magnitude of output power of the transmission circuit;
The amplitude amplification unit is
A series regulator that supplies a voltage corresponding to the magnitude of the delta-sigma modulation signal generated by the delta-sigma modulation signal generation unit to the amplitude modulation unit;
A switching regulator that supplies a voltage according to the power information to the series regulator,
The multiplying unit multiplies the power information by the discrete value signal output from the amplitude calculating unit,
The transmission circuit according to claim 2, wherein a discrete value signal is input to the variable gain amplifier from the multiplier. The amplitude amplification unit is
A plurality of series regulators for supplying a voltage corresponding to the magnitude of the delta-sigma modulation signal generated by the delta-sigma modulation signal generation unit to the amplitude modulation unit;
A switch for switching connection between the plurality of series regulators and the amplitude modulation unit;
A switching regulator that supplies a voltage according to the magnitude of the discrete value signal output from the amplitude calculator to the plurality of series regulators;
The plurality of series regulators include a first series regulator connected to the amplitude modulation unit via the switch, and a size larger than that of the first series regulator, and the amplitude modulation unit via the switch And a second series regulator connected to
When the magnitude of the delta sigma modulation signal is smaller than a predetermined threshold, the switch is switched so that the first series regulator and the amplitude modulation unit are connected, and the magnitude of the delta sigma modulation signal 2. The transmission circuit according to claim 1, wherein the switch is switched so that the second series regulator and the amplitude modulation unit are connected when the length is equal to or greater than a predetermined threshold value. The amplitude amplification unit is
A switching regulator for supplying a voltage corresponding to the magnitude of the delta-sigma modulation signal generated by the delta-sigma modulation signal generation unit to the amplitude modulation unit;
The transmission circuit according to claim 1, further comprising: a switching regulator that supplies the switching regulator with a voltage corresponding to a magnitude of a discrete value signal output from the amplitude calculation unit. The amplitude amplification unit is
A plurality of switching regulators for supplying a voltage corresponding to the magnitude of the delta-sigma modulation signal generated by the delta-sigma modulation signal generation unit to the amplitude modulation unit;
A switch for switching connection between the plurality of switching regulators and the amplitude modulation unit;
A switching regulator that supplies a voltage corresponding to the magnitude of the discrete value signal output from the amplitude calculation unit to the plurality of switching regulators;
The plurality of switching regulators are a first switching regulator connected to the amplitude modulation unit via the switch, and are larger in size than the first switching regulator, and the amplitude modulation unit via the switch And a second switching regulator connected to
When the magnitude of the delta sigma modulation signal is smaller than a predetermined threshold, the switch is switched so that the first switching regulator and the amplitude modulation unit are connected, and the magnitude of the delta sigma modulation signal 2. The transmission circuit according to claim 1, wherein the switch is switched so that the second switching regulator and the amplitude modulation unit are connected when the length is equal to or greater than a predetermined threshold value. A transmission circuit that generates and outputs a transmission signal based on input data,
A signal generation unit that generates a vector signal composed of an I signal and a Q signal orthogonal to each other based on the input data, and an amplitude signal representing the magnitude of the vector signal;
An amplitude calculation unit that performs predetermined calculation processing on the amplitude signal and outputs a discrete value signal having a plurality of discrete values according to the magnitude of the amplitude signal;
A modulation signal generation unit that modulates the vector signal based on the discrete value signal and generates a modulation signal;
An amplitude amplifying unit that outputs a signal corresponding to the magnitude of the discrete value signal;
Amplifying the modulated signal according to the signal output from the amplitude amplifier, and output as a transmission signal,
The amplitude calculator is
Holding at least one threshold value and two or more discrete values corresponding to the threshold value;
It is determined whether the amplitude signal exceeds the one or more thresholds every predetermined time, a discrete value to be output is selected based on the determination result, and the selected discrete value is used as the discrete value signal. A transmission circuit characterized by outputting. The modulation signal generator is
A division unit for dividing the vector signal by the discrete value signal;
A signal processing unit that performs predetermined signal processing on the vector signal divided by the division unit, quantizes the signal, and outputs the quantized signal;
A vector modulation unit that vector-modulates the quantized signal and outputs the modulated signal;
The transmission circuit according to claim 23, further comprising: a variable gain amplifying unit that amplifies the modulation signal output from the vector modulation unit with a gain corresponding to the magnitude of the discrete value signal. The modulation signal generator is
A division unit for dividing the vector signal by the discrete value signal;
A signal processing unit that performs predetermined signal processing on the divided vector signal, quantizes the signal, and outputs the quantized signal;
A variable gain amplifying unit for amplifying the quantized signal with a gain corresponding to the magnitude of the discrete value signal;
The transmission circuit according to claim 23, further comprising: a vector modulation unit that vector-modulates the quantized signal amplified by the variable gain amplification unit and outputs the modulated signal. The modulation signal generator is
A signal processing unit that performs predetermined signal processing on the vector signal, quantizes the signal, and outputs the quantized signal;
A vector modulation unit that vector-modulates the quantized signal and outputs the modulated signal,
The transmission circuit according to claim 23, wherein the signal processing unit changes the magnitude of the quantized signal so that the magnitude of the discrete value signal has a positive characteristic relationship.   27. The transmission circuit according to claim 26, wherein the signal processing unit changes the magnitude of the quantized signal so that the magnitude of the discrete value signal is directly proportional to the magnitude of the discrete value signal.   The signal processing unit changes the magnitude of the quantized signal with reference to a lookup table in which an optimum value is set in advance according to the magnitude of the discrete value signal. 27. The transmission circuit according to 26. The signal processing unit
A vector signal divided by the division unit is input, the input vector signal is a signal representing the magnitude of the input vector signal, and the input vector signal is input to the input vector signal. A signal conversion unit for converting into a normalized vector signal calculated by dividing by a signal representing the magnitude of
A delta-sigma modulator that delta-sigma-modulates a signal representing the magnitude of the input vector signal;
The transmission circuit according to claim 24, further comprising: a multiplication unit that multiplies the delta-sigma modulated signal and the normalized vector signal and outputs the result as the quantized signal. The signal processing unit
A vector calculation unit to which a vector signal divided from the division unit is input;
A vector quantization unit that quantizes an output signal of the vector operation unit and outputs the quantized signal,
The vector calculation unit includes:
A vector subtraction unit for subtracting the quantized signal from the input signal;
The transmission circuit according to claim 24, further comprising a vector integration unit that integrates and outputs a signal input via the vector subtraction unit.   The transmission circuit according to claim 30, wherein the signal processing unit further includes one or more vector calculation units at an output of the vector calculation unit.   The transmission circuit according to claim 23, further comprising a bandpass filter that removes quantization noise from the transmission signal output from the amplification unit.   The transmission circuit according to claim 23, further comprising a low-pass filter that removes quantization noise from the signal output from the amplitude amplifying unit.   The transmission circuit according to claim 1, wherein the predetermined time is a time shorter than a time for controlling output power of the transmission circuit.   2. The transmission circuit according to claim 1, wherein the amplitude calculation unit changes the length of the predetermined time in accordance with a fluctuation range of an envelope of the transmission signal.   The amplitude calculating unit changes the predetermined time short when the fluctuation width of the envelope of the transmission signal is small, and changes the predetermined time long when the fluctuation width of the envelope of the transmission signal is large. The transmission circuit according to claim 1.   The transmission circuit according to claim 1, wherein the amplitude calculation unit changes the length of the predetermined time according to a modulation mode of the transmission signal.   A distortion compensation unit that compensates at least one of the amplitude signal and the angle modulation signal at an output of the signal generation unit so that distortion generated at least in the amplitude modulation unit is suppressed; The transmission circuit according to claim 1, wherein:   The output of the signal generation unit further includes a distortion compensation unit that compensates at least one of the amplitude signal and the vector signal so that distortion generated in at least the amplification unit is suppressed. The transmission circuit according to claim 23. Communication equipment,
A transmission circuit for generating a transmission signal;
An antenna for outputting a transmission signal generated by the transmission circuit;
The communication device according to claim 1, wherein the transmission circuit is the transmission circuit according to claim 1. A receiving circuit for processing a received signal received from the antenna;
The communication according to claim 40, further comprising: an antenna sharing unit that outputs a transmission signal generated by the transmission circuit to the antenna and outputs a reception signal received from the antenna to the reception circuit. machine.

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