JP2008099345A - Inverter, fluorescent lamp appliance, and illumination appliance - Google Patents

Inverter, fluorescent lamp appliance, and illumination appliance Download PDF

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JP2008099345A
JP2008099345A JP2006274396A JP2006274396A JP2008099345A JP 2008099345 A JP2008099345 A JP 2008099345A JP 2006274396 A JP2006274396 A JP 2006274396A JP 2006274396 A JP2006274396 A JP 2006274396A JP 2008099345 A JP2008099345 A JP 2008099345A
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fluorescent lamp
channel fet
resistor
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JP4716968B2 (en
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Satoshi Nagai
敏 永井
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Mitsubishi Electric Corp
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<P>PROBLEM TO BE SOLVED: To provide an inverter capable of preventing a surge current from being applied to FETs of an N-channel and a P-channel when an fluorescent lamp is turned on. <P>SOLUTION: The inverter includes a smoothing capacitor 5 for smoothing an output of a full-wave rectification circuit 4; the FETs 6, 7 of N- and P-channels provided between output ends of the smoothing capacitor 5 and connected in serial; a ballast coil 8 connected to a connection point between the FET 6 of N-channel and the FET 7 of P-channel; a secondary winding 8b electromagnetically connected to the ballast coil 8; an oscillation circuit consisting of an inductor 15 and a capacitor 16 provided between both the ends of the secondary winding 8b; and a serial circuit consisting of a capacitor 17 and a resistor 21 provided between a connection point of the inductor 15 and the capacitor 16, and gate sides of the FETs 6, 7 of N-, P-channels. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、蛍光ランプを点灯するインバータ装置、インバータ装置を備えた蛍光灯装置及び蛍光灯装置を有する照明装置に関するものである。   The present invention relates to an inverter device for lighting a fluorescent lamp, a fluorescent lamp device including the inverter device, and an illumination device having the fluorescent lamp device.

従来、電球形蛍光ランプに内蔵されたインバータ装置として、NチャネルFETとPチャネルFETとが直列に接続されたハーフブリッジ型インバータが一般的に用いられている(例えば、特許文献1参照)。   Conventionally, a half-bridge inverter in which an N-channel FET and a P-channel FET are connected in series is generally used as an inverter device built in a bulb-type fluorescent lamp (for example, see Patent Document 1).

特許第3413754号(第3−5頁、図1−2)Japanese Patent No. 3413754 (page 3-5, Fig. 1-2)

しかしながら、前述した従来のインバータ装置は、電源投入時、即ち蛍光ランプの点灯開始時、NチャネルFETとPチャネルFETに流れる電流の位相が蛍光ランプの点灯時に比べ進み、電圧の位相と同位相となるためサージ電流が流れる。これは、バラストコイルと始動コンデンサの共振動作により電流の位相が進むことに起因する。いわゆるハードスイッチングとなりFETがONとなる瞬間にFETのドレインからソースに向かってパルス状の電流が流れる。このパルス状の電流は、FETのドレインとソース間に接続するスナバコンデンサ及びドレイン−ソース間容量の充放電電流であり、スナバコンデンサはFETを保護するために必須の部品となる。共振動作は蛍光ランプの放電を開始するために必要で、この共振動作により蛍光ランプに高電圧を印加するものである。   However, in the conventional inverter device described above, the phase of the current flowing through the N-channel FET and the P-channel FET is advanced when the power is turned on, that is, at the start of lighting of the fluorescent lamp, compared with the phase of the voltage. Therefore, a surge current flows. This is due to the fact that the current phase advances due to the resonant operation of the ballast coil and the starting capacitor. A pulsed current flows from the drain to the source of the FET at the moment when the FET is turned on by so-called hard switching. This pulsed current is a charge / discharge current of a snubber capacitor connected between the drain and source of the FET and a drain-source capacitance, and the snubber capacitor is an essential component for protecting the FET. The resonance operation is necessary for starting the discharge of the fluorescent lamp, and a high voltage is applied to the fluorescent lamp by this resonance operation.

例えば図9に示すように、PチャネルFETがONとなるタイミングでは、(1)に示すような急峻なパルス状の波形を有する電流がドレインからソースに流れ、(2)に示すドレイン−ソース間電圧との積が(3)に示すような電力波形(損失)となる。一方、NチャネルFETの電圧と電流は、Pチャネルのそれと極性が反転し、同様にパルス状の波形を有する電流がドレインからソースに流れることになる。このパルス状の電流即ちサージ電流は、電源ラインに重畳し、ノイズとしてインバータ装置を内蔵する照明装置や他の機器に影響を与えることがあった。また、これらサージ電流は、Nチャネル及びPチャネルの各FETの損失となり、この損失を許容できるFETを選定する必要があった。   For example, as shown in FIG. 9, at the timing when the P-channel FET is turned on, a current having a steep pulse waveform as shown in (1) flows from the drain to the source, and between the drain and source shown in (2). The product of the voltage is a power waveform (loss) as shown in (3). On the other hand, the voltage and current of the N-channel FET are reversed in polarity from that of the P-channel, and similarly, a current having a pulsed waveform flows from the drain to the source. This pulsed current, that is, surge current, is superimposed on the power supply line, and as a noise, it may affect the lighting device or other equipment incorporating the inverter device. Further, these surge currents cause losses in the N-channel and P-channel FETs, and it is necessary to select an FET that can tolerate this loss.

本発明は,前記のような課題を解決するためになされたもので、蛍光ランプ点灯開始時にサージ電流が流れないようにして、ノイズによる影響を抑えると共に、スイッチング素子の損失の小さいインバータ装置、このインバータ装置を有する蛍光灯装置、及びその蛍光灯装置を備えた照明装置を提供することを目的とする。   The present invention has been made in order to solve the above-described problems, and suppresses the influence of noise by preventing surge current from flowing at the start of lighting of a fluorescent lamp. It aims at providing the fluorescent lamp apparatus which has an inverter apparatus, and an illuminating device provided with the fluorescent lamp apparatus.

本発明に係るインバータ装置は、全波整流回路と、全波整流回路の出力を平滑する平滑コンデンサと、平滑コンデンサの出力端間に設けられ、直列に接続されたNチャネル及びPチャネルのスイッチング素子と、Nチャネルのスイッチング素子及びPチャネルのスイッチング素子の接続点に接続されたバラストコイルと、バラストコイルに磁気的に接続された二次巻線と、二次巻線の両端間に設けられた共振回路とを備え、共振回路で発生する共振電圧を抵抗とコンデンサの直列回路を経由してNチャネル及びPチャネルの各スイッチング素子に印加し交互にオン・オフ動作させるようにしたものである。   An inverter device according to the present invention includes a full-wave rectifier circuit, a smoothing capacitor for smoothing the output of the full-wave rectifier circuit, and an N-channel and P-channel switching element connected in series between the output terminals of the smoothing capacitor. A ballast coil connected to the connection point of the N-channel switching element and the P-channel switching element, a secondary winding magnetically connected to the ballast coil, and both ends of the secondary winding. A resonance circuit is provided, and a resonance voltage generated in the resonance circuit is applied to each of the N-channel and P-channel switching elements via a series circuit of a resistor and a capacitor so as to be turned on and off alternately.

本発明においては、Nチャネル及びPチャネルの各スイッチング素子に印加する共振電圧を抵抗とコンデンサの直列回路を経由させるようにしたので、バラストコイルと始動コンデンサで決定する共振周波数より高い周波数でNチャネル及びPチャネルの各スイッチング素子を交互にオン・オフ動作することができる。このため、蛍光灯点灯開始時に発生するサージ電流が各スイッチング素子に流れなくなり、ノイズによる本装置への影響や他の機器への影響がなくなり、スイッチング素子の損失の小さいインバータ装置を提供できる。   In the present invention, since the resonance voltage applied to each switching element of the N channel and the P channel is made to pass through a series circuit of a resistor and a capacitor, the N channel has a frequency higher than the resonance frequency determined by the ballast coil and the starting capacitor. In addition, the switching elements of the P channel and the P channel can be turned on and off alternately. For this reason, the surge current generated at the start of lighting of the fluorescent lamp does not flow to each switching element, and the influence of this noise on the apparatus and other equipment is eliminated, and an inverter apparatus with a small loss of the switching element can be provided.

図1は本発明の実施の形態を示すインバータ装置の回路図である。
図中に示す全波整流回路4は、コンデンサ2とインダクタ3とでなるLCフィルタ回路を介して印加される商用電源1の電圧を全波整流する。平滑コンデンサ5は、全波整流回路4の出力端間に接続され、全波整流回路4により全波整流された直流電圧を平滑する。スイッチング素子である例えばNチャネルFET6とPチャネルFET7は、ソース側同士及びゲート側同士がそれぞれ互いに接続され、NチャネルFET6のドレインが電源電圧の高電位側に、PチャネルFET6のドレインが電源電圧の低電位側に接続されている。
FIG. 1 is a circuit diagram of an inverter device showing an embodiment of the present invention.
A full-wave rectification circuit 4 shown in the figure performs full-wave rectification on the voltage of the commercial power supply 1 applied via an LC filter circuit composed of a capacitor 2 and an inductor 3. The smoothing capacitor 5 is connected between the output terminals of the full-wave rectifier circuit 4 and smoothes the DC voltage that has been full-wave rectified by the full-wave rectifier circuit 4. For example, the N-channel FET 6 and the P-channel FET 7 which are switching elements are connected to each other on the source side and on the gate side, the drain of the N-channel FET 6 is on the high potential side of the power supply voltage, and the drain of the P-channel FET 6 is the power supply voltage. Connected to the low potential side.

バラストコイル8は、一端がPチャネルFET6のソース側に、他端が直流カットコンデンサ9にそれぞれ接続された一次巻線8aと、この一次巻線8aに磁気的に接続される二次巻線8bとを備えている。始動コンデンサ11は、一端が本装置に接続された蛍光ランプ10のフィラメント10aを介して直流カットコンデンサ9に接続され、他端が蛍光ランプ10のフィラメント10bを介してPチャネルFET6のドレイン側に接続されている。前述したバラストコイル8の一次巻線8aと直流カットコンデンサ9及び始動コンデンサ11の直列容量で共振回路が形成される。直流カットコンデンサ9と始動コンデンサ11の容量は、直流カットコンデンサ9>始動コンデンサ11の関係にあり、共振回路として始動コンデンサ11が主体的に作用している。   The ballast coil 8 includes a primary winding 8a having one end connected to the source side of the P-channel FET 6 and the other end connected to the DC cut capacitor 9, and a secondary winding 8b magnetically connected to the primary winding 8a. And. The starting capacitor 11 has one end connected to the DC cut capacitor 9 via the filament 10a of the fluorescent lamp 10 connected to the apparatus, and the other end connected to the drain side of the P-channel FET 6 via the filament 10b of the fluorescent lamp 10. Has been. A resonance circuit is formed by the series capacitance of the primary winding 8 a of the ballast coil 8 and the DC cut capacitor 9 and the starting capacitor 11 described above. The capacities of the DC cut capacitor 9 and the start capacitor 11 are in a relationship of DC cut capacitor 9> start capacitor 11, and the start capacitor 11 mainly acts as a resonance circuit.

NチャネルFET6のドレインとソース間にスナバコンデンサ20を介在して並列に接続された抵抗12(第1の抵抗)と、バラストコイル8の二次巻線8bとNチャネルFET6及びPチャネルFET7の共通ゲートとの間に挿入された抵抗13(第2の抵抗)と、PチャネルFET7のゲートとドレイン間に並列に接続された抵抗14(第3の抵抗)とで起動回路が構成され、Nチャネル及びPチャネルの各FET6、7を起動する。バラストコイル8の二次巻線8bの両端間に直列接続されたインダクタ15とコンデンサ16とで共振回路が構成されている。   The resistor 12 (first resistor) connected in parallel with the snubber capacitor 20 interposed between the drain and the source of the N-channel FET 6, the secondary winding 8 b of the ballast coil 8, the N-channel FET 6 and the P-channel FET 7 in common A starter circuit is configured by the resistor 13 (second resistor) inserted between the gate and the resistor 14 (third resistor) connected in parallel between the gate and drain of the P-channel FET 7 to form an N channel. And activate the FETs 6 and 7 of the P channel. The inductor 15 and the capacitor 16 connected in series between both ends of the secondary winding 8b of the ballast coil 8 constitute a resonance circuit.

コンデンサ17と抵抗21の直列回路は、前述した共振回路のインダクタ15及びコンデンサ16の接続点とNチャネル及びPチャネルの各FET6、7の共通ゲートとの間に挿入されている。このコンデンサ17と抵抗21の直列回路は、バラストコイル8の二次巻線8bに誘起された電圧を、NチャネルFET6とPチャネルFET7の共通ゲートにゲート駆動信号として入力する。ツェナーダイオード18、19は、NチャネルFET6のゲート側とPチャネルFET7のソース側の間に直列に接続され、NチャネルFET6とPチャネルFET7の各ゲートを保護するために設けられている。   A series circuit of the capacitor 17 and the resistor 21 is inserted between the connection point of the inductor 15 and the capacitor 16 of the above-described resonance circuit and the common gate of the N-channel and P-channel FETs 6 and 7. This series circuit of the capacitor 17 and the resistor 21 inputs a voltage induced in the secondary winding 8 b of the ballast coil 8 to the common gate of the N-channel FET 6 and the P-channel FET 7 as a gate drive signal. Zener diodes 18 and 19 are connected in series between the gate side of the N-channel FET 6 and the source side of the P-channel FET 7, and are provided to protect the gates of the N-channel FET 6 and the P-channel FET 7.

次に、本実施の形態のインバータ装置の動作について、図1乃至図6を用いて説明をする。図2はコンデンサ16の容量値をパラメータに点灯時の発振周波数をプロットして示すグラフ、図3は蛍光ランプ点灯中のNチャネルFETの電圧と電流の波形図、図4は蛍光ランプ点灯中のPチャネルFETの電圧と電流の波形図、図5はコンデンサ16の容量値をパラメータに始動時の発振周波数をプロットして示すグラフ、図6は蛍光ランプ点灯開始時のPチャネルFETの電流と電圧及び電力の波形図である。なお、本実施の形態は次の回路定数で説明する。
一次巻線8aのインダクタンス =0.8mH
二次巻き線8bのインダクタンス=3.1μH
始動コンデンサ11の容量 =0.0055μF
直流カットコンデンサ9の容量 =0.1μH
インダクタ15のインダクタンス=1mH
コンデンサ17の容量 =0.1μH
Next, the operation of the inverter device of this embodiment will be described with reference to FIGS. FIG. 2 is a graph showing the oscillation frequency at the time of lighting with the capacitance value of the capacitor 16 as a parameter, FIG. 3 is a waveform diagram of the voltage and current of the N-channel FET during lighting of the fluorescent lamp, and FIG. FIG. 5 is a graph showing the oscillation frequency at the time of starting with the capacitance value of the capacitor 16 as a parameter, and FIG. 6 is the current and voltage of the P-channel FET at the start of lighting of the fluorescent lamp. FIG. 6 is a waveform diagram of electric power. This embodiment will be described using the following circuit constants.
Inductance of primary winding 8a = 0.8mH
Inductance of secondary winding 8b = 3.1 μH
Capacitance of starting capacitor 11 = 0.0055 μF
Capacitance of DC cut capacitor 9 = 0.1 μH
Inductance of inductor 15 = 1 mH
Capacitor 17 capacity = 0.1 μH

本装置に商用電源1が投入されると、全波整流回路4が商用電源1の交流電圧を全波整流し、平滑コンデンサ5が平滑する。そして、抵抗12、バラストコイル8の二次巻線8b、抵抗13、抵抗14を介してPチャネルFET7のゲートに電圧が印加され、PチャネルFET7がオンし、バラストコイル8の一次巻線8aを介して蛍光ランプ10に電圧が印加される。この時、バラストコイル8の二次巻線8bに電圧が誘起され、インダクタ15及びコンデンサ16が共振し、この共振電圧は、コンデンサ17及び抵抗20を介してNチャネルFET6とPチャネルFET7の各ゲートに交互に印加され、Nチャネル及びPチャネルの各FET6,7を交互にオン・オフ動作(発振)させ、蛍光ランプ10を高周波点灯させる。
商用電源1の電圧、点灯時のランプ10の電流、一次巻線8aのインダクタンスの値からインバータの発振周波数は80kHzに設定される。発振周波数は、バラストコイル8と始動コンデンサ11の共振回路、バラストコイルの巻き数比、インダクタ15とコンデンサ16の共振回路で決定され、例えば、コンデンサ16の容量をパラメータにすると図2に示すグラフとなる。図2において、グラフ(1)は抵抗21が0Ω、即ち従来の回路での発振周波数、グラフ(2)は330Ωの抵抗21をコンデンサ17に直列接続した場合の周波数特性となる。このように、コンデンサ17に直列に抵抗21を接続するとコンデンサ16が同容量であっても発振周波数が高くなることが分かる。図2のグラフでは抵抗21が330Ωで10kHz高い周波数となり、コンデンサ17に直列接続する抵抗21の抵抗値に比例する。図2のグラフから、発振周波数を80kHzに設定する場合、抵抗21が0Ωの場合は、Aのポイントとなりコンデンサ16の容量を0.0015μFに、また抵抗21が330Ωの場合はBのポイントとなりコンデンサ16の容量を0.002μFに調整される。
When the commercial power source 1 is turned on in the apparatus, the full-wave rectifier circuit 4 full-wave rectifies the AC voltage of the commercial power source 1 and the smoothing capacitor 5 smoothes. Then, a voltage is applied to the gate of the P-channel FET 7 through the resistor 12, the secondary winding 8b of the ballast coil 8, the resistor 13, and the resistor 14, and the P-channel FET 7 is turned on, and the primary winding 8a of the ballast coil 8 is turned on. Through this, a voltage is applied to the fluorescent lamp 10. At this time, a voltage is induced in the secondary winding 8 b of the ballast coil 8, and the inductor 15 and the capacitor 16 resonate. The resonance voltage passes through the capacitor 17 and the resistor 20, and the gates of the N-channel FET 6 and the P-channel FET 7. Are alternately applied to turn on and off (oscillate) the N-channel and P-channel FETs 6 and 7 alternately, and the fluorescent lamp 10 is turned on at high frequency.
The oscillation frequency of the inverter is set to 80 kHz from the voltage of the commercial power source 1, the current of the lamp 10 at the time of lighting, and the value of the inductance of the primary winding 8a. The oscillation frequency is determined by the resonance circuit of the ballast coil 8 and the starting capacitor 11, the turn ratio of the ballast coil, and the resonance circuit of the inductor 15 and the capacitor 16. For example, when the capacitance of the capacitor 16 is used as a parameter, the graph shown in FIG. Become. In FIG. 2, the graph (1) shows the frequency characteristics when the resistor 21 is 0Ω, that is, the oscillation frequency in the conventional circuit, and the graph (2) shows the frequency characteristics when the resistor 21 of 330Ω is connected in series with the capacitor 17. Thus, it can be seen that when the resistor 21 is connected in series with the capacitor 17, the oscillation frequency is increased even if the capacitor 16 has the same capacity. In the graph of FIG. 2, the resistance 21 is 330Ω and a frequency 10 kHz higher, and is proportional to the resistance value of the resistance 21 connected in series with the capacitor 17. From the graph of FIG. 2, when the oscillation frequency is set to 80 kHz, when the resistor 21 is 0Ω, the point becomes A, and the capacitance of the capacitor 16 becomes 0.0015 μF, and when the resistor 21 is 330Ω, the point becomes B. The capacity of 16 is adjusted to 0.002 μF.

蛍光ランプ10が点灯しているときのNチャネルFET6は、ドレインとソース間に図3(1)に示す電圧が発生、同図(2)に示す電流がドレインからソースに向かって流れる。また、蛍光ランプ10の点灯中のPチャネルFET7は、ドレインとソース間に図4(1)に示す電圧が発生、同図(2)に示す電流がドレインからソースに向かって流れる。このように蛍光ランプ10の点灯中は、各FET6、7の電圧に対し電流が遅れの位相となる。従来からの回路では抵抗21が0Ωであるが、点灯時は遅れの位相で動作し、抵抗21を330Ωにした場合は更に電流位相が遅れることになるが、両者の遅れ位相に大差がなく、両者とも問題がない。   When the fluorescent lamp 10 is lit, the N-channel FET 6 generates the voltage shown in FIG. 3A between the drain and the source, and the current shown in FIG. 3B flows from the drain toward the source. Further, in the P-channel FET 7 in which the fluorescent lamp 10 is turned on, the voltage shown in FIG. 4A is generated between the drain and the source, and the current shown in FIG. 4B flows from the drain toward the source. Thus, during the lighting of the fluorescent lamp 10, the current is in a phase that is delayed with respect to the voltages of the FETs 6 and 7. In the conventional circuit, the resistor 21 is 0Ω, but operates at a delayed phase when it is lit, and when the resistor 21 is set to 330Ω, the current phase is further delayed, but there is no great difference in the delayed phase between the two. Both have no problems.

一方、電源投入時、即ち点灯開始時は蛍光ランプ10が点灯していないため、NチャネルFET6とPチャネルFET7とから流れる電流は、バラストコイル8の一次巻線8aと始動コンデンサ11の直列共振により共振電流となる。バラストコイル8の一次巻線8aに流れる共振電流は点灯時の5倍近く流れ、二次巻線8bに誘起される電圧も高くなり、インダクタ15とコンデンサ16の共振回路を通過し、コンデンサ17と抵抗21の直列回路を経由してNチャネルFET6とPチャネルFET7のゲートにそれぞれ入力する。この時、抵抗21によりNチャネルFET6とPチャネルFET7のゲートに印加される電圧が低くなり、ツェナーダイオード18、19でクリップされる時間が短くなり、NチャネルFET6とPチャネルFET7のオン時間も同様に短くなることから発振周波数が高くなる。
図5のグラフは、始動時の発振周波数をコンデンサ16の容量をパラメータにプロットしたもので、(1)は抵抗21が0Ω、(2)は抵抗21が330Ωの特性を示す。抵抗21が0Ωの場合、点灯周波数からコンデンサ16は0.0015μFが接続され、この時の発振周波数はAのポイントであり75.5kHzとなる。また、抵抗21が0Ωの場合、点灯周波数からコンデンサ16は0.002μFが接続され、この時の発振周波数はBのポイントであり77.5kHzとなる。
一方、バラストコイル8の一次巻線8a(L)と始動コンデンサ11(C)の直列共振周波数(f)は、下記の数式から算出され76kHzとなる。
On the other hand, since the fluorescent lamp 10 is not lit when the power is turned on, that is, when lighting is started, the current flowing from the N-channel FET 6 and the P-channel FET 7 is caused by the series resonance of the primary winding 8a of the ballast coil 8 and the starting capacitor 11. Resonant current. The resonance current flowing in the primary winding 8a of the ballast coil 8 flows nearly five times as much as that during lighting, and the voltage induced in the secondary winding 8b also increases, passes through the resonance circuit of the inductor 15 and the capacitor 16, passes through the capacitor 17 and The signals are input to the gates of the N-channel FET 6 and the P-channel FET 7 through the series circuit of the resistor 21, respectively. At this time, the voltage applied to the gates of the N-channel FET 6 and the P-channel FET 7 by the resistor 21 is lowered, the time clipped by the Zener diodes 18 and 19 is shortened, and the on-time of the N-channel FET 6 and the P-channel FET 7 is the same. Therefore, the oscillation frequency becomes higher.
The graph of FIG. 5 is obtained by plotting the oscillation frequency at the time of starting with the capacitance of the capacitor 16 as a parameter. (1) shows the characteristic that the resistance 21 is 0Ω, and (2) shows the characteristic that the resistance 21 is 330Ω. When the resistance 21 is 0Ω, 0.0015 μF is connected to the capacitor 16 from the lighting frequency, and the oscillation frequency at this time is a point A and becomes 75.5 kHz. When the resistance 21 is 0Ω, the capacitor 16 is connected to 0.002 μF from the lighting frequency, and the oscillation frequency at this time is the point B and becomes 77.5 kHz.
On the other hand, the series resonance frequency (f) of the primary winding 8a (L) of the ballast coil 8 and the starting capacitor 11 (C) is calculated from the following formula and becomes 76 kHz.

Figure 2008099345
このように、抵抗21が0Ωの場合、共振周波数(f)より低い周波数で発振するためNチャネルFET6とPチャネルFET7の電圧に対して電流が進みの位相で発振する。抵抗21が330Ωの場合、共振周波数(f)より高い周波数で発振するためNチャネルFET6とPチャネルFET7の電圧に対して電流が遅れの位相で発振する。
Figure 2008099345
Thus, when the resistance 21 is 0Ω, the oscillation occurs at a frequency lower than the resonance frequency (f), so that the current oscillates in a phase in which the current advances with respect to the voltages of the N-channel FET 6 and the P-channel FET 7. When the resistance 21 is 330Ω, the current oscillates at a phase delayed with respect to the voltages of the N-channel FET 6 and the P-channel FET 7 because it oscillates at a frequency higher than the resonance frequency (f).

図6に示すように、PチャネルFETがONとなるタイミングでは、(1)に示すような電流がドレインからソースに流れ、(2)に示すドレイン−ソース間電圧との積が(3)に示すような電力波形(損失)となる。また、NチャネルFET6は、図示していないが、PチャネルFET7に印加された電圧に対し極性の反転した電圧がドレインとソース間に印加され、極性の反転した電流がドレインからソースに流れる。   As shown in FIG. 6, at the timing when the P-channel FET is turned on, a current as shown in (1) flows from the drain to the source, and the product of the drain-source voltage shown in (2) becomes (3). The power waveform (loss) is as shown. Although not shown, the N-channel FET 6 is applied with a voltage whose polarity is inverted between the drain and the source with respect to the voltage applied to the P-channel FET 7, and a current whose polarity is inverted flows from the drain to the source.

以上のように、点灯開始時にNチャネルFET6とPチャネルFET7に印加される電圧に対し,各FET6,7に流れる電流の位相を遅らせるようバラストコイル8の一次巻線8aと始動コンデンサ11の直列共振周波数より高い周波数で発振するようにしたので、図9(1)に示す電流波形と比べ急峻なパルス状のサージ電流がなくなり(図6(1)参照)、このため、点灯開始時のFET6、7の損失を小さく抑えることができ、ノイズによる本装置や他の機器への影響のないインバータ装置を提供できる。   As described above, the series resonance of the primary winding 8a of the ballast coil 8 and the starting capacitor 11 so as to delay the phase of the current flowing through the FETs 6 and 7 with respect to the voltage applied to the N-channel FET 6 and the P-channel FET 7 at the start of lighting. Since it oscillates at a frequency higher than the frequency, there is no steep pulse-like surge current compared to the current waveform shown in FIG. 9 (1) (see FIG. 6 (1)). 7 can be kept small, and an inverter device can be provided in which noise and other devices are not affected by noise.

なお、前記のインバータ装置では、スイッチング素子にNチャネルFET6とPチャネルFET7を用いたことを述べたが、これに代えて、NチャネルとPチャネルのIGBT(Insulate Gate Bipola Transistor )を用いてもよい。
また、前記のインバータ装置では、NチャネルFET6とPチャネルFET7を保護するスナバ回路にスナバコンデンサ20を用いているがコンデンサと抵抗の直列回路に代えてもよい。但し、この場合、スナバ回路の損失が増大し、インバータ装置の効率が低下する。
In the above inverter device, it has been described that the N-channel FET 6 and the P-channel FET 7 are used as the switching elements. Instead, N-channel and P-channel IGBTs (Insulate Gate Bipola Transistors) may be used. .
In the inverter device, the snubber capacitor 20 is used in the snubber circuit for protecting the N-channel FET 6 and the P-channel FET 7. However, the snubber capacitor 20 may be replaced with a series circuit of a capacitor and a resistor. However, in this case, the loss of the snubber circuit increases and the efficiency of the inverter device decreases.

図7は本発明の実施の形態のインバータ装置を備えた蛍光灯装置を示す断面図である。
図中に示す蛍光灯装置22は、電球形蛍光ランプに前述したインバータ装置を備えたものである。その電球形蛍光ランプの基体を構成するカバー24は、PBT樹脂などの耐熱性合成樹脂で形成され、その一端にはガラス製からなるほぼ球状のグローブ25が嵌着されており、外周にはエジソンタイプのE26型などのねじ込み型口金23が被着されている。蛍光ランプ26は、例えば渦状に形成されてその一端が仕切板28に固定され、グローブ25により覆われている。基板27は、前記の口金23内に収められ、図1に示すインバータ装置の回路が実装されている。前述した仕切板28は、蛍光ランプ26の固定の他に、蛍光ランプ26と基板27とを分離するために設けられている。
FIG. 7 is a sectional view showing a fluorescent lamp device provided with the inverter device according to the embodiment of the present invention.
A fluorescent lamp device 22 shown in the figure is a bulb-type fluorescent lamp provided with the inverter device described above. The cover 24 constituting the base of the bulb-type fluorescent lamp is formed of a heat-resistant synthetic resin such as PBT resin, and a substantially spherical globe 25 made of glass is fitted on one end thereof, and Edison is arranged on the outer periphery. A screw-type base 23 such as type E26 is attached. The fluorescent lamp 26 is formed in, for example, a spiral shape, one end of which is fixed to the partition plate 28, and is covered with the globe 25. The substrate 27 is housed in the base 23 and the circuit of the inverter device shown in FIG. 1 is mounted. The partition plate 28 described above is provided to separate the fluorescent lamp 26 and the substrate 27 in addition to fixing the fluorescent lamp 26.

このように、蛍光灯装置22(電球形蛍光ランプ)に、図1に示すインバータ装置を内蔵させたので、点灯開始時に発生するノイズがなくなり、このため、点灯開始時のノイズによる本装置や他の機器への影響がなくなった。   As described above, since the inverter device shown in FIG. 1 is built in the fluorescent lamp device 22 (bulb-shaped fluorescent lamp), noise generated at the start of lighting is eliminated. The effect on the equipment is gone.

次に、電球形蛍光ランプが用いられた照明装置について図8を用いて説明する。図8は電球形蛍光ランプを備えた照明装置の外観斜視図である。
図中に示す照明装置30は、例えばペンダント形の照明器具で、コード31に接続されたソケット(図示せず)と、このソケットを覆うように設けられた笠32と、ソケットに口金23が螺合接続された電球形蛍光ランプ22とから構成されている。
Next, an illumination device using a bulb-type fluorescent lamp will be described with reference to FIG. FIG. 8 is an external perspective view of an illuminating device including a bulb-type fluorescent lamp.
The lighting device 30 shown in the drawing is, for example, a pendant-type lighting fixture, and includes a socket (not shown) connected to a cord 31, a cap 32 provided so as to cover the socket, and a base 23 screwed into the socket. It is comprised from the bulb-type fluorescent lamp 22 connected together.

このように、照明装置30(照明器具)に、図1に示すインバータ装置が内蔵された蛍光灯装置(電球形蛍光ランプ)を備えたので、点灯開始時に発生するノイズがなくなり、このため、点灯開始時のノイズによる本装置や他の機器への影響を与えない照明器具を提供できる。   As described above, since the lighting device 30 (lighting fixture) includes the fluorescent lamp device (bulb-shaped fluorescent lamp) in which the inverter device shown in FIG. 1 is incorporated, noise generated at the start of lighting is eliminated, and thus the lighting device is turned on. It is possible to provide a lighting apparatus that does not affect the present apparatus and other equipment due to noise at the start.

なお、電球形蛍光ランプ22を有する照明器具としてペンダント形照明器具を例に示したが、廊下やトイレなどに設置されるダウンライト、シーリングファン付照明器具、複数の電球形蛍光ランプ22が用いられたシャンデリアなどでもよい。   In addition, although the pendant type lighting fixture was shown as an example as a lighting fixture which has the bulb-shaped fluorescent lamp 22, the downlight installed in a corridor, a toilet, etc., the lighting fixture with a ceiling fan, and the some bulb-shaped fluorescent lamp 22 are used. It may be a chandelier.

本発明の実施の形態を示すインバータ装置の回路図である。It is a circuit diagram of the inverter apparatus which shows embodiment of this invention. コンデンサ16の容量値をパラメータに点灯時の発振周波数をプロットして示すグラフである。It is a graph which plots and shows the oscillation frequency at the time of lighting with the capacitance value of the capacitor | condenser 16 as a parameter. 蛍光ランプ点灯中のNチャネルFETの電圧と電流の波形図である。It is a waveform diagram of the voltage and current of the N-channel FET when the fluorescent lamp is lit. 蛍光ランプ点灯中のPチャネルFETの電圧と電流の波形図である。It is a waveform diagram of the voltage and current of the P-channel FET when the fluorescent lamp is lit. コンデンサ16の容量値をパラメータに始動時の発振周波数をプロットして示すグラフである。It is a graph which plots and shows the oscillation frequency at the time of start-up with the capacitance value of capacitor 16 as a parameter. 蛍光ランプ点灯開始時のPチャネルFETの電流と電圧及び電力の波形図である。It is a waveform diagram of the current, voltage and power of the P-channel FET at the start of lighting of the fluorescent lamp. 本発明の実施の形態のインバータ装置を備えた蛍光灯装置を示す断面図である。It is sectional drawing which shows the fluorescent lamp apparatus provided with the inverter apparatus of embodiment of this invention. 電球形蛍光ランプを備えた照明装置の外観斜視図である。It is an external appearance perspective view of the illuminating device provided with the bulb-type fluorescent lamp. 従来技術における蛍光ランプ点灯開始時のPチャネルFETの電流と電圧及び電力の波形図である。It is a waveform diagram of the current, voltage and power of a P-channel FET at the start of lighting a fluorescent lamp in the prior art.

符号の説明Explanation of symbols

1 交流電源、2 コンデンサ、3 インダクタ、4 全波整流回路、5 平滑コンデンサ、6 NチャネルFET、7 PチャネルFET、8 バラストコイル、8a 一次巻線、8b 二次巻線、9 直流カットコンデンサ、10 蛍光ランプ、11 始動コンデンサ、12,13,14 起動用の抵抗、15 インダクタ、16 コンデンサ、
17 遅延回路のコンデンサ、18,19 ツェナーダイオード、20 スナバコンデンサ、21 遅延回路の抵抗、22 電球形蛍光ランプ、23 口金、24 カバー、
25 グローブ、26 蛍光ランプ、27 基板、28 仕切り板、30 照明器具、
31 コード、32 笠。
1 AC power supply, 2 capacitor, 3 inductor, 4 full wave rectifier circuit, 5 smoothing capacitor, 6 N channel FET, 7 P channel FET, 8 ballast coil, 8a primary winding, 8b secondary winding, 9 DC cut capacitor, 10 fluorescent lamp, 11 starting capacitor, 12, 13, 14 resistance for starting, 15 inductor, 16 capacitor,
17 Capacitor of delay circuit, 18, 19 Zener diode, 20 Snubber capacitor, 21 Resistance of delay circuit, 22 Light bulb type fluorescent lamp, 23 Base, 24 Cover,
25 Globe, 26 Fluorescent lamp, 27 Substrate, 28 Partition plate, 30 Lighting fixture,
31 code, 32 shades.

Claims (6)

全波整流回路と、
該全波整流回路の出力を平滑する平滑コンデンサと、
該平滑コンデンサの出力端間に設けられ、直列に接続されたNチャネル及びPチャネルのスイッチング素子と、
前記Nチャネルのスイッチング素子及びPチャネルのスイッチング素子の接続点に接続されたバラストコイルと、
該バラストコイルに磁気的に接続された二次巻線と、
該二次巻線の両端間に設けられた共振回路とを備え、
前記共振回路で発生する共振電圧を抵抗とコンデンサの直列回路を経由して前記Nチャネル及びPチャネルの各スイッチング素子に印加し交互にオン・オフ動作させることを特徴とするインバータ装置。
A full-wave rectifier circuit;
A smoothing capacitor for smoothing the output of the full-wave rectifier circuit;
N-channel and P-channel switching elements provided between the output terminals of the smoothing capacitor and connected in series;
A ballast coil connected to a connection point of the N-channel switching element and the P-channel switching element;
A secondary winding magnetically connected to the ballast coil;
A resonance circuit provided between both ends of the secondary winding,
An inverter device, wherein a resonance voltage generated in the resonance circuit is applied to each of the switching elements of the N channel and the P channel via a series circuit of a resistor and a capacitor to perform an on / off operation alternately.
前記Nチャネルのスイッチング素子を高電位側に設けたことを特徴とする請求項1記載のインバータ装置。   2. The inverter device according to claim 1, wherein the N-channel switching element is provided on a high potential side. 前記Nチャネル及びPチャネルの各スイッチング素子のソース側同士及びゲート側同士がそれぞれ互いに接続されていることを特徴とする請求項1又は2記載のインバータ装置。   3. The inverter device according to claim 1, wherein the source sides and the gate sides of the N-channel and P-channel switching elements are connected to each other. 前記Nチャネルのスイッチング素子のドレインとソース間に並列に接続された第1の抵抗と、前記二次巻線と前記Nチャネル及びPチャネルの各スイッチング素子のゲートとの間に挿入された第2の抵抗と、Pチャネルのスイッチング素子のゲートとドレインとの間に並列に接続された第3の抵抗とを有し、前記Nチャネル及びPチャネルの各スイッチング素子に電圧を印加する起動回路を備えたことを特徴とする請求項1乃至3の何れかに記載のインバータ装置。   A first resistor connected in parallel between the drain and source of the N-channel switching element, and a second resistor inserted between the secondary winding and the gate of each of the N-channel and P-channel switching elements. And a starting circuit for applying a voltage to each of the N-channel and P-channel switching elements, and a third resistor connected in parallel between the gate and drain of the P-channel switching element The inverter device according to any one of claims 1 to 3, wherein the inverter device is provided. 請求項1乃至4の何れかに記載のインバータ装置と、
該インバータ装置により点灯される蛍光灯と
を備えたことを特徴とする蛍光灯装置。
An inverter device according to any one of claims 1 to 4,
A fluorescent lamp device comprising a fluorescent lamp that is turned on by the inverter device.
請求項5記載の蛍光灯装置を備えたことを特徴とする照明装置。   An illumination device comprising the fluorescent lamp device according to claim 5.
JP2006274396A 2006-10-05 2006-10-05 Inverter device, fluorescent lamp device and lighting device Expired - Fee Related JP4716968B2 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10134972A (en) * 1996-10-29 1998-05-22 Mitsubishi Electric Corp Discharge lamp lighting device
JPH10327584A (en) * 1997-05-23 1998-12-08 Toshiba Lighting & Technol Corp Power supply, fluorescent lamp and lighting equipment
JP2002027762A (en) * 2000-07-04 2002-01-25 Mitsubishi Electric Corp Inverter device, discharge lamp lighting device and bulb- type fluorescent lamp apparatus
JP2002078347A (en) * 2000-08-28 2002-03-15 Mitsubishi Electric Corp Inverter device, discharge lamp lighting device, and luminaire

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10134972A (en) * 1996-10-29 1998-05-22 Mitsubishi Electric Corp Discharge lamp lighting device
JPH10327584A (en) * 1997-05-23 1998-12-08 Toshiba Lighting & Technol Corp Power supply, fluorescent lamp and lighting equipment
JP2002027762A (en) * 2000-07-04 2002-01-25 Mitsubishi Electric Corp Inverter device, discharge lamp lighting device and bulb- type fluorescent lamp apparatus
JP2002078347A (en) * 2000-08-28 2002-03-15 Mitsubishi Electric Corp Inverter device, discharge lamp lighting device, and luminaire

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