JP2008097367A - Onboard electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To properly control access from each CPU to a recording medium in a navigation system including a plurality of CPUs and a plurality of recording media like a hard disk. <P>SOLUTION: A slave CPU 12 outputs an access request signal to a master CPU 11 to request a connection to an HDD 16, in response to an access request to the HDD 16 in processing being executed. The master CPU 11 outputs a switching control signal for controlling the switching operation of a HDD connection switching circuit 15, in accordance with the access request from processing being executed by itself and the access request signal output from the slave CPU 12. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an in-vehicle electronic device such as a navigation device using a recording medium such as a hard disk.

  Conventionally, in a navigation device for a vehicle, a hard disk is mounted as a data recording device, and various data other than map data are recorded on the hard disk, so that navigation such as map display and route search performed by a normal navigation device is performed. In addition to the processing for use, what performs various processing according to recorded data is widely known. For example, Patent Document 1 discloses a navigation device that performs music playback using music data recorded on a hard disk.

JP 2004-317385 A

  In the conventional navigation device as disclosed in Patent Document 1, usually only one CPU accesses the hard disk and executes various processes. However, the functions and performance of navigation devices have become more complex and sophisticated in recent years, and the processing load on the CPU has increased accordingly. Therefore, one CPU has insufficient processing power. . Thus, it has been studied to use a plurality of CPUs to distribute the processing load. However, if a plurality of CPUs access the hard disk at the same time, there is a risk of data destruction or abnormality. Under such circumstances, a navigation apparatus having a plurality of CPUs and a recording medium such as a hard disk is required to appropriately control access from each CPU to the recording medium.

The in-vehicle electronic device according to the invention of claim 1 includes a recording medium on which various data including at least map data are recorded, a first processing means for executing a predetermined process based on the data recorded on the recording medium, Second processing means for executing processing different from processing executed by the first processing means based on data recorded on the recording medium, and data input / output destination of the recording medium as the first processing means or the second processing means. Switching means for switching to any one of the processing means, and the second processing means outputs an access request signal to the first processing means in response to an access request by the process being executed by the second processing means. The means outputs a switching control signal to the switching means according to the access request by the process being executed by itself and the access request signal output from the second processing means, and the switching means outputs from the first processing means. Was Based on the exchange control signals and switches the data output destination recording medium.
According to a second aspect of the present invention, in the in-vehicle electronic device according to the first aspect, the first processing means has an access request by a process being executed by itself and no access request signal is output from the second processing means. Outputs a switching control signal to the switching means so as to switch the data input / output destination of the recording medium to the first processing means, and there is no access request by the process being executed by itself, and the access request signal is received from the second processing means. If it is output, the switching control signal is output to the switching means so that the data input / output destination of the recording medium is switched to the second processing means, and there is an access request by the process being executed by the second processing means. When the access request signal is output from the output unit, a switching control signal is output to the switching unit so that the data input / output destination of the recording medium is switched alternately between the first processing unit and the second processing unit. A.
According to a third aspect of the present invention, in the on-vehicle electronic device according to the first or second aspect, the switching means is configured using a plurality of three-state buffers that switch an output state in accordance with a switching control signal.
According to a fourth aspect of the present invention, in the in-vehicle electronic device according to any one of the first to third aspects, the first processing unit is configured such that the data input / output destination of the recording medium is switched to the second processing unit. Based on a control signal output from the second processing means for controlling the recording medium, the data input / output state between the recording medium and the second processing means is monitored, and the second processing means When the data input / output destination is switched to the first processing means, based on the control signal output from the first processing means to control the recording medium, the recording medium and the first processing means The data input / output state is monitored.
According to a fifth aspect of the present invention, in the in-vehicle electronic device according to any one of the first to fourth aspects, the second processing means inputs a switching control signal output from the first processing means, and the switching control signal is used as the switching control signal. Based on this, the switching means determines whether the data input / output destination of the recording medium is switched to the first processing means or the second processing means.
According to a sixth aspect of the present invention, in the in-vehicle electronic device according to any one of the first to fifth aspects, the first processing means executes a vehicle position detection process based on the map data recorded on the recording medium, and the second processing means. The processing means executes a map drawing process based on the map data recorded on the recording medium.
A seventh aspect of the present invention is the vehicle-mounted electronic device according to any one of the first to sixth aspects, wherein music data is recorded on the recording medium, and the second processing means is provided on the music data recorded on the recording medium. Based music reproduction processing is executed.

  According to the present invention, in an in-vehicle electronic device such as a navigation apparatus having a plurality of CPUs and a recording medium such as a hard disk, access from each CPU to the recording medium can be appropriately controlled.

  FIG. 1 shows the configuration of a navigation device according to an embodiment of the present invention. This navigation device is mounted on a vehicle and used. When a destination is set by a user, a recommended route from the current location to the destination is searched based on a predetermined route search condition, and the host vehicle is detected according to the searched recommended route. To the destination. This navigation apparatus is provided with two CPUs (Central Processing Unit) and one HDD (Hard Disk Drive), and the CPU connected to the HDD in response to an access request for processing executed in each CPU. Is switched to either one.

  A navigation apparatus 1 shown in FIG. 1 includes a master CPU 11, a slave CPU 12, IDE interface circuits 13 and 14 connected to the master CPU 11 and the slave CPU 12, respectively, an HDD connection switching circuit 15, and an HDD 16. . Further, it has a ROM 21, a RAM 22, a current location detection device 23, an image memory 24, a display monitor 25, and an input device 26. The master CPU 11, slave CPU 12, ROM 21, RAM 22, current location detection device 23, image memory 24, display monitor 25, and input device 26 are connected to each other by a bus 27.

  Both the master CPU 11 and the slave CPU 12 execute various processes using the RAM 13 as a work area according to programs and application software recorded in the ROM 12 and the HDD 19. The processes executed by the master CPU 11 and the slave CPU 12 include various processes related to vehicle navigation such as vehicle position detection, destination setting, recommended route search, map drawing, and music data recorded in the HDD 19. The music reproduction process used is included, and separate processes are executed in the master CPU 11 and the slave CPU 12, respectively. Note that the sharing of processing contents between the master CPU 11 and the slave CPU 12 is determined in advance based on priorities determined according to the importance, continuity, real-time property, etc. of the processing, and processing with higher priority is performed. A process that is executed by the master CPU 11 and has a relatively low priority is executed by the slave CPU 12.

  The IDE interface circuits 13 and 14 perform interface control when either the master CPU 11 or the slave CPU 12 inputs / outputs data to / from the HDD 16, respectively. This interface control is performed according to an interface standard called IDE (Integrated Drive Electronics) or ATA (AT Attachment).

  The HDD connection switching circuit 15 is a circuit for switching the data input / output destination of the HDD 16 to either the master CPU 11 or the slave CPU 12. By the switching operation performed by the HDD connection switching circuit 15, either the master CPU 11 or the slave CPU 12 is connected to the HDD 16, accesses the HDD 16, reads necessary data from the HDD 16 at the time of execution of processing, and transmits necessary data to the HDD 16. You can write. In this way, only one of the master CPU 11 and the slave CPU 12 can access the HDD 16, so that accesses from a plurality of CPUs are not duplicated to cause data destruction or abnormality.

  The switching operation of the HDD connection switching circuit 15 is controlled by a switching control signal output from the master CPU 11. Specific contents of the switching operation at this time will be described in detail later.

  The HDD 16 stores various types of data such as map data used for map display and navigation processing for guiding a vehicle to a destination, various programs executed by the master CPU 11 or the slave CPU 12, and application software. Yes. Also, music data can be taken from a CD set in a CD drive (not shown) or a memory card set in a card slot and recorded on the HDD 16. Various types of data other than those listed here can be recorded in the HDD 16.

  The map data recorded in the HDD 16 includes route calculation data used for route search, route guidance data such as intersection names and road names used to guide the vehicle to the destination according to the recommended route, roads The road data to represent is included. The map data also includes background data representing map elements other than roads such as rivers, railways, various facilities on the map (landmarks), and the like.

  In the road data, the smallest unit representing a road section is called a link. That is, each road is composed of a plurality of links set for each predetermined road section. In addition, the length of the road section set with a link differs, and the length of a link is not constant. A point connecting the links is called a node, and each node has position information (coordinate information). Also, a point called a shape interpolation point may be set between nodes in the link. Each shape interpolation point also has position information (coordinate information) like each node. The link shape, that is, the shape of the road is determined based on the position information of the node and the shape interpolation point.

  The current location detection device 23 is a device that detects the current location of the host vehicle, that is, the location of the host vehicle. For example, a vibration gyro sensor 23a that detects the traveling direction of the host vehicle, a vehicle speed sensor 23b that detects the vehicle speed, and a GPS signal from a GPS satellite. It consists of various sensors, such as a GPS sensor 23c for detecting. The navigation device 1 can determine a route search start point, which will be described later, based on the vehicle position detected by the current position detection device 23, or display the vehicle position on a map.

  The image memory 24 temporarily stores image data to be displayed on the display monitor 25. This image data includes map drawing data for displaying a map, various graphic data, and the like, and map drawing processing executed in the master CPU 11 and slave CPU 12 based on the map data recorded in the HDD 16. Created by processing. A map and various images are displayed on the display monitor 25 using the image data stored in the image memory 24.

  The input device 26 has various input switches for a user to set a destination and a waypoint of the vehicle (hereinafter simply referred to as a destination) and to set a route search condition. The input device 26 is realized by an operation panel, a remote controller, a touch panel integrated with the display monitor 25, or the like. The user operates the input device 26 to input an address, a telephone number, a facility name, designate a specific point on the map, or select one of registered locations registered in advance. , You can set the destination.

  When the user operates the input device 26 to set the destination as described above, the navigation device 1 uses the current location detected by the current location detection device 23 as a route search start point, based on the above-described route calculation data. By calculating the algorithm, route search calculation from the current location to the destination is performed. The recommended route obtained by the route search calculation is displayed on the map displayed on the display monitor 25 by distinguishing it from other roads by changing its display form, for example, display color. Thereby, the user can recognize the recommended route on the map. Moreover, the navigation apparatus 1 guides the host vehicle by instructing the user in the traveling direction by an image or sound so that the host vehicle can travel according to the recommended route. Thus, route guidance to the destination is performed by displaying the map and guiding the vehicle to the destination according to the recommended route.

  Next, the switching operation performed by the HDD connection switching circuit 15 will be described in detail. FIG. 2 schematically shows a switching operation performed by the HDD connection switching circuit 15. As shown in this figure, the HDD connection switching circuit 15 receives a switching control signal from the master CPU 11 and switches the connection destination of the HDD 16 to either the master CPU 11 or the slave CPU 12 accordingly. The master CPU 11 or slave CPU 12 connected to the HDD 16 by the HDD connection switching circuit 15 accesses the HDD 16 and inputs / outputs necessary data.

  If there is an access request to the HDD 16 in the process being executed, the slave CPU 12 requests connection to the HDD 16 by outputting an access request signal to the master CPU 11. On the other hand, the master CPU 11 switches a switching control signal for controlling the switching operation to the HDD connection switching circuit 15 in accordance with an access request from a process executed by the master CPU 11 and an access request signal output from the slave CPU 12. Is output. As described above, the switching operation of the HDD connection switching circuit 15 is controlled by the master CPU 11 and not controlled by the slave CPU 12.

  Control of the switching operation of the HDD connection switching circuit 15 by the master CPU 11 is performed as follows. When the master CPU 11 itself has an access request due to a process being executed and the slave CPU 12 does not output an access request signal, the HDD connection switching circuit 15 is switched to switch the connection destination of the HDD 16 to the master CPU 11 side. Output a control signal. On the other hand, when there is no access request due to processing being executed by the master CPU 11 itself and an access request signal is output from the slave CPU 12, a switching control signal is output that switches the connection destination of the HDD 16 to the slave CPU 12 side.

  Further, when the access request by the process being executed in the master CPU 11 and the output of the access request signal from the slave CPU 12 are simultaneously performed, the switching control signal for switching the connection destination of the HDD 16 to the master CPU 11 side and the slave CPU 12 side are switched. The switching control signal is output alternately. The master CPU 11 determines whether the HDD 16 is connected to the master CPU 11 or the slave CPU 12 in this way, and outputs a switching control signal corresponding to the determination result to the HDD connection switching circuit 15.

  The circuit configuration of the HDD connection switching circuit 15 is shown in FIG. The HDD connection switching circuit 15 is configured by using a plurality of three-state buffers provided for each signal line wired between the master CPU 11 and slave CPU 12 and the HDD 16. The signal lines include a data signal line and an IDE control signal signal line used for operation control of the HDD 16. In FIG. 3, only signal lines for outputting data from the HDD 16 to the master CPU 11 or slave CPU 12 are shown for simplification, but there are signal lines for outputting data from the master CPU 11 or slave CPU 12 to the HDD 16. To do. This signal line is similar to the illustrated signal line except that the orientation of the 3-state buffer is opposite. Further, the number of signal lines in the figure is omitted from the actual number.

  The output states of the three-state buffers of the HDD connection switching circuit 15 are switched as follows in accordance with a switching control signal from the master CPU 11. When the switching control signal is at the H (high) level, each 3-state buffer provided on the master CPU 11 side is enabled, so that an output signal from the HDD 16 is output to the master CPU 11. On the other hand, since each of the three-state buffers on the slave CPU 12 side is input at the L (low) level with the switching control signal inverted, the output becomes a high impedance state in a disabled state. As a result, the output signal from the HDD 16 is cut off and is not output to the slave CPU 12. In this way, the data input / output destination of the HDD 16 is switched to the master CPU 11.

  On the contrary, when the switching control signal is at L level, the switching control signal is inverted and input to the slave CPU 12 at H level. As a result, each 3-state buffer provided on the slave CPU 12 side is enabled, and an output signal from the HDD 16 is output to the slave CPU 12. On the other hand, since each 3-state buffer on the master CPU 11 side is disabled and its output is in a high impedance state, the output signal from the HDD 16 is cut off and not output to the master CPU 11. In this way, the data input / output destination of the HDD 16 is switched to the slave CPU 12.

  An access request signal from the slave CPU 12 is output from the output port 20. This access request signal is input to the input port 17 of the master CPU 11, and the connection destination of the HDD 16 as described above is determined in the master CPU 11.

  A switching control signal from the master CPU 11 is output from the output port 18. This switching control signal is input to the HDD connection switching circuit 15 and also to the input port 19 of the slave CPU 12. When the switching control signal is input from the master CPU 11 in this way, also in the slave CPU 12, switching in which the data input / output destination of the HDD 16 is switched to the master CPU 11 or the slave CPU 12 by the HDD connection switching circuit 15 is input. The determination can be made based on the control signal. Based on the determination result, the processing contents of the slave CPU 12 can be controlled as necessary.

  When the master CPU 11 or the slave CPU 12 inputs / outputs data to / from the HDD 16, the IDE control signal output to the HDD 16 via the IDE interface circuit 13 or 14 to control the operation of the HDD 16 is sent to the input port 17 of the master CPU 11 and Input to the input port 19 of the slave CPU. As a result, the master CPU 11 and the slave CPU 12 can monitor the data input / output state when the data input / output destination of the HDD 16 is switched to a different one. Based on the monitoring result, the processing content of the master CPU 11 or the slave CPU 12 can be controlled as necessary.

  The manner in which the data input / output destination of the HDD 16 is switched between the master CPU 11 and the slave CPU 12 by the circuit operation as described above will be described with reference to the operation timing chart of FIG. FIG. 4 shows the timing at which access to the HDD 16 is performed by each process when the vehicle position detection process is executed by the master CPU 11 and the map drawing process and the music reproduction process are executed by the slave CPU 12. ing. In addition, the priority of the process in the navigation apparatus 1 shall be high in order of a vehicle position detection process, a map drawing process, and a music reproduction process.

  First, when an access request is generated from the music playback process being executed in the slave CPU 12, the slave CPU 12 outputs an access request signal to the master CPU 11. At this time, since the access request is not generated in the master CPU 11, the switching control signal is output at the L level. The HDD connection switching circuit 15 enables each three-state buffer on the slave CPU 12 side in response to the switching control signal, and connects the HDD 16 and the slave CPU 12. After the HDD 16 and the slave CPU 12 are thus connected, the slave CPU 12 accesses the HDD 16.

  Next, when an access request is generated from the map drawing process being executed in the slave CPU 12 during access to the HDD 16 by the music playback process, the slave CPU 12 accesses the HDD 16 by the map drawing process every time a predetermined number of sectors are accessed. Access and access to the HDD 16 by music reproduction processing are alternately performed. At this time, the switching control signal output from the master CPU 11 to the HDD connection switching circuit 15 remains at the L level.

  Assume that an access request is generated from the vehicle position detection process being executed in the master CPU 11 when the slave CPU 12 is accessing the HDD 16 as described above. At this time, the master CPU 11 first outputs a switching control signal at the H level to the HDD connection switching circuit 15. The HDD connection switching circuit 15 enables each 3-state buffer on the master CPU 11 side in response to the switching control signal, and connects the HDD 16 and the master CPU 11. After the HDD 16 and the master CPU 11 are thus connected, the master CPU 11 accesses the HDD 16 in response to an access request by the vehicle position detection process.

  When access to the HDD 16 by the vehicle position detection process being executed in the master CPU 11 is executed for a predetermined number of sectors, the master CPU 11 then outputs a switching control signal to the HDD connection switching circuit 15 at the L level. The data input / output destination of the HDD 16 is switched from the master CPU 11 to the slave CPU 12. As a result, when the HDD 16 and the slave CPU 12 are connected, the slave CPU 12 first performs an access by a map drawing process having a high priority, and thereafter performs an access by a music reproduction process.

  When the HDD 16 is further accessed by a predetermined number of sectors, the master CPU 11 outputs a switching control signal at the H level, so that the data input / output destination of the HDD 16 is switched to the master CPU 11 again. When an access request by a process being executed in the master CPU 11 and an access request by a process being executed by the slave CPU 12 are simultaneously performed, such a switching operation is repeated for each predetermined number of sectors. As a result, every time a predetermined number of sectors are accessed, the data input / output destination of the HDD 16 is alternately switched between the master CPU 11 and the slave CPU 12. Therefore, in the navigation device 1 having a plurality of CPUs including the master CPU 11 and the slave CPU 12 and one HDD 16, access from each CPU to the HDD 16 can be appropriately controlled.

  As described above, when the data input / output destination of the HDD 16 is alternately switched between the master CPU 11 and the slave CPU 12, the number of sectors that each CPU continuously accesses the HDD 16 may be constant. Alternatively, the number of sectors that are continuously accessed by the master CPU 11 and the number of sectors that are continuously accessed by the slave CPU 12 may be changed. For example, the number of sectors that are continuously accessed by the master CPU 11 can be made larger than the number of sectors that are continuously accessed by the slave CPU 12. Alternatively, the number of sectors in which each CPU continuously accesses the HDD 16 may be changed according to the access occurrence status in the master CPU 11. For example, as the number of accesses from the processing being executed in the master CPU 11 increases, the number of sectors that are continuously accessed by the master CPU 11 with the HDD 16 connected to the master CPU 11 can be increased. In this way, if the number of sectors to be accessed subsequently to the HDD 16 is increased as the priority is higher, the access from each CPU to the HDD 16 can be more appropriately controlled.

  As described above, the switching operation of the HDD connection switching circuit 15 is controlled by changing the output of the switching control signal according to the access request from the process being executed in the master CPU 11 and the access request signal output from the slave CPU 12. FIG. 5 shows a flowchart of processing executed by the master CPU 11 at times. In step S10, it is determined whether or not there is an access request from a process being executed by the master CPU 11 (vehicle position detection process in the example of FIG. 4). If there is an access request from the process being executed, the process proceeds to step S20, and if not, the process proceeds to step S90.

  When the process proceeds from step S10 to step S20, in step S20, whether or not there is an output of an access request signal from the slave CPU 12 due to the process being executed by the slave CPU 12 (the map drawing process and the music reproduction process in the example of FIG. 4). Determine. If there is an output of an access request signal, the process proceeds to step S30, and if not, the process proceeds to step S70.

  When the process proceeds from step S20 to step S30, in step S30, the HDD connection switching circuit 15 is connected so that the HDD 16 is connected to the master CPU 11 side by outputting a switching control signal to the HDD connection switching circuit 15 at the H level. To work. After this switching operation, the master CPU 11 accesses the HDD 16 in response to an access request by a process being executed in the master CPU 11.

  In step S40, it is determined whether or not the master CPU 11 has accessed the HDD 16 for a predetermined number of sectors after the HDD 16 is connected to the master CPU 11 by the process of step S30. The process stays at step S40 until the predetermined number of sectors is accessed, and proceeds to the next step S50 when the predetermined number of sectors is accessed.

  In step S50, the HDD connection switching circuit 15 is operated so that the HDD 16 is connected to the slave CPU 12 side by outputting a switching control signal to the HDD connection switching circuit 15 at the L level. As a result, the data input / output destination of the HDD 16 is switched from the master CPU 11 to the slave CPU 12. Thereafter, the slave CPU 12 accesses the HDD 16 in response to an access request by a process being executed in the slave CPU 12.

  In step S60, it is determined whether or not the slave CPU 12 has accessed the HDD 16 for a predetermined number of sectors after the HDD 16 is connected to the slave CPU 12 side in the process of step S50. Until the predetermined number of sectors is accessed, the process stays at step S60. When the predetermined number of sectors is accessed, the process returns to step S10.

  After returning from step S60 to step S10, the process of steps S30 to S60 is repeatedly executed as described above while there is an access request by the process being executed by the master CPU 11 and the access request signal is output from the slave CPU 12. Is done. Thus, every time the master CPU 11 or the slave CPU 12 accesses a predetermined number of sectors, the data input / output destination of the HDD 16 is switched alternately between the master CPU 11 and the slave CPU 12.

  On the other hand, when the process proceeds from step S20 to step S70, in step S70, as in step S30, the HDD 16 is connected to the master CPU 11 side by outputting a switching control signal to the HDD connection switching circuit 15 at the H level. Thus, the HDD connection switching circuit 15 is operated. After this switching operation, the master CPU 11 accesses the HDD 16 in response to an access request by a process being executed in the master CPU 11.

  In step S80, it is determined whether or not the master CPU 11 has accessed the HDD 16 for a predetermined number of sectors after the HDD 16 is connected to the master CPU 11 by the process of step S70. The process stays at step S80 until the predetermined number of sectors is accessed, and returns to step S10 when the predetermined number of sectors is accessed.

  After returning from step S80 to step S10, the processing of steps S70 and S80 as described above is repeatedly executed while there is an access request by the processing being executed by the master CPU 11 and the access request signal is not output from the slave CPU 12. Is done. Thereby, the data input / output destination of the HDD 16 is switched to the master CPU 11.

  When the process proceeds from step S10 to step S90, it is determined in step S90 whether there is an access request signal output from the slave CPU 12 as in step S20. If there is an output of an access request signal, the process proceeds to step S100, and if not, the process returns to step S10.

  In step S100, similarly to step S50, the HDD connection switching circuit 15 is operated so that the HDD 16 is connected to the slave CPU 12 side by outputting a switching control signal to the HDD connection switching circuit 15 at the L level. As a result, the slave CPU 12 accesses the HDD 16 in response to an access request by a process being executed in the slave CPU 12.

  In step S110, it is determined whether or not the slave CPU 12 has accessed the HDD 16 for a predetermined number of sectors after the HDD 16 is connected to the slave CPU 12 side in the process of step S100. The process stays in step S110 until the predetermined number of sectors is accessed, and returns to step S10 when the predetermined number of sectors is accessed.

  After returning from step S110 to step S10, the processing of steps S100 and S110 as described above is repeatedly executed while there is no access request by the processing being executed by the master CPU 11 and the access request signal is output from the slave CPU 12. Is done. As a result, the data input / output destination of the HDD 16 is switched to the slave CPU 12.

According to the embodiment described above, the following operational effects can be achieved.
(1) The slave CPU 12 outputs an access request signal to the master CPU 11 in response to an access request by a process being executed by the slave CPU 12 itself. The master CPU 11 outputs a switching control signal to the HDD connection switching circuit 15 in response to an access request by a process being executed by the master CPU 11 itself and an access request signal output from the slave CPU 12. The HDD connection switching circuit 15 that has received the switching control signal output from the master CPU 11 switches the data input / output destination of the HDD 16 to either the master CPU 11 or the slave CPU 12 based on the switching control signal. Thus, in a navigation device having a plurality of CPUs and a recording medium such as a hard disk, access from each CPU to the recording medium can be appropriately controlled.

(2) The master CPU 11 determines whether or not there is an access request by the process being executed (step S10), and determines whether or not an access request signal is output from the slave CPU 12 (step S20, In step S90, the data input / output destination of the HDD 16 is switched to either the master CPU 11 or the slave CPU 12 by changing the switching control signal output to the HDD connection switching circuit 15 according to the determination result.

  That is, when there is an access request due to a process being executed by the master CPU 11 itself and no access request signal is output from the slave CPU 12, the HDD connection switching circuit 15 is controlled to switch the data input / output destination of the HDD 16 to the master CPU 11. A signal is output (step S70). When there is no access request due to the process being executed by the master CPU 11 itself and an access request signal is output from the slave CPU 12, a switching control signal is sent to the HDD connection switching circuit 15 to switch the data input / output destination of the HDD 16 to the slave CPU 12. Output (step S100). When there is an access request due to a process being executed by the master CPU 11 and an access request signal is output from the slave CPU 12, the HDD connection switching circuit 15 switches the data input / output destination of the HDD 16 alternately between the master CPU 11 and the slave CPU 12. A switching control signal is output to (steps S30 to S60). Since it did in this way, according to the access request | requirement of the process performed in each CPU, the access to a recording medium from each CPU can be appropriately controlled.

(3) Since the HDD connection switching circuit 15 is configured using a plurality of three-state buffers that switch the output state in accordance with a switching control signal from the master CPU 11, the HDD connection switching circuit 15 can be configured with a simple circuit configuration. Switching operation can be realized.

(4) When the master CPU 11 or the slave CPU 12 inputs / outputs data to / from the HDD 16, an IDE control signal for controlling the operation of the HDD 16 is input to the master CPU 11 and the slave CPU 12. Thus, the master CPU 11 monitors the data input / output state between the HDD 16 and the slave CPU 12 based on the IDE control signal output from the slave CPU 12 when the data input / output destination of the HDD 16 is switched to the slave CPU 12. . Similarly, the slave CPU 12 monitors the data input / output state between the HDD 16 and the master CPU 11 based on the IDE control signal output from the master CPU 11 when the data input / output destination of the HDD 16 is switched to the master CPU 11. It was. Since it did in this way, the processing content of master CPU11 or slave CPU12 can be controlled as needed based on the monitoring result.

(5) A switching control signal from the master CPU 11 is input to the slave CPU 12, and the data input / output destination of the HDD 16 is switched to the master CPU 11 or the slave CPU 12 by the HDD connection switching circuit 15 based on the switching control signal. Is determined by the slave CPU 12. Since it did in this way, based on a discrimination | determination result, the processing content of the slave CPU12 can be controlled as needed.

  In the above-described embodiment, an example in which the data input / output destination of the HDD 16 is alternately switched between the master CPU 11 and the slave CPU 12 every time the master CPU 11 or the slave CPU 12 accesses a predetermined number of sectors has been described. The data input / output destination of the HDD 16 may be switched every elapsed time instead of the number. That is, the data input / output destination of the HDD 16 can be alternately switched between the master CPU 11 and the slave CPU 12 at predetermined time intervals set in advance. In this case as well, the time interval at which the HDD 16 is connected can be changed between the master CPU 11 side and the slave CPU 12 side as described in the above embodiment. Even if it does in this way, the effect similar to having demonstrated in the said embodiment can be acquired.

  In the above embodiment, an example in which a hard disk is used as a recording medium for recording various data has been described. However, the present invention can also be applied to a case where a recording medium other than a hard disk is used. For example, the present invention is applied to access control to various recording media such as optical disks such as CD-ROM and DVD-ROM, nonvolatile memories such as flash memory and various memory cards, and rewritable optical disks. be able to. Moreover, although said embodiment demonstrated the navigation apparatus for vehicles to the example, this invention is applicable also to other various vehicle-mounted electronic devices. For example, an automatic recording device that automatically captures a recorded photograph when a vehicle has an accident, a theft monitoring device that automatically collects and transmits surrounding information when a vehicle is stolen, and records music data The present invention can be applied to various in-vehicle electronic devices such as a music playback device for playback.

  In the above-described embodiment, the method of controlling access to one HDD 16 when two CPUs including the master CPU 11 and the slave CPU 12 are used has been described. However, the same method can be used when controlling access to one HDD using three or more CPUs. The same applies when two or more HDDs are connected to a plurality of CPUs.

  Furthermore, in the above embodiment, the master CPU 11 executes the vehicle position detection process and the slave CPU 12 executes the map drawing process and the music reproduction process. However, the contents of the processes executed by each CPU are limited to this. It is not something. For example, in the master CPU 11, processing for vehicle travel control performed based on map data, such as curvature calculation processing of the road ahead, processing for reading road regulation information, calculation processing of recommended vehicle speed, etc. as relatively high priority processing, The self-diagnosis process of the navigation device 1 can be executed. The slave CPU 12 can execute vehicle guidance processing based on map data, such as route calculation processing and route guidance processing, as lower priority processing than the master CPU 11.

  Note that it is not always necessary for the master CPU 11 to execute a process having a higher priority than the slave CPU 12. For example, the master CPU 11 is composed of highly reliable parts with excellent environmental resistance, the slave CPU 12 is composed of ordinary parts, and the master CPU 11 executes the minimum processing necessary for the navigation device, thereby causing severe conditions. A navigation device that can be used even in an environment can be provided. Alternatively, by performing the same processing in the master CPU 11 and the slave CPU 12, the processing can be duplicated and the reliability of the navigation device can be improved. In addition to this, various processes can be executed in the master CPU 11 and the slave CPU 12.

  The embodiment and various modifications described above are merely examples, and the present invention is not limited to these contents as long as the features of the invention are not impaired.

  In the above embodiment, the recording medium is realized by the HDD 16, the first processing means is realized by the master CPU 11, the second processing means is realized by the slave CPU 12, and the switching means is realized by the HDD connection switching circuit 15. However, this is merely an example, and when interpreting the invention, there is no limitation or restriction on the correspondence between the items described in the above embodiments and the items described in the claims.

It is a block diagram which shows the structure of the navigation apparatus by one Embodiment of this invention. It is the figure which represented typically the switching operation which an HDD connection switching circuit performs. It is a figure which shows the circuit structure of a HDD connection switching circuit. FIG. 10 is an operation timing chart showing how the data input / output destination of the HDD is switched between a master CPU and a slave CPU. 7 is a flowchart when the output of a switching control signal is changed in the master CPU to control the switching operation of the HDD connection switching circuit.

Explanation of symbols

1: Navigation device 11: Master CPU
12: Slave CPU 13, 14: IDE interface circuit 15: HDD connection switching circuit 16: HDD
21: ROM 22: RAM
23: Current location detection device 24: Image memory 25: Display monitor 26: Input device 27: Bus

Claims (7)

A recording medium on which various data including at least map data are recorded;
First processing means for executing predetermined processing based on data recorded on the recording medium;
Second processing means for executing processing different from processing executed by the first processing means based on data recorded on the recording medium;
Switching means for switching the data input / output destination of the recording medium to either the first processing means or the second processing means,
The second processing means outputs an access request signal to the first processing means in response to an access request by a process being executed by the second processing means,
The first processing means outputs a switching control signal to the switching means in response to an access request by a process being executed by itself and an access request signal output from the second processing means,
The on-vehicle electronic device characterized in that the switching means switches a data input / output destination of the recording medium based on a switching control signal output from the first processing means. The in-vehicle electronic device according to claim 1,
The first processing means sets the data input / output destination of the recording medium to the first when the access request signal is not output from the second processing means when there is an access request by the process being executed by the first processing means. Outputting a switching control signal to the switching means to switch to the processing means,
When there is no access request by the process being executed and the access request signal is output from the second processing means, the switching means is configured to switch the data input / output destination of the recording medium to the second processing means. Switch control signal to
When there is an access request by the process being executed and an access request signal is output from the second processing means, the data processing destination of the recording medium is designated as the first processing means and the second processing means. An in-vehicle electronic device characterized in that a switching control signal is output to the switching means so as to be switched alternately. The in-vehicle electronic device according to claim 1 or 2,
The on-vehicle electronic device characterized in that the switching means is configured using a plurality of three-state buffers that switch an output state according to the switching control signal. The in-vehicle electronic device according to any one of claims 1 to 3,
The first processing means outputs a control signal output from the second processing means for controlling the recording medium when the data input / output destination of the recording medium is switched to the second processing means. And monitoring the data input / output state between the recording medium and the second processing means,
The second processing means outputs a control signal output from the first processing means for controlling the recording medium when the data input / output destination of the recording medium is switched to the first processing means. And monitoring the data input / output state between the recording medium and the first processing means. In the vehicle-mounted electronic device as described in any one of Claims 1-4,
The second processing means receives the switching control signal output from the first processing means, and based on the switching control signal, the data input / output destination of the recording medium is set to the first processing by the switching means. An in-vehicle electronic device characterized in that it is switched to one of the means and the second processing means. In the vehicle-mounted electronic device as described in any one of Claims 1-5,
The first processing means executes vehicle position detection processing based on map data recorded on the recording medium,
The on-vehicle electronic device characterized in that the second processing means executes a map drawing process based on the map data recorded on the recording medium. The in-vehicle electronic device according to any one of claims 1 to 6,
Music data is recorded on the recording medium,
The on-vehicle electronic device characterized in that the second processing means executes music reproduction processing based on music data recorded on the recording medium.

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