JP2008089548A - Fail information storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that the necessity of scanning a fail memory after the completion of a full-function test and finding the number of fails and a function test address, resulting in increased test time. <P>SOLUTION: Fail information is written back to a fail memory. A file detection circuit detects the first time that the file information fails. A fail counter is incremented by an output of the fail detection circuit. When the counter is incremented, a function test address is stored in a fail address memory. This makes it unnecessary to scan the fail memory after a test, so that the test time can be shortened. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an information storage device for storing fail information, and more particularly to a fail information storage device suitable for use in a memory test system for testing a flash memory.

  In a memory test system that performs a memory test, a function test is performed on each memory cell of the memory under measurement to determine whether the memory under measurement is good or bad. A flash memory, which is a type of memory, can be used as a non-defective product if the defective rate is a certain value or less even if some of the memory cells are defective. Therefore, a memory test system for testing a flash memory must have a mechanism for detecting the number and address of defective cells.

  In order to detect the number of defective cells and their addresses, function test fail information is stored in a fail memory having the same capacity as the memory device under test or a capacity compressed to a fraction, and from this stored fail information The number of failures and their addresses are obtained to determine whether the memory device is good or bad. The fail information is 1-bit data that is “0” when the memory cell is a non-defective product and “1” when the memory cell is defective.

  FIG. 6 shows the configuration of a fail information storage device that stores fail information. In FIG. 6, a selector 10 receives a function test address, which is an address of a memory cell to be tested, and an address generated by an address generator 11 from a pattern generator (not shown). The selector 10 selects one of the two input addresses and outputs it to the address terminal A of the fail memory 12. During the function test, the selector 10 is set to select a function test address.

  Fail information, which is a test result of the memory cell, is input to the OR gate 15, and an output of the OR gate 15 is input to the three-state buffer 14. The output of the three-state buffer 14 is input to the data terminal D of the fail memory 12, the clock terminal CK of the fail counter 16, and the inverter 18. The output Q of the latch 13 is input to the other input terminal of the OR gate 15. The output of the inverter 18 controls the start and stop of the operation of the address generator 11. The controller 17 performs writing / reading of the fail memory 12, operation of the latch 13, and output control of the three-state buffer 14. The output of the three-state buffer 14 is enabled only when writing to the fail memory 12 so as not to collide with the output of the fail memory 12.

  In such a configuration, fail information and a function test address are output for each test cycle of the function test. During the function test, the function test address is input to the address terminal of the fail memory.

  The controller 17 reads out the data stored in the fail memory 12 and stores it in the latch 13. The stored value and fail information are ORed by the OR gate 15 and input to the data terminal D of the fail memory 12 via the three-state buffer 14. The controller 17 writes the output of the OR gate 15 back to the fail memory 12.

  That is, when both the value stored in the fail memory 12 and the fail information are “0” (pass), the data written back to the fail memory 12 is also “0”. When either or both of the value stored in the fail memory 12 and the fail information are “1”, the value written back to the fail memory 12 is “1” (fail). By repeating this function test, “1” is written to the address of the fail memory 12 corresponding to the memory cell whose fail information is “1” even once.

  When the function test is completed, the selector 10 is set to select the output of the address generator 11. The address generator 11 generates FM read addresses, and sequentially generates addresses within a given range. The controller 17 reads the contents of the fail memory for each generated address. The fail information is fixed to “0”. Every time the content of the fail memory 12 becomes “1”, the output of the three-state buffer 14 becomes “1”. The fail counter 16 counts the number of “1”, that is, the number of abnormal memory cells. By reading the count value of the fail counter 16, the number of abnormal memory cells in the given address range can be known.

  The output of the three-state buffer 14 is inverted by the inverter 18 and input to the START / STOP terminal of the address generator 11. Thus, every time the content of the fail memory 12 becomes “1”, the operation of the address generator 11 is stopped. Therefore, the address is read while the operation is stopped.

  Next, the operation will be described with reference to FIG. Note that the memory device to be tested has 64 memory cells, and the addresses of these memory cells are (X0, Y0) to (X7, Y7).

  FIG. 7A shows the contents of the fail memory 12 immediately after the function test. It is assumed that the cell in which “1” is written is defective. Since it becomes complicated, “0” is omitted and left blank. The address generator 11 generates addresses in the order of (X0, Y0), (X1, Y0) to (X7, Y7), and obtains the number of “1” and the fail address. That is, the memory cells are scanned in the order of the arrow 20.

  FIG. 5B shows the count value of the fail counter 16 and the address information of the memory cell that has failed. The upper stage is the value of the fail counter 16 and the lower stage is the fail address. When the output address of the address generator 11 becomes (X6, Y1), the fail counter 16 is incremented and its value becomes 1 as shown in (a). The address generator 11 stops and the address (X6, Y1) is taken.

  Similarly, as shown in (A), the count value is 2 at the address (X0, Y2), as shown in (C), the count value is 3 at the address (X1, Y2), and as shown in (D). The count value becomes 4 at the address (X2, Y5), and the address information is taken in each. Scan to address (X7, Y7) and finish. By doing so, it is possible to capture the number of memory cells determined to be defective and their address information.

JP 2004-348892 A

  However, in the fail information storage device having such a configuration, first, a function test is performed to store fail information in the fail memory 12, and after the function test is completed, the fail memory is scanned from the beginning to the end, and the number of defective memory cells and You must capture that address. Therefore, an extra time is required for scanning the fail memory 12, and there is a problem that the test time becomes long.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a fail information storage device capable of determining the number of addresses and their addresses at the same time as storing fail information.

In order to achieve such a problem, the invention according to claim 1 of the present invention is:
Fail information and a test address are input, and a fail memory unit that writes back a value stored in the test address and a value obtained by calculating the fail information to the test address;
A fail detection circuit that refers to a value stored in the fail memory unit and detects that the fail information has first failed;
A counter incremented by the output of the fail detection circuit;
A fail address memory for storing the test address at an address associated with the count value when the counter is incremented;
Is provided. Since the number of failures and the test address are obtained at the end of the test, the test time can be shortened.

The invention according to claim 2
A switching clock generator that receives a test cycle clock and generates at least two switching clocks generated by dividing the test cycle clock;
An interleave switching circuit that receives at least fail information and a test address, and holds data input by an output of the switching clock generator for a predetermined period;
At least two fail information storage circuits having the same configuration as the fail information storage device according to claim 1, to which an output of the interleave switching circuit is input;
After the test is completed, the test address stored in the fail address memory in the other fail information storage circuit excluding the first fail information storage circuit which is one of the fail information storage circuits is stored in the first fail information storage circuit. A controller that stores the test address in the fail address memory in the first fail information storage circuit and increments a counter when not stored in the fail address memory in the circuit;
Is provided. Even if the cycle of the test cycle is shorter than the access time of the fail memory or the like, the fail information can be reliably stored.

The invention according to claim 3 is the invention according to claim 1 or claim 2,
The fail detection circuit includes an inverter that inverts the output of the fail memory, and a gate that receives the output of the inverter and the fail information. Configuration is simplified.

As is apparent from the above description, the present invention has the following effects.
According to the first, second, and third aspects of the invention, the logical sum of the fail information and the value already stored in the fail memory is calculated and written back to the fail memory, and the counter is set when the fail information first fails. The test address at that time is incremented and stored in the fail address memory.

  Since the number of failures and the test address at that time are obtained at the end of the test, it is not necessary to scan the fail memory after the end of the test to obtain the number of failures and the test address at that time. Therefore, there is an effect that the test time can be shortened.

  Also, by using two or more fail information storage circuits in an interleaved manner, there is an effect that fail information can be stored reliably even if the test cycle period is shorter than the access time of the fail memory.

  Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a fail information storage device according to the present invention. In addition, the same code | symbol is attached | subjected to the same element as FIG. 6, and description is abbreviate | omitted. Also, the description will be made assuming that the memory test system is used for testing a memory.

  In FIG. 1, reference numeral 30 denotes a fail information storage device, which comprises a fail memory 12, a latch 13, a three-state buffer 14, an OR gate 15, a fail detection circuit 31, a fail counter 16, and a fail address memory 34. A controller 40 controls the fail memory 12, the latch 13, the three-state buffer 14, and the fail address memory 34.

  A function test address is input to the address terminal A of the fail memory 12. The fail information stored in the function test address is stored in the latch 13, is calculated as fail information by the OR gate 15, and is written back to the fail memory 12. This operation is the same as the conventional example of FIG. The fail memory 12, the three-state buffer 14 and the OR gate 15 constitute a fail memory unit.

  The fail detection circuit 31 includes an inverter 32 and an AND gate 33. The output of the latch 13 is input to the inverter 32, and the output is input to one input terminal of the AND gate 33. Fail information is input to the other input terminal of the AND gate 33. Therefore, the output of the AND gate 33 becomes “1” only when the output of the latch 13 is “0” and the fail information is “1”. That is, the output of the fail detection circuit 31 is “1” only when the fail information is initially “1”.

  Since the output of the fail detection circuit 31 is input to the clock terminal CK of the fail counter 16, the fail counter 16 is incremented when the fail information first becomes "1". The output (count value) of the fail counter 16 is input to the address terminal A of the fail address memory 34, and the function test address is input to the data bus D. When the output of the fail detection circuit 31 becomes “1”, the controller 40 stores the function test address in the address of the count value of the fail counter 16. As a result, the fail counter 16 stores the number of failures, and the fail address memory 34 stores the failed function test address. Note that the address of the fail address memory 34 in which the function test address is stored need not be the count value of the fail counter 16 but may be an address related thereto.

  Next, the operation of this embodiment will be described with reference to FIG. As in the conventional example of FIG. 6, it is assumed that the function test address is composed of two addresses, address X and address Y. Further, it is assumed that “0” is normal for the fail information. FIG. 2 is a time chart showing the address X, address Y, fail memory 12 output, fail information, OR gate 15 output, fail detection circuit 31 output, and fail counter 16 output from the top, and the horizontal axis represents the test cycle.

  In the test cycle n, the address X is X5, the address Y is Y1, and the count value of the fail counter 16 is m. Since both the output of the fail memory 12 and the fail information are “0” (normal), both the OR gate 15 output and the fail detection circuit 31 output are “0”. The fail counter 16 is not incremented.

  In the test cycle n + 1, the address X changes to X6 and the fail information changes to “1”. Since the output of the fail memory 12 is “0”, it becomes the first fail. The output of the OR gate 15 and the output of the fail detection circuit 31 change to “1”. For this reason, the fail counter 16 is incremented and the count value becomes m + 1. The controller 40 stores the function test address (X6, Y1) at the address m + 1 of the fail address memory 34.

  The address X changes to X7 in the test cycle n + 2. Since both the fail memory 12 output and the fail information are “0”, both the OR gate 15 output and the fail detection circuit 31 output are “0”, and the count value of the fail counter 16 maintains m + 1.

  In the test cycle n + 3, the address X changes to X0, the address Y changes to Y2, and the fail information changes to “1”. Since the output of the fail memory 12 is also “1”, the output of the fail detection circuit 31 maintains “0”, and the count value of the fail counter 16 does not change.

  In the test cycle n + 4, the address X changes to X1 and the fail information changes to “0”. Therefore, the output of the fail detection circuit 31 maintains “0”, and the count value of the fail counter 16 does not change. Since the output of the fail memory 12 is “1”, the output of the OR gate 15 is also “1”.

  The address X changes to X2 in the test cycle n + 5. Since the fail information is “0”, the output of the fail detection circuit 31 also maintains “0”. The count value of the fail counter 16 does not change. Further, since the output of the fail memory 12 is “0”, the output of the OR gate 15 is also “0”. Thus, the fail counter 16 is incremented only when the output of the fail memory 12 is “0” and the fail information is “1”.

  FIG. 3 shows the states of the fail memory 12, the fail counter 16, and the fail address memory 34 before and after a certain function test. (A) shows the state before the function test, (B) shows the state after the function test, the left side is the contents of the fail memory 12, the upper right is the count value of the fail counter 16, and the lower right is the address stored in the fail address memory 34. is there. In order to avoid complication, “0” in the diagram on the left is omitted and left blank.

  As shown in (A), “1” (fail) is written in the addresses (X0, Y2), (X1, Y2), and (X2, Y5) of the fail memory 12 before the function test. The count value of the fail counter 16 is 3, and addresses (X0, Y2), (X1, Y2), (X2, Y5) are stored in the fail address memory 34.

  In the function test, it is assumed that the fail information becomes “1” at addresses (X0, Y2) and (X6, Y1). At the address (X0, Y2), since a failure has occurred previously, the output of the fail detection circuit 31 does not change, so neither the count value of the fail counter 16 nor the contents of the fail address memory 34 change.

  Since the fail information becomes “1” for the first time at the address (X6, Y1), the output of the fail detection circuit 31 changes from “0” to “1”. Therefore, the fail counter 16 is incremented, and the address (X6, Y1) is stored in the fail address memory 34. When the function test is completed, the contents of the address (X6, Y1) of the fail memory 12 change to “1” as shown in FIG. Further, the count value of the fail counter 16 increases by 1 to 4, and the address (X6, Y1) is added to the fail address memory 34 to store four addresses.

  In this way, the fail detection circuit 31 first detects that the fail information has become “1”. At this time, the fail counter 16 is incremented, and the function test address at that time is stored in the fail address memory 34. I did it. Therefore, at the end of the function test, the number of fail information “1” and the function test address at that time are obtained, and it is not necessary to scan the fail memory 12 again. As a result, the test time can be shortened.

  FIG. 4 shows another embodiment of the present invention. The fail information storage device of FIG. 1 cannot accurately store fail information if the cycle of the test cycle is shorter than the write back time of the fail memory 12. Therefore, two fail information storage circuits are used and used in an interleaved manner.

  In FIG. 4, reference numeral 50 denotes a switching clock generator, which receives a test cycle clock generated every test cycle, and outputs a signal obtained by dividing the test cycle clock to outputs A and B. Reference numeral 60 denotes an interleave switching circuit, which includes 61 to 66 latches. The output A of the switching clock generator 50 is input to the clock input terminal CLK of the latches 61, 63, 65, and the output B of the switching clock generator 50 is input to the clock input terminal CLK of the latches 62, 64, 66.

  Fail information is input to the data terminals D of the latches 61 and 62, and a function test address is input to the data terminals D of the latches 63 and 64. The memory write enable signal of the fail memory 12 is input to the data terminals D of the latches 65 and 66. In general, a plurality of latches are required to latch a function test address, but in FIG. 4, only one latch is represented.

  Reference numeral 51 denotes a selector. A fixed value “1” is input to the input terminal A1, the output of the latch 62 is input to B1, the output of the fail address memory 34a is input to A2, and the output of the latch 64 is input to B2. The selector 51 selects either A1 or B1 according to the value input to the selection terminal S, selects either A1 or B2, and outputs it to Q2.

  A fail information storage circuit 53 has the same configuration as that of the fail information storage device of FIG. That is, 12a is a fail memory 12, 13a is a latch 13, 14a is a three-state buffer 14, 15a is an OR gate 15, 16a is a fail counter 16, 31a is a fail detection circuit 31, and 34a is a fail address memory 34. It corresponds to. Write control of the fail memory 12a is performed by a memory write enable signal latched in the latch 65. The output of the latch 61 is input to the AND gate and the OR gate 15a in the fail detection circuit 31a, and the output of the latch 63 is input to the address of the fail memory 12a.

  54 is a fail information storage circuit, which has the same configuration as the fail information storage device of FIG. That is, 12b is the fail memory 12, 13b is the latch 13, 14b is the three-state buffer 14, 15b is the OR gate 15, 16b is the fail counter 16, 31b is the fail detection circuit 31, and 34b is the fail address memory 34. It corresponds to. Write control of the fail memory 12b is performed by a memory write enable signal latched in the latch 66. The output of the latch 62 is input to the AND gate and OR gate 15b in the fail detection circuit 31b, and the output Q2 of the selector 51 is input to the address of the fail memory 12b.

  The controller 52 controls the selector 51, fail memories 12a and 12b, latches 13a and 13b, three-state buffers 14a and 14b, fail address memories 34a and 34b, and the selector 51. Since the figure becomes complicated, only representative connections are shown, and some connections are omitted.

  In such a configuration, the fail information storage circuits 53 and 54 operate alternately every test cycle. This will be described with reference to FIG. FIG. 5 shows the test cycle clock input to the switching clock generator 50 from the top, the internal signal of the switching clock generator 50, the output A and the output B of the switching clock generator 50, the function test address, and the input to the fail memory 12a. This represents a change in the address input to the fail memory 12b via the selector 51. Note that the cycle of the test cycle is T, and the signal of the selection terminal S is set so that the selector 51 selects B1 and B2 during the function test.

  The internal signal of the switching clock generator 50 is a signal having a cycle of 2T and a duty of 50%, which changes at the falling edge of the test cycle clock. The output A of the switching clock generator 50 is a signal that falls at the rise of the internal signal and rises at the rise of the test cycle clock immediately before that. The output B of the switching clock generator 50 is a signal that falls at the falling edge of the internal signal and rises at the rising edge of the test cycle clock immediately before. In either case, the cycle is 2T, and the phase difference between the output B and the output A is T.

  The function test address changes with the period T of the test cycle clock. In FIG. 5, n at time t <b> 1 and increases by 1 every period T. This function test address is stored in the latch 63 at the output A of the switching clock generator 50. Therefore, the input address of the fail memory 12a changes in the order of n, n + 2, n + 4,. Further, since the function test address is stored in the latch 64 at the output B of the switching clock generator 50, the input address of the fail memory 12b changes in a cycle of 2T in the order of n + 1, n + 3,.

  Since the fail information and the memory write enable signal are also latched by the latches 61, 62, 65 and 66, these signals input to the fail information storage circuits 53 and 54 are also held for a period 2T. Therefore, the fail information storage circuits 53 and 54 can use the time twice as long as the test cycle period T to write the fail information back to the fail memories 12a and 12b and write the fail address to the fail address memories 34a and 34b. Therefore, even when the cycle T is shorter than the access time of the fail memories 12a, 12b, etc., fail information can be written back and the fail address can be stored reliably.

  The function test may test memory cells having non-contiguous addresses, and may test the same memory cell multiple times. Therefore, fail information may be stored in only one of the fail information storage circuits 53 and 54. Therefore, after all the function tests are completed, an operation for integrating the fail information stored in the fail information storage circuit 53 into the fail information storage circuit 54 is performed.

Therefore, the controller 52 operates the selector 51 so that the selector 51 selects and outputs the signals A1 and A2. The controller 52 decrements the fail counter 16a, and reads the last stored fail address information from the fail address memory 34a. The fail address information is applied as an address to the fail memory 12b of the fail information storage circuit 54 via the selector 51. The fail memory 12b reads the fail information at the address, and determines whether the failure has already been stored in the fail information storage circuit 54 by the fail detection circuit 31b. If the failure has already been stored, the output of the fail detection circuit 31b is “0”, so nothing is done. If it is a new failure, the address information is stored in the fail address memory 34b and the fail counter 16b is incremented.

  The controller 52 decrements the fail counter 16a of the fail information storage circuit 53, reads the previous fail address information from the fail address memory 34a, and repeats the same process. By repeating until the fail count 16a becomes 0, the fail information in the fail information storage circuit 53 is transferred to the fail address memory 34b and the fail counter 16b in the fail information storage circuit 54.

  For this reason, the operation of transferring the fail information stored in the fail information storage circuit 53 to the fail address memory 34b and the fail counter 16b included in the fail information storage circuit 54 may be repeated as many times as the number of failures stored in the fail information storage circuit 53. The increase in time is slight.

  In the embodiment of FIG. 4, two fail information storage circuits are used and used alternately. However, three or more fail information storage circuits may be used and operated in order. In this way, it is possible to cope with a test cycle having a shorter period.

  In this embodiment, the controller 52 controls the fail memories 12a and 12b, the latches 13a and 13b, the three-state buffers 14a and 14b, and the fail address memories 34a and 34b. These control signals may be given from the outside.

  In these embodiments, a failure is indicated when the fail information is “1”. However, a failure may be indicated when the fail information is “0”. In this case, an AND gate is used as the OR gate 15 and an OR gate is used as the AND gate 33 so that “1” is written in all the cells of the fail memory 12 before the function test.

  Furthermore, although the case where this embodiment is used in a memory test system has been described, the present invention is not limited to this. It can also be used as a storage device for storing quality information of parts having a plurality of cells.

It is a block diagram which shows one Example of this invention. It is a time chart which shows operation | movement of one Example of this invention. It is a characteristic view for demonstrating operation | movement of one Example of this invention. It is a block diagram which shows the other Example of this invention. It is a time chart which shows operation | movement of the other Example of this invention. It is a block diagram of the conventional fail information storage device. It is a characteristic view for demonstrating operation | movement of the conventional fail information storage device.

Explanation of symbols

12, 12a, 12b Fail memories 13, 13a, 13b, 61-66 Latches 14, 14a, 14b Three-state buffers 15, 15a, 15b OR gates 16, 16a, 16b Fail counters 31, 31a, 31b Fail detection circuit 32 Inverter 33 and Gate 34, 34a, 34b Fail address memory 40, 52 Controller 50 Switching clock generator 51 Selector 53, 54 Fail information storage circuit 60 Interleave switching circuit

Claims (3)

Fail information and a test address are input, and a fail memory unit that writes back a value stored in the test address and a value obtained by calculating the fail information to the test address;
A fail detection circuit that refers to a value stored in the fail memory unit and detects that the fail information has first failed;
A counter incremented by the output of the fail detection circuit;
A fail address memory for storing the test address at an address associated with the count value when the counter is incremented;
A fail information storage device comprising: A switching clock generator that receives a test cycle clock and generates at least two switching clocks generated by dividing the test cycle clock;
An interleave switching circuit that receives at least fail information and a test address, and holds data input by an output of the switching clock generator for a predetermined period;
At least two fail information storage circuits having the same configuration as the fail information storage device according to claim 1, to which an output of the interleave switching circuit is input;
After the test is completed, the test address stored in the fail address memory in the other fail information storage circuit excluding the first fail information storage circuit which is one of the fail information storage circuits is stored in the first fail information storage circuit. A controller that stores the test address in the fail address memory in the first fail information storage circuit and increments a counter when not stored in the fail address memory in the circuit;
A fail information storage device comprising:   3. The fail information according to claim 1, wherein the fail detection circuit includes an inverter that inverts the output of the fail memory, and a gate to which the output of the inverter and the fail information are input. Storage device.

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