JP2008089484A - Semiconductor inspection mechanism, and inspection method of semiconductor integrated circuit - Google Patents

Semiconductor inspection mechanism, and inspection method of semiconductor integrated circuit Download PDF

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JP2008089484A
JP2008089484A JP2006272363A JP2006272363A JP2008089484A JP 2008089484 A JP2008089484 A JP 2008089484A JP 2006272363 A JP2006272363 A JP 2006272363A JP 2006272363 A JP2006272363 A JP 2006272363A JP 2008089484 A JP2008089484 A JP 2008089484A
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voltage
measured
conversion circuit
voltage source
circuit
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Harumi Nakada
晴己 中田
Kazunobu Miyasako
和宜 宮迫
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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<P>PROBLEM TO BE SOLVED: To provide a semiconductor inspection mechanism capable of accurately measuring the conversion characteristic of a D/A conversion circuit mounted on a semiconductor integrated circuit using a device of a voltage resolution lower than that of a measured D/A conversion circuit. <P>SOLUTION: The differential voltage obtained by subtracting supplied voltage of a voltage source 4 from the output voltage of the measured D/A conversion circuit 2 with a subtracting circuit 5 is measured by a voltage measurement device 6. The supplied voltage equal to the voltage occurring dependently on the state of upper level n bits in the measured D/A conversion circuit 2 is output from the voltage source 4. Only voltage of a small amplitude occurring dependently on the state of lower level bits in the measured D/A conversion circuit 2 is provided to the voltage measurement device 6. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、D/A変換回路やA/D変換回路を具備する半導体集積回路を検査する半導体検査機構、及び半導体集積回路の検査方法に関する。   The present invention relates to a semiconductor inspection mechanism for inspecting a semiconductor integrated circuit including a D / A conversion circuit and an A / D conversion circuit, and a semiconductor integrated circuit inspection method.

従来、半導体集積回路に搭載されるD/A変換回路のD/A変換特性の検査方法としては、被測定D/A変換回路の出力電圧を半導体検査装置に内蔵された電圧測定装置で測定する方法や、被測定D/A変換回路の出力電圧をA/D変換回路に与え、変換されたデジタルコードを基に被測定D/A変換回路の出力電圧を測定する方法が提案されている。また、被測定D/A変換回路の出力電圧をA/D変換回路へ与えて、被測定D/A変換回路へ入力したデジタルコードとA/D変換回路から出力されるデジタルコードとの一致を比較回路で判定することでD/A変換回路を検査する方法も提案されている(例えば特許文献1参照。)。   Conventionally, as a method for inspecting the D / A conversion characteristics of a D / A conversion circuit mounted on a semiconductor integrated circuit, the output voltage of the D / A conversion circuit to be measured is measured by a voltage measurement device built in the semiconductor inspection device. There have been proposed a method and a method of measuring the output voltage of the D / A converter circuit to be measured based on the converted digital code by supplying the output voltage of the D / A converter circuit to be measured to the A / D converter circuit. Also, the output voltage of the D / A conversion circuit to be measured is supplied to the A / D conversion circuit, and the digital code input to the D / A conversion circuit to be measured matches the digital code output from the A / D conversion circuit. A method for inspecting a D / A conversion circuit by making a determination with a comparison circuit has also been proposed (see, for example, Patent Document 1).

一方、従来、半導体集積回路に搭載されるA/D変換回路のA/D変換特性の検査方法としては、被測定A/D変換回路の最大入力電圧振幅を満たすステップ状の電圧や正弦波状の電圧を被測定A/D変換回路へ与え、被測定A/D変換回路から出力されるデジタルコードを半導体検査装置にて記録してA/D変換特性を検査する方法が提案されている。   On the other hand, conventionally, as an inspection method of A / D conversion characteristics of an A / D conversion circuit mounted on a semiconductor integrated circuit, a stepped voltage or a sinusoidal waveform that satisfies the maximum input voltage amplitude of the A / D conversion circuit to be measured is used. There has been proposed a method of inspecting A / D conversion characteristics by applying a voltage to a measured A / D conversion circuit and recording a digital code output from the measured A / D conversion circuit with a semiconductor inspection apparatus.

しかしながら、上記した従来の方法によりD/A変換回路やA/D変換回路を妥当な精度で検査するためには、その検査に関わる装置の電圧分解能は被測定D/A変換回路や被測定A/D変換回路よりも高くなくてはならない。例えば、電圧分解能が10ビットの被測定D/A変換回路のD/A変換特性は、電圧分解能が8ビットの電圧測定装置では高精度に検査することはできない。   However, in order to inspect the D / A conversion circuit and the A / D conversion circuit with a reasonable accuracy by the conventional method described above, the voltage resolution of the apparatus involved in the inspection is determined by the D / A conversion circuit to be measured or the A to be measured. It must be higher than the / D conversion circuit. For example, the D / A conversion characteristic of the D / A conversion circuit to be measured having a voltage resolution of 10 bits cannot be inspected with high accuracy by a voltage measuring device having a voltage resolution of 8 bits.

そのため、従来は、半導体集積回路に搭載されるD/A変換回路やA/D変換回路の高分解能化に伴い、より高分解能の半導体検査装置を採用しなくてはならず、検査コスト上昇の要因となっていた。
特開平2−8760号公報
For this reason, conventionally, as the resolution of the D / A conversion circuit and the A / D conversion circuit mounted on the semiconductor integrated circuit is increased, a higher-resolution semiconductor inspection apparatus must be employed, which increases the inspection cost. It was a factor.
Japanese Patent Laid-Open No. 2-8760

本発明は、上記問題点に鑑み、被測定D/A変換回路へ与えるデジタルコードの状態に合わせて電圧源の供給電圧を制御し、被測定D/A変換回路の出力電圧と前記電圧源の供給電圧との差分をとり、その差分電圧を測定することにより、半導体集積回路に搭載されるD/A変換回路のD/A変換特性を、D/A変換回路よりも電圧分解能の低い装置を用いて高精度に検査できる半導体検査機構、および半導体集積回路の検査方法を提供することを目的とする。   In view of the above problems, the present invention controls the supply voltage of the voltage source in accordance with the state of the digital code applied to the D / A converter circuit to be measured, and the output voltage of the D / A converter circuit to be measured and the voltage source By taking the difference from the supply voltage and measuring the difference voltage, the D / A conversion characteristic of the D / A conversion circuit mounted on the semiconductor integrated circuit can be reduced with a device having a lower voltage resolution than the D / A conversion circuit. It is an object of the present invention to provide a semiconductor inspection mechanism and a semiconductor integrated circuit inspection method that can be used with high accuracy.

また、本発明は、上記問題点に鑑み、2つの電圧源を用いて被測定A/D変換回路への入力電圧を生成することにより、半導体集積回路に搭載されるA/D変換回路のA/D変換特性を、A/D変換回路よりも電圧分解能の低い装置を用いて高精度に検査できる半導体検査機構、および半導体集積回路の検査方法を提供することを目的とする。   Further, in view of the above problems, the present invention generates an input voltage to the A / D conversion circuit to be measured using two voltage sources, thereby enabling A of the A / D conversion circuit mounted on the semiconductor integrated circuit. It is an object of the present invention to provide a semiconductor inspection mechanism and a semiconductor integrated circuit inspection method capable of inspecting the / D conversion characteristics with high accuracy using a device having a lower voltage resolution than the A / D conversion circuit.

本発明の請求項1記載の半導体検査機構は、電圧源と、被測定D/A変換回路へ与えるデジタルコードの状態に合わせて前記電圧源の供給電圧を制御する制御部と、前記被測定D/A変換回路から出力される電圧と前記電圧源の供給電圧との差分をとる減算部と、前記減算部の出力電圧を測定する測定部と、を備えることを特徴とする。   According to a first aspect of the present invention, there is provided a semiconductor inspection mechanism including a voltage source, a control unit for controlling a supply voltage of the voltage source in accordance with a state of a digital code supplied to the D / A conversion circuit to be measured, and the D to be measured. A subtractor that takes the difference between the voltage output from the / A converter circuit and the supply voltage of the voltage source, and a measuring unit that measures the output voltage of the subtractor.

また、本発明の請求項2記載の半導体検査機構は、請求項1記載の半導体検査機構であって、前記制御部は、前記被測定D/A変換回路においてデジタルコードの上位n(nは正の整数)ビットの状態に依存して発生する電圧と同等の供給電圧を前記電圧源から出力させることを特徴とする。   The semiconductor inspection mechanism according to a second aspect of the present invention is the semiconductor inspection mechanism according to the first aspect, wherein the control unit is configured such that the upper n (n is a positive value) of the digital code in the D / A conversion circuit to be measured. The supply voltage equivalent to the voltage generated depending on the bit state is output from the voltage source.

また、本発明の請求項3記載の半導体検査機構は、請求項1もしくは2のいずれかに記載の半導体検査機構であって、前記電圧源は電圧源用D/A変換回路であり、前記制御部は、前記被測定D/A変換回路へ与えるデジタルコードの一部を前記電圧源用D/A変換回路へ与えることを特徴とする。   A semiconductor inspection mechanism according to claim 3 of the present invention is the semiconductor inspection mechanism according to claim 1, wherein the voltage source is a D / A conversion circuit for a voltage source, and the control The unit supplies a part of the digital code to be supplied to the D / A conversion circuit to be measured to the D / A conversion circuit for voltage source.

また、本発明の請求項4記載の半導体検査機構は、請求項1ないし3のいずれかに記載の半導体検査機構であって、さらに、前記測定部で測定した電圧値に前記電圧源の供給電圧の値を加算する演算を行い、前記被測定D/A変換回路のD/A変換特性を得る演算部を備えることを特徴とする。   According to a fourth aspect of the present invention, there is provided a semiconductor inspection mechanism according to any one of the first to third aspects, wherein the supply voltage of the voltage source is added to the voltage value measured by the measurement unit. And an arithmetic unit for obtaining a D / A conversion characteristic of the D / A conversion circuit to be measured.

また、本発明の請求項5記載の半導体検査機構は、第1と第2の電圧源と、前記第1と第2の電圧源の供給電圧を加算して、被測定A/D変換回路へ与える電圧を生成する加算部と、前記被測定A/D変換回路から出力されるデジタルコードの論理値を判定するデジタルコード判定部と、を備えることを特徴とする。   The semiconductor inspection mechanism according to claim 5 of the present invention adds the first and second voltage sources and the supply voltages of the first and second voltage sources to the A / D conversion circuit to be measured. An addition unit that generates a voltage to be applied, and a digital code determination unit that determines a logical value of a digital code output from the measured A / D conversion circuit.

また、本発明の請求項6記載の半導体検査機構は、請求項5記載の半導体検査機構であって、前記第1の電圧源は、前記第2の電圧源の電圧分解能分の振幅を有する電圧を発生することを特徴とする。   The semiconductor inspection mechanism according to claim 6 of the present invention is the semiconductor inspection mechanism according to claim 5, wherein the first voltage source has a voltage having an amplitude corresponding to the voltage resolution of the second voltage source. It is characterized by generating.

また、本発明の請求項7記載の半導体検査機構は、請求項5もしくは6のいずれかに記載の半導体検査機構であって、さらに、前記第1の電圧源から出力される電圧の振幅と前記第2の電圧源から出力される電圧の最小変動幅とを比較する比較部を備えることを特徴とする。   A semiconductor inspection mechanism according to claim 7 of the present invention is the semiconductor inspection mechanism according to claim 5 or 6, further comprising: an amplitude of a voltage output from the first voltage source; A comparison unit that compares the minimum fluctuation range of the voltage output from the second voltage source is provided.

また、本発明の請求項8記載の半導体集積回路の検査方法は、請求項1ないし4のいずれかに記載の半導体検査機構を用いて、D/A変換回路を具備する半導体集積回路を検査する検査方法であって、所定のデジタルコードを与えたときの被測定D/A変換回路の出力電圧と電圧源の供給電圧とが一致するように前記電圧源の制御条件を予め調整しておき、半導体集積回路を検査する際に、その予め調整した制御条件を用いて前記電圧源の供給電圧を制御することを特徴とする。   A semiconductor integrated circuit inspection method according to claim 8 of the present invention inspects a semiconductor integrated circuit including a D / A conversion circuit using the semiconductor inspection mechanism according to any one of claims 1 to 4. In the inspection method, the control condition of the voltage source is adjusted in advance so that the output voltage of the D / A converter circuit to be measured when a predetermined digital code is given matches the supply voltage of the voltage source, When inspecting the semiconductor integrated circuit, the supply voltage of the voltage source is controlled using the control conditions adjusted in advance.

また、本発明の請求項9記載の半導体集積回路の検査方法は、請求項5ないし7のいずれかに記載の半導体検査機構を用いて、A/D変換回路を具備する半導体集積回路を検査する検査方法であって、第1の電圧源から出力される電圧の振幅と第2の電圧源から出力される電圧の最小変動幅とが一致するように前記第1および第2の電圧源の制御条件を予め調整しておき、半導体集積回路を検査する際に、その予め調整した制御条件を用いて前記第1と第2の電圧源の供給電圧を制御することを特徴とする。   According to a ninth aspect of the present invention, there is provided a semiconductor integrated circuit inspection method that inspects a semiconductor integrated circuit including an A / D conversion circuit using the semiconductor inspection mechanism according to any one of the fifth to seventh aspects. In the inspection method, the first and second voltage sources are controlled such that the amplitude of the voltage output from the first voltage source matches the minimum fluctuation range of the voltage output from the second voltage source. The condition is adjusted in advance, and when the semiconductor integrated circuit is inspected, the supply voltage of the first and second voltage sources is controlled using the previously adjusted control condition.

本発明によれば、半導体集積回路が具備するD/A変換回路のD/A変換特性やA/D変換回路のA/D変換特性を、D/A変換回路やA/D変換回路よりも電圧分解能が低い装置を用いて高精度に検査することができる。   According to the present invention, the D / A conversion characteristic of the D / A conversion circuit included in the semiconductor integrated circuit and the A / D conversion characteristic of the A / D conversion circuit are more improved than those of the D / A conversion circuit and the A / D conversion circuit. Inspection can be performed with high accuracy using an apparatus having a low voltage resolution.

すなわち、D/A変換回路の検査においては、被測定D/A変換回路の出力電圧から上位nビットの状態による電圧変動分を除いた小振幅の電圧波形を測定し、その測定結果に上位nビットによる電圧変動分を加算して、被測定D/A変換回路のD/A変換特性を取得することができる。また、測定部では、被測定D/A変換回路の下位ビットの状態による電圧変動のみを測定できればよく、測定部の電圧分解能が被測定D/A変換回路のビット数に満たない場合でも、高分解能の電圧測定装置を用いた場合と同様の精度でD/A変換特性を検査できる。   That is, in the inspection of the D / A conversion circuit, a small-amplitude voltage waveform obtained by removing the voltage fluctuation due to the state of the upper n bits from the output voltage of the D / A conversion circuit to be measured is measured, and the measurement result includes the upper n The D / A conversion characteristic of the D / A conversion circuit to be measured can be acquired by adding the voltage fluctuation due to the bits. In addition, the measurement unit need only be able to measure voltage fluctuations due to the state of the lower bits of the D / A converter circuit to be measured. Even if the voltage resolution of the measurement unit is less than the number of bits of the D / A converter circuit to be measured, The D / A conversion characteristics can be inspected with the same accuracy as when a voltage measuring device with a resolution is used.

また、A/D変換回路の検査においては、第1の電圧源から小振幅の電圧を発生させ、第2の電圧源から電圧ステップの大きい電圧を発生させ、これらを加算してステップが小さく、かつ振幅の大きい電圧を生成し、被測定A/D変換回路に与えることができる。したがって、第1と第2の電圧源に要求される電圧分解能を低減し、電圧源の電圧分解能が被測定A/D変換回路のビット数に満たない場合でも、高分解能の電圧源を用いた場合と同様の精度でA/D変換特性を検査できる。   In the inspection of the A / D conversion circuit, a voltage having a small amplitude is generated from the first voltage source, a voltage having a large voltage step is generated from the second voltage source, and these are added to reduce the step. In addition, a voltage having a large amplitude can be generated and supplied to the A / D conversion circuit to be measured. Therefore, the voltage resolution required for the first and second voltage sources is reduced, and a high-resolution voltage source is used even when the voltage resolution of the voltage source is less than the number of bits of the A / D conversion circuit to be measured. The A / D conversion characteristics can be inspected with the same accuracy as the case.

(実施の形態1)
図1は本発明の実施の形態1における半導体検査装置(半導体検査機構)の構成を示す図であり、検査対象の半導体集積回路が具備するD/A変換回路の出力測定に係る構成の概略を示している。
(Embodiment 1)
FIG. 1 is a diagram showing a configuration of a semiconductor inspection apparatus (semiconductor inspection mechanism) in Embodiment 1 of the present invention, and shows an outline of a configuration relating to output measurement of a D / A conversion circuit included in a semiconductor integrated circuit to be inspected. Show.

図1に示すように、当該半導体検査装置は、信号発生装置3、電圧源4、減算回路(減算部)5、および電圧測定装置(測定部)6を備え、これらを用いて、検査対象の半導体集積回路(被測定半導体集積回路)1が具備するD/A変換回路(被測定D/A変換回路)2の出力を測定する。   As shown in FIG. 1, the semiconductor inspection apparatus includes a signal generator 3, a voltage source 4, a subtraction circuit (subtraction unit) 5, and a voltage measurement device (measurement unit) 6. The output of the D / A conversion circuit (D / A conversion circuit to be measured) 2 included in the semiconductor integrated circuit (measured semiconductor integrated circuit) 1 is measured.

信号発生装置3は、被測定D/A変換回路2の検査に必要な入力信号系列(デジタルコード)を出力する。また、信号発生装置3は、被測定D/A変換回路2へ与える入力信号系列の各信号の状態に合わせて電圧源4の供給電圧を制御する制御部の機能を有する。電圧源4は、任意に供給電圧を制御可能な構成となっている。   The signal generator 3 outputs an input signal series (digital code) necessary for the inspection of the D / A conversion circuit 2 to be measured. In addition, the signal generator 3 has a function of a control unit that controls the supply voltage of the voltage source 4 in accordance with the state of each signal of the input signal series supplied to the D / A conversion circuit 2 to be measured. The voltage source 4 is configured to arbitrarily control the supply voltage.

具体的には、信号発生装置3は、被測定D/A変換回路2においてデジタルコードの上位n(nは正の整数)ビットの状態に依存して発生する電圧と同等の供給電圧を電圧源4から出力させるための制御信号を供給する。   Specifically, the signal generator 3 supplies a supply voltage equivalent to the voltage generated depending on the state of the upper n bits (n is a positive integer) of the digital code in the D / A conversion circuit 2 to be measured. 4 is supplied with a control signal for output.

例えば、被測定D/A変換回路2の電圧分解能が8ビットで、信号発生装置3からゼロコードからフルコードまで昇順に2進数デジタルコードを順次出力する場合、被測定D/A変換回路2からは図2に示す電圧が出力されるが、このとき、被測定D/A変換回路2においてデジタルコードの上位5ビットの状態に依存して発生する電圧と同等の供給電圧を電圧源4から出力させる場合、その電圧源4の供給電圧の波形は図3に示すようなステップ状の波形となる。すなわち、図3において、例えば最初のステップまでの供給電圧は「‘00000000’〜‘00000111’」のデジタルコードに対応しており、その電圧値は、被測定D/A変換回路2に入力されるデジタルコードが「00000000」の状態の場合に発生する電圧値と同等である。また、最初のステップの供給電圧は「‘00001000’〜‘00001111’」のデジタルコードに対応しており、その電圧値は、被測定D/A変換回路2に入力されるデジタルコードが「00001000」の状態の場合に発生する電圧値と同等である。   For example, when the voltage resolution of the D / A conversion circuit 2 to be measured is 8 bits and the binary digital code is sequentially output from the signal generator 3 in ascending order from the zero code to the full code, the D / A conversion circuit 2 to be measured The voltage shown in FIG. 2 is output. At this time, the supply voltage equivalent to the voltage generated depending on the state of the upper 5 bits of the digital code in the D / A conversion circuit 2 to be measured is output from the voltage source 4. In this case, the waveform of the supply voltage of the voltage source 4 is a stepped waveform as shown in FIG. That is, in FIG. 3, for example, the supply voltage up to the first step corresponds to a digital code of “'00000000' to '00000111'”, and the voltage value is input to the D / A conversion circuit 2 to be measured. This is equivalent to the voltage value generated when the digital code is in the “00000000” state. The supply voltage of the first step corresponds to a digital code of “'00001000' to '000011111'”, and the digital value input to the D / A conversion circuit 2 to be measured is “00001000”. It is equivalent to the voltage value generated in the case of this state.

減算回路5は、被測定D/A変換回路2から出力される電圧と電圧源4の供給電圧との差分をとる。ここで、減算回路5は差動アンプであってもよい。また、減算回路5を介さずに、電圧測定装置として、減算器の機能を有する差動電圧測定装置を用いてもよい。また、電圧源4の供給電圧の振幅が被測定D/A変換回路2の出力電圧振幅に対して大き過ぎたり小さ過ぎたりする場合は、電圧源4と減算回路5との間に電圧変換機能を有する回路を組み込んでもよい。また、電圧測定装置6で測定可能な電圧振幅が被測定D/A変換回路2の出力電圧振幅に対して大き過ぎたり小さ過ぎたりする場合は、減算回路5と電圧測定装置6との間に電圧変換機能を有する回路を組み込んでもよい。   The subtraction circuit 5 calculates the difference between the voltage output from the D / A conversion circuit 2 to be measured and the supply voltage of the voltage source 4. Here, the subtraction circuit 5 may be a differential amplifier. Moreover, you may use the differential voltage measuring apparatus which has a function of a subtracter as a voltage measuring apparatus not via the subtraction circuit 5. FIG. When the amplitude of the supply voltage of the voltage source 4 is too large or too small with respect to the output voltage amplitude of the D / A conversion circuit 2 to be measured, a voltage conversion function is provided between the voltage source 4 and the subtraction circuit 5. A circuit having: If the voltage amplitude measurable by the voltage measuring device 6 is too large or too small relative to the output voltage amplitude of the D / A conversion circuit 2 to be measured, the subtracting circuit 5 and the voltage measuring device 6 are not connected. A circuit having a voltage conversion function may be incorporated.

電圧測定装置6は、減算回路5の出力電圧を測定する。被測定D/A変換回路2の電圧分解能をaとし、被測定D/A変換回路2において上位nビットの状態に依存して発生する電圧と同等の電圧を電圧源4から供給する場合、減算回路5から出力される電圧の振幅は、被測定D/A変換回路2の出力電圧振幅の2(a−n)分の1となる。この減算回路5の出力を電圧測定装置6においてmビットの電圧分解能で測定すると、結果として、被測定D/A変換回路2の出力電圧を「m+(a−n)」ビットの電圧分解能で測定している場合と同等の測定を実現できる。 The voltage measuring device 6 measures the output voltage of the subtracting circuit 5. When the voltage resolution of the D / A conversion circuit 2 to be measured is a and a voltage equivalent to a voltage generated depending on the state of the upper n bits in the D / A conversion circuit 2 to be measured is supplied from the voltage source 4, subtraction is performed. The amplitude of the voltage output from the circuit 5 is 1/2 (an) of the output voltage amplitude of the D / A conversion circuit 2 to be measured. When the output of the subtracting circuit 5 is measured by the voltage measuring device 6 with m-bit voltage resolution, as a result, the output voltage of the D / A converter circuit 2 to be measured is measured with voltage resolution of “m + (a−n)” bits. The same measurement as when it is done.

例えば、被測定D/A変換回路2の電圧分解能が8ビットで、図2に示す電圧が出力され、被測定D/A変換回路2において上位5ビットの状態に依存して発生する、図3に示す電圧と同等の供給電圧を電圧源4から出力する場合、図4に示す電圧を電圧測定装置6で測定することになり、図2に示す電圧を測定する場合と比較して、3ビット少ない電圧分解能で、同精度の電圧測定が可能となる。   For example, the voltage resolution of the D / A conversion circuit 2 to be measured is 8 bits, and the voltage shown in FIG. 2 is output, which is generated depending on the state of the upper 5 bits in the D / A conversion circuit 2 to be measured. When the supply voltage equivalent to the voltage shown in FIG. 4 is output from the voltage source 4, the voltage shown in FIG. 4 is measured by the voltage measuring device 6, and compared with the case where the voltage shown in FIG. Voltage measurement with the same accuracy is possible with low voltage resolution.

また、図示しないが、半導体検査装置が具備する演算部において、電圧測定装置6で測定した電圧値に電圧源4の供給電圧の値を演算によって加算して、被測定D/A変換回路2のD/A変換特性を得ることで、被測定半導体集積回路1を検査することができる。   Further, although not shown in the figure, in the arithmetic unit provided in the semiconductor inspection apparatus, the value of the supply voltage of the voltage source 4 is added to the voltage value measured by the voltage measuring device 6 by calculation, and the D / A conversion circuit 2 to be measured By obtaining the D / A conversion characteristics, the semiconductor integrated circuit 1 to be measured can be inspected.

このように、本実施の形態1によれば、低分解能の電圧測定装置を用いて高精度に被測定D/A変換回路2のD/A変換特性を得ることができる。すなわち、被測定D/A変換回路2の出力電圧から上位nビットの状態による電圧変動分を除いた小振幅の電圧波形を測定し、その測定結果に上位nビットによる電圧変動分を加算して、被測定D/A変換回路2のD/A変換特性を取得することができる。また、電圧測定装置6では、被測定D/A変換回路2の下位ビットの状態による電圧変動のみを測定できればよく、電圧測定装置6の電圧分解能が被測定D/A変換回路2のビット数に満たない場合でも、高分解能の電圧測定装置を用いた場合と同様の精度でD/A変換特性を検査できる。   As described above, according to the first embodiment, it is possible to obtain the D / A conversion characteristics of the D / A conversion circuit 2 to be measured with high accuracy using the low-resolution voltage measurement device. That is, a voltage waveform with a small amplitude obtained by removing the voltage fluctuation due to the state of the upper n bits from the output voltage of the D / A converter circuit 2 to be measured is added, and the voltage fluctuation due to the upper n bits is added to the measurement result. The D / A conversion characteristics of the D / A conversion circuit 2 to be measured can be acquired. The voltage measuring device 6 only needs to measure voltage fluctuations due to the state of the lower bits of the D / A conversion circuit 2 to be measured. The voltage resolution of the voltage measuring device 6 is equal to the number of bits of the D / A conversion circuit 2 to be measured. Even if not, the D / A conversion characteristics can be inspected with the same accuracy as when a high-resolution voltage measuring device is used.

なお、電圧源4として、半導体検査装置と被測定半導体集積回路1を電気的に接続する検査ボードが具備する電圧源や、被測定半導体集積回路1が具備する電圧源を使用してもよい。この構成によれば、任意に供給電圧を制御可能な電圧源4を持たない半導体検査装置を用いても、本実施の形態1における検査方法で被測定D/A変換回路2の出力測定を実現することができる。   As the voltage source 4, a voltage source provided in an inspection board for electrically connecting the semiconductor inspection apparatus and the semiconductor integrated circuit 1 to be measured, or a voltage source provided in the semiconductor integrated circuit 1 to be measured may be used. According to this configuration, the output measurement of the D / A conversion circuit 2 to be measured can be realized by the inspection method in the first embodiment even when a semiconductor inspection apparatus that does not have the voltage source 4 capable of arbitrarily controlling the supply voltage is used. can do.

また、減算回路5として、半導体検査装置と被測定半導体集積回路1を電気的に接続する検査ボードが具備する減算回路や、被測定半導体集積回路1が具備する減算回路を使用してもよい。この構成によれば、減算回路5を持たない半導体検査装置を用いても、本実施の形態1における検査方法で被測定D/A変換回路2の出力測定を実現することができる。   Further, as the subtracting circuit 5, a subtracting circuit provided in an inspection board for electrically connecting the semiconductor inspection apparatus and the semiconductor integrated circuit 1 to be measured, or a subtracting circuit provided in the semiconductor integrated circuit 1 to be measured may be used. According to this configuration, even if a semiconductor inspection apparatus that does not have the subtracting circuit 5 is used, the output measurement of the D / A conversion circuit 2 to be measured can be realized by the inspection method in the first embodiment.

また、減算回路5および電圧測定装置6として、被測定半導体集積回路1が具備する差動入力A/D変換回路および半導体検査装置が具備するデジタルコード判定装置を使用してよい。具体的には、差動入力A/D変換回路の一方の入力端子を被測定D/A変換回路2の出力端子と接続し、他方の入力端子を電圧源4の出力端子と接続し、差動入力A/D変換回路の出力端子をデジタルコード判定装置に接続して、差動入力A/D変換回路において被測定D/A変換回路2から出力される電圧と電圧源4の供給電圧との差分をとり、デジタルコード判定装置において、差動入力A/D変換回路から出力されるデジタルコードの論理値を判定する。そして半導体検査装置が具備する演算部(図示せず)において、その判定結果を基に被測定D/A変換回路2の出力電圧と電圧源4の供給電圧との差分電圧を測定する。この構成によれば、電圧測定装置6を持たない半導体検査装置を用いても、本実施の形態1における検査方法で被測定D/A変換回路2の出力測定を実現することができる。   Further, as the subtraction circuit 5 and the voltage measuring device 6, a differential input A / D conversion circuit provided in the semiconductor integrated circuit 1 to be measured and a digital code determination device provided in the semiconductor inspection device may be used. Specifically, one input terminal of the differential input A / D conversion circuit is connected to the output terminal of the D / A conversion circuit 2 to be measured, and the other input terminal is connected to the output terminal of the voltage source 4 to obtain the difference. The output terminal of the dynamic input A / D conversion circuit is connected to the digital code determination device, and the voltage output from the D / A conversion circuit 2 to be measured and the supply voltage of the voltage source 4 in the differential input A / D conversion circuit In the digital code determination device, the logical value of the digital code output from the differential input A / D conversion circuit is determined. Then, a calculation unit (not shown) provided in the semiconductor inspection apparatus measures a differential voltage between the output voltage of the D / A conversion circuit 2 to be measured and the supply voltage of the voltage source 4 based on the determination result. According to this configuration, the output measurement of the D / A conversion circuit 2 to be measured can be realized by the inspection method according to the first embodiment even if a semiconductor inspection apparatus that does not have the voltage measurement apparatus 6 is used.

また、上位nビットを除くビットにゼロを入力した場合に、被測定D/A変換回路2から出力される電圧と電圧源4から出力される電圧との間に差があれば、被測定D/A変換回路2のD/A変換特性を正しく演算できない。   In addition, when zero is input to bits other than the upper n bits, if there is a difference between the voltage output from the D / A conversion circuit 2 to be measured and the voltage output from the voltage source 4, the D to be measured The D / A conversion characteristic of the / A conversion circuit 2 cannot be calculated correctly.

そこで、所定のデジタルコードを与えたときの被測定D/A変換回路2の出力電圧と電圧源4の供給電圧とが一致する電圧源4の制御条件を予め調べ、被測定半導体集積回路1を検査する際に、その結果を用いて検査を実施する。   Therefore, the control condition of the voltage source 4 in which the output voltage of the D / A conversion circuit 2 to be measured and the supply voltage of the voltage source 4 when a predetermined digital code is given is checked in advance, and the semiconductor integrated circuit 1 to be measured is When inspecting, the result is used for the inspection.

具体的には、被測定D/A変換回路2へ上位nビットを除くビットをゼロとしたデジタルコードを順次与え、それぞれの入力に対して、電圧測定装置6の測定結果が0ボルトとなるように電圧源4の制御条件を予め調整する。そして、被測定半導体集積回路1を検査する際に、その予め調整した制御条件を用いて電圧源4の供給電圧を制御する。このようにすれば被測定D/A変換回路2の出力測定精度の劣化を防止できる。   Specifically, a digital code with bits other than the upper n bits set to zero is sequentially given to the D / A conversion circuit 2 to be measured so that the measurement result of the voltage measuring device 6 becomes 0 volt for each input. The control conditions of the voltage source 4 are adjusted in advance. Then, when inspecting the semiconductor integrated circuit 1 to be measured, the supply voltage of the voltage source 4 is controlled using the control conditions adjusted in advance. In this way, it is possible to prevent deterioration in output measurement accuracy of the D / A conversion circuit 2 to be measured.

(実施の形態2)
図5は本発明の実施の形態2における半導体検査装置(半導体検査機構)の構成を示す図であり、検査対象の半導体集積回路が具備するD/A変換回路の出力測定に係る構成の概略を示している。但し、前述の実施の形態1で説明した部材と同一の部材には同一符号を付して、説明を省略する。
(Embodiment 2)
FIG. 5 is a diagram showing the configuration of the semiconductor inspection apparatus (semiconductor inspection mechanism) in the second embodiment of the present invention, and shows an outline of the configuration relating to the output measurement of the D / A conversion circuit included in the semiconductor integrated circuit to be inspected. Show. However, the same members as those described in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

当該半導体検査装置は、前述の実施の形態1で説明した電圧源4としてD/A変換回路(電圧源用D/A変換回路7)を用いる点に特徴がある。この電圧源用D/A変換回路7のデジタルコード入力端子の一部は、被測定D/A変換回路2のデジタルコード入力端子の一部と接続されており、信号発生装置(制御部)3は、被測定D/A変換回路2へ与える入力信号系列(デジタルコード)の一部を電圧源用D/A変換回路7へ与える。また、被測定D/A変換回路2の他のデジタルコード入力端子は接地されている。   The semiconductor inspection apparatus is characterized in that a D / A conversion circuit (voltage source D / A conversion circuit 7) is used as the voltage source 4 described in the first embodiment. A part of the digital code input terminal of the voltage source D / A conversion circuit 7 is connected to a part of the digital code input terminal of the D / A conversion circuit 2 to be measured, and the signal generator (control unit) 3 Supplies a part of the input signal sequence (digital code) to be supplied to the D / A conversion circuit 2 to be measured to the D / A conversion circuit 7 for voltage source. The other digital code input terminal of the D / A conversion circuit 2 to be measured is grounded.

具体的には、入力信号系列の上位nビットを被測定D/A変換回路2と電圧源用D/A変換回路7との間で共用することで、被測定D/A変換回路2より電圧分解能が低く且つ最大出力電圧振幅が被測定D/A変換回路2と同等のD/A変換回路を電圧源用D/A変換回路7に用いた場合、前述の実施の形態1における電圧源4と同様に、電圧源用D/A変換回路7は、被測定D/A変換回路2においてデジタルコードの上位nビットの状態に依存して発生する電圧と同等の供給電圧を発生する。この構成により、被測定D/A変換回路と電圧源用D/A変換回路を同時に制御可能となり、信号発生装置に必要とされる端子数を大幅に削減することができる。   Specifically, the upper n bits of the input signal series are shared between the D / A conversion circuit 2 to be measured and the D / A conversion circuit 7 for the voltage source, so that the voltage from the D / A conversion circuit 2 to be measured When a D / A conversion circuit having a low resolution and a maximum output voltage amplitude equivalent to the D / A conversion circuit 2 to be measured is used for the voltage source D / A conversion circuit 7, the voltage source 4 in the first embodiment is used. Similarly, the voltage source D / A conversion circuit 7 generates a supply voltage equivalent to the voltage generated in the D / A conversion circuit 2 to be measured depending on the state of the upper n bits of the digital code. With this configuration, the D / A conversion circuit to be measured and the D / A conversion circuit for voltage source can be controlled simultaneously, and the number of terminals required for the signal generator can be greatly reduced.

なお、電圧源用D/A変換回路7として、半導体検査装置と被測定半導体集積回路1を電気的に接続する検査ボードが具備するD/A変換回路や、被測定半導体集積回路1が具備するD/A変換回路を使用してもよい。この構成によれば、電圧源用D/A変換回路7を持たない半導体検査装置を用いても、本実施の形態2における検査方法で被測定D/A変換回路2の出力測定を実現することができる。   The voltage source D / A conversion circuit 7 includes a D / A conversion circuit included in an inspection board for electrically connecting the semiconductor inspection apparatus and the semiconductor integrated circuit 1 to be measured, and the semiconductor integrated circuit 1 to be measured. A D / A conversion circuit may be used. According to this configuration, the output measurement of the D / A conversion circuit 2 to be measured can be realized by the inspection method according to the second embodiment even if a semiconductor inspection apparatus that does not have the voltage source D / A conversion circuit 7 is used. Can do.

また、上位nビットを除くビットにゼロを入力した場合に、被測定D/A変換回路2から出力される電圧と電圧源用D/A変換回路7から出力される電圧との間に差があれば、被測定D/A変換回路2のD/A変換特性を正しく演算できない。   Further, when zero is input to bits other than the upper n bits, there is a difference between the voltage output from the D / A conversion circuit 2 to be measured and the voltage output from the voltage source D / A conversion circuit 7. If so, the D / A conversion characteristics of the D / A conversion circuit 2 to be measured cannot be calculated correctly.

そこで、所定のデジタルコードを与えたときの被測定D/A変換回路2の出力電圧と電圧源用D/A変換回路7の供給電圧とが一致する電圧源用D/A変換回路7の制御条件を予め調べ、被測定半導体集積回路1を検査する際に、その結果を用いて検査を実施する。   Therefore, the control of the voltage source D / A conversion circuit 7 in which the output voltage of the D / A conversion circuit 2 to be measured and the supply voltage of the voltage source D / A conversion circuit 7 coincide with each other when a predetermined digital code is given. When the conditions are checked in advance and the semiconductor integrated circuit 1 to be measured is inspected, an inspection is performed using the result.

具体的には、被測定D/A変換回路2へ上位nビットを除くビットをゼロとしたデジタルコードを順次与え、それぞれの入力に対して、電圧測定装置6の測定結果が0ボルトとなるように、電圧源用D/A変換回路7が入力デジタルコードに応じて出力する電圧値を生成するために使う参照電圧の値(制御条件)を予め調整する。そして、被測定半導体集積回路1を検査する際に、その予め調整した制御条件を用いて電圧源用D/A変換回路7の供給電圧を制御する。このようにすれば被測定D/A変換回路2の出力測定精度の劣化を防止できる。   Specifically, a digital code with bits other than the upper n bits set to zero is sequentially given to the D / A conversion circuit 2 to be measured so that the measurement result of the voltage measuring device 6 becomes 0 volt for each input. Further, the value (control condition) of the reference voltage used for generating the voltage value output by the voltage source D / A conversion circuit 7 in accordance with the input digital code is adjusted in advance. Then, when inspecting the semiconductor integrated circuit 1 to be measured, the supply voltage of the voltage source D / A conversion circuit 7 is controlled using the control conditions adjusted in advance. In this way, it is possible to prevent deterioration in output measurement accuracy of the D / A conversion circuit 2 to be measured.

(実施の形態3)
図6は本発明の実施の形態3における半導体検査装置(半導体検査機構)の構成を示す図であり、検査対象の半導体集積回路が具備するA/D変換回路のA/D変換特定の検査に係る構成の概略を示している。
(Embodiment 3)
FIG. 6 is a diagram showing a configuration of a semiconductor inspection apparatus (semiconductor inspection mechanism) according to the third embodiment of the present invention. For the A / D conversion specific inspection of the A / D conversion circuit included in the semiconductor integrated circuit to be inspected. An outline of such a configuration is shown.

図6に示すように、当該半導体検査装置は、第1の電源13、第2の電源14、加算回路(加算部)15、およびデジタルコード判定装置(デジタルコード判定部)16を備え、これらを用いて、検査対象の半導体集積回路(被測定半導体集積回路)11が具備するA/D変換回路(被測定A/D変換回路)12のA/D変換特定を検査する。   As shown in FIG. 6, the semiconductor inspection apparatus includes a first power supply 13, a second power supply 14, an adder circuit (adder unit) 15, and a digital code determination device (digital code determination unit) 16. The A / D conversion specification of the A / D conversion circuit (measured A / D conversion circuit) 12 included in the semiconductor integrated circuit (measured semiconductor integrated circuit) 11 to be inspected is used.

第1と第2の電源13、14は、任意に供給電圧を制御可能な構成となっており、第1の電圧源13からは被測定A/D変換回路12の最大入力電圧振幅よりも小さい振幅の電圧を発生させ、第2の電圧源14からは、第1の電圧源13が供給する電圧の振幅を最小単位の変動幅とするステップ状の電圧を発生させる。   The first and second power supplies 13 and 14 can arbitrarily control the supply voltage, and are smaller than the maximum input voltage amplitude of the A / D conversion circuit 12 to be measured from the first voltage source 13. A voltage having an amplitude is generated, and a stepped voltage is generated from the second voltage source 14 with the amplitude of the voltage supplied from the first voltage source 13 as a minimum unit fluctuation range.

加算回路15は、第1と第2の電圧源13、14から供給される電圧を加算して、被測定A/D変換回路12へ与える電圧を生成する。デジタルコード判定装置16は、被測定A/D変換回路12から出力されるデジタルコードの論理値を判定する。   The adder circuit 15 adds the voltages supplied from the first and second voltage sources 13 and 14 to generate a voltage to be supplied to the A / D conversion circuit 12 to be measured. The digital code determination device 16 determines the logical value of the digital code output from the A / D conversion circuit 12 to be measured.

例えば、被測定A/D変換回路12のA/D変換特性を検査するために図2に示す入力電圧が必要な場合、第1の電圧源13から図4に示す小振幅の電圧を発生させ、第2の電圧源14から図3に示す電圧ステップの大きい電圧を発生させ、これらを加算して、ステップが小さく、かつ振幅の大きい電圧を生成する。このとき、図4に示す電圧の振幅と図3に示す電圧の最小変動幅が一致するようにする。   For example, when the input voltage shown in FIG. 2 is necessary to inspect the A / D conversion characteristic of the A / D conversion circuit 12 to be measured, the first voltage source 13 generates a voltage having a small amplitude shown in FIG. A voltage having a large voltage step shown in FIG. 3 is generated from the second voltage source 14 and added to generate a voltage having a small step and a large amplitude. At this time, the amplitude of the voltage shown in FIG. 4 and the minimum fluctuation range of the voltage shown in FIG.

ここで、第1の電圧源13および第2の電圧源14は、D/A変換回路や任意波形発生器を用いてもよい。また、この2つの電圧源から発生させる電圧値の組み合わせは上記に限定されず、加算結果として検査に必要な所望の入力電圧が得られればよい。   Here, the first voltage source 13 and the second voltage source 14 may use a D / A conversion circuit or an arbitrary waveform generator. Moreover, the combination of the voltage values generated from these two voltage sources is not limited to the above, and it is only necessary to obtain a desired input voltage necessary for the inspection as an addition result.

第1の電圧源13の電圧分解能をiビット、第2の電圧源14の電圧分解能をjビットとすると、第1の電圧源13から第2の電圧源14の電圧分解能分の振幅を有する電圧を出力させ、第2の電圧源14から被測定A/D変換回路12の最大入力電圧振幅と同等の振幅を有する電圧を出力させ、これらを加算することで、i+jビットの電圧分解能で被測定A/D変換回路12へ検査用の電圧を供給することができる。   When the voltage resolution of the first voltage source 13 is i bits and the voltage resolution of the second voltage source 14 is j bits, the voltage having an amplitude corresponding to the voltage resolution of the second voltage source 14 from the first voltage source 13 Is output from the second voltage source 14 and a voltage having an amplitude equivalent to the maximum input voltage amplitude of the A / D conversion circuit 12 to be measured is output, and these are added together to measure the voltage with a voltage resolution of i + j bits. An inspection voltage can be supplied to the A / D conversion circuit 12.

以上のように、第1の電圧源13と第2の電圧源14の供給電圧を加算回路15で加算し、被測定A/D変換回路12の最大入力電圧振幅を満たす電圧を供給することで、被測定A/D変換回路12のA/D変換特性を得ることができ、被測定A/D変換回路よりも電圧分解能の低い電圧源を用いて、より電圧分解能の高い電圧源を用いた場合と同等精度の検査を実現できる。   As described above, the supply voltages of the first voltage source 13 and the second voltage source 14 are added by the adder circuit 15 to supply a voltage that satisfies the maximum input voltage amplitude of the A / D conversion circuit 12 to be measured. The A / D conversion characteristic of the measured A / D conversion circuit 12 can be obtained, and a voltage source having a higher voltage resolution is used by using a voltage source having a lower voltage resolution than the measured A / D conversion circuit. Inspection with the same accuracy as the case can be realized.

但し、第1の電圧源13が供給する電圧の振幅と第2の電圧源14が供給する電圧の最小単位の変動幅とが一致しない場合、加算回路15が出力する電圧は所望の波形にならない。   However, when the amplitude of the voltage supplied from the first voltage source 13 and the fluctuation range of the minimum unit of the voltage supplied from the second voltage source 14 do not match, the voltage output from the adder circuit 15 does not have a desired waveform. .

そこで、第1の電圧源13から供給する電圧の振幅と第2の電圧源14から供給する電圧の変動幅の最小単位とが一致する第1および第2の電圧源13、14の制御条件を予め調べ、被測定半導体集積回路11を検査する際に、その結果を用いて検査を実施する。   Therefore, the control conditions of the first and second voltage sources 13 and 14 in which the amplitude of the voltage supplied from the first voltage source 13 and the minimum unit of the fluctuation range of the voltage supplied from the second voltage source 14 coincide are set. When the semiconductor integrated circuit 11 to be measured is inspected in advance and inspected, the inspection is performed using the result.

具体的には、第1の電圧源13の出力端子と第2の電圧源14の出力端子をそれぞれ、半導体検査装置が具備する比較器(図示せず)の入力端子に接続し、第1の電圧源13から最大電圧を出力させ、第2の電圧源14からは電圧変動の最小単位に等しい電圧を出力させる。そして、比較器の比較結果を基に、第1の電圧源13の出力電圧と第2の電圧源14の出力電圧とが一致するように第1および第2の電圧源13、14の制御条件を予め調整する。そして、被測定半導体集積回路11を検査する際に、その予め調整した制御条件を用いて第1と第2の電圧源13、14の供給電圧を制御する。このようにすれば被測定A/D変換回路12の検査精度の劣化を防止できる。   Specifically, the output terminal of the first voltage source 13 and the output terminal of the second voltage source 14 are respectively connected to the input terminals of a comparator (not shown) included in the semiconductor inspection apparatus, and the first The maximum voltage is output from the voltage source 13 and the voltage equal to the minimum unit of voltage fluctuation is output from the second voltage source 14. Then, based on the comparison result of the comparator, the control conditions of the first and second voltage sources 13 and 14 are set so that the output voltage of the first voltage source 13 and the output voltage of the second voltage source 14 match. Is adjusted in advance. Then, when inspecting the semiconductor integrated circuit 11 to be measured, the supply voltages of the first and second voltage sources 13 and 14 are controlled using the control conditions adjusted in advance. In this way, it is possible to prevent deterioration in inspection accuracy of the A / D conversion circuit 12 to be measured.

なお、第1の電圧源13から出力される電圧の振幅と第2の電圧源14から出力される電圧の最小変動幅とを比較する比較器(比較部)として、半導体検査装置と被測定半導体集積回路11を電気的に接続する検査ボードが具備する比較器や、被測定半導体集積回路11が具備する比較器を使用してもよい。この構成によれば、比較器を持たない半導体検査装置を用いても、本実施の形態3における検査方法で被測定A/D変換回路12を検査することができる。   As a comparator (comparator) for comparing the amplitude of the voltage output from the first voltage source 13 and the minimum fluctuation range of the voltage output from the second voltage source 14, the semiconductor inspection apparatus and the semiconductor to be measured A comparator provided in an inspection board that electrically connects the integrated circuit 11 or a comparator provided in the semiconductor integrated circuit 11 to be measured may be used. According to this configuration, the A / D conversion circuit 12 to be measured can be inspected by the inspection method in the third embodiment even using a semiconductor inspection apparatus that does not have a comparator.

また、加算回路15として、半導体検査装置と被測定半導体集積回路11を電気的に接続する検査ボードが具備する加算回路や、被測定半導体集積回路11が具備する加算回路を使用してもよい。この構成によれば、加算回路15を持たない半導体検査装置を用いても、本実施の形態3における検査方法で被測定A/D変換回路12を検査することができる。   Further, as the adder circuit 15, an adder circuit provided in a test board for electrically connecting the semiconductor inspection apparatus and the semiconductor integrated circuit 11 to be measured, or an adder circuit provided in the semiconductor integrated circuit 11 to be measured may be used. According to this configuration, the A / D conversion circuit 12 to be measured can be inspected by the inspection method according to the third embodiment even if a semiconductor inspection apparatus that does not have the addition circuit 15 is used.

また、第1と第2の電圧源13、14として、半導体検査装置と被測定半導体集積回路11を電気的に接続する検査ボードが具備する電圧源(D/A変換回路などを含む)や、被測定半導体集積回路11が具備する電圧源(D/A変換回路などを含む)を使用してもよい。この構成によれば、任意に供給電圧を制御可能な電圧源(D/A変換回路などを含む)を持たない半導体検査装置を用いても、本実施の形態3における検査方法で被測定A/D変換回路12を検査することができる。   Further, as the first and second voltage sources 13 and 14, a voltage source (including a D / A conversion circuit) included in an inspection board that electrically connects the semiconductor inspection apparatus and the semiconductor integrated circuit 11 to be measured, A voltage source (including a D / A conversion circuit) included in the semiconductor integrated circuit 11 to be measured may be used. According to this configuration, even if a semiconductor inspection apparatus that does not have a voltage source (including a D / A conversion circuit or the like) that can arbitrarily control the supply voltage is used, the A / D The D conversion circuit 12 can be inspected.

本発明にかかる半導体検査機構、及び半導体集積回路の検査方法は、半導体集積回路が具備するD/A変換回路やA/D変換回路の変換特性を、D/A変換回路やA/D変換回路よりも電圧分解能が低い装置を用いて高精度に検査することができ、高分解能のD/A変換回路やA/D変換回路を具備する半導体製品の検査に有用である。   According to the semiconductor inspection mechanism and the semiconductor integrated circuit inspection method of the present invention, the conversion characteristics of the D / A conversion circuit and the A / D conversion circuit included in the semiconductor integrated circuit are converted into the D / A conversion circuit and the A / D conversion circuit. Therefore, it is possible to inspect with high accuracy using a device having a lower voltage resolution than that, and it is useful for inspecting semiconductor products having high-resolution D / A conversion circuits and A / D conversion circuits.

本発明の実施の形態1における半導体検査装置の構成を示す図The figure which shows the structure of the semiconductor inspection apparatus in Embodiment 1 of this invention. 本発明の実施の形態1ないし2における被測定D/A変換回路の出力電圧、および本発明の実施の形態3における被測定A/D変換回路の入力電圧の一例を示す図The figure which shows an example of the output voltage of the to-be-measured D / A converter circuit in Embodiment 1 or 2 of this invention, and the input voltage of the to-be-measured A / D converter circuit in Embodiment 3 of this invention 本発明の実施の形態1における電圧源の供給電圧、本発明の実施の形態2における電圧源用D/A変換回路の供給電圧、および本発明の実施の形態3における第2の電圧源の供給電圧の一例を示す図Supply voltage of the voltage source in the first embodiment of the present invention, supply voltage of the D / A conversion circuit for the voltage source in the second embodiment of the present invention, and supply of the second voltage source in the third embodiment of the present invention Diagram showing an example of voltage 本発明の実施の形態1ないし2における減算回路の出力電圧、および本発明の実施の形態3における第1の電圧源の供給電圧の一例を示す図The figure which shows an example of the output voltage of the subtraction circuit in Embodiment 1 or 2 of this invention, and the supply voltage of the 1st voltage source in Embodiment 3 of this invention 本発明の実施の形態2における半導体検査装置の構成を示す図The figure which shows the structure of the semiconductor inspection apparatus in Embodiment 2 of this invention. 本発明の実施の形態3における半導体検査装置の構成を示す図The figure which shows the structure of the semiconductor inspection apparatus in Embodiment 3 of this invention.

符号の説明Explanation of symbols

1、11 被測定半導体集積回路
2 被測定D/A変換回路
3 信号発生装置
4 電圧源
5 減算回路
6 電圧測定装置
7 電圧源用D/A変換回路
12 被測定A/D変換回路
13 第1の電圧源
14 第2の電圧源
15 加算回路
16 デジタルコード判定装置
DESCRIPTION OF SYMBOLS 1, 11 Semiconductor integrated circuit to be measured 2 D / A converter circuit to be measured 3 Signal generator 4 Voltage source 5 Subtractor circuit 6 Voltage measuring device 7 D / A converter circuit for voltage source 12 A / D converter circuit to be measured 13 1st Voltage source 14 Second voltage source 15 Adder circuit 16 Digital code determination device

Claims (9)

電圧源と、
被測定D/A変換回路へ与えるデジタルコードの状態に合わせて前記電圧源の供給電圧を制御する制御部と、
前記被測定D/A変換回路から出力される電圧と前記電圧源の供給電圧との差分をとる減算部と、
前記減算部の出力電圧を測定する測定部と、
を備えた半導体検査機構。
A voltage source;
A control unit for controlling the supply voltage of the voltage source in accordance with the state of the digital code applied to the D / A conversion circuit to be measured;
A subtractor that takes the difference between the voltage output from the D / A converter circuit to be measured and the supply voltage of the voltage source;
A measurement unit for measuring the output voltage of the subtraction unit;
Semiconductor inspection mechanism equipped with.
前記制御部は、前記被測定D/A変換回路においてデジタルコードの上位n(nは正の整数)ビットの状態に依存して発生する電圧と同等の供給電圧を前記電圧源から出力させることを特徴とする請求項1記載の半導体検査機構。   The controller causes the voltage source to output a supply voltage equivalent to a voltage generated depending on the state of upper n bits (n is a positive integer) of the digital code in the D / A converter circuit to be measured. The semiconductor inspection mechanism according to claim 1. 請求項1もしくは2のいずれかに記載の半導体検査機構であって、前記電圧源は電圧源用D/A変換回路であり、前記制御部は、前記被測定D/A変換回路へ与えるデジタルコードの一部を前記電圧源用D/A変換回路へ与えることを特徴とする半導体検査機構。   3. The semiconductor inspection mechanism according to claim 1, wherein the voltage source is a voltage source D / A conversion circuit, and the control unit provides a digital code to be supplied to the D / A conversion circuit to be measured. A part of the semiconductor inspection mechanism is provided to the voltage source D / A conversion circuit. 請求項1ないし3のいずれかに記載の半導体検査機構であって、さらに、前記測定部で測定した電圧値に前記電圧源の供給電圧の値を加算する演算を行い、前記被測定D/A変換回路のD/A変換特性を得る演算部を備えることを特徴とする半導体検査機構。   4. The semiconductor inspection mechanism according to claim 1, further comprising performing an operation of adding a value of a supply voltage of the voltage source to a voltage value measured by the measurement unit, and measuring the D / A to be measured. A semiconductor inspection mechanism comprising an arithmetic unit for obtaining D / A conversion characteristics of a conversion circuit. 第1と第2の電圧源と、
前記第1と第2の電圧源の供給電圧を加算して、被測定A/D変換回路へ与える電圧を生成する加算部と、
前記被測定A/D変換回路から出力されるデジタルコードの論理値を判定するデジタルコード判定部と、
を備えた半導体検査機構。
First and second voltage sources;
An adder for adding the supply voltages of the first and second voltage sources to generate a voltage to be supplied to the A / D converter circuit to be measured;
A digital code determination unit for determining a logical value of a digital code output from the measured A / D conversion circuit;
Semiconductor inspection mechanism equipped with.
前記第1の電圧源は、前記第2の電圧源の電圧分解能分の振幅を有する電圧を発生することを特徴とする請求項5記載の半導体検査機構。   6. The semiconductor inspection mechanism according to claim 5, wherein the first voltage source generates a voltage having an amplitude corresponding to a voltage resolution of the second voltage source. 請求項5もしくは6のいずれかに記載の半導体検査機構であって、さらに、前記第1の電圧源から出力される電圧の振幅と前記第2の電圧源から出力される電圧の最小変動幅とを比較する比較部を備えることを特徴とする半導体検査機構。   7. The semiconductor inspection mechanism according to claim 5, further comprising: an amplitude of a voltage output from the first voltage source; and a minimum fluctuation range of a voltage output from the second voltage source. A semiconductor inspection mechanism comprising a comparison unit for comparing the two. 請求項1ないし4のいずれかに記載の半導体検査機構を用いて、D/A変換回路を具備する半導体集積回路を検査する検査方法であって、所定のデジタルコードを与えたときの被測定D/A変換回路の出力電圧と電圧源の供給電圧とが一致するように前記電圧源の制御条件を予め調整しておき、半導体集積回路を検査する際に、その予め調整した制御条件を用いて前記電圧源の供給電圧を制御することを特徴とする半導体集積回路の検査方法。   An inspection method for inspecting a semiconductor integrated circuit having a D / A conversion circuit using the semiconductor inspection mechanism according to claim 1, wherein a D to be measured when a predetermined digital code is given. The control conditions of the voltage source are adjusted in advance so that the output voltage of the A / A converter circuit and the supply voltage of the voltage source match, and when the semiconductor integrated circuit is inspected, the control conditions adjusted in advance are used. A method for inspecting a semiconductor integrated circuit, comprising controlling a supply voltage of the voltage source. 請求項5ないし7のいずれかに記載の半導体検査機構を用いて、A/D変換回路を具備する半導体集積回路を検査する検査方法であって、第1の電圧源から出力される電圧の振幅と第2の電圧源から出力される電圧の最小変動幅とが一致するように前記第1および第2の電圧源の制御条件を予め調整しておき、半導体集積回路を検査する際に、その予め調整した制御条件を用いて前記第1と第2の電圧源の供給電圧を制御することを特徴とする半導体集積回路の検査方法。   An inspection method for inspecting a semiconductor integrated circuit including an A / D conversion circuit using the semiconductor inspection mechanism according to claim 5, wherein the amplitude of the voltage output from the first voltage source When the semiconductor integrated circuit is inspected, the control conditions of the first and second voltage sources are adjusted in advance so that the minimum fluctuation range of the voltage output from the second voltage source matches. A method for inspecting a semiconductor integrated circuit, comprising: controlling supply voltages of the first and second voltage sources using control conditions adjusted in advance.
JP2006272363A 2006-10-04 2006-10-04 Semiconductor inspection mechanism, and inspection method of semiconductor integrated circuit Pending JP2008089484A (en)

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