JP2008078303A - Mounting board for lga, and semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a mounting board for an LGA, and a semiconductor integrated circuit device wherein their thinning and reliability are enhanced. <P>SOLUTION: As a semiconductor integrated circuit and a mounting board for LGA, bonding leads and wiring are formed on the surface of a board core member, and a first solder resist is provided on the portion except the bonding leads. Openings for exposing the backside between lands are provided in a second solder resist on the backside of the board core member. The wiring has a part extending to the surface portion corresponding to the opening end in the second solder resist wherein the lands are formed. The thickness of the board core member is made thinner than the total sum of the thicknesses of the first and second solder resists and the board core member has a three-layer glass cloth. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a mounting substrate for an LGA (Land Grid Array) and a semiconductor integrated circuit device, and relates to a technology effective when applied to a package thinning technology.

  In order to prevent cracks at the interface between the solder balls and the conductor pattern of the mounting board due to thermal deformation of the mounting board, and improve the mounting reliability, the package-side land is entirely within the opening of the solder resist layer. Japanese Patent Laid-Open No. 11-297889 discloses an “over-resist type” semiconductor package and mounting substrate that are exposed in general, and a mounting method using these.

  Semiconductor devices incorporated in memory cards such as SD (Secure Digital) (there are standards standardized by the SD Card Association) and memory stick cards are required to be thin. Some memory cards incorporate a semiconductor device having a controller chip and a semiconductor device having a memory chip. In this case, since it is necessary to increase the capacity of the memory, the memory chips may be stacked in multiple stages, and the package thickness increases accordingly. Therefore, as a form of a semiconductor device to be incorporated in a memory card, BGA (Ball Grid Array) and LGA (Land Grid Array) having a smaller thickness than CSP (Chip Size Package) having almost the same size as the chip size are more effective. is there.

  The BGA and CSP are mounted on a motherboard using ball electrodes formed on lands as external terminals. The height from the surface of the land to the top of the solder ball formed by the ball supply method is larger than 100 μm, and satisfies the JEDEC (Joint Electron Device Engineering Council standards) standard of the BGA type package and the CSP type package. . On the other hand, since the land is mounted on the mother board as an external terminal, the LGA can reduce the thickness of the semiconductor device as much as the ball electrode is not used. Since the external terminal is a land, LGA has low mounting strength. As a measure for improving the mounting strength of the LGA, there is a semiconductor device in which each land is coated with solder beforehand and shipped.

A technique called NSMD (Non Solder Mask Defined) is known as a technique of a land structure for improving the connection strength between a land of a substrate and solder, as disclosed in Patent Document 1 above. In NSMD, the surface and side surfaces of the land are exposed at the opening of the resist, and therefore the solder wraps around the side surface of the land, so that the connection strength between the land and the solder can be increased. As a result, in the LGA, in order to improve its mountability, it is preferable to employ a solder coat on the land and NSMD as the land structure.
JP-A-11-297889

  Under the background art as described above, the inventors of the present application have studied to reduce the thickness of the mounting substrate itself on which the semiconductor chip is mounted in order to further reduce the thickness of the semiconductor integrated circuit device. There are 60 μm, 70 μm, and 80 μm as a lineup of core materials of less than 100 μm from manufacturers that manufacture core materials for mounting substrates. Therefore, a mounting substrate was constructed using the above 60 μm core material, and an LGA integrated circuit device having a total thickness of 0.13 mm was made as a prototype toward the memory card.

  In the temperature cycle test for the LGA integrated circuit device, it was found that an unexpected failure occurs. In the conventional LGA integrated circuit device using a core material of 100 μm, there is a phenomenon that the lead wiring part is disconnected from the land in the temperature cycle test, and this is solved by devising the lead part of the wiring. However, in the LGA integrated circuit device in which the core material is made thinner as in this case, a phenomenon that a disconnection occurs in the wiring formed on the surface side of the mounting substrate has occurred.

  FIG. 13 shows an LGA integrated circuit device in which the above-described problem has occurred. FIG. 13A is a cross-sectional view of a part of the LGA integrated circuit device, and FIG. 13B is an enlarged cross-sectional view of the part where the defect occurs. The problem is that a crack has occurred from the opening end of the solder resist for forming the land toward the surface side of the core material, and the Cu wiring on the surface side is disconnected as shown in the surface side pattern diagram of FIG. It is what will end up. That is, in the thin core substrate, cracks (disconnections) or the like are not observed in the wiring taken out from the land as before, and disconnection occurs in the wiring on the surface layer immediately above the solder resist opening end. Therefore, using a structure similar to that shown in FIG. 10 as a model and comparing the core material thickness of 100 μm with that of 60 μm by computer simulation, a large stress is applied to the opening edge of the solder resist in the case of 60 μm. Turned out to be concentrated.

  An object of the present invention is to provide an LGA mounting substrate and a semiconductor integrated circuit device which are reduced in thickness and improved in reliability. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, as a semiconductor integrated circuit device and an LGA mounting substrate used therefor, bonding leads and wirings are formed on the surface of the substrate core material, and a partial first solder resist excluding the bonding leads is provided. An opening for exposing the back surface is provided between the lands on the second solder resist on the back surface of the substrate core material. The wiring has a portion extending to a surface portion corresponding to the opening end of the second solder resist where the land is formed. The substrate core material is thinner than the sum of the thicknesses of the first and second solder resists and has a three-layer glass cloth.

  The outline of other representative ones of the inventions disclosed in the present application will be briefly described as follows. That is, as a semiconductor integrated circuit device and an LGA mounting substrate used therefor, bonding leads and wirings are formed on the surface of the substrate core material, and a partial first solder resist excluding the bonding leads is provided. An opening for exposing the back surface is provided between the lands on the second solder resist on the back surface of the substrate core material. The wiring is not formed on the surface portion corresponding to the opening end of the second solder resist where the land is formed. The substrate core material is thinner than the sum of the thicknesses of the first and second solder resists and has a two-layer glass cloth.

  In the core material of the three-layer glass cloth, the crack itself of the core material is prevented by strengthening against thermal stress. In the core material of the two-layer glass cloth, even if a crack occurs in the core material, the wiring itself does not exist. In any case, the LGA mounting substrate and the semiconductor integrated circuit device can be made thinner and more reliable.

  FIG. 1 is a partial schematic cross-sectional view of an embodiment of an LGA mounting substrate according to the present invention. In this embodiment, a plurality of lands are arranged in a matrix on the back surface (mounting surface) side of the wiring board. When secondary mounting is performed on the mounting board, solder balls are used as in a BGA type or CSP type semiconductor device. For example, it is directed to a so-called LGA semiconductor integrated circuit device that is mounted via a solder paste. In the case of an LGA type semiconductor device, the mounting height of the semiconductor device can be reduced as compared with a BGA type or a CSP type. In this embodiment, although not particularly limited, a three-layer glass cloth is provided in order to strengthen the core material of the mounting substrate (substrate, wiring substrate). That is, a 3PLY hard insulating substrate in which a three-layer glass cloth is hardened with an epoxy resin is employed.

  FIG. 11 shows a plan view on the surface side of one embodiment of the mounting board 3 of FIG. On the surface side of the substrate core material (mounting substrate) 3, a Cu (copper) wiring 2 b exemplarily shown is provided and covered with a solder resist. The solder resist is selectively provided with an opening 1, and a bonding lead 2 a formed in the same manner as the Cu wiring is formed in the opening 1. In FIG. 11, circles (2e) are shown so that the positional relationship between the wiring 2b formed on the front surface side and the SR opening 2e of the land formed on the back surface side can be understood. Along with the downsizing of the semiconductor device, the size of the mounting substrate to be used is also reduced, so that there is a demand for higher functionality and higher speed of the semiconductor device. There are many areas where the solder resist (SR) opening end 2e that opens the land 3d and the wiring 2b overlap, and there is a risk of disconnection due to the crack.

  FIG. 12 shows a plan view of the back side of one embodiment of the mounting board 3 of FIG. The bonding lead 2a formed on the front surface side in FIG. 11 is electrically connected to the lead wiring 2c formed on the back surface side through the wiring 2b and the through hole 2d in FIG. 12, and a part of the lead wiring 2c is formed. It is formed as a land 3d. The reason why the diameter of the solder resist (SR) opening 2e that opens the land 3d is larger than the area of the land 3d is that in the case of the LGA type semiconductor device, the LGA is mounted on the mounting substrate through solder paste, for example, in a later step. However, in order to improve the bonding strength of the solder paste, in order to wet the solder not only to the plane area of the land (wiring in the land area) 3d but also to the side surface portion of the land (wiring in the land area) 3d, In particular, the diameter of the solder resist (SR) opening 2e is made larger than the size of the land 3d. This shape is called an NSMD (Non-Solder Mask Defined) structure.

  In FIG. 1, for example, the 3PLY hard insulating substrate as the core material is provided with laminated copper on the front and back surfaces, and although not particularly limited, half etching is performed to reduce the thickness of the laminated copper. Next, drilling is performed. That is, a hole that penetrates the substrate is provided to form a through hole. Thereafter, copper plating is performed. Thereby, a copper plating layer is formed including the hole. The surface of these copper plating layers is subjected to copper surface polishing as the next pretreatment for lamination. Dry film lamination is performed on the front and back surfaces of the substrate. Baking and development are performed on the dry film.

  Thus, as shown in FIG. 11 and FIG. 12, the bonding lead consisting of the wiring portion and a part of the wiring portion on the front surface side, and the drawing wiring portion (not shown) and a part of the drawing wiring portion on the back surface side. A portion of the dry film excluding the land is removed. Here, the wiring portion on the front surface side and the lead wiring portion on the back surface side of the substrate are electrically connected via a copper plating layer (through hole wiring) formed in the through hole. Etching using the dry film as a mask is performed to selectively remove the laminated copper. Then, the dry film is peeled off, and a solder resist (insulating film) is printed on the front and back surfaces of the substrate. The opening is provided in this printing. In FIG. 1, the through holes are omitted because they are not directly related to the present invention.

  The reason why the 3PLY hard insulating substrate is used as the core material is as follows. The LGA integrated circuit device shown in FIGS. 13 and 14 uses a 2PLY hard insulating substrate in which a two-layer glass cloth is hardened with an epoxy resin. In the core material having the thickness of 60 μm, the open end of the solder resist is used. It is thought that cracks occurred due to the concentration of large stress on the surface. Therefore, in order to prevent the occurrence of such cracks, it is necessary to reinforce the core material itself if the thickness is maintained, and the three-layer glass cloth is used as described above.

  The solder resist is formed by printing as described above, and it is necessary to make the surface of the mounting substrate uniform. For this reason, it is necessary to maintain the thicknesses d1 and d2 of the solder resist at 30 μm to 40 μm. And this solder resist becomes one of the causes which generate | occur | produce a thermal stress in the said core material. As will be described later, a semiconductor chip is bonded to the surface of the mounting substrate with a die bond material. For this reason, the surface side including the solder resist is strengthened in a sense against thermal stress. On the other hand, on the back side, thermal stress due to the difference in thermal expansion coefficient between the solder resist and the core material is directly applied, and cracks are generated as described above.

  The inventor of the present application has found that the thickness d3 of the core material at which large stress concentrates on the opening end of the solder resist and cracks can be defined in association with the thickness of the solder resist. In other words, the total thickness of the solder resist (d1 + d2 = 60 to 80 μm) is at the limit as described above. Therefore, when using a thin core material (d3 ≦ d1 + d2) smaller than that, the above two-layer glass cloth is made of epoxy resin. In the hardened 2PLY hard insulating substrate, it was found that the solder resist side was relatively strong, and the probability of occurrence of the cracks on the core material side was very high. For this reason, when a mounting substrate having a relationship of d3 ≦ d1 + d2 is used, a 3PLY hard insulating substrate is used as the core material. Thereby, even if the thickness is reduced to about 60 μm, no crack is generated at the opening end of the solder resist corresponding to the land, and no disconnection occurs even if the wiring exists on the surface side. Such cracks have not been confirmed by computer simulation using the structure shown in FIG. 1 as a model.

  FIG. 2 is a plan view for explaining the glass cloth, and FIG. 3 is a cross-sectional view thereof. Thin glass fiber is knitted in the length and breadth to make a cross. In the three-layer glass cloth, the glass cloth as shown in FIGS. 2 and 3 is formed into three layers, and is hardened with an epoxy resin as described above to form a 3PLY hard insulating substrate.

  4 to 7 are process cross-sectional views of an embodiment for explaining a package assembly method of a semiconductor integrated circuit device using the mounting substrate shown in FIG. In FIG. 4 to FIG. 6, as a representative, the glass cloth of the core material of the mounting substrate is shown as an example.

  In FIG. 4, the mounting substrate shown in FIG. 1 is prepared. The mounting substrate is not particularly limited, but is formed so as to mount a plurality of semiconductor chips directed to a MAP (Mold Array Package), that is, a batch molding technique. Die bonding of a plurality of semiconductor chips is performed on the mounting substrate. In the figure, as an example, portions corresponding to two semiconductor integrated circuit devices are shown as an example. The semiconductor chip is bonded to the semiconductor chip mounting portion with a die bond material made of a paste made of a liquid epoxy resin. Although this embodiment is not particularly limited, it is directed to a flash memory, and two chips, chip 1 and chip 2, are mounted in a stacked structure in order to increase the storage capacity. That is, the first-stage chip 1 is mounted on the main surface of the mounting substrate via the die bond material. Subsequently, the second-stage chip 2 is mounted on the first-stage chip 1 via a die bonding material.

  In FIG. 5, wire bonding is performed. That is, a plurality of bonding pads of a semiconductor chip and a plurality of bonding leads (wire connection lands) provided on the front surface side of the mounting substrate are sequentially connected by Au wires made of Au (gold) wires or the like. That is, the first-stage chip 1 and the lead as the bonding electrode of the mounting substrate are electrically connected by the Au wire, and the second-stage chip 2 and the bonding lead of the mounting substrate are electrically connected by the Au wire. Connect to.

  In FIG. 6, the plurality of semiconductor chips are integrally molded with resin such as resin. Here, in order to clarify the relationship with FIG. 7, the semiconductor integrated circuit device is denoted by symbol 7, the mold resin is denoted by symbol 6, the mounting substrate is denoted by symbol 3, the land is denoted by symbol 3d, and the solder resist is denoted by symbol 3f. The

  In FIG. 7, after the baking process is performed, the mounting substrate is turned over, and a solder coat is formed on the back side. That is, when the mold of FIG. 7 is completed, the mounting substrate that has been molded as described above is turned over. In the next solder printing, solder is printed on each land 3d. That is, solder is formed by printing on each land 3d on the back surface 3b of the mounting substrate 3 by a solder printing method. At that time, the printing mask 13 is disposed on the main surface 3 a of the mounting substrate 3. At this time, the opening 13a of the printing mask 13 is arranged so that the position of the land 3d is aligned. Thereafter, the solder paste 15 is applied onto each land 3d by the squeegee 14 on the printing mask 13. That is, the solder paste 15 is embedded in the opening 13a of the printing mask 13 by the squeegee 14, and the solder paste 15 is applied on each land 3d. Thus, the solder printing is completed as shown in the solder printing completion of FIG. A heat treatment is performed by heat treatment to form a solder coat 5 on each land 3d. Although not shown in the drawings, in the batch molding technique, individual semiconductor integrated circuit devices are separated by dicing.

  FIG. 8 and FIG. 9 are explanatory views of the structure of a memory card 8 which is an example of a card type electronic device on which the LGA integrated circuit device according to the present invention is mounted. Two LGAs 7 are mounted on the front side of the card substrate 9, while a CSP (Chip Size Package) 10 that is a control package is mounted on the back side. Here, since the LGA 7 has a structure in which the semiconductor chips 1 are stacked, the thickness of the semiconductor device is higher than that of the CSP 10 mounted on the back side of the card substrate 9 of the memory card 8. Therefore, it is preferable to adopt an LGA type package for a semiconductor device on which the semiconductor chip 1 for memory is stacked. The two LGAs 7 on the front side and the CSP 10 on the back side are covered with a case 11 on the front side and a case 11 on the back side, respectively. Furthermore, as shown in FIG. 9, a plurality of external terminals 12 provided on the back side of the card substrate 9 are exposed in the opening 11a of the case 11 on the back side. Such card-type electronic devices are being thinned, and the thinness and high reliability of the LGA 7 according to the present invention are suitable for being mounted on such card-type electronic devices.

  FIG. 10 is a partial schematic cross-sectional view of another embodiment of the LGA mounting substrate according to the present invention. This embodiment is also directed to a semiconductor integrated circuit device having an LGA configuration. In this embodiment, a double-layer glass cloth is provided as a mounting substrate for easy reduction in thickness and cost reduction. That is, a 2PLY hard insulating substrate in which a two-layer glass cloth is hardened with an epoxy resin is employed. Cu (copper) wiring shown as an example is provided on the surface side of the substrate core material, and is covered with a solder resist. The solder resist is selectively provided with openings, and bonding leads formed in the same manner as the Cu wiring are formed in the openings.

  An important hint is shown in the pattern diagram shown in FIG. It has been found that when the 2PLY hard insulating substrate core material thinned to 60 μm as described above is used, cracks occur in the core material. There are two cracks such as crack 1 and crack 2, but the crack 1 is provided with a Cu wiring on the surface side, which causes a problem that the Cu wiring is disconnected. On the other hand, the crack 2 occurs in a portion where the Cu wiring is not formed, and there is no problem in itself.

  In the embodiment of FIG. 10, as described above, in order to achieve both a reduction in thickness and a reduction in cost, a contrivance is made so that no problem is caused by a crack generated when a double-layer glass cloth is used. In other words, Cu wiring is not formed on a portion corresponding to the opening end of the second solder resist on which the land on the back surface side is formed on the front surface side of the mounting substrate. As a result, even if a crack occurs, it does not cause any problems as a semiconductor integrated circuit device by itself. As a result, even if the thickness is reduced to about 60 μm, a crack is generated at the opening end of the solder resist corresponding to the land. Even if this occurs, the LGA mounting substrate and the semiconductor integrated circuit device can be made thinner and more reliable. However, in the case of this embodiment, the number of electrodes of the semiconductor chip mounted on the wiring board is small, that is, the case where there is a margin in the wiring routing with respect to the planar size of the mounting board. Therefore, when the number of electrodes is relatively large and the semiconductor device is required to be downsized at the same time as the speed and function of the semiconductor device are increased, the plane size of the mounting substrate is shown in FIG. Thus, since it is difficult to route the Cu wiring so as to bypass the portion corresponding to the opening end of the second solder resist, a 3PLY hard insulating substrate may be adopted as in the embodiment of FIG.

  Although the invention made by the inventor has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. For example, the solder resist may be formed by attaching a thin sheet in addition to the one formed by the printing method as described above. The LGA integrated circuit device may be based on an individual molding technique in addition to the MAP, that is, a collective molding technique. The present invention can be widely used for an LGA mounting substrate and a semiconductor integrated circuit device using the same.

It is a partial schematic sectional drawing which shows one Example of the mounting board | substrate for LGA which concerns on this invention. It is a top view for demonstrating the glass cloth of FIG. It is sectional drawing for demonstrating the glass cloth of FIG. FIG. 7 is a partial process cross-sectional view of one embodiment for explaining a package assembly method of the semiconductor integrated circuit device using the mounting substrate shown in FIG. 1. FIG. 7 is a partial process cross-sectional view of one embodiment for explaining a package assembly method of the semiconductor integrated circuit device using the mounting substrate shown in FIG. 1. FIG. 7 is a partial process cross-sectional view of one embodiment for explaining a package assembly method of the semiconductor integrated circuit device using the mounting substrate shown in FIG. 1. FIG. 7 is a partial process cross-sectional view of one embodiment for explaining a package assembly method of the semiconductor integrated circuit device using the mounting substrate shown in FIG. 1. 1 is a structure explanatory diagram of a memory card which is an example of a card type electronic device on which an LGA integrated circuit device according to the present invention is mounted. It is sectional drawing of the memory card of FIG. It is a partial schematic sectional drawing which shows another Example of the mounting board | substrate for LGA concerning this invention. It is a top view in the surface side of the mounting substrate of FIG. It is a top view in the back surface side of the mounting substrate of FIG. It is sectional drawing of the LGA integrated circuit device partial part which the malfunction verified prior to this invention produced. It is the surface side pattern figure of the malfunctioning part of FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Solder resist opening, 2a ... Bonding lead, 2b ... Wiring, 2c ... Lead wire, 2d ... Through hole, 2e ... SR opening, 3 ... Mounting board (wiring board), 3d ... Land, 3f ... Solder resist, 5 DESCRIPTION OF SYMBOLS ... Solder coat, 6 ... Mold resin, 7 ... LGA integrated circuit device, 8 ... Memory card (card type electronic device), 9 ... Card substrate, 10 ... CSP, 11 ... Case, 11a ... Opening, 12 ... External terminal 13 ... Printing mask, 14 ... Squeegee, 15 ... Solder paste.

Claims (14)

A substrate core material;
Bonding leads provided on the surface of the substrate core material;
Wiring provided on the surface of the substrate core material;
A first solder resist provided on a surface of the substrate core material and provided on a portion excluding the bonding lead;
A land provided on the back surface of the substrate core material;
The second solder resist provided on the back surface of the substrate core material and provided on the portion excluding the land,
The back surface of the substrate core material has a portion exposed between the land and the second solder resist,
The wiring has a portion extending to the surface portion corresponding to the opening end of the second solder resist where the land is formed,
The substrate core material is an LGA mounting substrate having a thickness smaller than a sum of thicknesses of the first and second solder resists and having a three-layer glass cloth. In claim 1,
The substrate core material is a mounting substrate for LGA, which is a 3PLY hard insulating substrate in which the three-layer glass cloth is hardened with an epoxy resin. In claim 2,
The substrate core material is an LGA mounting substrate of 60 μm or less. A substrate core material;
Bonding leads provided on the surface of the substrate core material;
Wiring provided on the surface of the substrate core material;
A first solder resist provided on a surface of the substrate core material and provided on a portion excluding the bonding lead;
A land provided on the back surface of the substrate core material;
The second solder resist provided on the back surface of the substrate core material and provided on the portion excluding the land,
The back surface of the substrate core material has a portion exposed between the land and the second solder resist,
The wiring is not formed in a portion corresponding to the opening end of the second solder resist where the land is formed,
The substrate core material is an LGA mounting substrate having a thickness smaller than a sum of thicknesses of the first and second solder resists and having two layers of glass cloth. In claim 4,
The substrate core material is a mounting substrate for LGA, which is a 2PLY hard insulating substrate in which the two-layer glass cloth is hardened with an epoxy resin. In claim 5,
The substrate core material is an LGA mounting substrate of 60 μm or less. An LGA mounting substrate;
A semiconductor chip;
A mold resin,
The LGA mounting board is
A substrate core material;
Bonding leads provided on the surface of the substrate core material;
Wiring provided on the surface of the substrate core material;
A first solder resist provided on a surface of the substrate core material and provided on a portion excluding the bonding lead;
A land provided on the back surface of the substrate core material;
The second solder resist provided on the back surface of the substrate core material and provided on the portion excluding the land,
The back surface of the substrate core material has a portion exposed between the land and the second solder resist,
The wiring has a portion extending a surface portion corresponding to the opening end of the second solder resist in which the land is formed,
The substrate core material is thinner than the sum of the thicknesses of the first and second solder resists, and has a three-layer glass cloth,
The semiconductor chip is
It is mounted on the surface side of the mounting board,
The bonding pad of the semiconductor chip and the bonding lead of the mounting substrate are connected by a bonding wire,
The mold resin seals the semiconductor chip on the surface side of the mounting substrate,
A semiconductor integrated circuit device in which a solder coat is provided on a land on the back side of the mounting substrate. In claim 7,
The semiconductor integrated circuit device, wherein the wiring forms an electrical path between the bonding lead and a land on the back side. In claim 8,
The semiconductor integrated circuit device, wherein the substrate core material is a hard insulating substrate having a 3PLY structure in which the three-layer glass cloth is hardened with an epoxy resin. In claim 9,
The semiconductor integrated circuit device, wherein the substrate core material is 60 μm or less. An LGA mounting substrate;
A semiconductor chip;
A mold resin,
The LGA mounting board is
A substrate core material;
Bonding leads provided on the surface of the substrate core material;
Wiring provided on the surface of the substrate core material;
A first solder resist provided on a surface of the substrate core material and provided on a portion excluding the bonding lead;
A land provided on the back surface of the substrate core material;
The second solder resist provided on the back surface of the substrate core material and provided on the portion excluding the land,
The back surface of the substrate core material has a portion exposed between the land and the second solder resist,
The wiring is not formed on the surface portion corresponding to the opening end of the second solder resist where the land is formed,
The substrate core material has a thickness smaller than the sum of the thicknesses of the first and second solder resists, and has two layers of glass cloth,
The semiconductor chip is
It is mounted on the surface side of the mounting board,
The bonding pad of the semiconductor chip and the bonding lead of the mounting substrate are connected by a bonding wire,
The mold resin seals the semiconductor chip on the surface side of the mounting substrate,
A semiconductor integrated circuit device in which a solder coat is provided on a land on the back side of the mounting substrate. In claim 11,
The semiconductor integrated circuit device, wherein the wiring forms an electrical path between the bonding lead and a land on the back side. In claim 12,
The semiconductor integrated circuit device, wherein the substrate core material is a hard insulating substrate having a 2PLY structure in which the two-layer glass cloth is hardened with an epoxy resin. In claim 13,
The semiconductor integrated circuit device, wherein the substrate core material is 60 μm or less.

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