JP2008071490A - Semiconductor integrated circuit device, ic card, and inspection device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device capable of using a nonvolatile semiconductor memory in a normal state. <P>SOLUTION: Data of one reading unit is read from the lines X1 to X16 of a memory cell array 61 to investigate the presence of an error (A). For the line X16 corresponding to the error-detected data, data of all reading units are read (B). Thus, time for diagnosing a nonvolatile semiconductor memory 60 is shortened. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device, an IC card, and an inspection device. More specifically, a semiconductor integrated circuit device having a nonvolatile semiconductor memory and a test circuit for diagnosing the nonvolatile semiconductor memory, a semiconductor integrated circuit device having a nonvolatile semiconductor memory and a cache memory, and the semiconductor integrated circuit device are provided. The present invention relates to an inspection device for diagnosing an IC card and a nonvolatile semiconductor memory.

  In recent years, IC cards with a built-in nonvolatile semiconductor memory have become widespread in the financial field and transportation field. It is desirable that an IC card used in such a field can be used for a long time in a normal state. However, the IC card may break down due to the IC card being pulled out from the reader / writer during the writing operation to the nonvolatile semiconductor memory or the number of times of writing to the nonvolatile semiconductor memory being increased.

  An object of the present invention is to provide a semiconductor integrated circuit device that can use a nonvolatile semiconductor memory in a normal state for a long period of time.

Means for Solving the Problems and Effects of the Invention

  According to one aspect of the present invention, a semiconductor integrated circuit device includes a nonvolatile semiconductor memory and an inspection circuit. The nonvolatile semiconductor memory includes a memory cell array and an error correction circuit. The memory cell array is divided into a plurality of read units in rows and columns. The error correction circuit performs error correction encoding of data to be written in each of the plurality of read units, and performs error detection and error correction of data read from each of the plurality of read units. The inspection circuit diagnoses the nonvolatile semiconductor memory. The inspection circuit gives a first instruction to the nonvolatile semiconductor memory to instruct to read one read unit of data from each row of the memory cell array. When an error in the data read in accordance with the first instruction is detected by the error correction circuit, the inspection circuit instructs to read out data in all read units in the row corresponding to the data in which the error is detected. 2 is given to the nonvolatile semiconductor memory.

  In the semiconductor integrated circuit device, diagnosis of the nonvolatile semiconductor memory is performed by the inspection circuit. In the diagnosis of the nonvolatile semiconductor memory, first, a first instruction is given from the inspection circuit to the nonvolatile semiconductor memory. In response to the first instruction, the nonvolatile semiconductor memory reads data of one read unit from a certain row of the memory cell array. Then, error detection and error correction processing of data read from the memory cell array is performed by the error correction circuit. When no error is detected, one read unit of data is read from another row. Normally, writing to the nonvolatile semiconductor memory is performed in units of rows. Therefore, when an error occurs during writing, there is a high possibility that an error has occurred in all the memory cells in the same row. Therefore, in the semiconductor integrated circuit device, when no error is detected, it is determined that the data is correctly written in the memory cell in the row, and then the data of one read unit is read from another row. I have to. On the other hand, when an error is detected, a second instruction is given from the inspection circuit to the nonvolatile semiconductor memory. In response to the second instruction, the non-volatile semiconductor memory reads data of all read units in the row corresponding to the data in which the error is detected. Such processing is performed for all the rows of the memory cell array of the nonvolatile semiconductor memory.

  As described above, since the semiconductor integrated circuit device is provided with the inspection circuit, it can be determined whether or not the nonvolatile semiconductor memory is in a normal state. As a result, it is possible to prevent a situation in which the nonvolatile semiconductor memory continues to be used in a failed state. As a result, the nonvolatile semiconductor memory is used for a long time in a normal state.

  In addition, data for one read unit is read for each row of the memory cell array, and all read unit data is read for the row corresponding to the data in which the error is detected, so the time required for diagnosis of the nonvolatile semiconductor memory is shortened. can do.

  Preferably, when there is data in which no error is detected by the error correction circuit among the data read according to the second instruction, the inspection circuit includes the error correction circuit among the data read according to the second instruction. A third instruction for giving an instruction to rewrite the data in which the error is detected is given to the nonvolatile semiconductor memory.

The errors detected by the error correction circuit include the following types (a) and (b).
(A) An error that occurs only for some of the memory cells in the same row.
・ Recording data has changed due to defective data retention characteristics of the memory cell. ・ It is possible that previous data remained in the memory cell and could not be written correctly. Such an error can be repaired by writing the same data again.
(B) An error that occurs for all memory cells in the same row.
-The desired data could not be recorded due to power-down during writing.

  In the semiconductor integrated circuit device, when there is data in which no error is detected by the error correction circuit among the data read according to the second instruction, that is, a part of the data read according to the second instruction When only an error is detected, it is determined that the error is an error as described in (a) above. Further, regarding the data in which the error is detected, it is determined that the data has not been correctly read but has been corrected to the correct data by the error correction process. Then, a third instruction is given from the inspection circuit to the nonvolatile semiconductor memory. In response to the third instruction, the nonvolatile semiconductor memory rewrites the data in which the error is detected. This repairs the error.

  Preferably, the inspection circuit outputs a signal indicating an abnormality when an error is detected by the error correction circuit in all of the data read in accordance with the second instruction.

  In the semiconductor integrated circuit device, when an error is detected by the error correction circuit in all the data read in accordance with the second instruction, the error is determined to be an error as described in (b) above. Further, it is determined that the data of the memory cell in the row corresponding to the data in which the error is detected is destroyed, that is, cannot be repaired. Then, a signal indicating abnormality is output. As a result, it is possible to prevent a situation in which the nonvolatile semiconductor memory continues to be used while the data in the memory cell is destroyed.

  Preferably, the inspection circuit gives a first instruction to read out data in a reading unit in an area where a defect occurrence frequency is expected to be high in the area of the memory cell array.

  With respect to the error as described above (b), a sufficient diagnosis can be performed by reading data of one read unit from each row of the memory cell array. However, in the case of an error as described above (a), data in a read unit other than the read unit in which the error exists may be read according to the first instruction, so that sufficient diagnosis cannot be performed.

  Since it is considered that there are a number of process factors that influence the characteristic failure of the memory cell of the non-volatile semiconductor memory, there are cases where it is possible to statistically predict the region where the occurrence of characteristic failure is high in the memory cell array region. is there. In the semiconductor integrated circuit device, in response to the first instruction from the inspection circuit, data of one read unit in an area where the defect occurrence frequency is expected to be high is read from each row of the memory cell array of the nonvolatile semiconductor memory. . Therefore, an efficient diagnosis can be performed for the error (a) described above.

  Preferably, the inspection circuit gives a first instruction to read out data in a reading unit corresponding to a different column for each row.

  It is difficult to predict in which area of the memory cell array a characteristic failure caused by an accidental factor will occur. According to the semiconductor integrated circuit device, it is possible to prevent the read unit read according to the first instruction from being biased to a specific region of the memory cell array. Thereby, an efficient diagnosis can be performed for the error as described in (a) above.

  Preferably, the inspection circuit gives a first instruction to read data of a read unit corresponding to one column of the memory cell array. The one column is different each time the first instruction is given.

  In the semiconductor integrated circuit device, in a certain diagnostic operation, data of one read unit corresponding to the first column of the memory cell array is read from each row in response to the first instruction. In the next diagnostic operation, data of one read unit corresponding to the second column of the memory cell array is read from each row in response to the first instruction. In this way, data for one read unit corresponding to a different column is read from each row in response to the first instruction for each diagnosis operation. As a result, even if memory cells having defective characteristics are present at random, all characteristic defects can be detected during the predetermined number of diagnostic operations.

  Preferably, the semiconductor integrated circuit device further includes a CPU. The inspection circuit gives a signal for starting the CPU to the CPU after the diagnosis of the nonvolatile semiconductor memory is completed.

  When a diagnostic program is stored in the ROM and the diagnostic program is read from the ROM and the nonvolatile semiconductor memory is diagnosed after the CPU is started, the access to the nonvolatile semiconductor memory is performed by analyzing the operation of the CPU. The procedure may be analyzed. However, in the semiconductor integrated circuit device, the nonvolatile semiconductor memory is diagnosed by the inspection circuit while the CPU stops operating. Therefore, it is difficult to analyze the access procedure to the nonvolatile semiconductor memory. Moreover, since the time required for diagnosis is short, it is difficult to analyze that the nonvolatile semiconductor memory is being diagnosed.

  Preferably, the inspection circuit gives a signal indicating abnormality to the CPU when an error is detected by the error correction circuit in all of the data read in accordance with the second instruction.

  In the semiconductor integrated circuit device, when an error is detected by the error correction circuit in all the data read in accordance with the second instruction, the error is determined to be an error as described in (b) above. Further, it is determined that the data of the memory cell in the row corresponding to the data in which the error is detected is destroyed, that is, cannot be repaired. Then, a signal indicating abnormality is given from the inspection circuit to the CPU. As a result, the CPU can recognize that the nonvolatile semiconductor memory has failed at the stage before starting and starting the processing.

  Preferably, the CPU stops activation in response to a signal indicating an abnormality from the inspection circuit.

  According to the semiconductor integrated circuit device, it is possible to prevent a situation in which the CPU proceeds with processing while the nonvolatile semiconductor memory is in a failed state.

  According to another aspect of the present invention, an IC card includes the semiconductor integrated circuit device.

  According to yet another aspect of the present invention, the inspection device is a device for diagnosing a nonvolatile semiconductor memory. The nonvolatile semiconductor memory includes a memory cell array and an error correction circuit. The memory cell array is divided into a plurality of read units in rows and columns. The error correction circuit performs error correction encoding of data to be written in each of the plurality of read units, and performs error detection and error correction of data read from each of the plurality of read units. The inspection apparatus gives a first instruction to the nonvolatile semiconductor memory to instruct to read one read unit of data from each row of the memory cell array. When an error in the data read in accordance with the first instruction is detected by the error correction circuit, the inspection apparatus instructs to read out data in all read units in the row corresponding to the data in which the error is detected. A second instruction is given to the nonvolatile semiconductor memory.

  According to still another aspect of the present invention, a semiconductor integrated circuit device includes a nonvolatile semiconductor memory, a cache memory, an address storage unit, and an access control unit. The address storage unit stores at least one address of the nonvolatile semiconductor memory. The access control unit writes the write data corresponding to the write address to the cache memory when the write address to the nonvolatile semiconductor memory matches any one of the addresses stored in the address storage unit.

  Usually, the nonvolatile semiconductor memory has an upper limit on the number of times of writing. When the number of times of writing approaches this upper limit, there is a high possibility that a failure such as a writing error will occur. In the semiconductor integrated circuit device, a predetermined address of the nonvolatile semiconductor memory is stored in advance in the address storage unit. When there is a write access to the nonvolatile semiconductor memory, the write address is compared with the address stored in the address storage unit. When any one of the addresses stored in the address storage unit matches the write address, the write data corresponding to the write address is written into the cache memory. Thereby, the number of times of writing to the nonvolatile semiconductor memory can be reduced. As a result, the nonvolatile semiconductor memory is used for a long time in a normal state.

  In general, a large amount of cache memory resources are required to accurately extract addresses that are likely to hit the cache (for example, the latest addresses or addresses that have been accessed many times) during program execution (address replacement mechanism). And Since the semiconductor integrated circuit device is provided with the address storage unit, an address that is likely to hit the cache can be stored in the address storage unit in advance. As a result, the number of times of writing to the nonvolatile semiconductor memory can be reduced with fewer resources than when no address storage unit is provided.

  Preferably, the access control unit changes the address stored in the address storage unit according to the status of write access to the nonvolatile semiconductor memory.

  Preferably, the address storage unit includes first and second areas for storing addresses of the nonvolatile semiconductor memory. The access control unit changes the address stored in the second area of the address storage unit according to the status of write access to the nonvolatile semiconductor memory.

  Preferably, the access control unit writes the address stored in the address storage unit to the cache memory. The access control unit writes the write data corresponding to the write address to the cache memory when the write address to the nonvolatile semiconductor memory matches one of the addresses stored in the cache memory.

  Preferably, the access control unit changes the address stored in the cache memory according to the status of write access to the nonvolatile semiconductor memory, and writes the changed address in the address storage unit.

  Preferably, the address storage unit includes first and second areas for storing addresses of the nonvolatile semiconductor memory. The cache memory includes a third area and a fourth area. The access control unit writes the address stored in the first area of the address storage unit to the third area of the cache memory, and writes the address stored in the second area of the address storage unit to the fourth area of the cache memory. Write to the area. The access control unit changes the address stored in the fourth area of the cache memory according to the status of the write access to the nonvolatile semiconductor memory, and the changed address is stored in the second area of the address storage unit. Write.

  According to yet another aspect of the present invention, an IC card includes the semiconductor integrated circuit device.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(First embodiment)
<Configuration of IC card>
FIG. 1 is a block diagram showing the configuration of an IC card according to the first embodiment of the present invention. The IC card shown in FIG. 1 is a non-contact type IC card, and includes an antenna coil 10 and an LSI chip 1.

  The antenna coil 10 transmits / receives data to / from a reader / writer (not shown) in a contactless manner and receives power from the reader / writer in a contactless manner.

  The LSI chip 1 includes an interface circuit 20, an inspection circuit 30, a CPU 40, a selector 50, and a nonvolatile semiconductor memory 60.

  The interface circuit 20 supplies the power received by the antenna coil 10 to each unit. Further, the interface circuit 20 supplies a clock serving as an operation reference to each unit. The interface circuit 20 transmits data to be transmitted to the reader / writer to the antenna coil 10 and transmits data received by the antenna coil 10 to a predetermined circuit. Further, the interface circuit 20 gives a reset signal RST1 corresponding to the power received by the antenna coil 10 to the inspection circuit 30. When the power received by the antenna coil 10 is less than a predetermined level, the interface circuit 20 supplies the L level (logic low level) reset signal RST1 to the test circuit 30. When the electric power received by the antenna coil 10 is equal to or higher than a predetermined level, the interface circuit 20 supplies an H level (logic high level) reset signal RST1 to the inspection circuit 30.

  The inspection circuit 30 diagnoses the nonvolatile semiconductor memory 60. The inspection circuit 30 includes a control unit 31, a data processing unit 32, and an address generation unit 33. The control unit 31 instructs the data processing unit 32 and the address generation unit 33 to start diagnosis of the nonvolatile semiconductor memory 60 in response to the reset signal RST1 from the interface circuit 20 being switched from the L level to the H level. In the diagnostic operation of the nonvolatile semiconductor memory 60, the control unit 31 controls the data processing unit 32 and the address generation unit 33. The control unit 31 gives an instruction corresponding to the error correction information from the nonvolatile semiconductor memory 60 to the data processing unit 32 and the address generation unit 33. Further, the control unit 31 gives a control signal for instructing reading / writing of data to the nonvolatile semiconductor memory 60 via the selector 50. When the diagnosis of the nonvolatile semiconductor memory 60 is completed, the control unit 31 gives an H level reset signal RST2 to the CPU 40 and the selector 50, and gives the diagnosis result of the nonvolatile semiconductor memory 60 to the CPU 40. The data processing unit 32 exchanges data with the nonvolatile semiconductor memory 60 via the selector 50. The address generator 33 gives the read / write address to the nonvolatile semiconductor memory 60 via the selector 50.

  The CPU 40 is activated in response to the reset signal RST2 from the control unit 31 of the inspection circuit 30 being switched from the L level to the H level. The CPU 40 performs processing according to the diagnosis result from the control unit 31. The CPU 40 gives a control signal and an address to the nonvolatile semiconductor memory 60 via the selector 50, and exchanges data with the nonvolatile semiconductor memory 60 via the selector 50.

  The selector 50 receives control signals, addresses, and data between the inspection circuit 30 and the nonvolatile semiconductor memory 60 or between the CPU 40 and the nonvolatile semiconductor memory 60 in accordance with the reset signal RST2 from the control unit 31 of the inspection circuit 30. Switch paths so that you can communicate. When the reset signal RST2 is at the L level, the selector 50 forms a path so that control signals, addresses, and data can be exchanged between the inspection circuit 30 and the nonvolatile semiconductor memory 60. When the reset signal RST2 is at the H level, the selector 50 forms a path so that control signals, addresses, and data can be exchanged between the CPU 40 and the nonvolatile semiconductor memory 60.

  The nonvolatile semiconductor memory 60 has an error correction function, and provides error correction information indicating the presence or absence of an error for each reading unit to the control unit 31 of the inspection circuit 30. As the nonvolatile semiconductor memory 60, EEPROM, flash memory, FeRAM, or the like can be used.

<Configuration of Nonvolatile Semiconductor Memory 60>
FIG. 2 is a block diagram showing an internal configuration of the nonvolatile semiconductor memory 60 shown in FIG. Referring to FIG. 2, nonvolatile semiconductor memory 60 includes a memory cell array 61, an address decoder 62, a row decoder 63, a column decoder 64, an error correction circuit 65, and an input / output buffer 66.

  The memory cell array 61 is divided into a plurality of (16 × 16) read units in rows (X1-X16) and columns (Y1-Y16). Data (32 bits) and error correction data (6 bits) are stored in each reading unit. In the memory cell array 61 of FIG. 2, the numbers (hexadecimal display) in the blocks representing the respective read units indicate addresses given to the address decoder 62 for designating the read units.

  The address decoder 62 gives a row address and a column address for designating a read unit according to the control signal from the selector 50 and the address to the row decoder 63 and the column decoder 64. The row decoder 63 selects a corresponding row in response to the row address from the address decoder 62. The column decoder 64 selects a corresponding column in response to the column address from the address decoder 62.

  The input / output buffer 66 temporarily stores write data and read data.

  The error correction circuit 65 adds an error correction bit (6 bits) to write data (32 bits) to each read unit designated by the row decoder 63 and the column decoder 64. Write data to which an error correction bit is added is written in each read unit. Writing is performed simultaneously on all the reading units (16) corresponding to one row (one line simultaneous writing). During the read operation, data (32 bits) and error correction bits (6 bits) are read from the read unit designated by the row decoder 63 and the column decoder 64. As shown in FIG. 3, the error correction circuit 65 performs error correction processing on the read data (32 bits) using error correction bits. However, normally, there is a limit to the number of bits that can correct an error, and if an error occurs exceeding this limit, the correctness of the data after correction processing is not guaranteed. The error correction circuit 65 outputs L level error correction information when the data after error correction processing (32 bits) and the data before error correction processing (32 bits) match, and when they do not match, the error correction circuit 65 outputs an H level error correction information. Output error correction information. The H level error correction information indicates that an error has been detected in the read data. The L level error correction information indicates that no error has been detected in the read data.

<Diagnosis of nonvolatile semiconductor memory 60>
Next, the operation of the IC card shown in FIG. 1 will be described with reference to FIG.

  Before time t1, the IC card and the reader / writer are separated from each other, so that sufficient power is not supplied from the reader / writer to the IC card. At this time, the reset signal RST1 provided from the interface circuit 20 to the inspection circuit 30 remains at the L level. When the reset signal RST1 is at the L level, the inspection circuit 30 enters an operation stop state (reset state). Further, the reset signal RST2 applied to the CPU 40 and the selector 50 remains at the L level. When the reset signal RST2 is at L level, the CPU 40 enters an operation stop state (reset state).

  The IC card is brought close to the reader / writer, and the power supplied from the reader / writer to the IC card reaches a predetermined level at time t1. In response to this, the interface circuit 20 switches the reset signal RST1 from L level to H level. When the reset signal RST1 switches from the L level to the H level, the inspection circuit 30 starts diagnosis of the nonvolatile semiconductor memory 60. On the other hand, the reset signal RST2 remains at the L level, and the CPU 40 remains in the operation stop state (reset state). Hereinafter, the diagnostic operation of the nonvolatile semiconductor memory 60 by the inspection circuit 30 will be described with reference to FIG.

[Step ST501]
First, the control unit 31 of the inspection circuit 30 selects any one of the columns Y1 to Y16 of the memory cell array 61. As shown in FIG. 6A, column Y2 is selected here. Next, the control unit 31 instructs the address generation unit 33 to give an address designating a read unit corresponding to the column Y2 of each row X1-X16 of the memory cell array 61. Then, the process proceeds to step ST502.

[Step ST502]
As shown in FIG. 6B, in response to an instruction from the control unit 31, the address generation unit 33 sets an address 4 (hexadecimal number) that specifies a read unit corresponding to the row X1 and the column Y2 of the memory cell array 61. Output. The control unit 31 outputs a control signal that instructs reading. The control signal from the control unit 31 and the address 4 from the address generation unit 33 are given to the address decoder 62 of the nonvolatile semiconductor memory 60 via the selector 50. In response to this, the address decoder 61 gives a row address corresponding to the row X1 to the row decoder 63, and gives a column address corresponding to the column Y2 to the column decoder 64. In response to the row address from the address decoder 61, the row decoder 63 selects the row X1 of the memory cell 61. In response to the column address from the address decoder 61, the column decoder 64 selects the column Y2. Then, as shown in FIG. 6B, the data D (4) of the read unit corresponding to the row X1 and the column Y2 is read. Then, the process proceeds to step ST503.

[Step ST503]
The error correction circuit 65 performs error detection and error correction processing on the data D (4) read in step ST502. When no error is detected in the read data D (4), the error correction circuit 65 outputs L level error correction information. When an error is detected in the read data D (4), the error correction circuit 65 outputs H level error correction information. The control unit 31 determines whether the error correction information from the error correction circuit 65 is at the H level or the L level. When it is determined that the level is H, the process proceeds to step ST507, and when it is determined that the level is L, the process proceeds to step ST504. Here, it is assumed that no error is detected in the read data D (4). The error correction circuit 65 outputs L level error correction information to the control unit 31 of the inspection circuit 30 as shown in FIG. Then, the process proceeds to step ST504.

[Step ST504]
The address generation unit 33 adds 40 (hexadecimal number) to the previous address 4. The address 44 obtained as a result of the addition is an address that designates a read unit corresponding to the column Y2 of the next row X2 of the previous row X1 of the memory cell array 61, as shown in FIG. Then, the process proceeds to step ST505.

[Step ST505]
The control unit 31 determines whether or not the address obtained in step ST504 exceeds the final address (3FC in this case). When it is determined that it has exceeded, the process proceeds to step ST506, and when it is determined that it does not exceed, the process returns to step ST502. Here, since the address 44 obtained in step ST504 does not exceed the final address 3FC, the process returns to step ST502. In step ST502, the address generation unit 33 outputs an address 44 that specifies a read unit corresponding to the row X2 and the column Y2 of the memory cell 61. The control unit 31 outputs a control signal that instructs reading.

  Normally, writing to the nonvolatile semiconductor memory 60 is performed in units of rows. Therefore, if an error occurs during writing, there is a high possibility that an error has occurred in all the memory cells in row X1. Therefore, when no error is detected by the error correction circuit 65, that is, when the error correction information is at the L level, data is correctly written in all the memory cells in the row X1 corresponding to the read data D (4). Therefore, one read unit of data is read from the next row X2. Then, error detection and error correction processing is similarly performed on the read data D (44) from the read unit corresponding to the row X2 and the column Y2.

  Thereafter, the processes in steps ST502 to ST505 are repeated until it is determined that the error correction information is at the H level (reference A in FIGS. 5 and 6). That is, data in a read unit corresponding to the column Y2 is read from each row X2-X16 of the memory cell array 61, and error detection and error correction processing are performed.

  Here, as shown in FIG. 6B, an error is detected in the read data D (3C4) from the read unit corresponding to the row X16 and the column Y2, and error correction information of H level is output. Then, the process proceeds to step ST507.

[Step ST507]
The control unit 31 of the inspection circuit 30 includes the read data D (3C4) after the error correction processing from the read unit corresponding to the row X16 and the column Y2, the address 4 indicating the column Y2 corresponding to the read unit, and the read unit The data processing unit 32 is instructed to store the error correction information H corresponding to. In response to an instruction from the control unit 31, the data processing unit 32 stores them.

  The address generation unit 33 adds 4 to the previous address 3C4. As shown in FIG. 6A, the address 3C8 obtained as a result of the addition is read corresponding to the column Y3 next to the column Y2 corresponding to the read unit on the row X16 corresponding to the read unit where the error is detected. This is an address that specifies the unit. Then, the process proceeds to step ST508.

[Step ST508]
The address generator 33 outputs an address 3C8 that designates a read unit corresponding to the row X16 and the column Y3 of the memory cell array 61. The control unit 31 outputs a control signal that instructs reading. The control signal from the control unit 31 and the address 3C8 from the address generation unit 33 are given to the address decoder 62 of the nonvolatile semiconductor memory 60 via the selector 50. In response to this, the address decoder 61 gives a row address corresponding to the row X16 to the row decoder 63, and gives a column address corresponding to the column Y3 to the column decoder 64. In response to the row address from the address decoder 61, the row decoder 63 selects the row X16 of the memory cell 61. In response to the column address from the address decoder 61, the column decoder 64 selects the column Y3. Then, as shown in FIG. 6B, data D (3C8) of the read unit corresponding to the row X16 and the column Y3 is read. The error correction circuit 65 performs error detection and error correction processing on the read data D (3C8). Then, the process proceeds to step ST509.

[Step ST509]
The control unit 31 of the inspection circuit 30 includes the read data D (3C8) after error correction processing from the read unit corresponding to the row X16 and the column Y3, the address 8 indicating the column Y3 corresponding to the read unit, and the read unit The data processing unit 32 is instructed to store the error correction information corresponding to. In response to an instruction from the control unit 31, the data processing unit 32 stores them. Then, the process returns to step ST507. Thereafter, the processes in steps ST507 to ST509 are repeated 15 times (reference B in FIGS. 5 and 6). As a result, data D (3C0) -D (3FC) of all read units in the row X16 where the error is detected in step ST503 is read. As shown in FIG. 7, the read data D (3C0) -D (3FC) is associated with the addresses 0-3C indicating the corresponding columns Y1-Y16 and the corresponding error correction information to the data processing unit 32. Remembered.

[Step ST510]
The control unit 31 of the inspection circuit 30 determines whether all of the error correction information stored in the data processing unit 32 is at the H level. When all the error correction information is at the H level, the process proceeds to step ST517. In other cases, that is, when some error correction information is at the L level, the process proceeds to step ST511.

As described above, since writing to the nonvolatile semiconductor memory 60 is performed in units of rows, the errors detected by the error correction circuit 65 include the following types (a) and (b).
(A) An error that occurs only for some of the memory cells in the same row.
・ Recording data has changed due to defective data retention characteristics of the memory cell. ・ It is possible that previous data remained in the memory cell and could not be written correctly. Such an error can be repaired by writing the same data again. When a part of the error correction information stored in the data processing unit 32 is at the L level, it is determined that the error detected in step ST503 is an error as shown in (a). Further, regarding the data in which the error is detected, it is determined that the data has not been correctly read but has been corrected to the correct data by the error correction process. Then, the process proceeds to step ST511 to perform the repair process.
(B) An error that occurs for all memory cells in the same row.
-The desired data could not be recorded due to power-down during writing. In the IC card, it is possible that the IC card is pulled away from the reader / writer during the writing operation to the nonvolatile semiconductor memory. For this reason, an error like (b) may occur. When all of the error correction information stored in the data processing unit 32 is at the H level, it is determined that the error detected in step ST503 is an error as shown in (b). Further, it is determined that the data of the memory cell in the row corresponding to the data in which the error is detected is destroyed, that is, cannot be repaired. Then, the process proceeds to step ST517, and the diagnosis of the nonvolatile semiconductor memory 60 by the inspection circuit 30 is completed. As shown at time t2 in FIG. 4, the control unit 31 switches the reset signal RST2 from the L level to the H level and notifies the CPU 40 of the diagnosis result “abnormal”.

  Here, as shown in FIG. 7, since some error correction information is at L level, the process proceeds to step ST511.

[Step ST511]
The control unit 31 of the inspection circuit 30 instructs the data processing unit 32 and the address generation unit 33 to rewrite the data stored in the data processing unit 32. As shown in FIG. 8, the address generation unit 33 outputs the address 0 stored in the data processing unit 32. The data processing unit 32 outputs data D (3C0) associated with address 0. The control unit 31 outputs a control signal instructing data latching. The input / output buffer 66 of the nonvolatile semiconductor memory 60 temporarily stores (latches) the data D (3C0) from the data processing unit 32 in association with the column Y1 indicated by the address 0 from the address generating unit 32. Similarly, data D (3C4) -D (3FC) from the data processing unit 32 is latched in the input / output buffer 66 in association with the column Y2-Y16 indicated by the address 4-3C from the address generation unit 32. .

[Step ST512]
As shown in FIG. 8, the address generator 33 outputs an address indicating the row X16 of the memory cell array 61. Row X16 is a row corresponding to data D (3C4) in which an error is detected in step ST503.

[Step ST513]
The control unit 31 outputs a control signal instructing writing. Then, the data D (3C0) -D (3FC) latched in the input / output buffer 66 is written in the read unit corresponding to the row X16 and the columns Y1-Y16 (one line simultaneous writing).

[Step ST514]
When the rewriting is completed, the address generation unit 33 of the inspection circuit 30 outputs the address 3C4 (row X16, column Y2) that specifies the read unit in which the error is detected in step ST503, as shown in FIG.

[Step ST515]
The control unit 31 outputs a control signal that instructs reading. In response to this, data D (3C4) is read from the read unit corresponding to row X16 and column Y2 of memory cell array 61. The error correction circuit 65 performs error detection and error correction processing on the read data D (3C4).

[Step ST516]
The control unit 31 of the inspection circuit 30 determines whether the error correction information regarding the data read in step ST515 is at the H level or the L level. When it is at the H level, it is determined that the error has not been repaired by rewriting, and the process proceeds to step ST517. When it is at the L level, it is determined that the error has been repaired by rewriting, and the process returns to step ST504. Here, since the error correction information is at the L level as shown in FIG. 8, the process returns to step ST504. Then, in step ST505, it is determined that the final address has been exceeded, the process proceeds to step ST506, and the diagnosis of the nonvolatile semiconductor memory 60 by the inspection circuit 30 is completed. As shown at time t2 in FIG. 4, the control unit 31 switches the reset signal RST2 from the L level to the H level and notifies the CPU 40 of the diagnosis result “repaired”. If no error is detected in step ST503, the CPU 40 is notified of the diagnosis result “no abnormality”.

The inspection circuit 30 diagnoses the nonvolatile semiconductor memory 60 as described above. When the diagnosis is completed, the control unit 31 of the inspection circuit 30 switches the reset signal RST2 from the L level to the H level and notifies the CPU 40 of the diagnosis result. The diagnostic result notified to the CPU 40 includes
"No abnormality" (when no error is detected in step ST503)
・ "Repaired" (when an error is detected in step ST503 but can be repaired by rewriting)
“There is an abnormality” (when the error detected in step ST503 cannot be repaired, if an error is detected in the data of all read units in the row in which the error is detected in step ST503)
There are three types.

  As shown in FIG. 4, in response to the switching of the reset signal RST2 from the L level to the H level, the test circuit 30 enters an operation stop state and the CPU 40 enters an operation state. That is, the CPU 40 is activated. The CPU 40 determines the contents of the diagnosis result simultaneously with the operation start (activation), and changes the activation method according to the contents. For example, when the diagnosis result is “no abnormality” or “repaired”, it is normally activated. On the other hand, when the diagnosis result is “abnormal”, the activation is stopped, and the system abnormality status is transmitted to the outside via the interface circuit 20 and the antenna coil 10.

<Effect>
As described above, since the inspection circuit 30 is provided in the IC card according to the first embodiment, it is determined every time the IC card is used whether or not the nonvolatile semiconductor memory 60 is in a normal state. it can. As a result, it is possible to prevent a situation in which the IC card continues to be used while the nonvolatile semiconductor memory 60 is in a failed state. As a result, the IC card is used for a long time in a normal state.

  Further, in the diagnosis of the nonvolatile semiconductor memory 60 by the test circuit 30, one read unit data is read for each row X1-X16 of the memory cell array 61, and all read operations are performed on the row corresponding to the data in which the error is detected. Read unit data. Thereby, the time required for diagnosis of the nonvolatile semiconductor memory 60 can be shortened.

  In the case of an IC card in which a diagnostic program is stored in the ROM and the diagnostic program is read from the ROM and the nonvolatile semiconductor memory is diagnosed after the CPU is started, the nonvolatile semiconductor memory is analyzed by analyzing the operation of the CPU. Access procedures may be analyzed. However, in the IC card according to the first embodiment, the non-volatile semiconductor memory 60 is diagnosed by the inspection circuit 30 while the CPU 40 stops operating. Therefore, the access procedure to the nonvolatile semiconductor memory 60 is difficult to analyze. In addition, since the time required for diagnosis is short, it is difficult to analyze that the nonvolatile semiconductor memory 60 is being diagnosed.

  In addition, the inspection circuit 30 notifies the CPU 40 of the diagnosis result of the nonvolatile semiconductor memory 60. Thereby, CPU40 can recognize immediately after starting that the non-volatile semiconductor memory 60 is out of order. Therefore, when an abnormality is detected, troubles such as a system hang-up can be prevented by the CPU 40 performing appropriate processing.

  Although a non-contact type IC card has been described here, it may be a contact type IC card.

<Modification 1>
With respect to the error as described above (b), sufficient diagnosis can be performed by reading data of one read unit from each of the rows X1 to X16 of the memory cell array 61. However, in the case of an error as described above (a), data in a read unit other than the read unit in which the error exists may be read, so that sufficient diagnosis cannot be performed.

  Since it is considered that there are a number of process factors affecting the characteristic defects of the memory cells of the nonvolatile semiconductor memory 60, it is possible to statistically predict areas where the frequency of characteristic defects is high among the areas of the memory cell array 61. There is a case. In such a case, in step ST501, the control unit 31 of the inspection circuit 30 is in an area where the defect occurrence frequency is expected to be high in the columns Y1-Y16 of the memory cell array 61, as shown in FIG. Column Y16 is selected. Thereby, an efficient diagnosis can be performed for the error as described in (a) above.

<Modification 2>
It is difficult to predict in which region of the memory cell array 61 a characteristic failure caused by an accidental factor will occur. Therefore, in steps ST501 and ST504, as shown in FIG. 9B, addresses (0, 44, 88,..., 3B8, etc.) that specify read units corresponding to columns Y1-Y16 that differ for each row X1-X16. 3FC) is controlled so that the address generator 33 of the inspection circuit 30 is controlled. Thereby, it is possible to prevent the read unit read from each of the rows X1 to X16 from being biased to a specific region of the memory cell array 61. As a result, an efficient diagnosis can be performed for the error as described in (a) above.

<Modification 3>
Different columns Y1-Y16 may be selected by the control unit 31 of the inspection circuit 30 in step ST501 for each diagnosis operation. For example, as shown in FIG. 9C, the column Y1 in the first diagnostic operation, the column Y2,... In the first diagnostic operation, the column Y16 in step ST501 in the 16th diagnostic operation. To be selected. As a result, even if memory cells having defective characteristics are present at random, all of the defective characteristics can be detected during a certain number of diagnostic operations (here, 16 times).

(Second Embodiment)
<Configuration of IC card>
FIG. 10 is a block diagram showing the configuration of an IC card according to the second embodiment of the present invention. The IC card shown in FIG. 10 is a non-contact type IC card, and includes an antenna coil 10 and an LSI chip 100. The LSI chip 100 includes an interface circuit 20, a CPU 40, a nonvolatile semiconductor memory 60, a cache memory 110, and an access control unit 120.

  In this IC card, an address storage unit is provided in the memory cell array 61 of the nonvolatile semiconductor memory 60. Here, as shown in FIG. 11, an area corresponding to the row X16 of the memory cell array 61 is used as an address storage unit. When an address with a high frequency of write access to the nonvolatile semiconductor memory 60 can be assumed in advance (for example, when a program mounted on the IC card is known in advance), a memory tester or the like in the inspection process of the nonvolatile semiconductor memory 60 The address is written into the address storage unit. Here, as shown in FIG. 11, addresses 00, 80, and 2C0 are stored in the address storage unit. Addresses 00, 80, and 2C0 are addresses indicating the rows X1, X3, and X12 of the memory cell array 61. As described above, the address storage unit stores in advance addresses that are frequently accessed for writing to the nonvolatile semiconductor memory 60.

  When the write address to the nonvolatile semiconductor memory 60 matches any one of the addresses stored in the address storage unit, the access control unit 120 writes the write data corresponding to the write address to the cache memory 110.

<Operation of IC card>
Next, the operation of the IC card configured as described above will be described with reference to FIG.

[Step ST1201]
When the IC card is brought close to the reader / writer and the power supplied from the reader / writer to the IC card reaches a predetermined level, the interface circuit 20 switches the reset signal RST1 from the L level to the H level.

[Step ST1202]
When the reset signal RST1 is switched from the L level to the H level, the access control unit 120 reads the addresses 00, 80, 2C0 stored in the address storage unit in the memory cell array 61 of the nonvolatile semiconductor memory 60 and stores them in the cache memory 110. Write. As shown in FIG. 13A, an address storage area and a data storage area are provided for each slot number in the cache memory 110, and addresses 00, 80, and 2C0 are stored in the address numbers of slot numbers 1, 2, and 3, respectively. Stored in the area. As described above, the addresses 00, 80, and 2C0 are stored in the cache memory 110 in association with the slot numbers 1-3.

[Step ST1203]
Next, the access control unit 120 reads the data corresponding to the addresses 00, 80, and 2C0 written to the cache memory 110, that is, the data corresponding to the rows X1, X3, and X12 of the memory cell array 61 from the nonvolatile semiconductor memory 60. 110 is written. As shown in FIG. 13B, data corresponding to the addresses 00, 80, 2C0, that is, data D (0) -D (3C), D (80)-corresponding to the rows X1, X3, X12 of the memory cell array 61. D (BC), D (2C0) -D (2FC) are stored in the data storage areas of slot numbers 1, 2, and 3. Thus, in the cache memory 110, data D (0) -D (3C), D (80) -D (BC), D (2C0) -D (2FC) corresponding to addresses 00, 80, 2C0 are slots. Stored in association with numbers 1, 2, and 3.

[Step ST1204]
Next, the access control unit 120 switches the reset signal RST2 given to the CPU 40 from the L level to the H level. In response to the switching of the reset signal RST2 from the L level to the H level, the CPU 40 is activated and the application program mounted on the IC card is executed.

[Step ST1205]
The access control unit 120 determines whether there is a system end signal from the CPU 40. The system end signal is a control signal given from the CPU 40 to the access control unit 120 when a series of processing of the application program ends. When a system end signal is given from the CPU 40 to the access control unit 120, the process proceeds to step ST1211. Otherwise, the process proceeds to step ST1206.

[Step ST1206]
The access control unit 120 determines whether or not there is a write access from the CPU 40 to the nonvolatile semiconductor memory 60. If there is a write access, the process proceeds to step ST1207. Otherwise, the process returns to step ST1205.

[Step ST1207]
When a control signal / write address / write data for instructing writing to the nonvolatile semiconductor memory 60 is supplied from the CPU 40 to the access control unit 120, the access control unit 120 stores the write address from the CPU 40 and the cache memory 110. Compare the address. The access control unit 120 compares the write address from the CPU 40 and the address stored in the cache memory 110 ignoring the lower 4 bits. For example, when there is a write access instructing to write 32-bit data D (84w) to address 84 (row X3 and column Y2) of memory cell array 61, access controller 120 writes as shown in FIG. The value 8 in which the lower 4 bits of the address 84 are ignored is compared with the values 0, 8, and 2C in which the lower 4 bits of the addresses 00, 80, and 2C0 stored in the cache memory 110 are ignored.

[Step ST1208]
As a result of the comparison in step ST1207, when the write address from the CPU 40 matches any one of the addresses stored in the cache memory 110, the process proceeds to step ST1209. If the write address from the CPU 40 does not match any of the addresses stored in the cache memory 110, the process proceeds to step ST1210. For example, when there is a write access instructing to write data D (84w) to address 84 (row X3 and column Y2) of memory cell array 61, the value 8 which ignores the lower 4 bits of write address 84 and the cache memory Since the value 4 ignoring the lower 4 bits of the address 80 stored in 110 matches, the process proceeds to step ST1209.

[Step ST1209]
When the write address from the CPU 40 matches any one of the addresses stored in the cache memory 110, the access control unit 120 writes the write data into the cache memory 110. The access control unit 120 overwrites the data corresponding to the write address among the data stored in the cache memory 110 with the write data. For example, when there is a write access for instructing to write data D (84w) to address 84 (row X3 and column Y2) of memory cell array 61, it is stored in cache memory 110 as shown in FIG. The write data D (84w) is overwritten on the data corresponding to the write address 84, that is, the data D (84) corresponding to the row X3 and the column Y2 among the stored data. When the writing to the cache memory 110 is completed, the process returns to step ST1205.

[Step ST1210]
When the write address from the CPU 40 does not match any of the addresses stored in the cache memory 110, the access control unit 120 writes the write data into the nonvolatile semiconductor memory 60. Then, the process returns to step ST1205.

[Step ST1211]
When a series of processing of the application program ends, a system end signal is given from the CPU 40 to the access control unit 120 (ST1205). Upon receiving the system end signal, the access control unit 120 reads all the data stored in the cache memory 110 and writes it to the corresponding address of the memory cell array 61.

<Effect>
Usually, the nonvolatile semiconductor memory has an upper limit on the number of times of writing. When the number of times of writing approaches this upper limit, there is a high possibility that a failure such as a writing error will occur. In the IC card according to the second embodiment, an address storage unit is provided in the memory cell array 61 of the nonvolatile semiconductor memory 60, and an address having a high write access frequency is stored in the address storage unit in advance. When the write address to the nonvolatile semiconductor memory 60 matches one of the addresses stored in the address storage unit, the write data corresponding to the write address is written to the cache memory 110. Thereby, the number of times of writing to the nonvolatile semiconductor memory 60 can be reduced. As a result, the nonvolatile semiconductor memory 60 is used for a long time in a normal state.

  In general, cache memory resources are used to accurately extract addresses that are likely to hit the cache (for example, addresses that have been accessed recently or addresses that have been accessed many times) during program execution (address replacement mechanism). Is required in large quantities. In the IC card according to the second embodiment, an address storage unit is provided, and an address that is likely to hit the cache is stored in the address storage unit in advance. Therefore, the number of times of writing to the nonvolatile semiconductor memory 60 can be reduced with fewer resources than in the case where no address storage unit is provided.

  In addition, the capacity required for management can be reduced as compared with a technique for managing the number of writes for each row of the memory cell array of the nonvolatile semiconductor memory. For example, in the case of a non-volatile semiconductor memory having a capacity of 32 Kbytes (512 bits / 1 word line × 512 lines), in order to manage the number of times of writing up to about 60,000 times for each row, 16 bits for each word line, that is, 32 Kbytes Of this nonvolatile semiconductor memory, 1 Kbyte is consumed to manage the number of writes. On the other hand, in order to show 512 word lines, a 9-bit address is required, and even if 10 addresses are stored, the capacity required for the address storage unit is only 90 bits.

<Modification>
Here, an address storage unit is provided in the memory cell array 61 of the nonvolatile semiconductor memory 60. Instead of this, an address may be directly stored in a ROM (not shown) in the manufacturing process of the LSI chip 100, or an address storage unit may be built in the cache memory 110 in a circuit form.

  Here, the timing for writing the data stored in the cache memory 110 to the nonvolatile semiconductor memory 60 is after the end of the series of processing of the application program. Instead of this, the write access to the nonvolatile semiconductor memory 60 may be performed a predetermined number of times (for example, 10 times).

  Although the non-contact type IC card has been described here, it may be a contact type IC card.

(Third embodiment)
<Configuration and operation of IC card>
Some IC cards with a built-in nonvolatile semiconductor memory can download a desired application to the nonvolatile semiconductor memory, and some can mount a plurality of applications on the nonvolatile semiconductor memory. In such an IC card, the status of write access to the non-volatile semiconductor memory differs depending on the user and application used. The IC card according to the third embodiment is such that the address stored in the address storage unit in the IC card shown in FIG. 10 is dynamically changed according to the status of write access to the nonvolatile semiconductor memory 60. Features. The operation of the IC card according to the third embodiment will be described below with reference to FIG. Here, steps ST1509 to ST1513 different from the flowchart shown in FIG. 12 will be described.

[Step ST1509]
When the write address from the CPU 40 matches any one of the addresses stored in the cache memory 110, the access control unit 120 writes the write data to the cache memory 110. Specifically, the write data is overwritten on the data corresponding to the write address among the data stored in the cache memory 110. For example, data D (0) -D (3C), D (80) -D (BC), and D (2C0) -D (2FC) corresponding to addresses 00, 80, and 2C0 correspond to slot numbers 1, 2, and 3, respectively. When there is a write access instructing to write the data D (84w) to the address 84 (row X3 and column Y2) of the memory cell array 61, as shown in FIG. Of the data stored in the cache memory 110, the data corresponding to the write address 84, that is, the data D (84) corresponding to the row X3 and the column Y2 is overwritten with the write data D (84w).

  Next, the access control unit 120 changes the slot number in the cache memory 110. Specifically, the slot number of the slot in which the write data is written is set to 1, and the remaining slots are changed to 2, 3,. For example, when writing as shown in FIG. 16A is performed, the slot number corresponding to the address 80 and data D (80) -D (BC) is set to 1 as shown in FIG. 16B. The slot number corresponding to address 00 and data D (0) -D (3C) is changed to 2, and the slot number corresponding to address 2C0 and data D (2C0) -D (2FC) is changed to 3. By changing the slot number in this way, the smaller slot number is associated with the address that has been recently accessed for writing. When the slot number replacement is completed, the process returns to step ST1205.

[Step ST1510]
When the write address from the CPU 40 does not match any of the addresses stored in the cache memory 110, the access control unit 120 determines whether there is an empty slot in the cache memory 110. Here, an empty slot refers to a slot number that does not correspond to an address and data. If there is an empty slot in the cache memory 110, the process proceeds to step ST1511. If there is no empty slot, the process proceeds to step ST1512. For example, as shown in FIG. 17A, data D (0) -D (3C) and D (80) -D (BC) corresponding to addresses 00 and 80 are stored in association with slot numbers 1 and 2, respectively. If the slot number 3 is an empty slot and there is a write access instructing to write the data D (44w) to the address 44 (row X2 and column Y2) of the memory cell array 61, the access control unit 120 Determines that there is an empty slot in the cache memory 110 and proceeds to step ST1511.

[Step ST1511]
When there is an empty slot in the cache memory 110, the access control unit 120 reads all data (512 bits = 32 bits × 16 data) of the row corresponding to the write address from the nonvolatile semiconductor memory 60, and data in the empty slot Write to storage area. The access control unit 120 writes an address indicating a row corresponding to the write address in the address storage area of the empty slot. For example, when there is a write access instructing to write data D (44w) to address 44 (row X2 and column Y2) of memory cell array 61 in the situation shown in FIG. 17A, it is shown in FIG. 17B. As described above, all the data D (40) -D (7C) in the row X2 corresponding to the write address 44 is read from the nonvolatile semiconductor memory 60 and written in the data storage area of the slot number 3 (empty slot). Further, the address 40 indicating the row X2 corresponding to the write address 44 is written into the address storage area of the slot number 3 (empty slot).

  Next, the access control unit 120 writes the write data into the cache memory 110. Specifically, the write data is overwritten on the data corresponding to the write address among the data written in the empty slot. For example, in the situation shown in FIG. 17B, it corresponds to the write address 44 among the data D (40) -D (7C) written in the data storage area of slot number 3 as shown in FIG. 17C. The data to be written, that is, the data D (44) corresponding to the row X2 and the column Y2 is overwritten with the write data D (44w).

  Next, the access control unit 120 changes the slot number in the cache memory 110. As described above, the slot number is changed so that the smaller the slot number is associated with the address that has been recently accessed for writing. For example, when writing as shown in FIG. 17C is performed, the slot number corresponding to the address 40 and the data D (40) -D (7C) is set to 1 as shown in FIG. The slot number corresponding to address 00 and data D (0) -D (3C) is changed to 2, and the slot number corresponding to address 80 and data D (80) -D (BC) is changed to 3. When the slot number replacement is completed, the process returns to step ST1205.

[Step ST1512]
When there is no empty slot in the cache memory 110, the access control unit 120 reads all the data stored in the data storage area of the largest slot number in the cache memory 110, and reads the corresponding row of the nonvolatile semiconductor memory 60. Write to. For example, as shown in FIG. 18A, data D (0) -D (3C), D (80) -D (BC), D (2C0) -D (2FC) corresponding to addresses 00, 80, 2C0 are obtained. Consider a case where there is a write access instructing to write data D (44w) to address 44 (row X2 and column Y2) of memory cell array 61 in the case of being stored in association with slot numbers 1, 2, and 3. . At this time, the access control unit 120 reads the data D (2C0) -D (2FC) stored in the data storage area of the largest slot number 3 and writes it in the corresponding row X12 of the nonvolatile semiconductor memory 60.

  Next, the access control unit 120 reads all the data (512 bits = 32 bits × 16 data) in the row corresponding to the write address from the nonvolatile semiconductor memory 60 and writes it in the data storage area of the largest slot number. Further, the access control unit 120 writes the address indicating the row corresponding to the write address in the address storage area of the largest slot number. For example, in the situation shown in FIG. 18A, all the data D (40) -D (7C) in the row X2 corresponding to the write address 44 are transferred from the nonvolatile semiconductor memory 60 as shown in FIG. It is read and written to the data storage area of slot number 3 (the largest slot number). Further, the address 40 indicating the row X2 corresponding to the write address 44 is written into the address storage area of the slot number 3 (the largest slot number).

  Next, the access control unit 120 writes the write data into the cache memory 110. Specifically, the write data is overwritten on the data corresponding to the write address among the data written in the data storage area of the largest slot number. For example, in the situation shown in FIG. 18B, it corresponds to the write address 44 among the data D (40) -D (7C) written in the data storage area of slot number 3 as shown in FIG. 18C. The data to be written, that is, the data D (44) corresponding to the row X2 and the column Y2 is overwritten with the write data D (44w).

  Next, the access control unit 120 changes the slot number in the cache memory 110. As described above, the slot number is changed so that the smaller the slot number is associated with the address that has been recently accessed for writing. For example, when writing as shown in FIG. 18C is performed, the slot number corresponding to the address 40 and the data D (40) -D (7C) is set to 1 as shown in FIG. 18D. The slot number corresponding to address 00 and data D (0) -D (3C) is changed to 2, and the slot number corresponding to address 80 and data D (80) -D (BC) is changed to 3. When the slot number replacement is completed, the process returns to step ST1205.

[Step ST1513]
When a series of processing of the application program ends, a system end signal is given from the CPU 40 to the access control unit 120 (ST1205). Upon receiving the system end signal, the access control unit 120 reads all the data stored in the cache memory 110 and writes it to the corresponding address of the memory cell array 61 (ST1211). The access control unit 120 reads all addresses stored in the cache memory 110 and writes (rewrites) them to the address storage unit of the nonvolatile semiconductor memory 60. As a result, the contents of the address storage unit are updated to the address where the write access has been recently made. That is, the address that has been recently accessed for writing is always stored in the address storage unit. The updated address storage unit address is used in the next processing.

<Effect>
As described above, the IC card according to the third embodiment can dynamically change the address stored in the address storage unit (the address that is likely to hit the cache). Therefore, the number of times of writing to the nonvolatile semiconductor memory 60 can be reduced even when the status of write access to the nonvolatile semiconductor memory 60 differs depending on the user and the application to be used.

  In addition, since the address extracted by the address replacement mechanism of the cache memory 110 is stored in the address storage unit and used for the next processing, even in the case of a small resource such as an IC card, an address that hits frequently is accurately detected. Can be extracted.

  Here, a case has been described in which an address that has been recently accessed for writing is dynamically stored in the address storage unit. Instead of this, an address having a high write access frequency may be dynamically stored in the address storage unit.

  In addition, since the address storage unit is built in the nonvolatile semiconductor memory 60, if the address is rewritten frequently, the reliability of the nonvolatile semiconductor memory 60 may be reduced. Therefore, it is desirable to use it in a system in which an address with high write access frequency is relatively determined.

(Fourth embodiment)
<Configuration of IC card>
The overall configuration of the IC card according to the fourth embodiment of the present invention is the same as that of the IC card shown in FIG. However, in the IC card according to the fourth embodiment, as shown in FIG. 19A, the address storage unit in the memory cell array 61 of the nonvolatile semiconductor memory 60 includes a fixed address storage area and a dynamic address storage area. Here, an area corresponding to the row X15 of the memory cell array 61 is a fixed address storage area, and an area corresponding to the row X16 is a dynamic address storage area.

  Each application program mounted on the IC card includes a program part common to all applications and a program part different for each application. As for a program portion common to all applications, an address with a high write access frequency to the nonvolatile semiconductor memory 60 can be assumed in advance. Such an address is written in advance in a fixed address storage area of the address storage unit. On the other hand, with respect to program portions that differ for each application, the status of write access to the nonvolatile semiconductor memory 60 differs depending on the person who uses it and the application used. For such a part, the address (address that is likely to hit the cache) stored in the dynamic address storage area of the address storage unit is dynamically changed according to the status of write access to the nonvolatile semiconductor memory 60.

  Further, in the IC card according to the fourth embodiment, a fixed address area and a dynamic address area are provided in the cache memory 110 as shown in FIG. Here, the address storage area and data storage area of slot numbers 1-3 are fixed address areas, and the address storage area and data storage areas of slot numbers 4-5 are dynamic address areas.

<Operation of IC card>
Next, the operation of the IC card according to the fourth embodiment will be described with reference to FIG. Here, steps ST2002 and ST2009-ST2015 different from the flowchart shown in FIG. 12 will be described.

[Step ST2002]
The access control unit 120 reads the address stored in the fixed address storage area of the address storage unit of the nonvolatile semiconductor memory 60, writes the address in the fixed address area of the cache memory 110, and stores it in the dynamic address storage area of the address storage unit. The read address is read and written in the dynamic address area of the cache memory 110.

[Step ST2009]
When the write address from the CPU 40 matches one of the addresses stored in the cache memory 110, the access control unit 120 determines whether the address is an address stored in the fixed address area of the cache memory 110. to decide. If the address is stored in the fixed address area, the process proceeds to step ST2010. If not, that is, if the address is stored in the dynamic address area of the cache memory 110, the process proceeds to step ST2011.

[Step ST2010]
The access control unit 120 writes the write data to the fixed address area of the cache memory 110. Specifically, the write data is overwritten on the data corresponding to the write address among the data stored in the fixed address area of the cache memory 110. When the writing is completed, the process returns to step ST1205.

[Step ST2011]
The access control unit 120 writes the write data to the dynamic address area of the cache memory 110. Specifically, the write data is overwritten on the data corresponding to the write address among the data stored in the dynamic address area of the cache memory 110.

  Next, the access control unit 120 changes the slot number in the dynamic address area of the cache memory 110. Specifically, the slot number of the slot in which the write data is written is changed to the smallest slot number in the dynamic address area, and the remaining slots are the second smallest in the dynamic address area in ascending order of the slot numbers. Change the slot number to the third smallest slot number. By changing the slot number in this way, in the dynamic address area, the slot number which is smaller as the address has recently been accessed for writing is associated. When the slot number replacement is completed, the process returns to step ST1205.

[Step ST2012]
When the write address from the CPU 40 does not match any of the addresses stored in the cache memory 110, the access control unit 120 determines whether there is an empty slot in the dynamic address area of the cache memory 110. When there is an empty slot in the dynamic address area of the cache memory 110, the process proceeds to step ST2013, and when there is no empty slot, the process proceeds to step ST2014.

[Step ST2013]
When there is an empty slot in the dynamic address area of the cache memory 110, the access control unit 120 reads all data (512 bits = 32 bits × 16 data) of the row corresponding to the write address from the nonvolatile semiconductor memory 60, Write to empty slot data storage area. The access control unit 120 writes an address indicating a row corresponding to the write address in the address storage area of the empty slot.

  Next, the access control unit 120 writes the write data into the cache memory 110. Specifically, the write data is overwritten on the data corresponding to the write address among the data written in the empty slot.

  Next, the access control unit 120 changes the slot number in the dynamic address area of the cache memory 110. As described above, the slot number is changed so that the smaller the slot number is associated with the address that has been recently accessed for writing. When the slot number replacement is completed, the process returns to step ST1205.

[Step ST2014]
When there is no empty slot in the dynamic address area of the cache memory 110, the access control unit 120 reads all the data stored in the data storage area of the largest slot number in the dynamic address area of the cache memory 110, Write to the corresponding row of the nonvolatile semiconductor memory 60.

  Next, the access control unit 120 reads all data (512 bits = 32 bits × 16 data) of the row corresponding to the write address from the nonvolatile semiconductor memory 60, and the largest slot in the dynamic address area of the cache memory 110 Write to the number data storage area. Further, the access control unit 120 writes an address indicating a line corresponding to the write address in the address storage area of the largest slot number in the dynamic address area of the cache memory 110.

  Next, the access control unit 120 writes the write data into the cache memory 110. Specifically, the write data is overwritten on the data corresponding to the write address among the data written in the data storage area having the largest slot number in the dynamic address area.

  Next, the access control unit 120 changes the slot number in the dynamic address area of the cache memory 110. As described above, the slot number is changed so that the smaller the slot number is associated with the address that has been recently accessed for writing. When the slot number replacement is completed, the process returns to step ST1205.

[Step ST2015]
When a series of processing of the application program ends, a system end signal is given from the CPU 40 to the access control unit 120 (ST1205). Upon receiving the system end signal, the access control unit 120 reads all the data stored in the cache memory 110 and writes it to the corresponding address of the memory cell array 61 (ST1211). Further, the access control unit 120 reads all addresses stored in the dynamic address area of the cache memory 110 and writes (rewrites) them in the dynamic address storage area of the address storage unit of the nonvolatile semiconductor memory 60. As a result, the contents of the dynamic address storage area of the address storage unit are updated to the address where the write access has been recently made. That is, the address that has recently been accessed for writing is always stored in the dynamic address storage area of the address storage unit. The updated address of the dynamic address storage area is used in the next processing.

<Example of processing flow>
The flow of processing when the route indicated by the thick line shown in FIG. 21 is passed is shown in FIGS. The flowchart shown in FIG. 21 is the same as the flowchart shown in FIG. Here, it is assumed that addresses 00, 80, and 2C0 are stored in advance in the fixed address storage area of the address storage unit, and 100 and 40 are stored in the dynamic address storage area.

(1) (ST2002)
The address stored in the address storage unit is read and written to the cache memory 110. At this time, addresses 00, 80, and 2C0 stored in the fixed address storage area are written into the fixed address area of the cache memory 110, and addresses 100 and 40 stored in the dynamic address storage area are stored in the cache memory 110. Written to the target address area.

(2) (ST1203)
Data in the row corresponding to the addresses 00, 80, 2C0, 100, and 40 written in the cache memory 110 is read from the nonvolatile semiconductor memory 60 and written into the cache memory 110.

(3) (ST1207)
A write access “write data 12345678 at address 44!” Occurs. The access control unit 120 compares the write address 44 with the address stored in the cache memory 110. Here, the lower 4 bits are ignored for comparison. Therefore, the address 40 stored in the dynamic address area of the cache memory 110 matches the write address 44.

(4) (ST2011)
Write data 12345678 is written into the cache memory 110.

(5) (ST2011)
The slot number of the dynamic address area is changed. The slot number of the slot in which data is written is changed to 4 (the smallest slot number in the dynamic address area), and the slot number of the slot corresponding to the address 100 is changed to 5.

(6) (ST1211)
Data stored in the cache memory 110 is read and written into the nonvolatile semiconductor memory 60.

(7) (ST2015)
The address stored in the cache memory 110 is written into the address storage unit. Addresses 00, 80, and 2C0 stored in the fixed address area are written to the fixed address storage area of the address storage unit, and addresses 40 and 100 stored in the dynamic address area are dynamic address storage areas of the address storage unit. Is remembered.

It is a block diagram which shows the structure of the IC card by 1st Embodiment of this invention. FIG. 2 is a block diagram showing an internal configuration of the nonvolatile semiconductor memory shown in FIG. 1. FIG. 3 is a diagram for explaining error detection and error correction processing by the error correction circuit shown in FIG. 2. 4 is a timing chart for explaining the operation of the IC card shown in FIG. 1. It is a flowchart which shows the diagnostic procedure of a non-volatile semiconductor memory. (A) is a figure which shows the reading order of the data in the diagnosis of a non-volatile memory. (B) is a timing chart for explaining the diagnostic operation of the nonvolatile memory. It is a figure which shows an example of the address data error correction information memorize | stored in the data processing part of a test | inspection circuit. It is a timing chart for explaining restoration operation. (A)-(c) is a figure which shows the reading order of the data in the modification of the 1st Embodiment of this invention. It is a block diagram which shows the structure of the IC card by 2nd Embodiment of this invention. It is a figure which shows the memory cell array of the non-volatile semiconductor memory shown in FIG. It is a flowchart for demonstrating operation | movement of the IC card shown in FIG. (A)-(c) is a figure which shows the correspondence of the address and data which are stored in a cache memory. It is a figure which shows an example of a comparison with a write address and the address memorize | stored in the cache memory. It is a flowchart for demonstrating operation | movement of the IC card by 3rd Embodiment of this invention. (A)-(b) is a figure which shows the correspondence of the address and data which are stored in a cache memory. (A)-(d) is a figure which shows the correspondence of the address and data which are stored in a cache memory. (A)-(d) is a figure which shows the correspondence of the address and data which are stored in a cache memory. (A) is a figure which shows the fixed address storage area and dynamic address storage area of an address storage part. (B) is a diagram showing a fixed address area and a dynamic address area in the cache memory. It is a flowchart for demonstrating operation | movement of the IC card by 4th Embodiment of this invention. It is a figure for demonstrating an example of the flow of a process. It is a figure for demonstrating an example of the flow of a process. It is a figure for demonstrating an example of the flow of a process. It is a figure for demonstrating an example of the flow of a process.

Explanation of symbols

1,100 LSI chip (semiconductor integrated circuit device)
30 inspection circuit 40 CPU
60 Nonvolatile semiconductor memory 110 Cache memory 120 Access control unit.

Claims (11)

Non-volatile semiconductor memory;
An inspection circuit for diagnosing the nonvolatile semiconductor memory,
The nonvolatile semiconductor memory is
A memory cell array divided into a plurality of read units in rows and columns;
An error correction circuit that performs error correction encoding of data to be written to each of the plurality of read units, and performs error detection and error correction of data read from each of the plurality of read units,
The inspection circuit includes:
Providing the nonvolatile semiconductor memory with a first instruction for instructing to read data in one read unit from each row of the memory cell array;
When an error in data read in accordance with the first instruction is detected by the error correction circuit, a second instruction is issued to read out data in all read units in a row corresponding to the data in which the error is detected. Is given to the nonvolatile semiconductor memory. The semiconductor integrated circuit device according to claim 1,
The inspection circuit includes:
When there is data in which no error is detected by the error correction circuit among the data read according to the second instruction, an error is detected by the error correction circuit among data read according to the second instruction. 3. A semiconductor integrated circuit device, wherein a third instruction for instructing to rewrite the written data is given to the nonvolatile semiconductor memory. The semiconductor integrated circuit device according to claim 1,
The inspection circuit includes:
A semiconductor integrated circuit device, wherein an error signal is output when an error is detected by the error correction circuit in all of the data read in accordance with the second instruction. The semiconductor integrated circuit device according to claim 1,
The inspection circuit includes:
2. The semiconductor integrated circuit device according to claim 1, wherein the first instruction is given so as to read out data in a reading unit in an area of the memory cell array which is expected to have a high defect occurrence frequency. The semiconductor integrated circuit device according to claim 1,
The inspection circuit includes:
The semiconductor integrated circuit device according to claim 1, wherein the first instruction is given so as to read data in a reading unit corresponding to a different column for each row. The semiconductor integrated circuit device according to claim 1,
The inspection circuit includes:
Giving the first instruction to read data in a reading unit corresponding to one column of the memory cell array;
The semiconductor integrated circuit device according to claim 1, wherein the one column is different every time the first instruction is given. The semiconductor integrated circuit device according to claim 1,
A CPU,
The inspection circuit includes:
A semiconductor integrated circuit device, wherein after the diagnosis of the nonvolatile semiconductor memory is completed, a signal for starting the CPU is given to the CPU. The semiconductor integrated circuit device according to claim 7,
The inspection circuit includes:
A semiconductor integrated circuit device, wherein an error signal is given to the CPU when an error is detected by the error correction circuit in all of the data read in accordance with the second instruction. The semiconductor integrated circuit device according to claim 8.
The CPU
A semiconductor integrated circuit characterized in that the activation is stopped in response to a signal indicating an abnormality from the inspection circuit. An IC card comprising the semiconductor integrated circuit device according to any one of claims 1 to 9. An inspection device for diagnosing nonvolatile semiconductor memory,
The nonvolatile semiconductor memory is
A memory cell array divided into a plurality of read units in rows and columns;
An error correction circuit that performs error correction encoding of data to be written to each of the plurality of read units, and performs error detection and error correction of data read from each of the plurality of read units,
The inspection device includes:
Providing the nonvolatile semiconductor memory with a first instruction for instructing to read data in one read unit from each row of the memory cell array;
When an error in data read in accordance with the first instruction is detected by the error correction circuit, a second instruction is issued to read out data in all read units in a row corresponding to the data in which the error is detected. Is given to the nonvolatile semiconductor memory.

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