JP2008066378A - Semiconductor device, and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To actualize a semiconductor device including a full-silicide gate electrode having a stable work function value and a threshold value. <P>SOLUTION: The semiconductor device is provided with a gate insulating film 15a formed on a semiconductor substrate and a gate electrode 23 formed on the gate insulating film. The gate electrode 23 is a full silicide gate electrode including a metal silicide film formed by laminating a plurality of crystal grain layers. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a MOS type semiconductor device having a gate electrode made of a metal silicide film and a manufacturing method thereof.

With the recent progress in technology for higher integration and higher speed in semiconductor devices, metal oxide field effect transistors (MOSFETs) are being miniaturized. If the gate insulating film made of silicon oxide (SiO ₂ ), silicon oxynitride (SiON), or the like, which has been conventionally used for miniaturization of the MOSFET, is thinned, the gate leakage current increases due to the tunnel current. Becomes apparent. Therefore, in order to further reduce the thickness, it is necessary to take measures such as changing the material of the gate electrode from polysilicon to a metal electrode to prevent a decrease in capacity due to electrode depletion.

On the other hand, as a material for the gate insulating film, replacement with a high dielectric material made of a metal oxide such as hafnium oxide (HfO ₂ ) or zirconium oxide (ZrO ₂ ) instead of SiO ₂ or SiON has been studied. By using a metal oxide for the gate insulating film, an effect of increasing the physical film thickness while realizing a thin equivalent film thickness of the silicon oxide film, that is, reducing the leakage current can be expected.

  However, when metal oxide is used as the gate insulating film, the absolute value of the threshold voltage when the transistor is operated due to the reaction at the upper interface of the gate insulating film, that is, the interface between the gate insulating film and the polysilicon gate electrode. The problem arises that becomes large.

  Although the cause is not clear, in the transistor manufacturing process, it is suspected that the gate electrode material reacts with the gate insulating film material because the substrate is exposed to a high temperature process of about 1000 ° C.

The reaction between the gate electrode material and the gate insulating film material causes a phenomenon called Fermi level pinning in which the effective work function of the gate electrode material changes. For example, Non-Patent Document 1 discloses that when polysilicon is used as the gate electrode material, the effective work function value of polysilicon does not depend on the type of polysilicon dopant, but the silicon midgap (bandgap energy). It has been reported that it is fixed slightly closer to n ⁺ polysilicon than the intermediate value). Thereby, in particular, the absolute value of the threshold voltage of the p-type MOSFET is considerably increased.

Therefore, in the case of a high dielectric gate insulating film, in addition to the electrode depletion suppression effect expected in the SiO ₂ gate insulating film, an optimum work function can be selected using a metal electrode, and the threshold voltage can be controlled. is needed.

  A full silicide gate electrode has been proposed as one of the metal electrodes. The full silicide electrode is formed by depositing a metal directly on the polysilicon film deposited on the gate insulating film and silicidizing the entire polysilicon layer by heat treatment (see, for example, Patent Document 1). . According to this process, a gate electrode made of polysilicon is first formed, and then a silicide process of the gate electrode is performed. For this reason, as compared with the dual metal gate electrode, which needs to make two kinds of metal materials separately for nMOS and pMOS, it can be manufactured relatively easily because it uses a manufacturing process that follows the conventional process.

Therefore, in order to prevent a decrease in capacitance due to electrode depletion in the conventional SiO ₂ or SiON gate insulating film and to avoid an increase in threshold voltage of the p-type MOSFET due to Fermi level pinning in the high dielectric gate insulating film, It is expected to use electrodes.
C. Hobbs, L. Fonseca, V. Dhandapani, S. Samavedam, B. Taylor, J. Grant, L. Dip, D. Triyoso, R. Hegde, D. Gilmer, R. Garcia, D. Roan, L. Lovejoy, R. Rai, L. Hebert, H. Tseng, B. White, and P. Tobin, “Fermi level pinning at the polySi / metal oxide interface”, Proceedings of the 2003 Symposium on VLSI Technology, 2003, p. 9-10 JP 2005-228868 A

  However, the conventional full silicide gate electrode has a problem in that the control of the full silicidation reaction is insufficient and the work function and threshold value of the gate electrode fluctuate.

  When forming a full silicide gate electrode, a polysilicon film is deposited on the gate insulating film, a metal is deposited on the gate insulating film, and then the polysilicon film is completely silicided to a position just above the gate insulating film by heat treatment. (Full silicide). The work function of the full silicide gate electrode is the physical properties such as the type of metal used for silicidation, the composition ratio between metal and silicon, the crystal orientation of the material, the film thickness, and the distribution of dopants contained in the polysilicon film before silicidation. Depends on specific nature. These physical characteristics change in a complicated manner depending on the thickness of the deposited polysilicon, the thickness of the metal film, the ratio between the polysilicon film and the metal film, the heat treatment temperature, the heat treatment time, and the like.

  For example, when a full silicide gate electrode for an n-type MOSFET that requires a relatively small work function is formed of nickel silicide, the composition ratio of nickel and silicon is one to one or less in order to keep the work function small. It is desirable to make it smaller. However, nickel that contributes to the silicidation reaction is not only supplied from directly above the gate, but also supplied by surface diffusion from a portion deposited on a portion other than directly above the gate. For this reason, the composition ratio of nickel silicide depends not only on the film thickness ratio between the polysilicon film and the nickel film but also on the gate length of the MOSFET. That is, as the gate length is narrower, the amount of nickel supplied from a portion other than the portion directly above the gate increases, so that nickel tends to be excessive.

  When the composition ratio of nickel silicide varies, the work function varies. The variation in work function causes variation in threshold voltage in, for example, a MOSFET.

  On the other hand, the formed silicide layer is composed of crystal grains (grains) of various sizes. These non-uniform grain sizes also cause variations in the work function and hence the threshold because the distribution varies with respect to the gate length and gate width.

  An object of the present invention is to solve the above-mentioned conventional problems and to realize a semiconductor device having a full silicide gate electrode with a stable work function value and threshold value.

  In order to achieve the above object, according to the present invention, a semiconductor device is provided with a full silicide gate electrode formed of a silicide layer having large crystal grains.

  Specifically, a semiconductor device according to the present invention includes a gate insulating film formed on a semiconductor substrate and a gate electrode formed on the gate insulating film, and the gate electrode includes a plurality of layered crystal grains. It is a full silicide gate electrode having a metal silicide film formed by laminating.

  According to the semiconductor device of the present invention, since the gate electrode has the metal silicide film formed by laminating a plurality of layered crystal grains, the crystal grain boundary is reduced, and in particular, the crystal grain boundary in contact with the gate insulating film. Almost disappears. Therefore, the influence of the crystal grain size and orientation on the work function value and the threshold voltage can be reduced, and a semiconductor device having excellent characteristics can be realized. In addition, the occurrence of leakage current due to the crystal grain boundary can be suppressed.

  In the semiconductor element of the present invention, the metal silicide film preferably has a crystal grain size in a region on the gate insulating film side larger than a crystal grain size in a region on the side opposite to the gate insulating film. In the metal silicide film, the number of crystal grain boundaries in the region on the gate insulating film side may be smaller than the number of crystal grain boundaries in the region on the opposite side to the gate insulating film. With such a configuration, the number of crystal grain boundaries in contact with the gate insulating film can be surely reduced.

  In the semiconductor device of the present invention, the metal silicide film is preferably made of at least one nitride of nickel, cobalt, titanium, platinum, ruthenium, iridium, yttrium, and a transition metal.

  In the semiconductor device of the present invention, the metal silicide film has an excess of silicon in the region on the gate insulating film side, and the composition ratio of the metal in the region on the gate insulating film side is the composition of the metal in the region on the opposite side to the gate insulating film. The ratio is preferably smaller than the ratio. With such a configuration, the value of the work function can be reduced, so that the threshold value of the nMOS transistor can be kept low.

  In the semiconductor device of the present invention, the gate insulating film is preferably a metal oxide film. In this case, the metal oxide film is preferably made of at least one oxide of hafnium, zirconium, titanium, tantalum, aluminum, silicon, lanthanum, and rare earth elements.

  The first semiconductor device manufacturing method according to the present invention includes a step (a) of sequentially forming a gate insulating film forming film and a silicon electrode forming film on a semiconductor substrate, and a gate insulating film forming film and a silicon electrode forming film. A step (b) of forming a plurality of gate insulating films and a plurality of silicon electrodes by patterning; a step (c) of implanting at least one of nitrogen and oxygen into at least one of the plurality of silicon electrodes; After step (c), a step (d) of forming a metal film on each silicon electrode, and reacting each silicon electrode with the metal film to silicidate each silicon electrode, thereby forming a full silicide gate electrode. And a step (e) of forming.

  According to the first method for manufacturing a semiconductor device, since the method includes the step of ion-implanting at least one of nitrogen and oxygen into at least one of the plurality of silicon electrodes, the metal diffusion is suppressed and the silicidation reaction is performed. It is possible to proceed slowly. Therefore, since the size of the crystal grains can be increased and aligned, the threshold value can be made less susceptible to the influence of the crystal grains. In addition, since the crystal grain boundary can be reduced, leakage current can be reduced. Furthermore, since it becomes difficult for the metal to diffuse downward, a full silicide gate electrode having a small work function can be formed, so that the threshold value of the n-type MOS transistor can be further reduced. Also, variations in electrical characteristics can be reduced for both the n-type MOS transistor and the p-type MOS transistor.

  The first semiconductor device manufacturing method further includes a step (f) of forming a sidewall on each side surface of each silicon electrode after the step (b) and before the step (c). Is preferred.

  In the first method for manufacturing a semiconductor device, a step (g) of forming a hard mask film on the silicon electrode formation film after the step (a) and before the step (b), and a step (f) ) And before the step (c), the step (h) of forming the source / drain regions in both sides of the silicon electrode in the semiconductor substrate, and the step (h) after the step (h) Step (i) of siliciding the upper portion of the source / drain region before c), and step (j) of removing the hard mask film after step (i) and before step (c) It is preferable to further comprise.

  According to the second method for manufacturing a semiconductor device of the present invention, after forming a gate insulating film forming film on a semiconductor substrate, the first silicon film, the silicidation suppressing film, and the gate insulating film forming film are formed. A step (a) of forming a silicon electrode forming film by laminating a second silicon film; and a step of forming a plurality of gate insulating films and a plurality of silicon electrodes by patterning the gate insulating film forming film and the silicon electrode forming film. (B), after step (b), step (c) of forming a metal film on each silicon electrode, and reacting each silicon electrode with the metal film to silicidate each silicon electrode. And a step (d) of forming a full silicide gate electrode, wherein the silicidation suppression film is made of silicon oxide, silicon nitride, or silicon oxynitride.

  According to the second method for manufacturing a semiconductor device, the method includes the step of forming a gate electrode formation film by laminating at least the first silicon film, the silicidation suppression film, and the second silicon film. It is possible to suppress metal diffusion during full silicidation. Therefore, since a metal silicide film having large crystal grains and few crystal grain boundaries can be formed, the threshold value can be stabilized and the occurrence of leakage current can be suppressed. In addition, since a metal silicide film containing excess silicon can be formed in the lower portion, the work function of the full silicide gate electrode can be reduced and the threshold value can be further reduced.

  In the second method for manufacturing a semiconductor device, it is preferable that at least one of the first silicon film and the second silicon film has an amorphous phase.

  In the second method for fabricating a semiconductor device, in the step (a), the silicidation suppression film is preferably formed by subjecting the first silicon film to wet oxidation treatment, dry oxidation treatment, or dry oxynitridation treatment.

  In the second method for manufacturing a semiconductor device, the semiconductor substrate has an n-type transistor formation region and a p-type transistor formation region, and is after the step (b) and before the step (c). It is preferable to further include a step of removing the second silicon film and the silicidation suppression film in the silicon electrode formed in the p-type transistor formation region. With such a configuration, the gate electrode of the p-type transistor can be a full silicide gate electrode with excess metal.

  According to the semiconductor device and the manufacturing method thereof according to the present invention, a semiconductor device having a full silicide gate electrode with a stable work function value and threshold value can be realized.

(First embodiment)
A first embodiment of the present invention will be described with reference to the drawings. The semiconductor device according to this embodiment includes an nMOS transistor and a pMOS transistor having a full silicide gate electrode formed on a substrate.

  1 and 2 show the semiconductor device manufacturing method according to the first embodiment in the order of steps. First, as shown in FIG. 1A, for example, an element isolation film 12 made of shallow trench isolation (STI) is selected on a substrate 11 made of silicon whose principal surface has a (100) plane orientation. Form.

  Subsequently, ion implantation is performed on the substrate 11 to form a plurality of n-type transistor formation regions 13A and p-type transistor formation regions 13B on the substrate 11, respectively. The n-type transistor formation region 13A has a p-type well, and the p-type transistor formation region 13B has an n-type well.

  Subsequently, the substrate 11 is sequentially subjected to known RCA cleaning and diluted hydrofluoric acid cleaning, and then heat treatment is performed in an oxidizing atmosphere at a temperature of about 600 ° C. to 1000 ° C. Thus, the base film 14 made of silicon oxide is formed on the n-type transistor formation region 13A and the p-type transistor formation region 13B of the substrate 11. The base film 14 preferably has a film thickness of 1.0 nm or less. Further, the base film 14 may be a chemical silicon oxide film formed by a wet process.

Subsequently, a metal oxide film 15 made of a high dielectric material having a film thickness of 2 nm is formed on the base film 14 by using, for example, metal organic chemical vapor deposition (MOCVD). For example, when forming a metal oxide film made of hafnium silicate (HfSiO ₄ ), the following is performed. A source gas generated by bubbling by bubbling a carrier gas composed of nitrogen or the like into a mixed solution of Hf (Ot-C ₃ H ₇ ) ₄ and Si (Ot-C ₃ H ₇ ) ₄ is used. And introduced into the reactor together with the carrier gas. The inside of the reaction furnace is set to a temperature of about 500 ° C., and a metal oxide film 15 made of hafnium silicate is deposited. At this time, the concentration of Hf with respect to Si is adjusted by the supply amount of Hf (Ot-C ₃ H ₇ ) ₄ and Si (Ot-C ₃ H ₇ ) ₄ .

  Thereafter, in order to remove residual impurities such as carbon or hydrogen, heat treatment at about 700 ° C. to 1000 ° C. is performed. The heating atmosphere at this time is preferably nitrogen containing a small amount of oxygen so that the film thicknesses of the metal oxide film 15 and the base film 14 do not change greatly. Thereafter, nitriding treatment is performed to prevent the metal oxide film 15 from crystallizing in the heat treatment for activating ions in the source / drain regions. For example, heat treatment is performed at a temperature of 800 ° C. for 1 minute in an ammonia atmosphere. Further, the heat treatment may be performed in a nitrogen atmosphere excited by plasma.

  Note that a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like may be used instead of the metal oxide film made of a high dielectric material.

  Thereafter, a gate electrode forming film 16 made of silicon having a thickness of about 100 nm is deposited on the metal oxide film 15 by CVD. The gate electrode formation film 16 may be doped. The gate electrode formation film 16 is preferably amorphous. In the case of amorphous silicon, the silicide reaction can be suppressed more than in the case of crystallized silicon. Further, a hard mask forming film 17 made of a silicon oxide film is deposited. Subsequently, a resist mask 28 having a gate pattern is formed on the hard mask forming film 17 by lithography.

  Next, as shown in FIG. 1B, the hard mask formation film 17 to the base film 14 are sequentially patterned by dry etching using, for example, chlorine gas as an etchant. As a result, a laminated pattern 18 is formed which includes the silicon electrode 16a formed on the substrate 11 and the hard mask 17a covering the upper surface of the silicon electrode 16a via the base film 14a and the gate insulating film 15a.

  Next, as shown in FIG. 1C, ion implantation is performed on the substrate 11 using the laminated pattern 18 as a mask. Subsequently, sidewalls 19 made of a silicon nitride film are formed on both side surfaces of the laminated pattern 18. Further, ion implantation is performed again on the substrate 11 using the sidewalls 19 and the laminated pattern 18 as masks, thereby forming source / drain regions 20. Subsequently, heat treatment is performed at a temperature of 1000 ° C. or higher to electrically activate the implanted impurities.

  Next, after depositing metallic nickel (not shown) on the substrate 11, heat treatment is performed at a temperature of 300 ° C. or higher. Thereby, a metal silicide source / drain 21 is formed on the source / drain region 20. At this time, the hard mask 17a functions as a protective insulating film that protects the silicon electrode 16a from being silicided. Next, unreacted metallic nickel is removed with a mixed solution of sulfuric acid and hydrogen peroxide solution, and a heat treatment for controlling the crystal phase is performed.

  Next, as shown in FIG. 1D, an interlayer film 22 made of a silicon oxide film is deposited until the hard mask 17a is sufficiently covered. Subsequently, the interlayer film 22 is polished using a chemical mechanical polishing (CMP) method so as not to reach the hard mask 17a. Thereafter, the hard mask 17a and a part of the interlayer film 22 are removed by dry etching to expose the silicon electrode 16a.

Next, as shown in FIG. 2A, the p-type transistor formation region 13B is covered with a resist mask 29, and only the n-type transistor formation region 13A is doped with nitrogen by an ion implantation method. Thus, the silicon electrode 16a formed in the n-type transistor formation region 13A is used as a silicon electrode 16b doped with impurities. The ion implantation energy may be between 5 keV and 30 keV. The implantation dose may be between 1 × 10 ¹⁴ cm ^{−2 and} 1 × 10 ¹⁶ cm ⁻² . Further, oxygen may be doped instead of nitrogen.

  Next, as shown in FIG. 2B, after removing the resist mask 29, a resist is applied again, and a resist mask 30 exposing the p-type transistor formation region 13B is formed by photolithography. Thereafter, the silicon electrode 16a formed in the p-type transistor formation region 13B is etched by dry etching until the film thickness becomes 30 nm to 50 nm, thereby forming a thinned silicon electrode 16c.

Further, a resist is applied again, and a resist mask 30 exposing the p-type transistor formation region 13B is formed again by photolithography, and nitrogen is doped only into the thinned silicon electrode 16c by an ion implantation method. Thus, the silicon electrode 16c formed in the p-type transistor formation region 13B is used as a silicon electrode 16d doped with impurities. The ion implantation energy is preferably 5 keV or less. This is because, since the silicon electrode 16c is thinned, nitrogen penetrates into the substrate when the implantation energy is excessively high. The implantation dose may be between 1 × 10 ¹⁴ cm ^{−2 and} 1 × 10 ¹⁶ cm ⁻² . Further, oxygen may be doped instead of nitrogen. In this embodiment, nitrogen is ion-implanted for both n-type and p-type, but only one of n-type and p-type may be used.

  Next, as shown in FIG. 2C, after depositing metallic nickel (not shown) on the substrate 11, heat treatment is performed at a temperature of 300 ° C. or higher. As a result, the silicon electrode 16b and the silicon electrode 16d react with the metallic nickel and are silicided. At this time, since the doped nitrogen is bonded to the silicon of the silicon electrode, the silicidation reaction proceeds more slowly than when nitrogen is not doped. As a result, a silicide having a larger grain size and an energetically stable crystal structure with less grain boundary is grown. At the same time, since the diffusion of nickel is inhibited, a full silicide gate electrode 23 made of a metal silicide film having a small work function value is formed on the silicon electrode of the nMOSFET. On the other hand, in the thin silicon electrode 16c of the pMOSFET, in addition to the silicide grain control, the thickness of the silicon is small, so the ratio of nickel to silicon is high, the nickel is excessive and the work function value is large. A full silicide gate electrode 24 made of a film is formed.

  Subsequently, unreacted metallic nickel is removed with a mixed solution of sulfuric acid and hydrogen peroxide solution, and a heat treatment for controlling the crystal phase is performed. Then, although not shown, a wiring process or the like is performed.

  In the method for manufacturing a semiconductor device according to the present embodiment, before the gate electrode is fully silicided, a process for suppressing silicidation is performed by implanting impurity ions into the silicon film. As a result, the silicidation reaction rate is reduced, and a metal silicide film having large crystal grains can be obtained.

  FIG. 5 shows a result of observing a cross section of the full silicide gate electrode 23 of the nMOSFET according to the present embodiment with a secondary electron scanning electron microscope. Although the crystal grains (grains) identified in FIG. 5 are indicated by dotted lines, large grains are formed in the full silicide gate electrode 23 of the present embodiment. In particular, the grain size is larger on the gate insulating film side (lower side) of the metal silicide film than on the upper side, and the layered grains are stacked. For this reason, the number of crystal grain boundaries (grain boundaries) is small, and there is almost no grain boundary in contact with the gate insulating film.

  On the other hand, FIG. 7 shows a result of observing a cross section of a full silicide gate electrode of a conventional nMOSFET not subjected to silicidation suppression treatment with a secondary electron scanning electron microscope. As shown in FIG. 7, in the conventional full silicide gate electrode, small grains are irregularly arranged, a large number of grain boundaries are formed, and there are many grain boundaries in contact with the gate insulating film.

  When the grain size in the full silicide gate electrode is small and many grain boundaries are generated, the work function value and the threshold voltage are affected, and at the same time, the leakage current increases. In particular, when the gate length and the gate width are shortened, there is a case where the volume of the full silicide gate electrode included in one transistor is smaller than one grain. In this case, since it is more strongly affected by the crystallinity (orientation) of the grains, when a plurality of transistors are formed on the substrate, there is a possibility that the threshold voltages of the respective transistors may have completely different values. . Further, the variation in grain size results in variation in the resistance value of the gate electrode.

  However, since the semiconductor device of this embodiment has a large grain size and a small number of grain boundaries, it is less likely to cause such a problem and a transistor with excellent electrical characteristics can be obtained. When a plurality of transistors are formed on the top, characteristics of each transistor can be made uniform.

  In addition, since the silicidation of the full silicide gate electrode 23 of the nMOS transistor of this embodiment is suppressed, silicon is excessive with respect to nickel in the lower region of the nickel silicide layer. Therefore, the value of the work function in the region in contact with the gate insulating film can be reduced, and an nMOS transistor having a low threshold voltage can be obtained.

  On the other hand, in the pMOSFET transistor, silicidation is performed after the thickness of the silicon film is reduced, so that the full silicide gate electrode 24 having a large work function and a large amount of metal can be formed. In order to make the full silicidation karate of the pMOS transistor more metal-rich, it is preferable to increase the heat treatment temperature for silicidation. Even if the silicidation heat treatment is performed at a high temperature and the processing time is increased, the silicidation of the nMOSFET is suppressed, so that the full silicide gate electrode of the nMOSFET does not become excessive in metal. Accordingly, even in this case, the value of the work function can be kept low, and an nMOSFET having a low threshold voltage can be obtained. The grain size and crystal orientation can be controlled also in a pMOSFET transistor, and can be performed by changing the implantation energy and dose of ions implanted into the gate electrode. However, since the silicon film thickness of the pMOSFET is thin, it is necessary to set it to low energy and low dose.

(Second Embodiment)
The second embodiment of the present invention will be described below with reference to the drawings. 3 and 4 show the semiconductor device manufacturing method according to the second embodiment in the order of steps.

  First, as shown in FIG. 3A, for example, an element isolation film 12 made of shallow trench isolation (STI) is selected on a substrate 11 made of silicon whose principal surface has a (100) plane orientation. Form.

  Subsequently, ion implantation is performed on the substrate 11 to form a plurality of n-type transistor formation regions and p-type transistor formation regions on the substrate 11. The n-type transistor formation region has a p-type well 13A, and the p-type transistor formation region has an n-type well 13B.

  Subsequently, the substrate 11 is sequentially subjected to known RCA cleaning and diluted hydrofluoric acid cleaning, and then heat treatment is performed in an oxidizing atmosphere at a temperature of about 600 ° C. to 1000 ° C. As a result, the base film 14 made of silicon oxide is formed on the transistor formation region of the substrate 11. The base film 14 preferably has a film thickness of 1.0 nm or less. Further, the base film 14 may be a chemical silicon oxide film formed by a wet process.

Subsequently, a metal oxide film 15 made of a high dielectric material having a film thickness of 2 nm is formed on the base film 14 by using, for example, metal organic chemical vapor deposition (MOCVD). For example, when forming a metal film made of hafnium silicate, the following is performed. A source gas generated by bubbling by bubbling a carrier gas composed of nitrogen or the like into a mixed solution of Hf (Ot-C ₃ H ₇ ) ₄ and Si (Ot-C ₃ H ₇ ) ₄ is used. And introduced into the reactor together with the carrier gas. The inside of the reaction furnace is set to a temperature of about 500 ° C., and a metal oxide film 15 made of hafnium silicate is deposited. At this time, the concentration of Hf with respect to Si is adjusted by the supply amount of Hf (Ot-C ₃ H ₇ ) ₄ and Si (Ot-C ₃ H ₇ ) ₄ .

  Thereafter, in order to remove residual impurities such as carbon or hydrogen, heat treatment at about 700 ° C. to 1000 ° C. is performed. The heating atmosphere at this time is preferably nitrogen containing a small amount of oxygen so that the film thicknesses of the metal oxide film 15 and the base film 14 do not change greatly. Thereafter, nitriding treatment is performed to prevent the metal oxide film 15 from crystallizing in the heat treatment for activating ions in the source / drain regions. For example, heat treatment is performed at a temperature of 800 ° C. for 1 minute in an ammonia atmosphere. Further, the heat treatment may be performed in a nitrogen atmosphere excited by plasma.

  Note that a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like may be used instead of the metal oxide film made of a high dielectric material.

  Thereafter, a silicon electrode formation film 41 is formed on the metal oxide film 15. The silicon electrode formation film 41 includes a first silicon film 42, a silicon oxide film 43, and a second silicon film 44 that are sequentially stacked as follows.

  Subsequently, a first silicon film 42 having a thickness of about 50 nm is deposited on the metal oxide film 15 by a CVD method. The first silicon film 42 may be doped. The first silicon film 42 is desirably amorphous.

  Next, a silicon oxide film 43 is formed on the surface of the first silicon film 42 by immersing the substrate 11 in a mixed aqueous solution (APM) of ammonia and hydrogen peroxide. The film thickness of the silicon oxide film 43 is desirably 1.0 nm or less. If the film thickness is 1.0 nm or less, silicidation is not completely stopped. Note that ozone water may be used in place of the APM liquid. Alternatively, it may be formed by dry oxidation. Further, silicon nitride, silicon oxynitride, or the like may be used instead of silicon oxide.

  Thereafter, a second silicon film 44 having a thickness of about 50 nm is deposited on the silicon oxide film 43. The second silicon film 44 may be doped. The second silicon film 44 is preferably amorphous. Amorphous silicon can suppress silicidation more than crystallized silicon.

  Subsequently, a hard mask forming film 17 made of a silicon oxide film is deposited on the silicon electrode forming film 41. Subsequently, a resist mask 28 having a gate pattern is formed on the hard mask forming film 17 by lithography.

  Next, as shown in FIG. 3B, the hard mask formation film 17 to the base film 14 are sequentially patterned by dry etching using, for example, chlorine gas as an etchant. Thus, the silicon electrode 41a formed of the patterned first silicon film 42a, silicon oxide film 42a, and second silicon film 43a formed on the base film 14a and the gate insulating film 15a, and the upper surface of the silicon electrode 41a. A laminated pattern 18 is formed which is composed of a hard mask 17a covering the substrate.

  Next, as shown in FIG. 3C, ion implantation is performed on the substrate 11 using the laminated pattern 18 as a mask. Subsequently, sidewalls 19 made of a silicon nitride film are formed on both side surfaces of the laminated pattern 18. Further, ion implantation is performed again on the substrate 11 using the sidewalls 19 and the laminated pattern 18 as masks, thereby forming source / drain regions 20. Subsequently, heat treatment is performed at a temperature of 1000 ° C. or higher to electrically activate the implanted impurities.

  Next, after depositing metallic nickel (not shown) on the substrate 11, heat treatment is performed at a temperature of 300 ° C. or higher. Thereby, a metal silicide source / drain 21 is formed on the source / drain region 20. At this time, since the silicon electrode 41a is covered with the hard mask 17a, it does not react with metallic nickel. Next, unreacted metallic nickel is removed with a mixed solution of sulfuric acid and hydrogen peroxide solution, and a heat treatment for controlling the crystal phase is performed.

  Next, as shown in FIG. 4A, an interlayer film 22 made of a silicon oxide film is deposited until the hard mask 17a is sufficiently covered. Subsequently, the interlayer film 22 is polished using a chemical mechanical polishing (CMP) method so as not to reach the hard mask 17a. Thereafter, the hard mask 17a and a part of the interlayer film 22 are removed by dry etching to expose the silicon electrode 41a.

  Next, as shown in FIG. 4B, a resist is applied, and a resist mask 31 that exposes the p-type transistor formation region 13B is formed by photolithography. Thereafter, by dry etching, the silicon electrode 41a formed in the p-type transistor formation region 13B is etched until the film thickness becomes 30 nm to 50 nm to form a thinned silicon electrode 41b. Specifically, the second silicon film 44a and the silicon oxide film 43a are removed, leaving only the first silicon film 42a.

  Next, as shown in FIG. 4C, after depositing metallic nickel (not shown) on the substrate 11, heat treatment is performed at a temperature of 300 ° C. or higher. As a result, the silicon electrode 41a and the silicon electrode 41b react with the metallic nickel and are fully silicided. However, in the gate electrode 41a, silicidation is inhibited by the influence of the silicon oxide film 43a, and the silicidation reaction proceeds slowly. As a result, the full silicide gate electrode 23 having an excessive silicon and a small work function value is formed. On the other hand, in the thinned gate electrode 41b, since the film thickness of silicon is thin, the ratio of nickel to silicon is high, and the full silicide gate electrode 24 having a large work function value due to excessive nickel is formed.

  Subsequently, unreacted metallic nickel is removed with a mixed solution of sulfuric acid and hydrogen peroxide solution, and a heat treatment for controlling the crystal phase is performed. Thereafter, although not shown, a wiring process or the like is performed.

  In the semiconductor device manufacturing method of this embodiment, a process for suppressing silicidation is performed by inserting thin silicon oxide that suppresses silicidation reaction between stacked silicon films. As a result, the reaction rate of silicidation is reduced, and a silicide film having large crystal grains can be obtained.

  FIG. 6 shows a result of observing a cross section of the full silicide gate electrode 23 of the nMOSFET according to this embodiment with a secondary electron scanning electron microscope. As shown in FIG. 6, the full silicide gate electrode of this embodiment is formed so that the grain size is large and layered grains are laminated. For this reason, the number of grain boundaries is small, and almost no grain boundary in contact with the gate insulating film is recognized.

  In the present embodiment, the grain size and crystal orientation can be controlled by changing the film thickness ratio between the first silicon film 41 and the second silicon film 43. Further, the thickness of the electrode of the p-type MOS transistor is determined by the thickness of the first silicon electrode formation film. Therefore, the variation in the film thickness of the electrode can be reduced as compared with the case where the silicon film is thinned by etching.

  As described above, the semiconductor device and the manufacturing method thereof according to the first embodiment and the second embodiment control the grain size, grain orientation, silicide composition, film thickness, and the like in the full silicide gate electrode. Can do. By suppressing the silicide reaction, excessive metal supply accompanying surface diffusion can be restricted, so that variations in work function and threshold voltage can be reduced.

  When the n-type MOS transistor and the p-type MOS transistor are formed on the substrate, if the silicidation reaction is suppressed for the n-type MOS transistor and silicidation is performed simultaneously with the p-type MOS transistor, the n-type transistor is fully formed. Since the silicide gate electrode has an excess of silicon and the full silicide gate electrode of the p-type MOS transistor has an excess of nickel, a full silicide electrode having an optimum work function can be realized. As a result, a semiconductor device with a low threshold voltage can be realized.

 The semiconductor device and the manufacturing method thereof according to the present invention can realize a semiconductor device having a full silicide gate electrode with a stable work function value and threshold value, and a MOS type semiconductor device having a gate electrode made of a metal silicide film and its manufacture. This is useful as a method.

It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention in process order. 4 is an electron micrograph showing a cross section of a full silicide gate electrode of an nMOS transistor in the semiconductor device according to the first embodiment of the present invention. It is an electron micrograph which shows the cross section of the full silicide gate electrode of the nMOS transistor in the semiconductor device which concerns on the 2nd Embodiment of this invention. It is an electron micrograph which shows the cross section of the full silicide gate electrode of the nMOS transistor in the conventional semiconductor device. It is a cross-sectional image of a pole.

Explanation of symbols

11 Substrate 12 Element isolation film 13A n-type transistor formation region 13B p-type transistor formation region 14 base film 14a patterned base film 15 metal oxide film 15a gate insulating film 16 gate electrode formation film 16a silicon electrode 16b silicon electrode 16c silicon electrode 16d Silicon electrode 17 Hard mask formation film 17a Hard mask 18 Stack pattern 19 Side wall 20 Source / drain region 21 Metal silicide source / drain 22 Interlayer film 23 Full silicide gate electrode 24 Full silicide gate electrode 28 Resist mask 29 Resist mask 30 Resist mask 31 Resist mask 41 Gate electrode formation film 41a Silicon electrode 41b Silicon electrode 42 First silicon film 42a First silicon film 43 Silicon oxide film 43a Silicon oxide Film 44 second silicon film 44a second silicon film

Claims (14)

A gate insulating film formed on the semiconductor substrate;
A gate electrode formed on the gate insulating film,
The semiconductor device, wherein the gate electrode is a full silicide gate electrode having a metal silicide film in which a plurality of layered crystal grains are stacked.   2. The semiconductor element according to claim 1, wherein the metal silicide film has a crystal grain size in a region on the gate insulating film side larger than a crystal grain size in a region opposite to the gate insulating film. .   2. The metal silicide film according to claim 1, wherein the number of crystal grain boundaries in the region on the gate insulating film side is smaller than the number of crystal grain boundaries in the region on the opposite side to the gate insulating film. Semiconductor element.   4. The metal silicide film according to claim 1, wherein the metal silicide film is made of at least one nitride of nickel, cobalt, titanium, platinum, ruthenium, iridium, yttrium, and a transition metal. 5. Semiconductor device.   In the metal silicide film, silicon in the region on the gate insulating film side is excessive, and the metal composition ratio in the region on the gate insulating film side is higher than the metal composition ratio in the region on the opposite side to the gate insulating film. The semiconductor device according to claim 1, wherein the semiconductor device is small.   4. The semiconductor device according to claim 1, wherein the gate insulating film is a metal oxide film. 5.   The semiconductor device according to claim 6, wherein the metal oxide film is made of at least one oxide of hafnium, zirconium, titanium, tantalum, aluminum, silicon, lanthanum, and rare earth elements. A step (a) of sequentially forming a gate insulating film formation film and a silicon electrode formation film on the semiconductor substrate;
(B) forming a plurality of gate insulating films and a plurality of silicon electrodes by patterning the gate insulating film forming film and the silicon electrode forming film;
A step (c) of implanting at least one of nitrogen and oxygen into at least one of the plurality of silicon electrodes;
A step (d) of forming a metal film on each silicon electrode after the step (c);
A step (e) of forming a full silicide gate electrode by reacting each silicon electrode with the metal film to silicide each silicon electrode. .   9. The method according to claim 8, further comprising a step (f) of forming a sidewall on each side surface of each silicon electrode after the step (b) and before the step (c). The manufacturing method of the semiconductor device as described in any one of Claims 1-3. A step (g) of forming a hard mask film on the silicon electrode forming film after the step (a) and before the step (b);
A step (h) of forming source / drain regions in both sides of the silicon electrode in the semiconductor substrate after the step (f) and before the step (c);
A step (i) of siliciding the upper portion of the source / drain region after the step (h) and before the step (c);
9. The semiconductor device according to claim 8, further comprising a step (j) of removing the hard mask film after the step (i) and before the step (c). Manufacturing method. After forming a gate insulating film forming film on the semiconductor substrate, a first silicon film, a silicidation suppressing film, and a second silicon film are stacked on the formed gate insulating film forming film to form a silicon electrode forming film Forming step (a);
(B) forming a plurality of gate insulating films and a plurality of silicon electrodes by patterning the gate insulating film forming film and the silicon electrode forming film;
A step (c) of forming a metal film on each of the silicon electrodes after the step (b);
A step (d) of forming a full silicide gate electrode by reacting each of the silicon electrodes with the metal film to silicide the silicon electrode;
The method of manufacturing a semiconductor device, wherein the silicidation suppression film is made of silicon oxide, silicon nitride, or silicon oxynitride.   12. The method of manufacturing a semiconductor device according to claim 11, wherein at least one of the first silicon film and the second silicon film has an amorphous phase.   12. The semiconductor according to claim 11, wherein, in the step (a), the silicidation suppression film is formed by subjecting the first silicon film to wet oxidation treatment, dry oxidation treatment, or dry oxynitridation treatment. Device manufacturing method. The semiconductor substrate has an n-type transistor formation region and a p-type transistor formation region,
The step of removing the second silicon film and the silicidation suppression film in the silicon electrode formed in the formation region of the p-type transistor after the step (b) and before the step (c). The method of manufacturing a semiconductor device according to claim 11, further comprising: