JP2008060594A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To actualize an excellent process stability even elements are fine sized, and to prevent the increase of resistance in a region formed a silicide. <P>SOLUTION: The method includes a step of forming a silicon region defined by an insulation film in a substrate main surface, a step of forming a silicon oxide film on the surface of the silicon region, a step of forming a mixed film including a first metal and a second metal on the substrate formed the silicon oxide film, a step of allowing the reduction of the silicon oxide film formed in the silicon region by the second metal by heat treatment, and a step of forming a silicide film only on the surface of the silicon region by allowing the reaction between the first metal and the silicon in the silicon region by heat treatment, wherein the first metal is Co, Ni, Pt or Pd, and the second metal is Ti, Zr, Hf, V, Nb, Ta or Cr. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a fine MIS transistor having a short gate length.

  In order to cope with an increase in parasitic resistance due to the recent miniaturization of devices, a salicide (hereinafter referred to as silicide) in which metal silicide (hereinafter referred to as silicide) is bonded in a self-aligned manner on the polysilicon gate electrode and the source / drain diffusion layer of the MOSFET. SALICIDE: Self ALIgned siliCIDE) process is becoming widely used.

  An example of a salicide process using titanium, which has been widely used in the past, will be described with reference to FIGS.

  First, an isolation insulating film (silicon oxide film) region 102 is formed on a silicon substrate 101, a MOSFET gate oxide film 103, a polycrystalline silicon gate electrode 104, and a shallow source / drain diffusion layer 105 are formed. A deep source / drain diffusion layer 107 is formed using the sidewall film 106 using a silicon nitride film as a mask (FIG. 3A).

  Next, after the dilute hydrofluoric acid treatment or the dilute hydrofluoric acid treatment, a RCA treatment or the like is performed to deposit a titanium film 108 and a titanium nitride film 109 on the entire surface (FIG. 3B).

Next, annealing is performed for a short time at a temperature of about 650 to 750 ° C. using a lamp annealing apparatus or the like, and the exposed silicon substrate 101 and polycrystalline silicon film 104 are reacted with the titanium film 108 to form a titanium die having a C49 crystal structure. A silicide (TiSi ₂ ) film 110 is formed. Thereafter, the titanium nitride film 109 and the unreacted titanium film 108 are removed by etching using an etching solution such as a mixed solution of sulfuric acid and hydrogen peroxide solution (FIG. 3C).

Next, annealing is performed for a short time at a temperature of about 750 to 900 ° C. using a lamp annealing apparatus or the like, and the titanium disilicide (TiSi ₂ ) film 110 is changed to a low resistance titanium disilicide (TiSi ₂ ) film 111 having a C54 crystal structure. It is changed (FIG. 3 (d)).

  Next, silicon oxide films 112 and 113 are deposited on the entire surface by a low pressure CVD method and a plasma CVD method, and planarized by a CMP process or the like (FIG. 3E).

  Next, contact holes are formed in the silicon oxide films 112 and 113, and a metal 114 such as tungsten is embedded in the contact holes. Thereafter, the wiring layer 115 such as aluminum is connected to the source / drain diffusion layer and the gate electrode (FIG. 3F).

Such a salicide process using titanium has the effect of greatly reducing the parasitic resistance of the source / drain diffusion layers and the gate polycrystalline silicon region. However, when the device is further miniaturized and the gate length is reduced to 0.2 μm or less, the crystal structure of the TiSi ₂ film is not changed to C54 even by the second lamp annealing, so that the resistance does not decrease. Since the effect is generated, the merit applied to the semiconductor element is reduced.

  Therefore, in recent years, a salicide process using a cobalt silicide film, which is less likely to cause a fine line effect than titanium silicide, has attracted attention.

  An example of a salicide process using cobalt will be described with reference to FIGS.

  After removing the native oxide film on the surface of the silicon substrate 101 and the surface of the polycrystalline silicon film 104 by dilute hydrofluoric acid treatment for the MOSFET element in the state of FIG. 3A, a cobalt film 116 and a titanium nitride film 109 are formed on the entire surface. Deposits (FIG. 4A).

  Next, annealing is performed for a short time at a temperature of about 450 to 550 ° C. using a lamp annealing apparatus or the like, and the exposed silicon substrate 101 and polycrystalline silicon film 104 are reacted with the cobalt film 116 to obtain cobalt monosilicide (CoSi). A film 117 is formed. Subsequently, the titanium nitride film 109 and the unreacted cobalt film 116 are removed by etching using an etching solution such as a mixed solution of sulfuric acid and hydrogen peroxide (FIG. 4B).

Next, annealing is performed for a short time at a temperature of about 700 to 850 ° C. by using a lamp annealing apparatus or the like to change the cobalt monosilicide (CoSi) film 117 into a low-resistance cobalt disilicide (CoSi ₂ ) film 118 (FIG. 4 (c)).

  Next, silicon oxide films 112 and 113 are deposited on the entire surface by a low pressure CVD method and a plasma CVD method, and planarized by a CMP process or the like. Subsequently, a contact hole is formed in the silicon oxide films 112 and 113, a metal 114 such as tungsten is embedded in the contact hole, and a wiring layer 115 such as aluminum is connected to the source / drain diffusion layer and the gate electrode (see FIG. FIG. 4 (d)).

  Such a salicide process using a cobalt silicide film has the advantage that the thin line effect is less likely to occur than the salicide process using a titanium silicide film, but also has the following drawbacks.

  That is, when cobalt is deposited, there is a natural oxide film generated after RCA treatment on the surface of the silicon substrate or the polycrystalline silicon film because cobalt has a poor ability to reduce the silicon oxide film compared to titanium. Hinders the silicide reaction. Therefore, the cobalt monosilicide (CoSi) film 117 as shown in FIG. 4B may not be formed at all. Also, even when trying to deposit a cobalt film in a state where the natural oxide film is removed by pretreatment using dilute hydrofluoric acid, if a non-uniform natural oxide film is formed due to factors such as the elapsed time after the pretreatment, As shown in FIG. 5, there is a problem that the deposition of the cobalt monosilicide (CoSi) film 117 becomes non-uniform. In addition, when only dilute hydrofluoric acid-based treatment is used as a pretreatment, a silicon-based material called a watermark or water glass is formed on the exposed silicon substrate surface or polycrystalline silicon film surface, particularly near the interface with the element isolation insulating film. In some cases, an oxide film adheres and inhibits the silicidation reaction.

Further, since the cobalt silicide film is inferior to the titanium silicide film from the viewpoint of heat resistance, the cobalt disilicide is formed by heat at the time of depositing the silicon oxide film for the interlayer film after the completion of the salicide process as shown in FIG. The (CoSi ₂ ) film 118 agglomerates, which causes a problem of increasing the resistance.

  On the other hand, in the cobalt salicide process, various problems occur in the amorphous silicon-aluminum replacement process for reducing the resistance of the contact plug.

  This problem will be described with reference to FIGS.

  Interlayer insulating films 112 and 113 are deposited on the structure in which the cobalt silicide film 118 shown in FIG. After forming contact holes in the interlayer insulating films 112 and 113, an amorphous silicon film 119 is deposited and etched back to leave the amorphous silicon film 119 only inside the contact holes. Subsequently, an aluminum film 120 and a titanium film 121 are deposited on the entire surface (FIG. 7A).

  Next, the amorphous silicon 119, the aluminum 120, and the titanium 121 are reacted by a heat process of 600 ° C. or lower, so that the amorphous silicon 119 inside the contact hole is replaced with the aluminum 122. Thereafter, the aluminum 120 and titanium 121 remaining outside the contact hole and the silicon 119 sucked out by the substitution reaction are polished and removed by a CMP process or the like (FIG. 7B).

  Next, a wiring metal 124 such as aluminum is deposited on the entire surface and patterned to connect the semiconductor element portion and the wiring layer (FIG. 7C).

  When the contact portion is formed by such a process, an aluminum spike 123 enters the cobalt silicide 118 in a thermal process for replacing amorphous silicon and aluminum, and in some cases, reaches the diffusion layer. When such an aluminum spike occurs, it causes deterioration of bonding characteristics.

  In order to prevent the occurrence of such aluminum spikes, a technique of previously depositing a titanium nitride film effective as a diffusion barrier inside the contact hole is also used. A process for depositing the titanium nitride film in advance will be described with reference to FIGS.

  First, interlayer insulating films 112 and 113 are deposited on the structure to which the cobalt silicide film 118 shown in FIG. 4C is attached, and contact holes are formed. Thereafter, a titanium nitride film 125 and an amorphous silicon film 119 are sequentially deposited and etched back to leave the amorphous silicon film 119 only inside the contact hole. Subsequently, an aluminum film 120 and a titanium film 121 are deposited on the entire surface (FIG. 8A).

  Next, the amorphous silicon 119, the aluminum 120, and the titanium 121 are reacted by a heat process of 600 ° C. or lower to replace the amorphous silicon 119 inside the contact hole with the aluminum 122, and then the aluminum 120 remaining outside the contact hole by a CMP process or the like. The titanium 121, the silicon 119 sucked out by the substitution reaction, and the titanium nitride film 125 are removed (FIG. 8B).

  Next, a wiring metal 124 such as aluminum is deposited on the entire surface and patterned to connect the semiconductor element portion and the wiring layer (FIG. 8C).

  By using such a process, aluminum spikes do not enter the silicide layer and the diffusion layer below it, but on the other hand, the number of titanium nitride film formation processes is increased, and titanium having higher resistance than aluminum is formed. There is a problem that the resistance increases due to the contact hole being narrowed by the nitride film.

  As described above, in the conventional salicide process using titanium, there is a problem that when the gate length is 0.2 μm or less, the resistance is not sufficiently lowered due to the thin line effect. Further, in the salicide process using cobalt, there are problems that the silicide reaction is hindered by the natural oxide film and that the silicide is aggregated by the thermal process during the deposition of the interlayer film. Further, the salicide process using cobalt has a problem that an aluminum spike enters the cobalt silicide in the amorphous silicon-aluminum replacement process for reducing the resistance of the contact plug. In order to prevent the occurrence of such aluminum spikes, it may be possible to deposit a titanium nitride film or the like as a diffusion barrier in advance in the contact hole. However, an increase in the number of titanium nitride film formation processes, There arises a problem of an increase in resistance due to the contact hole being narrowed.

  The present invention has been made to solve the above-mentioned conventional problems, and even if the element is miniaturized, a method of manufacturing a semiconductor device that can suppress an increase in resistance in a region where silicide is formed and has excellent process stability. The purpose is to provide.

  In the semiconductor device according to the present invention, a silicide film mainly composed of the first metal and silicon is formed only on the surface of the silicon region divided by the insulating film on the main surface side of the substrate, and the surface of the silicide film or the silicide film A nitride film mainly composed of a second metal and nitrogen is formed on the surface and the crystal grain boundary.

  As the silicon region, a silicon region constituting a gate electrode of a MIS transistor (a region formed of polycrystalline silicon) and a silicon constituting a source / drain diffusion layer (a region formed on a single crystal silicon substrate) of the MIS transistor. At least one of the areas is raised.

  Examples of the first metal include Co, Ni, Pt, and Pd, and examples of the second metal include Ti, Zr, Hf, V, Nb, Ta, and Cr. Examples of the insulating film include an element isolation insulating film and a gate sidewall insulating film. Further, the nitride film may contain silicon in addition to the second metal and nitrogen.

  According to the invention, it is possible to sufficiently reduce the parasitic resistance in the gate portion or the source / drain portion even if the MIS transistor is miniaturized. Further, when a metal or the like is embedded in the opening on the gate electrode or the source / drain diffusion layer, if the nitride film is selectively formed only on the surface of the silicide film or only on the surface of the silicide film and the crystal grain boundary, Compared with the case where a nitride film is also formed on the side wall of the opening, an increase in resistance due to the narrowing of the opening can be suppressed.

  The method of manufacturing a semiconductor device according to the present invention includes a step of forming a silicon region partitioned by an insulating film on the substrate main surface side, and a first metal and a second metal on the substrate on which the silicon region is formed. Forming a mixed film; reacting the first metal and the second metal with silicon in the silicon region by heat treatment to form a first silicide film only on the surface of the silicon region; and By heat-treating the first silicide film in a nitriding atmosphere, the second silicide film and the surface of the second silicide film or the surface of the second silicide film and the crystal grain boundary are exposed to the second metal and nitrogen. And a step of forming a nitride film as a main component.

  According to the invention, it is possible to reduce a natural oxide film or the like on the silicon region by the second metal, and a good silicide film can be formed on the silicon region. Further, by forming a nitride film mainly composed of the second metal and nitrogen on the surface of the second silicide film or the like, it is possible to prevent a problem that the thermal stability of the silicide film is lowered. Therefore, even if the MIS transistor is miniaturized, it is possible to reduce the parasitic resistance in the gate portion or the source / drain portion with high process stability.

  The method for manufacturing a semiconductor device according to the present invention includes a step of forming a silicon region partitioned by an insulating film on the substrate main surface side, a step of forming a silicon oxide film on the surface of the silicon region, and the silicon oxide film. Forming a mixed film of the first metal and the second metal on the substrate on which the metal is formed, a step of reducing the silicon oxide film formed in the silicon region by the heat treatment with the second metal, and a heat treatment And a step of reacting the first metal with silicon in the silicon region to form a silicide film only on the surface of the silicon region.

  The heat treatment in the step of reducing the silicon oxide film and the step of forming the silicide film is preferably performed by the same heat treatment step.

  According to the invention, when the silicon oxide film is reduced by the second metal, the amorphous layer is formed at the interface between the first metal and the mixed film of the second metal and the silicon region. This makes it possible to grow a monocrystalline silicide film at the interface between the amorphous layer and the silicon region. Accordingly, the uniformity of the silicide film can be improved, and a device having high process stability and excellent characteristics can be manufactured even if the MIS transistor is miniaturized.

  From the viewpoint of sufficiently reducing the silicon oxide film with the second metal, the film thickness of the silicon oxide film formed on the surface of the silicon region is the same as that of the second metal in the mixed film. It is preferable that the ratio is not more than a value multiplied by a ratio (a ratio of the number of atoms of the second metal to the number of atoms of the first and second metals in the mixed film).

  Further, if the silicon oxide film is too thin, the amorphous layer becomes thin and it becomes difficult to form a single-crystal silicide film. Therefore, the thickness of the silicon oxide film formed on the silicon region surface is preferably 0.5 nm or more. .

  In addition, in the method of manufacturing a semiconductor device according to the present invention, a silicide film mainly composed of a first metal and silicon is formed only on the silicon region surface separated by the first insulating film on the substrate main surface side. Forming a nitride film mainly composed of a second metal and nitrogen on the surface of the silicide film or the surface of the silicide film and the crystal grain boundary; and a second insulating film having an opening on the nitride film surface. A step of forming amorphous silicon in the opening, a step of forming aluminum on at least the amorphous silicon (usually forming further titanium on the aluminum), and heat treatment to form the amorphous silicon and aluminum. And a step of burying aluminum in the opening.

  According to the invention, since the nitride film is formed on the surface of the silicide film in advance, the occurrence of spikes due to aluminum can be prevented. In addition, since it is not necessary to deposit a nitride film inside the opening, it is possible to suppress an increase in the number of processes and an increase in resistance due to the opening being narrowed.

  According to the present invention, it is possible to form a high-quality silicide film on a silicon region, and it is possible to prevent the problem that the thermal stability of the silicide film is lowered, and it is excellent even if the element is miniaturized. Thus, it is possible to obtain a semiconductor device having excellent characteristics such as reduced process resistance and reduced parasitic resistance.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  First, a first embodiment of the present invention will be described with reference to FIG.

  First, an element isolation insulating film (silicon oxide film) 2 is formed on a silicon substrate 1. Subsequently, a gate oxide film 3 of the MOSFET, a gate electrode 4 made of polycrystalline silicon, and a shallow source / drain diffusion layer 5 are formed, and a deep source / drain diffusion layer 7 is formed using the gate sidewall film 6 made of a silicon nitride film as a mask. Is formed (FIG. 1A).

  Next, the silicon oxide film on the surface of the polycrystalline silicon gate electrode 4 and the deep source / drain diffusion layer 7 is removed by dilute hydrofluoric acid treatment or the like. After that, surface treatment with a mixed solution of an aqueous solution containing an oxidizing agent such as ozone water or aqueous hydrogen peroxide and hydrochloric acid, sulfuric acid, ammonia water, etc. is performed, and the surface of the silicide film formation region is uniformly and thinly oxidized naturally. A film (not shown) is formed. Subsequently, a cobalt film 8 containing about 10 to 30% titanium is deposited on the entire surface, and a titanium nitride film 9 is further deposited thereon. At this time, the deposition of the titanium nitride film 9 can be omitted (FIG. 1B).

  Next, annealing is performed for a short time at a temperature of about 550 to 700 ° C. using a lamp annealing apparatus or the like, and the silicon substrate 1 and the polycrystalline silicon film 4 are reacted with the cobalt film 8 containing titanium to thereby obtain cobalt monosilicate containing titanium. Side (CoSi) film 10 is formed. Thereafter, the titanium nitride film 9 and the cobalt film 8 containing unreacted titanium are removed by etching using an etching solution such as a mixed solution of sulfuric acid and hydrogen peroxide solution (FIG. 1C).

Next, annealing is performed for a short time at a temperature of about 800 to 900 ° C. in a nitrogen or ammonia atmosphere using a lamp annealing apparatus or the like, and the cobalt monosilicide (CoSi) film 10 containing titanium is converted into a low resistance cobalt disilicide (CoSi ₂ ). While changing to the film 11, titanium contained in the film is sucked out by a nitridation reaction on the film surface, and a titanium nitride film 12 is selectively formed on the surface of the cobalt disilicide (CoSi ₂ ) film 11. At this time, when the cobalt disilicide is polycrystalline, titanium nitride (film) is selectively formed also at the crystal grain boundary (FIG. 1D).

  Next, silicon oxide films 13 and 14 are deposited on the entire surface by a low pressure CVD method and a plasma CVD method, and flattened by a CMP process or the like (FIG. 1E).

  Next, a contact hole is formed in the silicon oxide films 13 and 14, a metal film 15 such as tungsten is buried as a contact plug in the contact hole, and a wiring layer 16 such as aluminum is further formed to form source / drain diffusions. It connects with a layer and a gate electrode (FIG.1 (f)).

Through the above steps, the cobalt disilicide (CoSi ₂ ) film 11 is formed only on the polycrystalline silicon gate electrode 4 and the source / drain diffusion layer 7, and the titanium is selectively formed on the surface of the cobalt disilicide film 11. A nitride film 12 is formed. When the cobalt disilicide is polycrystalline, a titanium nitride film is selectively formed also at the crystal grain boundary.

According to the present embodiment, since the cobalt film contains titanium having high reducibility with respect to the silicon oxide film as well as the reduction of the parasitic resistance in the thin wire region having a gate length of 0.2 μm or less, It is possible to prevent the silicide reaction from being inhibited by the natural oxide film, which has been a problem in the salicide process, and the occurrence of a non-uniform reaction. In addition, problems such as the generation of watermarks that occur in hydrofluoric acid-based pretreatments do not occur. Further, it is possible to form a cobalt disilicide (CoSi ₂₎ self-aligned manner with high heat resistance titanium nitride film on the film surface, a cobalt disilicide by heat at the time of the silicon oxide film is deposited as an interlayer film (CoSi ₂₎ Problems such as film aggregation can also be prevented. Further, since the titanium nitride film is formed only on the surface of the cobalt disilicide (CoSi ₂ ) film, the resistance due to the contact hole being narrowed compared to the case where the titanium nitride film is also formed on the side wall of the contact hole. Can be suppressed.

  By the way, in the step of FIG. 1B of this embodiment, the thickness of the silicon oxide film formed on the surfaces of the polycrystalline silicon gate electrode 4 and the source / drain diffusion layer 7 when the cobalt film 8 containing titanium is deposited. The thickness is determined by the thickness (T) and the titanium concentration (N) of the cobalt film 8 containing titanium to be deposited. That is, the amount of titanium that can contribute to the reduction of the silicon oxide film is T × N in terms of film thickness.

  FIG. 9 shows the upper limit of the oxide film thickness that can be reduced by titanium with respect to the titanium concentration (atomic%) when the film thickness of the cobalt film containing titanium (cobalt-titanium alloy) is changed to 10, 15, and 20 nm. Measurement results. For example, the thickness of the silicon oxide film formed on the surfaces of the polycrystalline silicon gate electrode 4 and the source / drain diffusion layer 7 is calculated in terms of film thickness when the thickness of the cobalt-titanium alloy is 10 nm and the titanium concentration is 10%. T × N = 1 nm, which is substantially equal to the upper limit value of the oxide film thickness shown on the vertical axis. It can be seen from FIG. 9 that the same result is obtained for other values. In other words, it can be said that the maximum film thickness of the silicon oxide film that can be reduced by titanium is substantially the same as the equivalent titanium film thickness (T × N). Therefore, in order to obtain a uniform cobalt silicide film, it is necessary to suppress the thickness of the silicon oxide film on the silicon surface forming the cobalt silicide to be equal to or less than the equivalent titanium thickness (T × N). .

  Also, it is necessary to limit the titanium concentration in the cobalt-titanium alloy film from the viewpoint of the resistivity of the formed cobalt silicide. FIG. 10 shows the relationship between the titanium concentration in the cobalt-titanium alloy film and the resistivity of the cobalt silicide formed. From this figure, it can be seen that the resistivity of the formed cobalt silicide increases as the titanium concentration in the cobalt-titanium alloy film increases. This resistivity rise curve varies depending on the thermal process or the like for forming cobalt silicide, but it is considered that the resistivity exceeds the allowable range at a titanium concentration of 30% or more. Therefore, the titanium concentration in the cobalt-titanium alloy film needs to be suppressed to 30% or less.

  From the above, in order to obtain a uniform cobalt silicide film, it is preferable that the thickness of the silicon oxide film on the silicon surface on which the cobalt silicide is formed be in the range shown in FIG.

  Further, according to the present embodiment, the cobalt disilicide film formed on the (100) plane-oriented silicon substrate can be made a single crystal instead of a polycrystal.

When a silicon oxide film is formed on the silicon surface on which cobalt silicide is formed and this silicon oxide film is reduced by titanium in the cobalt-titanium alloy film, titanium, silicon, and silicon are formed at the interface between the silicon substrate and the cobalt-titanium alloy film. An amorphous layer mainly composed of oxygen is formed. In the absence of such an amorphous layer, the reaction between cobalt and silicon occurs in all parts of the cobalt-titanium alloy film as a result of both diffusing, as shown in FIG.
Co → Co ₂ Si → CoSi → CoSi ₂
And so on. On the other hand, when an amorphous layer as described above is present at the interface, the supply of cobalt atoms to the silicon substrate is rate limited by the amorphous layer, and only at the interface between the amorphous layer and the silicon substrate,
Co → CoSi ₂
The reaction that comes to occur. Since this cobalt disilicide (CoSi ₂ ) film has a crystal structure very close to that of silicon, cobalt disilicide is epitaxially grown at the interface between the amorphous layer and silicon to form single crystal cobalt disilicide. Therefore, when forming a cobalt film containing titanium in the step of FIG. 1B, a silicon oxide film having a desired thickness is formed, so that a single crystal cobalt die is formed in the heat treatment step of FIG. It is also possible to form silicide.

  As described above, when a single crystal cobalt disilicide is formed on a (100) -oriented silicon substrate, an amorphous material mainly composed of titanium, silicon, and oxygen formed at the interface between the cobalt-titanium alloy film and the silicon substrate. The layer plays an important role. In the step of FIG. 1B, the cobalt disilicide formed when the thickness of the silicon oxide film formed on the surface of the source / drain diffusion layer 7 when depositing the cobalt film 8 containing titanium is too thin. The film becomes polycrystalline. It has been confirmed by experiments that the thickness of the silicon oxide film necessary for forming the single crystal cobalt disilicide film is at least 0.5 nm.

  As described above, when depositing a cobalt film containing titanium, it is very important to control the thickness of the silicon oxide film formed on the silicon. In order to control the film thickness of the silicon oxide film, the silicon surface is chemically oxidized again by a desired thickness after the silicon oxide film peeling step in the process performed before depositing the cobalt film containing titanium. In addition, the concentration of oxidizing agents such as ozone, active oxygen, nitrogen oxides, halogen oxides, and hydrogen peroxide in the processing solution and the processing time are controlled, and titanium is contained after the processing is completed. It is important not to change the silicon oxide film thickness until the cobalt film is deposited.

  In the atmosphere, the silicon oxide film thickness increases with time due to oxygen and water vapor in the atmosphere. Therefore, it is important to keep the substrate in an atmosphere in which the concentration of oxygen and water vapor is lower than that in the air after the process of controlling the oxide film thickness and before the deposition of the cobalt film containing titanium. It is. According to the examination results of the present inventors, the natural oxide film thickness is 3 nm at the maximum when the humidity exceeds 50% at room temperature in a mixed gas atmosphere or air in which the mixing ratio of oxygen and nitrogen is 1: 4. It has been found to grow up to. Therefore, it is necessary to keep the humidity lower than this, or store it in an atmosphere with less oxygen and carbon dioxide. By using a drying box containing silica gel, magnesia (MgO) or activated carbon and keeping the humidity at 20% or less, the thickness of the natural oxide film can be suppressed to 1 nm or less.

  As described above, in the present embodiment, a single crystal cobalt disilicide film can be obtained on a (100) -oriented silicon substrate, and the film uniformity is higher than that of polycrystalline cobalt disilicide. The minimum distance between the bottom surface of the cobalt disilicide film and the junction position of the gate oxide film and the source / drain diffusion layer can be kept large, and the deterioration of the gate breakdown voltage and the occurrence of junction leakage can be suppressed. At the same time, the heat resistance of the cobalt silicide is improved.

  In the above embodiment, the cobalt film 8 containing titanium is used. However, Zr, Hf, V, Nb, Ta, or Cr can be used instead of titanium, and Ni, Pt, or Pd can be used instead of Co. is there.

  Next, a second embodiment of the present invention will be described with reference to FIG.

  Since the manufacturing process of the MOS transistor and the like are the same as those of the first embodiment shown in FIG. 1, the first embodiment is referred to up to the intermediate process, and the description is omitted.

  After forming a structure in which a cobalt silicide film 11 whose surface is covered with a titanium nitride film 12 is pasted as shown in FIG. 1D, interlayer insulating films (silicon oxide films) 13 and 14 are deposited on the entire surface, and contact holes are formed. Form. Thereafter, an amorphous silicon film 17 is deposited and etched back to leave the amorphous silicon 17 only in the contact holes. Subsequently, an aluminum film 18 and a titanium film 19 are deposited on the entire surface (FIG. 2A).

  Next, the amorphous silicon 17, the aluminum 18 and the titanium 19 are reacted by a heat process at 600 ° C. or less to replace the amorphous silicon 17 inside the contact hole with the aluminum 20. Thereafter, the aluminum 18 and titanium 19 remaining outside the contact hole and the silicon 17 sucked out by the substitution reaction are removed by a CMP process or the like (FIG. 2B).

  Next, a wiring metal 21 such as aluminum is deposited on the entire surface and patterned to connect the semiconductor element portion and the wiring layer (FIG. 2C).

  Thus, according to the present embodiment, since the surface of the silicide film 11 is previously covered with the titanium nitride film 12 having a high diffusion barrier property, it is possible to prevent the occurrence of spikes due to aluminum. In addition, since it is not necessary to deposit a titanium nitride film inside the contact hole again, it is possible to suppress an increase in resistance due to an increase in the number of processes and a narrowing of the contact hole.

Process sectional drawing which showed the manufacturing process which concerns on the 1st Embodiment of this invention. Process sectional drawing which showed the manufacturing process which concerns on the 2nd Embodiment of this invention. Process sectional drawing which showed the manufacturing process which concerns on a prior art. Process sectional drawing which showed the manufacturing process which concerns on another prior art. Sectional drawing shown about the problem of the prior art. Sectional drawing shown about the problem of the prior art. Process sectional drawing which showed the manufacturing process which concerns on another prior art. Process sectional drawing which showed the manufacturing process which concerns on another prior art. The figure shown about the upper limit of the silicon oxide film thickness which can be formed in the silicon surface when depositing a cobalt titanium alloy. The figure shown about the upper limit of the titanium concentration in a cobalt-titanium alloy. The figure shown about the range of the silicon oxide film thickness which can be formed in the silicon | silicone surface when depositing a cobalt titanium alloy. The figure shown about silicidation reaction when a silicon oxide film does not exist on the silicon surface when depositing a cobalt-titanium alloy. The figure shown about silicidation reaction in case a certain amount or more of silicon oxide films exist on the silicon surface when depositing a cobalt-titanium alloy.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 2 ... Element isolation insulating film 3 ... Gate insulating film 4 ... Polycrystalline silicon gate electrode 5, 7 ... Source / drain diffused layer 6 ... Gate side wall film 8 ... Cobalt film containing titanium 9 ... Titanium nitride film 10 Cobalt monosilicide film containing titanium 11 Cobalt disilicide film 12 Titanium nitride film 13, 14 Silicon oxide film 15 Contact plug 16 Wiring 17 Amorphous silicon film 18 Aluminum film 19 Titanium film 20 Silicon Replaced with aluminum 21 ... wiring

Claims (3)

Forming a silicon region partitioned by an insulating film on the main surface side of the substrate; forming a silicon oxide film on the surface of the silicon region; and forming a first metal and a second metal on the substrate on which the silicon oxide film is formed. A step of forming a metal mixed film, a step of reducing a silicon oxide film formed in the silicon region by heat treatment with the second metal, and a step of heat treating the first metal and silicon in the silicon region. Reacting to form a silicide film only on the surface of the silicon region,
The method of manufacturing a semiconductor device, wherein the first metal is Co, Ni, Pt, or Pd, and the second metal is Ti, Zr, Hf, V, Nb, Ta, or Cr.   2. The film thickness of the silicon oxide film formed on the surface of the silicon region is set to be equal to or less than a value obtained by multiplying the film thickness of the mixed film by the ratio of the second metal in the mixed film. Semiconductor device manufacturing method.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the thickness of the silicon oxide film formed on the surface of the silicon region is 0.5 nm or more.

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