JP2008054126A - Device and method for processing video signal, and video signal decoding device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a video signal processing device and method capable of efficiently transferring data between a module of a preceding stage and a module of a post stage, and to provide a video signal decoding device. <P>SOLUTION: Data in a predetermined pixel unit which continue in a direction perpendicular to a block boundary including data processed by an overlap smoothing filter 31 are respectively written in parallel in a prescribed number of memories, and the data to be processed by a deblocking filter 32 are read in parallel in the predetermined pixel unit, starting from the prescribed number of memories. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a video signal processing apparatus and method, and a video signal decoding apparatus, and in particular, a video signal that performs block boundary smoothing processing when decoding encoded data obtained by encoding a video signal in units of blocks. The present invention relates to a processing apparatus and method, and a video signal decoding apparatus.

  In recent years, various moving image compression coding techniques have been proposed. The VC-1 moving image compression coding method known as one of them is based on MPEG (Moving Picture Exparts Group) -4 Part 2. Further, various ideas for improving the compression efficiency have been applied, and standardization by SMPTE (American Film and Television Engineers Association) has been made and announced as SMPTE 421M.

  In general, a decoder in the VC-1 encoding method has a configuration proposal described in a reference source code of VC-1 or a decoding process overview of a standard SMTPE 421M. According to this standard, a bit stream signal encoded by a VC-1 codec (Codec) is input to a decoder system and subjected to a structure analysis (Parsing). Separately, data is classified into data that has been intra-encoded (intra-frame predictive encoding) and inter-encoded (inter-frame predictive encoding). The classified intra-coded data and inter-coded data are different in data reconstruction processing when a decoded picture (Decode Picture) is generated.

  FIG. 19 is a block diagram schematically showing an example of this VC-1 decoder system, and the bitstream structure analysis module 11 analyzes the structure of the input bitstream. Intra-coded data and inter-coded data from the bitstream structure analysis module 11 are sent to an inverse quantization / inverse DCT (IQ / IDCT) module 13 via an AC / DC prediction (Prediction) module 12, and inversely processed. After the quantization and inverse DCT are performed, the data is sent to the selection switch 14, the intra-coded data is sent to the overlap smoothing filter 15, and the inter-coded data is sent to the adder 16.

  The overlap smoothing filter 15 is a filter for smoothing the block boundary in order to reduce distortion at the block boundary (edge), and performs the overlap smoothing process only on the intra-coded data and sends it to the adder 16. Also, a motion vector (MV) is sent from the bitstream structure analysis module 11 to the motion compensation (MC) module 22 via the motion vector prediction module 21, and the motion compensation module 22 reads it from the external memory by the control unit 23. Motion compensation is performed using the decoded data, and the obtained data (inter-coded data) is sent to the adder 16. In the adder 16, the inter-encoded data from the selection switch 14, the intra-encoded data from the overlap smoothing filter 15, and the inter-encoded data from the motion compensation module 22 are added to a deblocking filter (Deblocking Filter) 17. Sent. The deblocking filter 17 smoothes only the block boundary (edge) and suppresses the generation of block noise. By performing such decoding processing, an image (Picture) is reconstructed (decoded).

  Next, the overlap smoothing process that is standardized as a VC-1 decoder by the standard SMTPE 421M will be described.

  As shown in FIG. 20, this overlap smoothing process performs a 4-tap filter process on the boundary (edge) of a block of 8 × 8 pixels, and is performed in the order of vertical edge and horizontal edge. The same calculation is performed on the data of the (luminance) / C (chroma) signal, and processing is performed only on the I picture (intra-frame encoded image) or P picture (forward prediction encoded image).

  FIG. 21 shows a time series of data sent from the preceding module or from the external memory, and the unit of picture reconstruction processing is a macroblock (MB). As a method for reducing the latency (waiting time for processing) with respect to the time series of data sent as shown by the arrows in FIG. 21, it is required to perform the overlap smoothing processing. A macroblock (MB) is shown in FIG. In FIG. 22, the range in which overlap smoothing processing is performed on the current macroblock (Current MB) C-MB sent from the previous module to be processed (or read from the external memory). (Processing completion area) is Xos. In order to perform the overlap smoothing process in the range Xos in FIG. 22, the current macroblock C-MB, the previous macroblock (Left MB) L-MB, and the current macroblock C-MB are pictured. The upper macroblock (Above MB) A-MB located at the top when the image is reconstructed, and the macroblock (Left Above MB) LA-MB immediately before the upper macroblock A-MB (when the picture is reconstructed) Data belonging to a total of four macroblocks C-MB, L-MB, A-MB, and LA-MB of the upper macroblock A-MB).

  Further, the range to be subjected to the deblocking filter processing is the range Xdb in FIG. 22, and the four macroblocks C-MB, L-MB, A-MB, LA as in the case of the overlap smoothing processing. -Data belonging to MB is required. The deblocking filter processing in the VC-1 standard is applied only to an 8 × 8 block boundary for I pictures and B pictures (bidirectional predictive coded images), and up to a 4 × 4 block boundary for P pictures. It is. This deblocking filter process changes only two pixels from the boundary by an 8-tap filter process, and the process is performed in the order of the horizontal edge and the vertical edge. The same calculation is also performed on the Y (luminance) / C (chroma) signal data. Note that the range Xdb shown in FIG. 22 indicates a region where the deblocking filter processing is completed in consideration of field encoding and frame encoding.

  As described above, when the filtering process is performed using the data belonging to the four macro blocks C-MB, L-MB, A-MB, and LA-MB, the structure analysis (Parsing) method of the bitstream structure analysis module 11 is performed. However, in addition to the data sent from the previous module, data necessary for processing is generally read out from an external memory or the like by the control unit 23. For example, SDRAM is used as the external memory, and the control unit 23 accesses the SDRAM via the arbiter / SDRAM control circuit.

  Here, the macroblock L-MB immediately before the current macroblock C-MB can be solved by using the internal cache, but the upper macroblock A-MB is the picture of the picture to be decoded. Since the number of macroblocks in the horizontal direction changes arbitrarily depending on the number of pixels that make up the picture, if the data is to be retained inside the system, the storage area is standard for the arbitrarily variable number of pixels. It must be prepared with the maximum amount shown, which also wastes resources. For this reason, the data after filtering by the modules of the overlap smoothing filter 15 and the deblocking filter 17 is stored in the external memory by the control unit 23, and the data necessary for the subsequent processing is stored in the external memory at an arbitrary timing. In general, it is a configuration to collect by reading again.

  In the example of FIG. 19, since the inverse quantization / inverse DCT (IQ / IDCT) module 13 handles both intra / inter coded data, the AC / DC prediction module 12 corresponding to the preceding stage also handles inter coded data. It has become. For example, in FIG. 19, the encoded data for which the inverse DCT processing has been completed is selected before the overlap smoothing filter 15 depending on whether it is intra encoded data or inter encoded data, and the intra encoded data is sent to the overlap smoothing filter 15. Sent.

  At the timing when the overlap smoothing filter 15 is processed, as shown in the path R1 of FIG. 19, the data required for the data of the upper macroblock A-MB and the macroblock LA-MB immediately before it is stored in the external memory. To the overlap smoothing filter 15. The pixel data for which the overlap smoothing process is completed is in a range surrounded by a frame Xos in FIG. Further, all of the data filtered by the overlap smoothing filter 15 is a portion corresponding to the frame Xos in FIG. All the filtered data or the pixel data belonging to a macroblock other than the current macroblock C-MB is stored again in the external memory by the control unit 23 through the path W2 in FIG. 19 as filtered data.

  Here, as shown in FIG. 22, with respect to the current macroblock C-MB, the macroblock (Below MB) B-MB located at the bottom in the reconstructed picture after decoding is the current macroblock C-MB. Data as an intermediate result to be used at this time is also stored in the external memory through the path W2 in FIG. This corresponds to the pixel data of the portion of the frame KX in FIG.

  The data belonging to the current macroblock C-MB after the processing by the overlap smoothing filter 15 after the above processing or the data belonging to the macroblock L-MB immediately before being filtered by the overlap smoothing filter 15 is as follows. The inter-coded data processed by another path such as motion compensation is added and sent to the deblocking filter 17.

  The above is the description of the data of the luminance (Y) signal, but the overlap smoothing process is similarly performed on the macroblocks of the chroma signals Cb and Cr in the case of a color image, and this overlap smoothing process is performed. As shown in FIG. 24, the range is a range surrounded by frames Xbos and Xros.

  In this specification, the filtering process of luminance (Y) signal data is mainly described, and the description of chroma (Cb, Cr) signal data is omitted.

  In the next deblocking process in the deblocking filter 17, the macroblock immediately before the current macroblock C-MB is required for the current macroblock C-MB in the same route as indicated by R 3 in FIG. 19 as in the overlap smoothing filter 15. Data belonging to four macroblocks of the L-MB, the upper macroblock A-MB, and the macroblock LA-MB immediately before the L-MB is taken into the deblocking filter 17. Finally, the decoded picture (Decode Picture) is stored in the external memory through the path W4 in FIG. Of course, the L-MB data can also be taken into the internal cache of the deblocking filter 32 via the adder 16.

  As a prior art, Non-Patent Document 1 discloses a standard for the VC-1 moving image compression encoding method.

SMPTE 421M Standard, SMPTE Draft Standard for Television, SMPTE (American Film and Television Engineers Association), August 23, 2005

  As described above, there is a difference between the overlap smoothing process and the deblocking filter process. The overlap smoothing process uses four pixels sandwiching an 8 × 8 block boundary for an I picture (intra-frame encoded image) and a P picture (forward prediction encoded image) as shown in FIG. It is performed for two pixels, and it is specified that the horizontal edge is processed after the vertical edge processing is completed.

  On the other hand, the deblocking filter process is performed on an I picture, a P picture, and a B picture (bidirectional predictive coded image). In the case of an I picture and a B picture, an 8 × 8 block boundary is processed, and in the case of a P picture, as shown in FIG. 26, 8 × 8, 8 × 4, 4 × 8 depending on whether there is a prediction error. 4x4 block boundaries are processed. In FIG. 26, the block (sub-block) in the hatched area is a block having a prediction error, and the block (sub-block) in the blank area is a block having no prediction error. A thick line is a boundary where the deblocking filter process is performed, and a thin line is a boundary where the deblocking filter process is not performed. In FIG. 26, the motion vectors of the respective blocks are equal. Note that deblocking filter processing is always performed when the motion vectors are different. FIG. 26 shows the case where the blocks are arranged in the horizontal direction, but the same applies to the case where the blocks are arranged in the vertical direction.

  As shown in FIG. 27, the deblocking filter processing is performed on the boundary except when both block data on both sides of the boundary are inter-coded data, both motion vectors are equal, and both have no prediction error. In addition, two pixels at the boundary are changed using an 8-tap filter. In addition, this deblocking filter process is defined to process a vertical edge after a horizontal edge process is completed.

  That is, in the overlap smoothing process, the part required for the vertical edge process becomes data arranged as shown in FIG. 25a processed by the 4-tap filter, and the part required for the horizontal edge process is shown in FIG. The data is arranged like 25 b. On the other hand, the portion required for the horizontal edge processing in the deblocking filter processing is data arranged as shown in FIG. 27c processed by the 8-tap filter, and the portion required for the vertical edge processing is shown in FIG. The data is arranged like 25 d.

  As described above, in the overlap smoothing process and the deblocking filter process, it is desirable to efficiently pass data between the overlap smoothing process and the deblocking filter process because the processing target includes a common pixel. Yes.

  However, in the overlap smoothing process, as shown in FIGS. 25A and 25B, the pixel to be processed is in units of 4 pixels, whereas in the deblocking filter process, it is in units of 8 pixels and is a unit recorded in the memory. Is different. In the deblocking filter processing, there are sub-blocks as shown in FIG. 26, and the processing is necessary depending on whether the interlace-coded data is frame-coded or field-coded. The pixel range to be processed and the edge to be processed will change.

  For this reason, in a conventional VC-1 decoder having a general configuration, a temporary storage area for temporarily storing overlap smoothed data and a function for changing the data storage method so that the deblocking filter module can be used easily In addition, a temporary storage area for changing the data storage method is required, and an increase in the temporary storage area has been a problem. Further, when the temporary storage area is an external memory, there has been a problem that the amount of memory bandwidth consumed for accessing the external memory increases.

  Specifically, when the memory area for temporarily storing the data subjected to the overlap smoothing process and the memory for the deblocking filter module to read out pixels necessary for the horizontal edge process are shared, for example, the horizontal edge in the overlap smoothing process When the processed pixel data of the vertical 4-pixel arrangement as shown in FIG. 25b is stored as a processing unit, the deblocking filter module module uses the upper two pixels and the lower two pixels shown in FIG. In order to read data, the memory must be accessed at least twice, and a total of three or more data reads are required. In addition, when the assumed vertical 4-pixel arrangement is used as one storage unit, in the case of the vertical edge of the deblocking filter processing, a total of 8 readings are required. Therefore, the vertical edge is used in the overlap smoothing processing. Therefore, a means for aligning the results of the side-by-side processing obtained by processing vertically is necessary.

  The present invention has been proposed in view of such a conventional situation, and a video signal processing apparatus and method capable of efficiently passing data between a front-stage module and a rear-stage module, and a video signal An object is to provide a decoding device.

  In order to solve the above-described problems, the present invention provides a video signal processing apparatus that performs block boundary smoothing processing when decoding encoded data obtained by encoding a video signal in units of blocks. A first filter that performs a first block boundary smoothing process on the data and a data that includes the data that is arranged in succession to the first filter and that has been subjected to the first block boundary smoothing process A second filter that performs the second block boundary smoothing process; and a predetermined number of memories that perform writing / reading of data in predetermined pixel units in parallel, and the first block boundary smoothing process is performed The memory is specified so that the data of the predetermined pixel unit that is continuous in a direction orthogonal to the block boundary including the data is written in different memories.

  The present invention also provides a video signal processing method for performing block boundary smoothing processing when decoding encoded data obtained by encoding a video signal in units of blocks, with respect to data being decoded first. A first filter processing step for performing block boundary smoothing processing, and a second processing for data including data that has been processed in succession to the first filter processing step and has been subjected to the first block boundary smoothing processing. A second filter processing step for performing the block boundary smoothing process, and in the first filter processing step, a direction orthogonal to the block boundary including the data subjected to the first block boundary smoothing process The data of the predetermined pixel unit continuous to the predetermined number of memories is written in parallel, and in the first filter processing step, the second block boundary smoothing process is performed. Characterized in that the parallel read out in a predetermined pixel unit from the predetermined number of the memory.

  In addition, the present invention provides a video signal decoding apparatus that performs inverse quantization / inverse DCT processing on encoded data obtained by encoding a video signal in units of blocks, and performs decoding processing by performing motion compensation. The first filter that performs the first block boundary smoothing process and is continuously arranged in the first filter is supplied with the addition data of the data subjected to the normalization / inverse DCT process and the motion compensated data A second filter that performs a second block boundary smoothing process on data including the data subjected to the first block boundary smoothing process, and a predetermined number for writing / reading data in predetermined pixel units in parallel Each of the predetermined pixel unit data that is continuous in a direction orthogonal to the block boundary including the data subjected to the first block boundary smoothing process. Characterized by designating the memory to be written to the directory.

  According to the present invention, in order to designate a memory so that data of a predetermined pixel unit continuous in a direction orthogonal to a block boundary including data subjected to the first block boundary smoothing process is written to different memories, In the subsequent block boundary smoothing process, data can be efficiently read without requiring rearrangement.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram schematically showing a configuration of an example of an embodiment of the present invention. A bit stream signal (Bit Stream) signal encoded based on the SMTPE 421M (so-called VC-1) standard is input to a decoder system as shown in FIG. 1 and is analyzed by a bit stream structure analysis (Parsing) module 11. Depending on the data encoding method, the data is classified into intra-coded data and inter-coded data. Intra-coded data and inter-coded data differ in data reconstruction processing when generating a decoded picture (Decode Picture). The bit stream structure analysis module 11 also outputs a motion vector.

  Intra-coded data and inter-coded data from the bitstream structure analysis module 11 are sent to an inverse quantization / inverse DCT (IQ / IDCT) module 13 via an AC / DC prediction (Prediction) module 12, and inversely processed. Quantization and inverse DCT are performed. The motion vector from the bitstream structure analysis module 11 is sent to the motion compensation module 22 via the motion vector prediction module 21, and the motion compensation module 22 uses the decoded data read from the external memory by the control unit 23. Motion compensation is applied.

  Here, since intra-encoded data is not subjected to data processing after the overlap smoothing filter process, if the inter-encoded data is added immediately before the deblocking filter process, a difference occurs in the deblocking filter process. Absent. In consideration of this point, as shown in FIG. 1, an adder 25 is provided immediately before the overlap smoothing filter 31 to mix the intra coded data and inter coded data from the inverse quantization / inverse DCT module 13. The inter-coded data from the motion compensation module 22 is added to the data.

  The added data from the adder 25 is sent to the filter processing unit 30 in which the overlap smoothing filter 31 and the deblocking filter 32 are integrated. In this filter processing unit 30, the intra smoothed filter 31 and the decoded data are selected and the required smoothing filter 31 and the decoded data are processed by performing a necessary process on the respective coded data. The blocking filter 32 can be continuously arranged. As a result of the integration, an overlapping pixel area (a range MX in FIG. 2 to be described later) of a decoded picture (Decode Picture) necessary for processing between the two filters 31 and 32 is stored in an internal storage holding area as shown in FIG. By storing it in the internal module as the memory 33 (for example, a cache such as SRAM), it is possible to configure a system capable of reducing the frequency of access to the external memory and the amount of data transfer when processing intra-coded data. ing.

  The filter processing unit 30 in which the overlap smoothing filter 31 and the deblocking filter 32 are integrated has means for selecting data to be processed first into intra-coded data and inter-coded data, and overlap smoothing filter processing Required for deblocking filter processing, and a memory 34 such as SRAM, which is a means for storing temporary data necessary for the above and a means for temporarily storing data of the upper macro block (Above MB) A-MB in FIG. Memory 35 such as SRAM, which is a means for storing temporary data, and memory 36 such as SRAM, which is a means for temporarily storing data of the upper macroblock A-MB, and data common to the two filter processes. The memory 33 is a means for storing.

  Here, the pixel range required for the overlap smoothing filter process and the deblocking filter process will be described with reference to FIG. In FIG. 2, as described with reference to FIG. 22, in order to perform the above two filter processes, the currently sent macroblock (Current MB) C-MB and the immediately preceding macroblock (Left MB) L -MB, the upper macroblock (Above MB) A-MB located at the top when the picture is reconstructed for the current macroblock C-MB, and the macroblock immediately before this upper macroblock A-MB ( Left Above MB) LA-MB (macroblock located to the left of the upper macroblock A-MB when the picture is reconstructed), a total of four macroblocks C-MB, L-MB, A-MB, LA- Requires data belonging to MB. In the case of the filter processing unit 30 of the decoder system of FIG. 1 according to the embodiment of the present invention, the range required for the overlap smoothing process is Mos, and the range required for the deblocking filter process is Mdb. The portion MX overlaps between each range required by these two filtering processes. Data of the overlapping range MX is stored in the memory 33 in the filter processing unit 30.

  The processing method of the data sent to the filter processing unit 30 is first selected based on intra-coded data or inter-coded data. In the case of intra-coded data, data is sent to the overlap smoothing filter 31, and data necessary for processing other than the data belonging to the currently transmitted macroblock (Current MB) C-MB is R1 in FIG. The path is read from an external storage device (memory such as SDRAM: external memory). The data read from the external memory through the path R1 in FIG. 1 is the data of the upper macroblock A-MB and the macroblock LA-MB immediately before the current macroblock C-MB. In addition, the data belonging to the immediately preceding macroblock L-MB but required at this timing when the current macroblock C-MB is sent to the module is that the previous macroblock L-MB is the current macro. It is stored in the internal memory 34 at the previous timing to be processed as a block (path W5 in FIG. 1), and is devised to read from the inside at the current timing as shown by the path R5 in FIG. be able to. The next macroblock to be overlapped among the data read by the route R1 and R5 in FIG. 1 and the data subjected to the overlap smoothing filter processing by the current data (current macroblock C-MB). Data necessary for the above process is written to the memory 34 through the path W5 in FIG. Further, in the reconstructed picture (Picture) as shown in FIG. 15, the intermediate data to be finally processed when the lower macroblock B-MB becomes the current macroblock is the path W2 in FIG. Is written to the external memory.

  Further, the completely processed data is written into the memory 33 of the data storage means inside the module as shown by the path W6 in FIG. Next, the deblocking filter process is performed on the data subjected to the overlap smoothing process. At this time, the overlapping data in the two filter processes is not transmitted from the memory 33 via the path R6 in FIG. Read out.

  Further, the pixel data belonging to the immediately preceding macroblock L-MB among the pixel data necessary for the deblocking filter processing is adjusted by adjusting the amount of data stored in the memory 33, so that the data storage configuration shown in FIG. By continuously storing the data of the macro block L-MB and the current macro block C-MB, etc. and holding them in the module like an internal cache, it becomes possible to read from the memory 33. FIG. 3 shows three macroblock sizes as the storage size of the memory 33 because of restrictions on the timing of writing the data after overlap smoothing processing and the timing of reading at the time of deblocking filter processing for the convenience of the actual hardware system. It is shown as a range of Ma that two macro lines (MB-0, MB-1, MB-2) and two lines to be subjected to the overlap smoothing process above these three macro blocks are prepared. Also, the decoded image pixels belonging to the upper macroblock A-MB and the macroblock LA-MB immediately before the upper macroblock A-MB that do not overlap with the overlap smoothing process are prepared by reading from the external memory via the path R3 in FIG. The In the deblocking filter process, an intermediate result of the process is temporarily stored in the memory 35 of FIG. Then, the data for which the deblocking filter process has been completed is written to the external memory as a reconstructed decoded image through a path toward the external memory W4 in FIG.

  In FIG. 3, a range Xos indicates a region where the overlap smoothing process is completed, and a range Xdb indicates a region where the deblocking filter process is completed. The data of the range Ma including three macroblocks (MB-0, MB-1, MB-2) and two lines subjected to the overlap smoothing process above these three macroblocks are internally held in the memory 33. Then, the data in the range Mb obtained by removing the two internally reserved lines from the macroblock area above the macroblocks MB-0 and MB-1 is read from the external memory into the memory 36 via the path R3. Further, the data of the range Mc of the upper two lines within the overlap smoothing processing range Xos is read from the external memory during the overlap smoothing processing.

  The inter-encoded data selected by the input-side selecting means of the filter processing unit 30 is not processed in the overlap smoothing processing block, and the same data range as that of the intra-encoded data is set in the memory shown in FIG. 33. As a result, the subsequent deblocking filter block can process the reading range regardless of whether it is inter or intra. As described above, the frequency of access to the external memory and the amount of data can be improved in both cases of writing and reading the data area that can be shared between the two filter processing blocks to the external memory. . At the same time, by reducing the access to the external memory having a large latency (waiting time for processing), the latency of the module can be improved.

  Next, the memory access according to the embodiment of the present invention will be described.

  FIG. 4 is a diagram illustrating a configuration example of the memory 33. The memory 33 is composed of four independent memories A to D, and data can be written into or read from each of the memories A to D simultaneously.

  FIG. 5 is a diagram illustrating a configuration example of a bank of the memory 33. The memory 33 is configured with data in the range Ma shown in FIG. 3, that is, a size having two horizontal lines in three MB sizes of 18 pixels × 48 pixels. The memory 33 includes three banks Bank0 to Bank2, and data is written in the order of Bank0, Bank1, and Bank2.

  In addition, the data of Bank 0 and 1 is read to the deblocking filter 32 at the MB timing at which the data processed by the overlap smoothing filter 31 is written to the Bank 2. In this operation, as shown in FIG. 5, by using the memory 33 like a ring buffer, the data after the overlap smoothing process can be passed to the subsequent stage in MB units regardless of the timing of the deblocking filter process. it can.

  Here, the pixels after the overlap smoothing process are written across the banks. For example, when writing Bank0, the data in the range a shown in FIG. 5 is written as “a ′” in Bank2.

  FIG. 6 is a schematic diagram illustrating a data storage method after the overlap smoothing process. In this data storage method, two pixels in the horizontal direction are configured (packed) as one unit (subpack). In other words, two pixels, which are the greatest common divisor of the pixels required for the overlap smoothing process, the pixels required for the deblocking filter process, and the offset (offset) pixels between them, are taken as one unit. In addition, in order to efficiently read out 8 pixels required for the deblocking filter processing, it is configured by four memories. As a result, the four subpacks can be stored in the independent memories A to D shown in FIG.

  In addition, as shown in FIG. 6, this data storage method differs in the configuration of the pack for storing in the memory by vertical edge processing or horizontal edge processing. That is, when two horizontally arranged pixels are used as one subpack, the upper 2 pixels and the lower 2 pixels of the 8 × 8 block are packed in 4 vertical pixels × 2 horizontal pixels as shown in FIG. Pixel regions other than the upper two pixels and the lower two pixels of the 8 × 8 block are packed as 1 vertical pixel × 8 horizontal pixels as shown in FIG. In this way, by changing the pack configuration for storing in the memory by vertical edge processing or horizontal edge processing, the frequency of access to the memory 33 can be reduced, and the image to be interlaced decoded will be interlaced as described later. It is possible to deal with cases. Further, by recording in the form of two horizontal pixels as one unit, all the data in the macroblock can be recorded regardless of the difference in vertical alignment and horizontal alignment after overlap smoothing processing.

  FIG. 7 is a schematic diagram showing a vertical 1 pixel × horizontal 8 pixel pack at a vertical edge after overlap smoothing processing. In this pack, four subpacks are arranged in the horizontal direction, and the data after the overlap smoothing process is a block in which one subpack is different. As shown in FIG. 7, the mapping of A to D in four memories is packed and stored in the order of B, C, D, and A, and the next line is in the order of A, B, C, and D. Pack and remember.

  FIG. 8 is a schematic diagram showing a pack of 4 vertical pixels × 2 horizontal pixels at the horizontal edge after the overlap smoothing process. In this pack, four subpacks are arranged in the vertical direction, and the data after the overlap smoothing process is a block in which the two subpacks are different. As shown in FIG. 8, the mapping of A to D in the four memories is packed and stored in the order of B, C, D, and A, and then packed in the order of C, D, A, and B. Remember.

  Further, as shown in FIG. 9, the relationship of mapping of 1 vertical pixel × 8 horizontal pixel pack and 4 vertical pixel × 2 horizontal pixel pack to the memory is the left of the line immediately below the subpack a stored in the memory A Subpack b designates the memory next to the current memory, that is, the memory B. The subpack a and the subpack c two lines below specify different memories.

  By specifying the memory in this way, four consecutive subpack data are written in different memories in a direction orthogonal to the block boundary including the data subjected to the overlap smoothing process. Therefore, it is possible to efficiently read out the pixels required for the deblocking filter processing at the block boundary and the subblock boundary. Furthermore, by writing the data of four consecutive subpacks in the processing direction including the data subjected to the overlap smoothing process to different memories, the frequency of access to the memory 33 can be reduced, and will be described later. Thus, it is possible to cope with the case where the image to be decoded is interlaced.

  FIG. 10 is a schematic diagram showing pixels (Y component) in the range Mos required for the overlap smoothing process shown in FIG. 2, and FIG. 11 is a schematic diagram showing memory addresses viewed from the spatial pixel position. is there.

  The changed pixels after the overlap smoothing process, for example, the pixels in the packed region of 1 vertical pixel × 8 horizontal pixels (pY1_6, pY1_7, Y0_0, Y0_1, Y0_2, Y0_3, Y0_4, Y0_5) shown in FIG. As shown in the pack (00) a shown, different memories A to D are allocated to each subpack. In addition, the pack (00) a in FIG. 11 uses the pixels of the immediately preceding macroblock for the vertical edge processing, and thus straddles two banks. On the other hand, for example, the pixels in the pack area (apY3_54, apY3_55, apY3_62, apY3_63, pY1_6, pY1_7, pY1_14, pY1_15) shown in FIG. Different memories A to D are allocated to each subpack.

  That is, each subpack is stored in a different memory, with 2 pixel units as subpacks, and the 4 subpacks at the boundary required for the deblocking filter processing are stored in different memories. As a result, like the packs c1 and c2 shown in FIG. 11, the pixel data of the block boundary required for the deblocking filter process can be obtained by reading twice. Further, as in the packs d1 and d2 shown in FIG. 11, the pixel data at the sub-block boundary required for the deblocking filter process can be obtained by reading twice.

  Even when an image is reproduced by interlace, edge processing is required for each odd and even. FIG. 12 is a schematic diagram showing memory addresses viewed from the spatial pixel position when the reproduced image is interlaced. In FIG. 12, the pixels of the macroblock shown in FIG. 10 are divided into Odd and Even, and the memory addresses shown in FIG. 11 are rearranged into Odd and Even. By rearranging in this way, even when the reproduced image is interlaced, the pixel data required for the deblocking filter process can be obtained by reading twice. For example, like the packs a1 and a2 shown in FIG. 12, the pixel data of the block boundary required for the deblocking filter process can be obtained by the number of times of reading twice. Further, as in the packs b1 and b2 shown in FIG. 11, pixel data at the sub-block boundary required for the deblocking filter process can be obtained by reading twice.

  Although the memory mapping after the overlap smoothing process described with reference to FIGS. 10 to 12 is for the luminance (Y) component, the color difference (Cb, Cr) component can be similarly processed.

  FIG. 13 is a schematic diagram showing pixels (Cb component) in a range required for the overlap smoothing process. FIG. 14 is a schematic diagram showing memory addresses viewed from the spatial pixel position. The changed pixels after the overlap smoothing processing are subpacked in units of 2 pixels as in the Y component, and each subpack is stored in a different memory, and 4 subpacks at the boundary required for the deblocking filter processing are stored. Store them in different memories. For example, the pixels (pCb_22, pCb_23, Cb_16, Cb_17, Cb_18, Cb_19, Cb_20, Cb_21) of the vertical 1 pixel × horizontal 8 pixel pack area shown in FIG. 13 are subpacks D36 (bank 2), C36, As in B36 and A36, different memories A to D are allocated to the respective subpacks. By storing in this way, the data of 8 pixels at the horizontal edge boundary required for the deblocking filter process can be read out by two memory accesses such as a1 and a2.

  Also, in the case of interlaced reproduction of an image, pixel data can be efficiently read from the memory by treating it in the same way as the luminance (Y) component. That is, as shown in FIG. 15, by rearranging the memory addresses shown in FIG. 14 into Odd and Even, the pixel data of the horizontal edge boundary required for the deblocking filter processing is changed to 2 such as a1 and a2, for example. It can be obtained by reading once.

  The Cr component is the same as the Cb component described above. FIG. 16 is a schematic diagram showing pixels (Cr components) in a range required for overlap smoothing processing, and FIG. 17 is a schematic diagram showing memory addresses viewed from the spatial pixel position. The changed pixels after the overlap smoothing processing are subpacked in units of 2 pixels as in the Y component, and each subpack is stored in a different memory, and 4 subpacks at the boundary required for the deblocking filter processing are stored. Store them in different memories. For example, pixels (pCr_22, pCr_23, Cr_16, Cr_17, Cr_18, Cr_19, Cr_20, Cr_21) in the pack area of 1 vertical pixel × 8 horizontal pixels shown in FIG. Different memories A to D are allocated to the respective subpacks as in B44 and A44. By storing in this way, the data of 8 pixels at the horizontal edge boundary required for the deblocking filter process can be read out by two memory accesses such as a1 and a2.

  Also, in the case of interlaced reproduction of an image, pixel data can be efficiently read from the memory by treating it in the same way as the luminance (Y) component. That is, as shown in FIG. 18, by rearranging the memory addresses shown in FIG. 17 into Odd and Even, the pixel data required for the deblocking filter process can be read out twice, for example, a1 and a2. Obtainable.

  According to the embodiment of the present invention as described above, when data is passed from the overlap smoothing filter 31 to the deblocking filter 32, the memory 33 that holds the data subjected to the overlap smoothing filter processing is used as it is. Since it can be shared as a reading memory of the blocking filter 32, a memory for rearranging data becomes unnecessary.

  Further, the memory mapping and the memory configuration in consideration of the deblocking filter processing after the overlap smoothing filter processing can reduce the pixel readout latency during the deblocking filter processing. That is, it is possible to reduce the load-reading and to perform high-speed processing.

  Also, due to the characteristic memory mapping, the image to be decoded is constant regardless of the picture type, regardless of whether the decoded image is interlaced or progressive, and even if there are sub macroblocks. Pixels can be read out with latency. As a result, constant reading is possible, and the system exception handling is reduced, resulting in a stable system.

  The present invention is not limited to the above-described embodiment. For example, the subpack unit may be 2 pixels × 2 pixels. The present invention can also be realized with a conventional apparatus configuration as shown in FIG. That is, the memory mapping according to the present invention is performed by the temporary storage device that passes the data after the overlap smoothing filter processing to the deblocking filter 17. The present invention can also be realized by, for example, a software program. In this case, when decoding encoded data for each macroblock that is a unit for encoding a video signal, a plurality of the macroblocks are configured. The block boundary smoothing process is performed for each block, the data being decoded is read for each block, and the block boundary smoothing process is sequentially performed by the computer in units of the blocks. Of course, various modifications can be made without departing from the scope of the present invention.

It is a block diagram which shows schematic structure of an example of embodiment of this invention. It is a figure which shows the pixel range required for the overlap smoothing filter process and deblocking filter process in embodiment of this invention. It is a figure which shows the area | region where an overlap smoothing process and a deblocking filter process are carried out. It is a figure which shows the structural example of a memory. It is a figure which shows the structural example of the bank of memory. It is a schematic diagram for demonstrating the data storage method after an overlap smoothing process. It is a schematic diagram which shows a vertical 1 pixel × horizontal 8 pixel pack at a vertical edge after overlap smoothing processing. It is a schematic diagram which shows the vertical 4 pixel x horizontal 2 pixel pack in the horizontal edge after an overlap smoothing process. It is a schematic diagram which shows the relationship of the mapping to the memory of vertical 1 pixel x horizontal 8 pixel pack and vertical 4 pixel x horizontal 2 pixel pack. It is a schematic diagram which shows the pixel (Y component) of the range required for an overlap smoothing process. It is a schematic diagram which shows the memory address seen from the spatial pixel position. It is a schematic diagram which shows the memory address seen from the spatial pixel position in case a reproduced image is interlaced. It is a schematic diagram which shows the pixel (Cb component) of the range required for an overlap smoothing process. It is a schematic diagram which shows the memory address seen from the spatial pixel position. It is a schematic diagram which shows the memory address seen from the spatial pixel position in the case of carrying out the interlace reproduction | regeneration of an image. It is a schematic diagram which shows the pixel (Cr component) of the range required for an overlap smoothing process. It is a schematic diagram which shows the memory address seen from the spatial pixel position. It is a schematic diagram which shows the memory address seen from the spatial pixel position in the case of carrying out the interlace reproduction | regeneration of an image. It is a block diagram which shows schematic structure of the conventional image decoding apparatus. It is a figure for demonstrating an overlap smoothing process. It is a figure which shows the time series of the data sent from the module of the front | former stage, or external memory. It is a figure for demonstrating the relationship between the decoded image, the overlap smoothing process, the deblocking filter process range, and each macroblock. It is a figure which shows the relationship between the memory operation range before and behind an overlap smoothing process, and a macroblock. It is a figure which shows the range in which the overlap smoothing process of the macroblock of the chroma signals Cb and Cr in the case of a color image is carried out. It is a schematic diagram for demonstrating an overlap smoothing process. It is a schematic diagram which shows the edge boundary processed by a deblocking filter. It is a schematic diagram for demonstrating a deblocking filter process.

Explanation of symbols

  11 bit stream structure analysis module, 13 inverse quantization / inverse DCT module, 31 overlap smoothing filter, 32 deblocking filter, 22 motion compensation module, 23 control unit

Claims (8)

In a video signal processing apparatus that performs block boundary smoothing processing when decoding encoded data obtained by encoding a video signal in units of blocks,
A first filter that performs a first block boundary smoothing process on the data being decoded;
A second filter that performs a second block boundary smoothing process on data including data that is arranged in succession to the first filter and has been subjected to the first block boundary smoothing process;
A predetermined number of memories for writing / reading data in predetermined pixel units in parallel;
A video that designates a memory so that the data of the predetermined pixel unit that is continuous in a direction orthogonal to a block boundary including the data subjected to the first block boundary smoothing process is written in different memories. Signal processing device.   2. The video signal processing apparatus according to claim 1, wherein the first block boundary smoothing process is an overlap smoothing process, and the second block boundary smoothing process is a deblocking filter process.   2. The video signal processing apparatus according to claim 1, wherein the predetermined pixel unit data including the data subjected to the first block boundary smoothing processing is written in the predetermined number of memories continuously in the processing direction.   2. The video signal processing apparatus according to claim 1, wherein the encoded data is a bit stream signal encoded based on a standard of SMTPE 421M. In a video signal processing method for performing block boundary smoothing processing when decoding encoded data obtained by encoding a video signal in units of blocks,
A first filter processing step for performing a first block boundary smoothing process on the data being decoded;
A second filter processing step for performing a second block boundary smoothing process on the data including the data subjected to the first block boundary smoothing process by performing the processing continuously to the first filter processing step. Have
In the first filter processing step, the predetermined pixel unit data continuous in a direction orthogonal to the block boundary including the data subjected to the first block boundary smoothing process is respectively written in parallel to a predetermined number of memories. ,
In the first filter processing step, the data for the second block boundary smoothing process is read in parallel from the predetermined number of memories in units of the predetermined pixels.   6. The video signal processing method according to claim 5, wherein the first block boundary smoothing process is an overlap smoothing process, and the second block boundary smoothing process is a deblocking filter process. In a video signal decoding apparatus that performs inverse quantization / inverse DCT processing on encoded data obtained by encoding a video signal in units of blocks, and performs decoding processing with motion compensation.
A first filter that is supplied with the addition data of the dequantized / inverse DCT processed data and the motion compensated data, and performs a first block boundary smoothing process;
A second filter that performs a second block boundary smoothing process on data including data that is arranged in succession to the first filter and has been subjected to the first block boundary smoothing process;
A predetermined number of memories for writing / reading data in predetermined pixel units in parallel;
A video that designates a memory so that the data of the predetermined pixel unit that is continuous in a direction orthogonal to a block boundary including the data subjected to the first block boundary smoothing process is written in different memories. Signal decoding device.   8. The video signal decoding apparatus according to claim 7, wherein the first block boundary smoothing process is an overlap smoothing process, and the second block boundary smoothing process is a deblocking filter process.

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