JP2008053505A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a semiconductor device which prevents the warpage of a package and can prevent the mutual contact of adjoining wires. <P>SOLUTION: The semiconductor device has a substrate 11, a chip 13 mounted on the substrate, a plurality of wires 18 which connects respectively a plurality of pads 16 on the chip and a plurality of pads 17 on the substrate, and a mold resin 41 which seals the chip and the plurality of wires. The mold resin contains 80 wt.% or more of filler whose mean particle diameter is 3-7 μm, and maximum particle diameter is 20-30 μm; and the pitch of the plurality of the pads is 100 μm or more. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device using a mold resin containing a fine filler, and more particularly to a semiconductor device capable of preventing package warpage and preventing contact between adjacent wires.

  A semiconductor device in which a substrate in which two or more chips are stacked is placed on a lower mold, and a mold resin is filled in a cavity formed by sandwiching the substrate between the lower mold and the upper mold, thereby sealing the chips The manufacturing method is known.

  In addition, when two chips are stacked using an adhesive layer, the upper chip may overhang the adhesive layer. In this case, a hard filler contained in the mold resin may be caught in the gap between the upper and lower chips. If it does so, there existed a problem that a filler will bite into a chip | tip of a lower side by the pressure at the time of injection | pouring of mold resin, and hardening shrinkage, and it will be damaged. On the other hand, a spacer may be provided to increase the gap between the upper chip and the lower chip, but there is a problem that the height of the entire apparatus increases.

  On the other hand, when the die bond film is pasted for each chip before the chip is mounted after dicing the wafer, or when a resin paste is applied for each chip, the die attach film is larger than the upper chip as an adhesive layer. The filler is prevented from biting into the gap between the upper and lower chips by using the resin or by protruding the resin paste. However, there is a case where there is no space for the adhesive layer to protrude or a gap between the upper and lower chips may occur due to a manufacturing error or the like.

  Further, when the wafer is diced after the die attach film is attached to the back surface of the wafer, the size of the die attach film is basically the same as the size of the chip. However, when the die attach film is wound around the blade during dicing or the die attach film cures and shrinks, the die attach film becomes smaller than the chip. May occur. Then, there is a problem that the filler bites into the gap and damages the surface of the lower chip.

  Therefore, in order to prevent the filler from biting between the stacked chips, a fine filler having a maximum particle size smaller than the thickness of the adhesive layer has been used. A conventional mold resin contained 78 wt% of a filler having an average particle size of 5 μm and a maximum particle size of 25 μm.

JP 2002-368029 A

  When the above conventional mold resin is used, the warpage of the package is about 1.2 mm. As a result of the warping of the package, a ball mounting defect occurs in the ball mounting process, or the package flies or a chipping defect occurs in the individual dicing process due to a poor contact between the warped package and the adhesive tape. There was a problem. As a first countermeasure for avoiding this problem, there is a method for preventing warpage of the package by placing a weight on the package during curing after molding. However, this method has a problem in that it is a manual operation and a resin burr placed on the base material is driven into the base material to cause a ball defect. Further, as a second countermeasure, there is a method for preventing defective bonding between the package and the adhesive tape by first cutting a place other than the cut line of the package to make the package smaller. However, this method has a problem that the production capacity of the individual dicing decreases by 5 to 10% due to an increase in the number of times of cutting.

  In addition, there is a problem in that when a wire is caused to flow by a resin flow at the time of transfer molding and adjacent wires come into contact with each other, a short circuit is caused. In order to prevent this, when a method (for example, refer patent document 1), such as connecting and fixing wires with a fixed body, is used, there is a problem that the manufacturing cost increases.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a semiconductor device that can prevent package warpage and contact between adjacent wires. .

  A semiconductor device according to the present invention includes a substrate, a chip mounted on the substrate, a plurality of wires connecting the plurality of pads on the chip and the plurality of pads on the substrate, and the chip and the plurality of wires. The mold resin contains 80 wt% or more of filler having an average particle diameter of 3 to 7 μm and a maximum particle diameter of 20 to 30 μm, and the pitch of the plurality of pads is 100 μm or more. Other features of the present invention will become apparent below.

  By this invention, the curvature of a package can be prevented and the contact of adjacent wires can be prevented.

Embodiment 1 FIG.
Hereinafter, the manufacturing process of the semiconductor device according to the first embodiment of the present invention will be described with reference to the drawings.

  First, as shown in FIG. 1, a chip 13 is mounted on a substrate 11 via an adhesive layer 12. Then, another chip 15 is bonded onto the chip 13 via the adhesive layer 14. However, the width of the adhesive layer 14 is narrower than the widths of the chips 13 and 15. FIG. 2 is a cross-sectional view showing a laminated structure of chips, and FIG. 3 is a plan view thereof. FIG. 4 is an enlarged plan view of the wire bonding portion. As illustrated, a plurality of pads 16 on the chip 13 and a plurality of pads 17 on the substrate 11 are connected by a plurality of wires 18, respectively. Here, the pitch of the plurality of pads 16 and 17 is preferably 100 μm or more, or the length of the plurality of wires 18 is preferably 3.0 mm or less. More preferably, the pitch between the plurality of pads 16 and 17 is 100 μm or more, and the length of the plurality of wires 18 is 3.0 mm or less. The substrate 11 is provided with a positioning hole 19, a taper pin hole 21, and an air vent 22.

  Here, a method of chip dicing and stacking will be described. First, as shown in FIG. 5, a plurality of semiconductor elements are formed on the wafer 23, and after polishing the wafer 23, the wafer 23 is attached to the dicing sheet 24 and placed on the table 25. Next, as shown in FIG. 6, the wafer 23 is diced together with the dicing sheet 24 by the dicing blade 26 and separated into chips 13. Then, as shown in FIG. 7, UV irradiation is performed.

  Next, as shown in FIG. 8, a die bond film is bonded onto the substrate 11 as the adhesive layer 12 using a tool 27. Note that a resin paste may be applied to the substrate 11 as the adhesive layer 12. Then, as shown in FIG. 9, the chip 13 is mounted on the adhesive layer 12. The above steps are repeated to stack any number of chips 13.

  FIG. 10 is a top view showing the upper mold, and FIG. 11 is a top view showing the lower mold. The upper die 28 is provided with a cull 29, a part of the cull-side runner 31, an overflow cavity 32, a part of the overflow cavity runner 33, a positioning pin receiving part 34, and a taper pin 35. On the other hand, the lower mold 39 is provided with a cull 29, a part of the cull-side runner 31, a part of the overflow cavity runner 33, a recess 36 for placing the substrate 11, a cavity 37, and a positioning pin 38. . In the present embodiment, the case where the cavity 37 is formed in the lower mold is shown. However, the present invention is not limited to this, and the cavity 37 is formed in the upper mold and the chips 13 and 15 of the substrate 11 are mounted. It is also possible to apply the present invention when the resin surface is placed with the surface facing upward.

  Next, as shown in FIG. 12, the substrate 11 is placed in the recess 36 of the lower mold 39 so that the chips 13 and 15 are placed in the cavity 37. At this time, the positioning pins 38 provided in the lower mold 39 are passed through the positioning holes 19 provided in the substrate 11 to position the substrate 11. Then, the substrate 11 is sandwiched between the lower mold 39 and the upper mold 28. At this time, the taper portion of the tip of the taper pin 35 provided on the upper mold 28 is brought into pressure contact with the opening edge portion of the taper pin hole 21 provided on the substrate 11, and the substrate 11 is slid, The end side over which the runner 31 spans is brought into pressure contact with the side wall of the recess 36 of the lower mold 39. In this state, the cavity 37 is filled with the mold resin 41 from the cull 29 through the cull-side runner 31 to seal the plurality of chips 13 and 15 and the plurality of wires 18 together.

  Here, in order to prevent the filler from biting between the chips 13 and 15, the filler contained in the mold resin 41 is formed by a sieve having an opening smaller than the gap between the lower chip 13 and the upper chip 15. It is preferable to use a sorted product. In the present embodiment, the gap between the lower chip 13 and the upper chip 15 is 35 μm, and the filler contained in the mold resin 41 has an average particle size of 3 to 7 μm and a maximum particle size of 20 to 30 μm. Fine filler. The mold resin 41 contains 80 wt% or more of fine filler. The maximum particle size of the filler is most preferably less than or equal to the gap between the lower chip 13 and the upper chip 15, but even if a filler having a larger particle size than the gap is included, the amount is If the amount is extremely small, the influence on the reliability of the semiconductor device remains within an acceptable range. For example, the content of the filler having a particle size larger than the gap is preferably 0.1 wt% or less. In particular, when the maximum particle size of the filler is 30 μm or less, or when the content of the filler having a particle size of 30 μm or less is 0.1 wt% or less and the total content of the filler is 80 wt% or more. The viscosity of the resin at the time of transfer molding tends to increase extremely compared to the conventional resin.

  Then, as shown in FIG. 13, after attaching the solder balls 42 to the terminals on the back surface of the substrate 11, the substrate 11 and the mold resin 41 are cut for each chip to obtain individual semiconductor devices.

  Here, FIG. 14 is a diagram showing the relationship between the fine filler content (filler amount) in the mold resin and the cavity warp amount when the thickness of the mold resin is 840 μm (left side) and 910 μm (right side). It is. From this figure, it can be seen that warpage of the package can be prevented by using a mold resin containing 80 wt% or more of fine filler.

  FIG. 15 is a diagram showing the relationship between the amount of filler and the linear expansion coefficient α1 below the glass transition temperature of the mold resin, and FIG. 16 shows the relationship between the amount of filler and the linear expansion coefficient α2 above the glass transition temperature of the mold resin. 17 is a diagram showing the filler amount and the molding shrinkage rate of the mold resin, FIG. 18 is a diagram showing the filler amount and the spiral flow of the mold resin, and FIG. 19 is a diagram showing the filler amount. It is a figure which shows the quantity and the viscosity of mold resin. From these figures, it can be seen that the fluidity of the mold resin decreases as the content of the fine filler increases. In particular, when the content of the fine filler exceeds 80 wt%, an extreme increase in viscosity occurs, so that the plurality of wires 18 are easily deformed with a decrease in the fluidity of the mold resin. Even if the resin has a high viscosity, if the flow rate of the mold resin 41 in the cavity 37 is extremely slow, deformation of the wire can be prevented, but a long time is required for filling the cavity 37 with the resin. Therefore, a decrease in productivity becomes a problem. In order to prevent a decrease in productivity, it is preferable to employ a maximum flow rate of the resin in the cavity 37 of at least 10 mm / second or more, more preferably 20 mm / second or more. However, when the resin is injected at a large flow rate, deformation of the wire 18 becomes a problem. Therefore, as described above, the pitch of the plurality of pads 16 and 17 is set to 100 μm or more, or the length of the plurality of wires 18 is set to 3.0 mm or less. Thereby, the contact of adjacent wires can be prevented.

Further, when the resin is filled in the cavity 37, the resin in the cavity 37 is caused to overflow into the overflow cavity 32 provided outside the substrate 11 through the overflow cavity runner 33. In order to remove the surface voids generated in the cavity 37, the pressure applied at the completion of the resin filling is set to 100 kg / cm ² or more. Further, when filling the chip region, the resin injection speed is increased, and the injection speed is decreased until the resin reaches the air vent 22. Thereby, the deformation of the plurality of wires 18 becomes more and more serious. Therefore, it is important to set the pitch of the plurality of pads 16 and 17 or the length of the plurality of wires 18 as described above to prevent contact between adjacent wires.

Embodiment 2. FIG.
FIG. 20 is a sectional view showing a semiconductor device according to the second embodiment of the present invention. As shown in the figure, another chip 15 is flip-chip connected to the chip 13 via a bump electrode 43. A mold resin 41 is injected into the gap between the chip 13 and the other chip 15. Other configurations are the same as those of the first embodiment. In particular, in order to prevent the filler from biting between the chips 13 and 15, it is preferable to use a filler selected by a sieve having an opening smaller than the gap between the lower chip 13 and the upper chip 15. In the present embodiment, the distance between the surface protective insulating film on the main surface of the lower chip 13 and the surface protective insulating film of the upper chip 15 is 35 μm, and the filler contained in the mold resin 41 is As in Embodiment 1, the fine filler has an average particle size of 3 to 7 μm and a maximum particle size of 20 to 30 μm. The mold resin 41 contains 80 wt% or more of fine filler as in the first embodiment, and the pitch of the plurality of pads 16 and 17 or the length of the plurality of wires 18 is set in the same manner as in the first embodiment. . As a result, the same effects as those of the first embodiment can be obtained.

It is a top view which shows the board | substrate which mounted several chip | tip. It is sectional drawing which shows the laminated structure of a chip | tip. It is a top view which shows the laminated structure of a chip | tip. It is the top view which expanded the wire junction part. It is a perspective view for demonstrating the method of chip | tip dicing and lamination | stacking. It is a perspective view for demonstrating the method of chip | tip dicing and lamination | stacking. It is a perspective view for demonstrating the method of chip | tip dicing and lamination | stacking. It is a perspective view for demonstrating the method of chip | tip dicing and lamination | stacking. It is a perspective view for demonstrating the method of chip | tip dicing and lamination | stacking. It is a top view which shows an upper metal mold | die. It is a top view which shows a lower mold. It is a top view which shows a mode that resin is filled in a cavity. It is sectional drawing which shows the semiconductor device which concerns on Embodiment 1 of this invention. It is a figure which shows the relationship between the amount of fillers, and the amount of cavity curvature. It is a figure which shows the relationship between the amount of fillers, and the linear expansion coefficient (alpha) 1 below the glass transition temperature of mold resin. It is a figure which shows the relationship between the amount of fillers, and the linear expansion coefficient (alpha) 2 more than the glass transition temperature of mold resin. It is a figure which shows the amount of fillers, and the molding shrinkage rate of mold resin. It is a figure which shows the amount of fillers, and the spiral flow of mold resin. It is a figure which shows the amount of fillers, and the viscosity of mold resin. It is sectional drawing which shows the semiconductor device which concerns on Embodiment 2 of this invention.

Explanation of symbols

11 substrate 13 chip 14 adhesive layer 15 chip (other chip)
16, 17 Multiple pads 18 Multiple wires 41 Mold resin

Claims (4)

A substrate,
A chip mounted on the substrate;
A plurality of wires respectively connecting a plurality of pads on the chip and a plurality of pads on the substrate;
A mold resin for sealing the chip and the plurality of wires;
The mold resin contains 80 wt% or more filler having an average particle size of 3 to 7 μm and a maximum particle size of 20 to 30 μm,
A semiconductor device, wherein a pitch of the plurality of pads is 100 μm or more. A substrate,
A chip mounted on the substrate;
A plurality of wires respectively connecting a plurality of pads on the chip and a plurality of pads on the substrate;
A mold resin for sealing the chip and the wire;
The mold resin contains 80 wt% or more filler having an average particle size of 3 to 7 μm and a maximum particle size of 20 to 30 μm,
The semiconductor device, wherein a length of the plurality of wires is 3.0 mm or less. It further has another chip bonded on the chip through an adhesive layer,
The semiconductor device according to claim 1, wherein a width of the adhesive layer is narrower than a width of the chip and the other chip. And further comprising another chip flip-chip connected on the chip,
3. The semiconductor device according to claim 1, wherein the molding resin is injected into a gap between the chip and the other chip.

Images