JP2008053249A - Process for fabricating semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a process for fabricating a semiconductor device in which a gate electrode having the dimensions just as designed can be formed with good reproducibility, even when that gate is arranged in the vicinity of the pole of second trench having a large area. <P>SOLUTION: The process for fabricating a semiconductor device comprises a step for forming a first trench Tr1 of small area on an Si substrate 1 in the CMOS region, a step for filling the first trench Tr1 by forming an SiO<SB>2</SB>film 5 on the entire surface of the Si substrate 1 where the first trench Tr1 is formed, a step for removing the SiO<SB>2</SB>film 5 from above the Si substrate 1 excepting the first trench Tr1 by planarizing the SiO<SB>2</SB>film 5, a step for forming a gate electrode 11 in the CMOS region on the Si substrate 1 from which the SiO<SB>2</SB>film 5 is removed, a step for forming a second trench Tr2 of large area in the high frequency region on the Si substrate 1 after forming the gate electrode 11, a step for filling the second trench Tr2 with an interlayer insulating film 15, and a step for forming an MIM capacitor 30 on the interlayer insulating film 15 located directly above the second trench Tr2. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device.

A semiconductor device (hereinafter also referred to as “RF-CMOS”) in which a high-frequency circuit including a resistor (R) and a capacitor (C) and a CMOS circuit are mixedly mounted on the same silicon (Si) substrate is known. Yes. In an RF-CMOS MIM (metal insulator metal) capacitor, an STI (shallow trench isolation) layer is formed under the MIM capacitor to reduce the parasitic capacitance with the Si substrate, and the distance between the MIM capacitor and the Si substrate is increased. There is a device to open. Here, the STI means a structure in which a groove (trench) is formed in the Si substrate in the element isolation region, and an insulator such as a silicon oxide (SiO ₂ ) film is embedded in the groove (for example, a patent) Reference 1).

FIG. 5A to FIG. 7B are process diagrams showing a method for manufacturing an RF-CMOS according to a conventional example. In FIG. 5A, first, a SiO ₂ film (not shown) is formed on the Si substrate 101, and a silicon nitride (SiN) film 103 is formed thereon. Next, a first trench Tr′1 for element isolation is formed on the Si substrate 101 in a region where a CMOS circuit is formed (hereinafter referred to as “CMOS region”) by photolithography technology and etching technology. In addition, a second trench Tr′2 having a larger area than the first trench Tr′1 is formed in the Si substrate 101 in a region where the capacitor is formed in the high-frequency circuit (hereinafter referred to as “capacitor region”).

Next, as shown in FIG. 5B, a SiO ₂ film 105 is formed on the entire upper surface of the Si substrate 101 to fill the first trench Tr′1 and the second trench Tr′2. The formation of the SiO ₂ film 105 is performed by, for example, a CVD (chemical vapor deposition) method. Then, as shown in FIG. 5C, the entire upper surface of the SiO ₂ film 105 is polished by CMP (chemical mechanical polish) to remove the SiO ₂ film 105 from the SiN film 103. In this way, the first STI layer 110 composed of the first trench Tr′1 and the SiO ₂ film 5 embedded in the first trench Tr′1 is formed, and the second trench Tr′2 A second STI layer 120 made of the SiO ₂ film 105 embedded in the second trench Tr ′ 2 is formed.

Next, for example, the SiN film 103 is wet-etched using hot phosphoric acid, and the SiO ₂ film 105 is lightly etched using a hydrofluoric acid-based solution. As a result, as shown in FIG. 6A, the surface of the Si substrate 101 is exposed in a region other than the first and second STi layers 110 and 120.
Next, a gate insulating film (not shown) is formed on the entire upper surface of the Si substrate 101, and a polysilicon film 107 is formed thereon as shown in FIG. 6B. Then, as shown in FIG. 6C, a resist film 109 is applied over the polysilicon film 107. The resist film 109 is applied by, for example, a spin coating method. Next, the resist film 109 is exposed and developed to form a gate electrode patterning resist pattern on the polysilicon film 107.

  Next, the polysilicon film 107 is etched using this resist pattern as a mask to form a gate electrode 111 as shown in FIG. Then, by using the gate electrode 111 as a mask, impurities such as As, P, and B are ion-implanted into the Si substrate 101, whereby LDD layers (not shown) each made of a low concentration impurity introduction layer are formed in the Si substrate 101 on both sides of the gate electrode 111. Z). Further, an insulating layer is formed on the Si substrate 101 on which the LDD layer is formed by a method such as CVD, and the insulating layer is etched back using dry etching such as RIE (reactive ion etching).

As a result, a sidewall 113 is formed on the sidewall of the gate electrode 111. Then, by using the gate electrode 111 and the sidewall 113 as a mask, impurities such as As, P, and B are ion-implanted into the Si substrate 101, so that a source layer made of a high-concentration impurity introduction layer is formed in the Si substrate 101 on both sides of the gate electrode 111, A drain layer (not shown) is formed. As a result, a MOS transistor is completed on the Si substrate 101 in the CMOS region. Next, as shown in FIG. 7B, an interlayer insulating film 115 made of a SiO ₂ film or the like is formed on the entire upper surface of the Si substrate 101. Then, the interlayer insulating film 115 is planarized by, for example, CMP or etch back.
Thereafter, the MIM capacitor 130 is formed on the interlayer insulating film 115 in the capacitor region. Here, as shown in FIG. 7B, the MIM capacitor 130 is formed immediately above the second STI layer 120 having a large area.
JP-A-8-70039

By the way, in the RF-CMOS manufacturing process, the inventor of the present invention has a larger amount of the SiO ₂ film 105 by CMP in the second STI layer 120 than in the first STI layer 110, and in the immediate vicinity of the second STI layer 120, I noticed that it was difficult to form the gate electrode 111 according to the design dimensions due to the difference in the amount of shaving.
More specifically, in the RF-CMOS, the difference in size between the first STI layer 110 for element isolation and the second STI layer 120 for reducing parasitic capacitance disposed under the capacitor is extremely large compared to other semiconductor devices. large. For example, the first STI layer 110 has a vertical and horizontal dimension of 1 μm × 1 μm or less in plan view, whereas the second STI layer 120 has a size of about 100 μm × 100 μm.

In this way, if the sizes of the first STI layer 110 and the second STI layer 120 differ by orders of magnitude, when the SiO ₂ film 105 is CMPed, as shown in FIG. The CMP polishing pad contacts (that is, follows) the bottom surface A of the recess on the surface of the SiO ₂ film 105 located above, and the bottom surface A of the recess is scraped from the initial stage of CMP. Further, since a relatively large force is applied to the SiO ₂ film 105 at the peripheral edge B of the recess from the polishing pad, the polishing rate is relatively higher than others.

Therefore, as shown in FIG. 8B, there is a difference in the amount of scraping of the SiO ₂ film 105 and the SiN film 103 between the CMOS region and the capacitor region. Further, in the second STI layer 120 and its periphery, a large step D is generated between the surface of the SiN film 103 left on the outer periphery of the second STI layer 120 and the surface of the SiO ₂ film 105 constituting the _second STI layer 120. Become. Due to such a step D, the film thickness of the resist film 109 is likely to vary between the second STI layer 120 and its periphery.

  Here, when the thickness of the resist film 109 varies, it becomes difficult to form the gate electrode 111 according to the design dimensions. According to the knowledge of the present inventor, for example, as shown in FIG. 8C, the film thickness of the resist film 109 tends to be thin in the second STI layer 120 and its periphery, and the gate electrode 111 is located very close to the second STI layer 120. When this is arranged, there is a problem that the dimensions are often thinner than others as shown in FIG.

Recently, the gate electrodes of MOS transistors have become smaller due to demands for miniaturization of semiconductor devices, and capacitors and MOS transistors have to be formed closer together due to the demand for higher integration of semiconductor devices. The above problems are expected to become even more prominent in the future.
Therefore, the present invention has been made in view of the above-mentioned problems discovered by the present inventors, and even when the gate electrode is arranged in the very vicinity of the second trench having a large area, the gate electrode is designed according to the design dimensions. An object of the present invention is to provide a method for manufacturing a semiconductor device which can be formed with good reproducibility.

  In order to achieve the above object, a manufacturing method of a semiconductor device according to a first aspect of the present invention is a manufacturing method of a semiconductor device in which a high-frequency circuit including a capacitor and a CMOS circuit are mixedly mounted on the same substrate, wherein the CMOS circuit is formed. Forming a first trench having a small area in the substrate in a region, forming a first insulating film on the entire surface of the substrate where the first trench is formed, and embedding the first trench; A step of planarizing the first insulating film to remove the first insulating film from the substrate other than the first trench, and the first insulating film in a region where the CMOS circuit is formed is removed. Forming a gate electrode for the CMOS circuit on the substrate; and, after forming the gate electrode, forming a second trench having a large area in the substrate in a region where the high-frequency circuit is formed Forming a second insulating film on the entire surface of the substrate on which the second trench is formed, and embedding the second trench, and the second insulating film positioned immediately above the second trench. Forming the capacitor thereon.

Here, the “high-frequency circuit” is a high-frequency oscillation circuit including, for example, a capacitor, a coil, and an inductance. In addition, for example, a first STI layer is configured by the “first trench” and the “first insulating film” embedded in the first trench. The first STI layer is used as, for example, an element isolation layer in a CMOS circuit or an element isolation layer between a CMOS circuit and a high frequency circuit. The “second trench” and the “second insulating film” embedded in the second trench constitute, for example, a second STI layer. The second STI layer is used as a layer for ensuring a long separation distance between the substrate and the capacitor and reducing the parasitic capacitance therebetween.
The method for manufacturing a semiconductor device according to a second aspect is the method for manufacturing a semiconductor device according to the first aspect, wherein the area of the first trench is 1 [μm ² ] or less, and the area of the second trench is 1 × 10. ⁴ [μm ² ] or more.

  According to the method for manufacturing a semiconductor device of the first and second aspects, the first trench formation step and the second trench formation step are both divided into separate steps and the gate electrode is formed as compared with the conventional technique. The second trench having a large area is formed. Therefore, no step due to the large area of the second trench is formed before the gate electrode is formed, so that the film thickness variation of the resist film for gate electrode patterning can be prevented. Thereby, even when the gate electrode is arranged in the very vicinity of the second trench, the gate electrode can be formed with good reproducibility according to the design dimensions. That is, it is possible to solve the above-described problems caused by the proximity of the first trench having a small area and the second trench having a large area. Therefore, it can contribute to further miniaturization and higher integration of the semiconductor device.

Embodiments of the present invention will be described below with reference to the drawings.
1A to 4 are process diagrams showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
In FIG. 1A, first, a silicon oxide (SiO ₂ ) film (not shown) is formed on a Si substrate 1, and a silicon nitride (SiN) film 3 is formed thereon. Next, a first trench Tr1 for element isolation is formed in the Si substrate 1 in a region where a CMOS circuit is formed (that is, a CMOS region) by photolithography technology and etching technology. The area of the first trench Tr1 is, for example, 0. Several μm × 0. It is about several μm, that is, 1 [μm ² ] or less. The depth of the first trench Tr1 from the surface of the Si substrate 1 is, for example, about 3 [μm].

In this embodiment, when the first trench Tr1 is formed, the second trench Tr2 is not formed in the Si substrate 1 in the region where the capacitor is formed in the high-frequency circuit (that is, the capacitor region). That is, unlike the prior art, in the present invention, the first trench Tr1 and the second trench Tr2 are formed separately.
After the formation of the first trench Tr1, as shown in FIG. 1B, a SiO ₂ film 5 is formed on the entire upper surface of the Si substrate 1 to embed the first trench Tr1. The formation of the SiO ₂ film 5 is performed by, for example, a CVD (chemical vapor deposition) method. Then, as shown in FIG. 1C, the entire upper surface of the SiO ₂ film 5 is polished by CMP (chemical mechanical polish) to remove the SiO ₂ film 5 from the SiN film 3. In this way, the first STI layer 10 including the first trench Tr1 and the SiO ₂ film 5 embedded in the first trench Tr1 is formed in a step before the second STI layer.

Next, for example, the SiN film is wet etched using hot phosphoric acid, and the SiO ₂ film is lightly etched using a hydrofluoric acid-based solution. Thereby, as shown in FIG. 2A, the surface of the Si substrate 1 is exposed in a region other than the first STI layer 10 (that is, the element region). Next, a gate insulating film (not shown) is formed on the entire upper surface of the Si substrate 1, and a polysilicon film 7 for a gate electrode is further formed thereon as shown in FIG. 2 (B). The gate insulating film is formed by, for example, thermally oxidizing the Si substrate 1. The polysilicon film 7 is formed by, for example, CVD. Then, as shown in FIG. 2C, a resist film 9 is applied on the polysilicon film 7. The resist film 9 is applied by, for example, a spin coating method.

  Next, the resist film 9 is exposed and developed to form a gate electrode patterning pattern on the polysilicon film 7 (that is, cover the region where the gate electrode is formed and expose the other region). Form. Then, using this resist pattern as a mask, the polysilicon film 7 is etched to form a gate electrode 11 as shown in FIG. Then, by using the gate electrode 11 as a mask, impurities such as As, P, and B are ion-implanted into the Si substrate 1, whereby LDD layers (not shown) each made of a low concentration impurity introduction layer are formed in the Si substrate 1 on both sides of the gate electrode. ). Further, an insulating layer is formed on the Si substrate 1 on which the LDD layer is formed by a method such as CVD, and the insulating layer is etched back using dry etching such as RIE (reactive ion etching).

  Thereby, the sidewall 13 is formed on the sidewall of the gate electrode 11. Then, by using the gate electrode 11 and the sidewall 13 as a mask, impurities such as As, P, and B are ion-implanted into the Si substrate 1, so that a source layer composed of a high-concentration impurity introduction layer is formed in the Si substrate 1 on both sides of the gate electrode 11. A drain layer (not shown) is formed. Thereby, a MOS transistor is completed on the Si substrate 1 in the CMOS region.

Next, as shown in FIG. 3B, a second trench Tr2 having a large area is formed in the Si substrate 1 in the capacitor region by a photolithography technique and an etching technique. The area of the second trench Tr2 is, for example, about 100 × 100 μm, that is, about 1 × 10 ⁴ [μm ² ] in the vertical and horizontal dimensions in plan view. The depth of the second trench Tr2 from the surface of the Si substrate 1 is, for example, about 3 [μm].

Next, as shown in FIG. 3C, an interlayer insulating film 15 made of a SiO ₂ film or the like is formed on the entire upper surface of the Si substrate 1. The formation of the interlayer insulating film 15 fills the second trench Tr2, and the second STI layer 20 including the second trench Tr2 and the interlayer insulating film 15 embedded in the second trench Tr2 is formed. Then, the interlayer insulating film 15 is planarized by, for example, CMP or etch back.

  Thereafter, as shown in FIG. 4, an MIM capacitor 30 is formed on the interlayer insulating film 15 in the capacitor region. Here, as shown in FIG. 4, the MIM capacitor 30 is formed on the interlayer insulating film 15 located immediately above the second STI layer 20. In this example, considering the misalignment between the MIM capacitor 30 and the second STI layer 20 in a plan view, the MIM capacitor 30 is formed on the interlayer insulating film 15 in a region located somewhat inside the outer periphery of the second STI layer 20. Form. The lower electrode 21 of the MIM capacitor 30 is, for example, aluminum (Al), the dielectric 23 is, for example, a silicon nitride film (SiN), and the upper electrode 25 is, for example, aluminum (Al).

  As described above, according to the method of manufacturing a semiconductor device according to the embodiment of the present invention, compared to the conventional technique, the process of forming the first trench Tr1 for element isolation and the second trench under the MIM capacitor 30 are performed. The formation process of Tr2 is divided into separate processes, and the second trench Tr2 is formed after the gate electrode 11 is formed.

Accordingly, no step due to the large area of the second trench Tr2 is formed before the gate electrode 11 is formed, so that the film thickness variation of the resist film 9 in the capacitor region can be prevented. Thereby, even when the gate electrode 11 is arranged in the very vicinity of the second trench Tr2, the gate electrode 11 can be formed with good reproducibility according to the design dimensions. That is, the above-mentioned problems caused by the close proximity of the first trench Tr1 having a small area and the second trench Tr2 having a large area can be solved, contributing to further miniaturization and higher integration of the semiconductor device. can do.
In this embodiment, the Si substrate 1 corresponds to the “substrate” of the present invention, the SiO ₂ film 5 corresponds to the “first insulating film” of the present invention, and the interlayer insulating film 15 corresponds to the “second insulating film” of the present invention. Corresponds to "membrane".

FIG. 6 is a diagram (No. 1) illustrating a method for manufacturing a semiconductor device according to an embodiment. FIG. 6 is a diagram (part 2) illustrating the method for manufacturing the semiconductor device according to the embodiment. FIG. 3 is a diagram (part 3) illustrating the method for manufacturing the semiconductor device according to the embodiment. FIG. 4 is a diagram (part 4) illustrating the method for manufacturing the semiconductor device according to the embodiment. The figure which shows the manufacturing method of the semiconductor device which concerns on a prior art example (the 1). FIG. 8 is a diagram (No. 2) illustrating a method for manufacturing a semiconductor device according to a conventional example. FIG. 3 is a diagram illustrating a method for manufacturing a semiconductor device according to a conventional example (part 3); The enlarged view which shows the trouble of a prior art example.

Explanation of symbols

1 Si substrate, 3 SiN film, 5 SiO ₂ film, 7 polysilicon film, 9 resist film, 10 first STI layer, 11 gate electrode, 13 sidewall, 15 interlayer insulating film, 20 second STI layer, 21 lower electrode, 23 Dielectric, 25 upper electrode, 30 MIM capacitor, Tr1 first trench, Tr2 second trench

Claims (2)

A method of manufacturing a semiconductor device in which a high-frequency circuit including a capacitor and a CMOS circuit are mixedly mounted on the same substrate,
Forming a first trench having a small area in the substrate in a region where the CMOS circuit is formed;
Forming a first insulating film on the entire surface of the substrate on which the first trench is formed, and embedding the first trench;
Performing a planarization process on the first insulating film to remove the first insulating film from the substrate other than the first trench;
Forming a gate electrode for the CMOS circuit on the substrate from which the first insulating film in the region where the CMOS circuit is to be formed is removed;
Forming a second trench having a large area in the substrate in a region where the high-frequency circuit is formed after forming the gate electrode;
Forming a second insulating film on the entire surface of the substrate on which the second trench is formed, and embedding the second trench;
Forming the capacitor on the second insulating film located immediately above the second trench. A method for manufacturing a semiconductor device, comprising: 2. The semiconductor device according to claim 1, wherein the area of the first trench is 1 [μm ² ] or less, and the area of the second trench is 1 × 10 ⁴ [μm ² ] or more. Production method.

Images