JP2008052842A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit in which the detection of the number of clocks for every command is performed surely, a program is prevented from being erroneously written, and a circuit scale is not increased even though the number of command is increased. <P>SOLUTION: This semiconductor integrated circuit comprises: a command decode part in which write and read of a memory element is programmed by input of a command of the prescribed number of clocks from a serial interface, each of input commands is decoded, and a command signal corresponding to the decoded result is output; a clock count part in which a count result being the number of clocks counted is output from terminals being different for each count result, and a latch part in which a command execution signal is set by a command signal and a count result being same as the number of clocks required for input of program processing corresponding to the command signal, when the count result which exceeds the number of clocks used for the setting is input, the command execution signal is reset. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a serial EEPROM or the like, and relates to a semiconductor integrated circuit having a program control circuit for writing data to a storage element.

Conventionally, transmission / reception of signals when a CPU on a CPU board writes and reads data to / from a serial input memory such as a serial EEPROM is performed as shown in FIG.
That is, at the time of data writing, a chip select signal CS, a serial clock signal SK, and memory write data DI are input from the CPU to the serial EEPROM. On the other hand, when reading data, memory read data DO is input from the serial EEPROM to the CPU.

At this time, when performing data writing or data reading, the CPU runs out of control at a command input that is programmed with a predetermined number of clocks, so that a number of clocks greater than the number of clocks necessary for memory programming is input, and an extra signal is output. It may be transferred to a serial EEPROM.
As a result, unintended data is written to the serial EEPROM, or data is read from unrelated addresses.

For this reason, when programming the data writing and reading processing to the serial EEPROM, the number of clocks required for writing the program for each processing is counted, and a signal having a clock number other than the number of clocks is input. In such a case, there is disclosed a semiconductor integrated circuit configured to prevent erroneous program writing by ignoring processing by the command (for example, see Patent Document 1).
Japanese Patent Laid-Open No. 06-309887

However, the semiconductor integrated circuit disclosed in Patent Document 1 requires a counter that counts the number of input clocks in a clock number detection circuit that detects whether the number of clocks is required for each command.
For this reason, the clock number detection circuit in the conventional semiconductor integrated circuit increases the number of commands for inputting these programs as the number of write and read modes increases, so that the number of counters corresponds to the increase in the number of commands. As a result, the circuit scale increases, the chip area increases, and the manufacturing cost increases.

    The present invention has been made in view of such circumstances, and reliably detects the number of clocks for each command, prevents erroneous program writing, and does not increase the circuit scale even if the number of commands increases. An object of the present invention is to provide a semiconductor integrated circuit having a clock number detection circuit.

  In order to solve the above-described problems, a semiconductor integrated circuit according to the present invention programs writing and reading to a memory element by inputting a command with a predetermined number of clocks from a serial interface, and decodes each input command. A command decoding unit that outputs a command signal corresponding to the decoding result, a clock counting unit that outputs a counting result obtained by counting the number of clocks from a different terminal for each counting result, the command signal, and the command signal A command execution signal is set based on the same count result as the number of clocks required for input of the corresponding program processing, and a latch unit that resets the command execution signal when a count result exceeding the number of clocks used for the setting is input; It is characterized by having.

  In the semiconductor integrated circuit of the present invention, the latch circuit generates a set signal for setting a command execution signal by a combination of the command signal and a count result corresponding to the command signal, and a command execution signal And a reset signal generation circuit that generates a reset signal by resetting a combination of the command signal and a count result one more than the count result corresponding to the command signal.

  The semiconductor integrated circuit according to the present invention is characterized in that the clock counter circuit includes a shift register that shifts data according to the clock and outputs the result as a count result.

  As described above, according to the semiconductor integrated circuit of the present invention, it is possible to prevent malfunction due to input of a clock number other than the number of clocks specified for each command, and to increase the number of commands. However, since one clock counter circuit is configured to manage the number of clocks required for each of a plurality of commands, it is not necessary to provide one count detection circuit for each command as in the conventional example. Compared to the conventional configuration, the manufacturing cost can be reduced compared to the conventional configuration.

Hereinafter, a semiconductor integrated circuit according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration example of the semiconductor integrated circuit according to the embodiment. As shown in FIG. 3, the present embodiment is a serial input serial EEPROM that inputs a command indicating program processing from a CPU or the like at a predetermined number of clocks, as shown in FIG.
In this figure, the clock count unit 1 receives “H” level data bits at the start of counting, and each time a clock SK is input as a serial input pulse train, the data bits are shifted by one bit. Data bits are output as count results from the output terminal of the position stage.
Here, the counting result is output from the output terminal of the stage corresponding to the number of clocks required for input of each command in the shift register of the clock count unit 1.

That is, when n clocks SK are input, the data bits move to the nth stage of the shift register, and when nth stage output terminals, for example, 16 clocks SK are input, 16 bits of the shift register are input. The data bit is shifted to the stage, and the clock count unit 1 outputs the “H” level count result from the 16th stage output terminal.
With this configuration, the semiconductor integrated circuit according to the present embodiment is configured to count the clocks necessary for inputting all commands with a single counter, and therefore count detection for counting the number of clocks for each command. Even if the circuit is not provided and the number of commands is increased, the chip size is not increased as compared with the configuration of the conventional example, and the manufacturing cost can be suppressed.

The decoding unit 2 performs a decoding process at a timing when a command is input in synchronization with the clock SK and a command recognition signal is input, and a command signal (..., Cn,. Cn + 1,...
In the AND circuit 3, one input terminal is connected to an output terminal that outputs a command signal as a decoding result of the decoding unit 2, and the other input terminal counts the same as the number of clocks necessary for inputting a command of the command signal. It is connected to the resulting output terminal (the output terminal of the clock counter unit 1).
The AND circuit 3 functions as a set signal generation circuit. When both the command signal input and the count result corresponding to the number of clocks of the command signal are input at the “H” level, An H level set signal is output.

In the AND circuit 4, one input terminal is connected to an output terminal that outputs a command signal as a decoding result of the decoding unit 2, and the other input terminal exceeds the number of clocks necessary for inputting a command of the command signal by one. It is connected to the output terminal (the output terminal of the clock counter unit 1) of the same counting result as the number of clocks.
The AND circuit 4 functions as a reset signal generation circuit, and both the input command signal and the counting result of the number of clocks exceeding the number of clocks of the command signal, for example, one more, are set to the “H” level. If it is input, an “H” level reset signal is output.
The AND circuit 3 described above is provided for each command, that is, for each command signal. For example, the AND circuit 3 corresponds to the AND circuits..., 3n, 3n + 1,. For example, it corresponds to the AND circuits..., 4n, 4n + 1,.

In response to the set signal input to the set terminal S, the latch unit 5 outputs the command execution signal KCOUNT indicating the program enable state from the output terminal Q at “H” level, and the reset signal input to the reset terminal R. Thus, the command execution signal KCOUNT output from the output terminal Q is reset to “L” level.
The latch unit 5 is also provided for each command, that is, for each command signal, and corresponds to, for example, the latch circuits..., 5n, 5n + 1,.

In the AND circuit 6, one input terminal is connected to the output terminal Q of the latch unit 5, and the command establishment signal PGCY is input to the other input terminal. The command establishment signal PGCY is an inverted signal of the chip select signal CS that activates the semiconductor integrated circuit.
The AND circuit 6 is also provided for each command, that is, for each command signal, and corresponds to the AND circuits..., 6n, 6n + 1,.

The AND circuit 6 performs program processing on the instruction signal when both the command execution signal KCOUNT and the command establishment signal PGCY from the corresponding latch unit 5 are input, that is, when both signals are at “H” level. Outputs to part 7 at "H" level.
The program processing unit 7 performs processing corresponding to the input command signal on each memory element of the memory unit 8.

For example, when an instruction signal is generated from a command corresponding to a program process for writing data, a process of writing data input from the outside to the memory element at an address input from the outside is performed.
When an instruction signal is generated from a command corresponding to a program process for reading data, data is read as data DO from a memory element at an address input from the outside.
The clock count unit 1 does not use a shift register, but compares the output value of the counter circuit with the set value corresponding to the number of clocks required for inputting each command, and corresponds to the number of clocks that match. The coincidence signal may be output as the counting result.

Next, an operation example of the semiconductor integrated circuit according to the embodiment will be described with reference to FIGS. 1 and 2. Here, FIG. 2 is a timing chart for explaining the command input operation of the semiconductor integrated circuit of FIG. 2A shows a normal case where the number of clocks required by the command is input, and FIG. 2B shows an abnormal case where a number of clocks required by the command is input. Yes.
As described above, the number of bits of data indicating program processing, that is, the number of clocks required for input is different for each command.

For example, in the case of data writing, an address for writing data and the data to be written are transferred after a command indicating data writing. If the number of bits of the command is 4 bits, the address is 4 bits, and the data is 8 bits, a 16-bit clock number is required.
Hereinafter, the operation of the semiconductor integrated circuit will be described by taking n as 16 in the circuit of FIG.

In FIG. 2A, after the chip select signal CS transits from the “L” level to the “H” level and enters the command input mode, the clock SK is input to the clock counter unit 1 and the decoder unit 2 as a pulse train. Is done.
After the chip select signal CS becomes “H” level, the clock count unit 1 sequentially shifts the data bits in correspondence with the clock SK.
Here, the decoding unit 2 sequentially inputs bit data indicating commands from the input terminal of the semiconductor integrated circuit in synchronization with the clock SK.
In this embodiment, since the number of bits of the command is 4, when the clock SK is input four times, the clock count unit 1 uses the fourth count result as a command recognition signal to the decoding unit 2. Output.

Then, the decoding unit 2 decodes the input command and outputs a command signal corresponding to the decoding result.
At this time, since the input command is the command signal Cn that requires the clock number n (= 16), the decoding unit 2 outputs the “H” level command signal Cn.
As a result, the “H” level command signal Cn is input to one input terminal of each of the AND circuit 3n and the AND circuit 4n.

Next, every time the clock SK is input, the clock count unit 1 shifts the output terminal from which the output result is output by one stage. When n (16) is input, the clock count unit 1 outputs “H” from the terminal Tn. 'Level output result is output to the AND circuit 3n.
As a result, the AND circuit 3n outputs an “H” level set signal to the latch unit 5n because both of the two input terminals become “H” level signals.
When the set signal is input, the latch unit 5n is set, and the command execution signal KCOUNT is output from the output terminal Q to one input terminal of the AND circuit 6n at the “H” level.

Since the 17th clock SK is not input and the pulse train of the clock SK is completed with only the number of clocks corresponding to the command of the command signal Cn, the chip select signal CS is changed from “H” level to “L”. The level shifts to a “H” level command establishment signal and is input to the other input terminal of the AND circuit 6n.
As a result, the AND circuit 6 n outputs the instruction signal PGCY to the program processing unit 7 when the “H” level is input to both of the two input terminals.
Then, the program processing unit 7 receives the command signal PGCY and performs processing such as writing the input data to a specified address of the memory unit 8.

Next, in FIG. 2B, after the chip select signal CS transits from the “L” level to the “H” level to enter the command input mode, the clock SK is used as a pulse train, and the clock counter unit 1 and the decoder unit 2 is input.
After the chip select signal CS becomes “H” level, the clock count unit 1 sequentially shifts the data bits in correspondence with the clock SK.
Here, the decoding unit 2 sequentially inputs bit data indicating commands from the input terminal of the semiconductor integrated circuit in synchronization with the clock SK.
In this embodiment, since the number of bits of the command is 4, when the clock SK is input four times, the clock count unit 1 uses the fourth count result as a command recognition signal to the decoding unit 2. Output.

Then, the decoding unit 2 decodes the input command and outputs a command signal corresponding to the decoding result.
At this time, since the input command is the command signal Cn that requires the clock number n (= 16), the decoding unit 2 outputs the “H” level command signal Cn.
As a result, the “H” level command signal Cn is input to one input terminal of each of the AND circuit 3n and the AND circuit 4n.

Next, every time the clock SK is input, the clock count unit 1 shifts the output terminal from which the output result is output by one stage. When n (16) is input, the clock count unit 1 outputs “H” from the terminal Tn. 'Level output result is output to the AND circuit 3n.
As a result, the AND circuit 3n outputs an “H” level set signal to the latch unit 5n because both of the two input terminals become “H” level signals.
When the set signal is input, the latch unit 5n is set, and the command execution signal KCOUNT is output from the output terminal Q to one input terminal of the AND circuit 6n at the “H” level.

Since the 17th clock SK is input, the clock count unit 1 shifts the output terminal from which the output result is output by one stage each time the clock SK is input, and n + 1 (17th) is generated. When inputted, an output result of “H” level is outputted from the terminal Tn + 1 to the AND circuit 4n.
As a result, the AND circuit 4n has already received the "H" level command signal Cn, and both of the two input terminals have become the "H" level. Therefore, the AND circuit 4n sends the "H" level reset signal to the latch unit 5n. To the reset terminal R.

When the reset signal is input, the latch unit 5n shifts the command execution signal KCOUNT output from the output terminal Q from the “H” level to the “L” level.
As a result, when the chip select signal CS transits from the “H” level to the “L” level and the “H” level command establishment signal is input to the other input terminal of the AND circuit 6n, the AND circuit 6n Since the terminal is at “L” level, the command signal PGCY is not output to the program processing unit 7.
Therefore, according to the present embodiment, when an abnormal command is input, the input command is ignored without being executed, and erroneous writing to the semiconductor integrated circuit can be prevented.

1 is a block diagram illustrating a configuration example of a semiconductor integrated circuit (serial EEPROM) according to an embodiment of the present invention. 2 is a timing chart for explaining the operation of the semiconductor integrated circuit of FIG. It is a conceptual diagram explaining transmission and reception of signals between a serial EEPROM and a CPU.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Clock count part 2 ... Decoding part 3n, 3n + 1, 4n, 4n + 1, 6n, 6n + 1 ... AND circuit 5n, 5n + 1 ... Latch part 7 ... Program processing part 8 ... Memory part

Claims (3)

A semiconductor integrated circuit that programs writing and reading to a memory element by inputting a command with a predetermined number of clocks from a serial interface,
A command decoding unit that decodes each input command and outputs a command signal corresponding to the decoding result;
A clock count unit that outputs a count result obtained by counting the number of clocks from a different terminal for each count result; and
When a command execution signal is set based on the command signal and the count result equal to the number of clocks required for input of program processing corresponding to the command signal, and a count result exceeding the number of clocks used for the setting is input A semiconductor integrated circuit comprising: a latch unit that resets a command execution signal. The latch circuit is
A set signal generating circuit for generating a set signal for setting a command execution signal by a combination of the command signal and a count result corresponding to the command signal;
2. The reset signal generation circuit that generates a reset signal for resetting a command execution signal by combining the command signal and a count result that is one more than a count result corresponding to the command signal. Semiconductor integrated device.   3. The semiconductor memory device according to claim 1, wherein the clock counter circuit includes a shift register that shifts data according to the clock and outputs the result as a count result.

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